1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
47 P_CORE_BI_PLL_TEST_SE,
50 static struct clk_fixed_factor gpll0_div = {
53 .hw.init = &(struct clk_init_data){
54 .name = "mmss_gpll0_div",
55 .parent_data = &(const struct clk_parent_data){
60 .ops = &clk_fixed_factor_ops,
64 static const struct clk_div_table post_div_table_fabia_even[] = {
72 static struct clk_alpha_pll mmpll0 = {
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
77 .enable_mask = BIT(0),
78 .hw.init = &(struct clk_init_data){
80 .parent_data = &(const struct clk_parent_data){
85 .ops = &clk_alpha_pll_fixed_fabia_ops,
90 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
93 .post_div_table = post_div_table_fabia_even,
94 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
97 .clkr.hw.init = &(struct clk_init_data){
98 .name = "mmpll0_out_even",
99 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
101 .ops = &clk_alpha_pll_postdiv_fabia_ops,
105 static struct clk_alpha_pll mmpll1 = {
107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
110 .enable_mask = BIT(1),
111 .hw.init = &(struct clk_init_data){
113 .parent_data = &(const struct clk_parent_data){
118 .ops = &clk_alpha_pll_fixed_fabia_ops,
123 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
126 .post_div_table = post_div_table_fabia_even,
127 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
130 .clkr.hw.init = &(struct clk_init_data){
131 .name = "mmpll1_out_even",
132 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
134 .ops = &clk_alpha_pll_postdiv_fabia_ops,
138 static struct clk_alpha_pll mmpll3 = {
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
141 .clkr.hw.init = &(struct clk_init_data){
143 .parent_data = &(const struct clk_parent_data){
148 .ops = &clk_alpha_pll_fixed_fabia_ops,
152 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
155 .post_div_table = post_div_table_fabia_even,
156 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
159 .clkr.hw.init = &(struct clk_init_data){
160 .name = "mmpll3_out_even",
161 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
163 .ops = &clk_alpha_pll_postdiv_fabia_ops,
167 static struct clk_alpha_pll mmpll4 = {
169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
170 .clkr.hw.init = &(struct clk_init_data){
172 .parent_data = &(const struct clk_parent_data){
177 .ops = &clk_alpha_pll_fixed_fabia_ops,
181 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
184 .post_div_table = post_div_table_fabia_even,
185 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
187 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "mmpll4_out_even",
190 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
192 .ops = &clk_alpha_pll_postdiv_fabia_ops,
196 static struct clk_alpha_pll mmpll5 = {
198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
199 .clkr.hw.init = &(struct clk_init_data){
201 .parent_data = &(const struct clk_parent_data){
206 .ops = &clk_alpha_pll_fixed_fabia_ops,
210 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
213 .post_div_table = post_div_table_fabia_even,
214 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "mmpll5_out_even",
219 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
221 .ops = &clk_alpha_pll_postdiv_fabia_ops,
225 static struct clk_alpha_pll mmpll6 = {
227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
228 .clkr.hw.init = &(struct clk_init_data){
230 .parent_data = &(const struct clk_parent_data){
235 .ops = &clk_alpha_pll_fixed_fabia_ops,
239 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
242 .post_div_table = post_div_table_fabia_even,
243 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
245 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
246 .clkr.hw.init = &(struct clk_init_data){
247 .name = "mmpll6_out_even",
248 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
250 .ops = &clk_alpha_pll_postdiv_fabia_ops,
254 static struct clk_alpha_pll mmpll7 = {
256 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
257 .clkr.hw.init = &(struct clk_init_data){
259 .parent_data = &(const struct clk_parent_data){
264 .ops = &clk_alpha_pll_fixed_fabia_ops,
268 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
271 .post_div_table = post_div_table_fabia_even,
272 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
275 .clkr.hw.init = &(struct clk_init_data){
276 .name = "mmpll7_out_even",
277 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
279 .ops = &clk_alpha_pll_postdiv_fabia_ops,
283 static struct clk_alpha_pll mmpll10 = {
285 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
286 .clkr.hw.init = &(struct clk_init_data){
288 .parent_data = &(const struct clk_parent_data){
293 .ops = &clk_alpha_pll_fixed_fabia_ops,
297 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
300 .post_div_table = post_div_table_fabia_even,
301 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "mmpll10_out_even",
306 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
308 .ops = &clk_alpha_pll_postdiv_fabia_ops,
312 static const struct parent_map mmss_xo_hdmi_map[] = {
315 { P_CORE_BI_PLL_TEST_SE, 7 }
318 static const struct clk_parent_data mmss_xo_hdmi[] = {
319 { .fw_name = "xo", .name = "xo" },
320 { .fw_name = "hdmipll", .name = "hdmipll" },
321 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
324 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
328 { P_CORE_BI_PLL_TEST_SE, 7 }
331 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
332 { .fw_name = "xo", .name = "xo" },
333 { .fw_name = "dsi0dsi", .name = "dsi0dsi" },
334 { .fw_name = "dsi1dsi", .name = "dsi1dsi" },
335 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
338 static const struct parent_map mmss_xo_dsibyte_map[] = {
340 { P_DSI0PLL_BYTE, 1 },
341 { P_DSI1PLL_BYTE, 2 },
342 { P_CORE_BI_PLL_TEST_SE, 7 }
345 static const struct clk_parent_data mmss_xo_dsibyte[] = {
346 { .fw_name = "xo", .name = "xo" },
347 { .fw_name = "dsi0byte", .name = "dsi0byte" },
348 { .fw_name = "dsi1byte", .name = "dsi1byte" },
349 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
352 static const struct parent_map mmss_xo_dp_map[] = {
356 { P_CORE_BI_PLL_TEST_SE, 7 }
359 static const struct clk_parent_data mmss_xo_dp[] = {
360 { .fw_name = "xo", .name = "xo" },
361 { .fw_name = "dplink", .name = "dplink" },
362 { .fw_name = "dpvco", .name = "dpvco" },
363 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
366 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
370 { P_CORE_BI_PLL_TEST_SE, 7 }
373 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
374 { .fw_name = "xo", .name = "xo" },
375 { .fw_name = "gpll0", .name = "gpll0" },
376 { .hw = &gpll0_div.hw },
377 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
380 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
382 { P_MMPLL0_OUT_EVEN, 1 },
385 { P_CORE_BI_PLL_TEST_SE, 7 }
388 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
389 { .fw_name = "xo", .name = "xo" },
390 { .hw = &mmpll0_out_even.clkr.hw },
391 { .fw_name = "gpll0", .name = "gpll0" },
392 { .hw = &gpll0_div.hw },
393 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
396 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
398 { P_MMPLL0_OUT_EVEN, 1 },
399 { P_MMPLL1_OUT_EVEN, 2 },
402 { P_CORE_BI_PLL_TEST_SE, 7 }
405 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
406 { .fw_name = "xo", .name = "xo" },
407 { .hw = &mmpll0_out_even.clkr.hw },
408 { .hw = &mmpll1_out_even.clkr.hw },
409 { .fw_name = "gpll0", .name = "gpll0" },
410 { .hw = &gpll0_div.hw },
411 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
414 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
416 { P_MMPLL0_OUT_EVEN, 1 },
417 { P_MMPLL5_OUT_EVEN, 2 },
420 { P_CORE_BI_PLL_TEST_SE, 7 }
423 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
424 { .fw_name = "xo", .name = "xo" },
425 { .hw = &mmpll0_out_even.clkr.hw },
426 { .hw = &mmpll5_out_even.clkr.hw },
427 { .fw_name = "gpll0", .name = "gpll0" },
428 { .hw = &gpll0_div.hw },
429 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
432 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
434 { P_MMPLL0_OUT_EVEN, 1 },
435 { P_MMPLL3_OUT_EVEN, 3 },
436 { P_MMPLL6_OUT_EVEN, 4 },
439 { P_CORE_BI_PLL_TEST_SE, 7 }
442 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
443 { .fw_name = "xo", .name = "xo" },
444 { .hw = &mmpll0_out_even.clkr.hw },
445 { .hw = &mmpll3_out_even.clkr.hw },
446 { .hw = &mmpll6_out_even.clkr.hw },
447 { .fw_name = "gpll0", .name = "gpll0" },
448 { .hw = &gpll0_div.hw },
449 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
452 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
454 { P_MMPLL4_OUT_EVEN, 1 },
455 { P_MMPLL7_OUT_EVEN, 2 },
456 { P_MMPLL10_OUT_EVEN, 3 },
459 { P_CORE_BI_PLL_TEST_SE, 7 }
462 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
463 { .fw_name = "xo", .name = "xo" },
464 { .hw = &mmpll4_out_even.clkr.hw },
465 { .hw = &mmpll7_out_even.clkr.hw },
466 { .hw = &mmpll10_out_even.clkr.hw },
467 { .fw_name = "gpll0", .name = "gpll0" },
468 { .hw = &gpll0_div.hw },
469 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
472 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
474 { P_MMPLL0_OUT_EVEN, 1 },
475 { P_MMPLL7_OUT_EVEN, 2 },
476 { P_MMPLL10_OUT_EVEN, 3 },
479 { P_CORE_BI_PLL_TEST_SE, 7 }
482 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
483 { .fw_name = "xo", .name = "xo" },
484 { .hw = &mmpll0_out_even.clkr.hw },
485 { .hw = &mmpll7_out_even.clkr.hw },
486 { .hw = &mmpll10_out_even.clkr.hw },
487 { .fw_name = "gpll0", .name = "gpll0" },
488 { .hw = &gpll0_div.hw },
489 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
492 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
494 { P_MMPLL0_OUT_EVEN, 1 },
495 { P_MMPLL4_OUT_EVEN, 2 },
496 { P_MMPLL7_OUT_EVEN, 3 },
497 { P_MMPLL10_OUT_EVEN, 4 },
500 { P_CORE_BI_PLL_TEST_SE, 7 }
503 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
504 { .fw_name = "xo", .name = "xo" },
505 { .hw = &mmpll0_out_even.clkr.hw },
506 { .hw = &mmpll4_out_even.clkr.hw },
507 { .hw = &mmpll7_out_even.clkr.hw },
508 { .hw = &mmpll10_out_even.clkr.hw },
509 { .fw_name = "gpll0", .name = "gpll0" },
510 { .hw = &gpll0_div.hw },
511 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
514 static struct clk_rcg2 byte0_clk_src = {
517 .parent_map = mmss_xo_dsibyte_map,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "byte0_clk_src",
520 .parent_data = mmss_xo_dsibyte,
522 .ops = &clk_byte2_ops,
523 .flags = CLK_SET_RATE_PARENT,
527 static struct clk_rcg2 byte1_clk_src = {
530 .parent_map = mmss_xo_dsibyte_map,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "byte1_clk_src",
533 .parent_data = mmss_xo_dsibyte,
535 .ops = &clk_byte2_ops,
536 .flags = CLK_SET_RATE_PARENT,
540 static const struct freq_tbl ftbl_cci_clk_src[] = {
541 F(37500000, P_GPLL0, 16, 0, 0),
542 F(50000000, P_GPLL0, 12, 0, 0),
543 F(100000000, P_GPLL0, 6, 0, 0),
547 static struct clk_rcg2 cci_clk_src = {
550 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
551 .freq_tbl = ftbl_cci_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "cci_clk_src",
554 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
556 .ops = &clk_rcg2_ops,
560 static const struct freq_tbl ftbl_cpp_clk_src[] = {
561 F(100000000, P_GPLL0, 6, 0, 0),
562 F(200000000, P_GPLL0, 3, 0, 0),
563 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
564 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
565 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
566 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
567 F(600000000, P_GPLL0, 1, 0, 0),
571 static struct clk_rcg2 cpp_clk_src = {
574 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
575 .freq_tbl = ftbl_cpp_clk_src,
576 .clkr.hw.init = &(struct clk_init_data){
577 .name = "cpp_clk_src",
578 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
580 .ops = &clk_rcg2_ops,
584 static const struct freq_tbl ftbl_csi_clk_src[] = {
585 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
586 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
587 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
588 F(300000000, P_GPLL0, 2, 0, 0),
589 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
590 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
594 static struct clk_rcg2 csi0_clk_src = {
597 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
598 .freq_tbl = ftbl_csi_clk_src,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "csi0_clk_src",
601 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
603 .ops = &clk_rcg2_ops,
607 static struct clk_rcg2 csi1_clk_src = {
610 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
611 .freq_tbl = ftbl_csi_clk_src,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "csi1_clk_src",
614 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
616 .ops = &clk_rcg2_ops,
620 static struct clk_rcg2 csi2_clk_src = {
623 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
624 .freq_tbl = ftbl_csi_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "csi2_clk_src",
627 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
629 .ops = &clk_rcg2_ops,
633 static struct clk_rcg2 csi3_clk_src = {
636 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
637 .freq_tbl = ftbl_csi_clk_src,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "csi3_clk_src",
640 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
642 .ops = &clk_rcg2_ops,
646 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
647 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
648 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
649 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
650 F(300000000, P_GPLL0, 2, 0, 0),
651 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
655 static struct clk_rcg2 csiphy_clk_src = {
658 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
659 .freq_tbl = ftbl_csiphy_clk_src,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "csiphy_clk_src",
662 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
664 .ops = &clk_rcg2_ops,
668 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
674 static struct clk_rcg2 csi0phytimer_clk_src = {
677 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
678 .freq_tbl = ftbl_csiphytimer_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "csi0phytimer_clk_src",
681 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
683 .ops = &clk_rcg2_ops,
687 static struct clk_rcg2 csi1phytimer_clk_src = {
690 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
691 .freq_tbl = ftbl_csiphytimer_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "csi1phytimer_clk_src",
694 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
696 .ops = &clk_rcg2_ops,
700 static struct clk_rcg2 csi2phytimer_clk_src = {
703 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
704 .freq_tbl = ftbl_csiphytimer_clk_src,
705 .clkr.hw.init = &(struct clk_init_data){
706 .name = "csi2phytimer_clk_src",
707 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
709 .ops = &clk_rcg2_ops,
713 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
714 F(19200000, P_XO, 1, 0, 0),
718 static struct clk_rcg2 dp_aux_clk_src = {
721 .parent_map = mmss_xo_gpll0_gpll0_div_map,
722 .freq_tbl = ftbl_dp_aux_clk_src,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "dp_aux_clk_src",
725 .parent_data = mmss_xo_gpll0_gpll0_div,
727 .ops = &clk_rcg2_ops,
731 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
732 F(101250, P_DPLINK, 1, 5, 16),
733 F(168750, P_DPLINK, 1, 5, 16),
734 F(337500, P_DPLINK, 1, 5, 16),
738 static struct clk_rcg2 dp_crypto_clk_src = {
741 .parent_map = mmss_xo_dp_map,
742 .freq_tbl = ftbl_dp_crypto_clk_src,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "dp_crypto_clk_src",
745 .parent_data = mmss_xo_dp,
747 .ops = &clk_rcg2_ops,
751 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
752 F(162000, P_DPLINK, 2, 0, 0),
753 F(270000, P_DPLINK, 2, 0, 0),
754 F(540000, P_DPLINK, 2, 0, 0),
758 static struct clk_rcg2 dp_link_clk_src = {
761 .parent_map = mmss_xo_dp_map,
762 .freq_tbl = ftbl_dp_link_clk_src,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "dp_link_clk_src",
765 .parent_data = mmss_xo_dp,
767 .ops = &clk_rcg2_ops,
771 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
772 F(154000000, P_DPVCO, 1, 0, 0),
773 F(337500000, P_DPVCO, 2, 0, 0),
774 F(675000000, P_DPVCO, 2, 0, 0),
778 static struct clk_rcg2 dp_pixel_clk_src = {
781 .parent_map = mmss_xo_dp_map,
782 .freq_tbl = ftbl_dp_pixel_clk_src,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "dp_pixel_clk_src",
785 .parent_data = mmss_xo_dp,
787 .ops = &clk_rcg2_ops,
791 static const struct freq_tbl ftbl_esc_clk_src[] = {
792 F(19200000, P_XO, 1, 0, 0),
796 static struct clk_rcg2 esc0_clk_src = {
799 .parent_map = mmss_xo_dsibyte_map,
800 .freq_tbl = ftbl_esc_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "esc0_clk_src",
803 .parent_data = mmss_xo_dsibyte,
805 .ops = &clk_rcg2_ops,
809 static struct clk_rcg2 esc1_clk_src = {
812 .parent_map = mmss_xo_dsibyte_map,
813 .freq_tbl = ftbl_esc_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "esc1_clk_src",
816 .parent_data = mmss_xo_dsibyte,
818 .ops = &clk_rcg2_ops,
822 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
823 { .src = P_HDMIPLL },
827 static struct clk_rcg2 extpclk_clk_src = {
830 .parent_map = mmss_xo_hdmi_map,
831 .freq_tbl = ftbl_extpclk_clk_src,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "extpclk_clk_src",
834 .parent_data = mmss_xo_hdmi,
836 .ops = &clk_byte_ops,
837 .flags = CLK_SET_RATE_PARENT,
841 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
842 F(100000000, P_GPLL0, 6, 0, 0),
843 F(200000000, P_GPLL0, 3, 0, 0),
844 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
845 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
846 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
850 static struct clk_rcg2 fd_core_clk_src = {
853 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
854 .freq_tbl = ftbl_fd_core_clk_src,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "fd_core_clk_src",
857 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
859 .ops = &clk_rcg2_ops,
863 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
864 F(19200000, P_XO, 1, 0, 0),
868 static struct clk_rcg2 hdmi_clk_src = {
871 .parent_map = mmss_xo_gpll0_gpll0_div_map,
872 .freq_tbl = ftbl_hdmi_clk_src,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "hdmi_clk_src",
875 .parent_data = mmss_xo_gpll0_gpll0_div,
877 .ops = &clk_rcg2_ops,
881 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
882 F(75000000, P_GPLL0, 8, 0, 0),
883 F(150000000, P_GPLL0, 4, 0, 0),
884 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
885 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
889 static struct clk_rcg2 jpeg0_clk_src = {
892 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
893 .freq_tbl = ftbl_jpeg0_clk_src,
894 .clkr.hw.init = &(struct clk_init_data){
895 .name = "jpeg0_clk_src",
896 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
898 .ops = &clk_rcg2_ops,
902 static const struct freq_tbl ftbl_maxi_clk_src[] = {
903 F(19200000, P_XO, 1, 0, 0),
904 F(75000000, P_GPLL0_DIV, 4, 0, 0),
905 F(171428571, P_GPLL0, 3.5, 0, 0),
906 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
907 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
911 static struct clk_rcg2 maxi_clk_src = {
914 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
915 .freq_tbl = ftbl_maxi_clk_src,
916 .clkr.hw.init = &(struct clk_init_data){
917 .name = "maxi_clk_src",
918 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
920 .ops = &clk_rcg2_ops,
924 static const struct freq_tbl ftbl_mclk_clk_src[] = {
925 F(4800000, P_XO, 4, 0, 0),
926 F(6000000, P_GPLL0_DIV, 10, 1, 5),
927 F(8000000, P_GPLL0_DIV, 1, 2, 75),
928 F(9600000, P_XO, 2, 0, 0),
929 F(16666667, P_GPLL0_DIV, 2, 1, 9),
930 F(19200000, P_XO, 1, 0, 0),
931 F(24000000, P_GPLL0_DIV, 1, 2, 25),
932 F(33333333, P_GPLL0_DIV, 1, 2, 9),
933 F(48000000, P_GPLL0, 1, 2, 25),
934 F(66666667, P_GPLL0, 1, 2, 9),
938 static struct clk_rcg2 mclk0_clk_src = {
941 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
942 .freq_tbl = ftbl_mclk_clk_src,
943 .clkr.hw.init = &(struct clk_init_data){
944 .name = "mclk0_clk_src",
945 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
947 .ops = &clk_rcg2_ops,
951 static struct clk_rcg2 mclk1_clk_src = {
954 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
955 .freq_tbl = ftbl_mclk_clk_src,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "mclk1_clk_src",
958 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
960 .ops = &clk_rcg2_ops,
964 static struct clk_rcg2 mclk2_clk_src = {
967 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
968 .freq_tbl = ftbl_mclk_clk_src,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "mclk2_clk_src",
971 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
973 .ops = &clk_rcg2_ops,
977 static struct clk_rcg2 mclk3_clk_src = {
980 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
981 .freq_tbl = ftbl_mclk_clk_src,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "mclk3_clk_src",
984 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
986 .ops = &clk_rcg2_ops,
990 static const struct freq_tbl ftbl_mdp_clk_src[] = {
991 F(85714286, P_GPLL0, 7, 0, 0),
992 F(100000000, P_GPLL0, 6, 0, 0),
993 F(150000000, P_GPLL0, 4, 0, 0),
994 F(171428571, P_GPLL0, 3.5, 0, 0),
995 F(200000000, P_GPLL0, 3, 0, 0),
996 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
997 F(300000000, P_GPLL0, 2, 0, 0),
998 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
999 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1003 static struct clk_rcg2 mdp_clk_src = {
1006 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1007 .freq_tbl = ftbl_mdp_clk_src,
1008 .clkr.hw.init = &(struct clk_init_data){
1009 .name = "mdp_clk_src",
1010 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1012 .ops = &clk_rcg2_ops,
1016 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1017 F(19200000, P_XO, 1, 0, 0),
1021 static struct clk_rcg2 vsync_clk_src = {
1024 .parent_map = mmss_xo_gpll0_gpll0_div_map,
1025 .freq_tbl = ftbl_vsync_clk_src,
1026 .clkr.hw.init = &(struct clk_init_data){
1027 .name = "vsync_clk_src",
1028 .parent_data = mmss_xo_gpll0_gpll0_div,
1030 .ops = &clk_rcg2_ops,
1034 static const struct freq_tbl ftbl_ahb_clk_src[] = {
1035 F(19200000, P_XO, 1, 0, 0),
1036 F(40000000, P_GPLL0, 15, 0, 0),
1037 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1041 static struct clk_rcg2 ahb_clk_src = {
1044 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
1045 .freq_tbl = ftbl_ahb_clk_src,
1046 .clkr.hw.init = &(struct clk_init_data){
1047 .name = "ahb_clk_src",
1048 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1050 .ops = &clk_rcg2_ops,
1054 static const struct freq_tbl ftbl_axi_clk_src[] = {
1055 F(75000000, P_GPLL0, 8, 0, 0),
1056 F(171428571, P_GPLL0, 3.5, 0, 0),
1057 F(240000000, P_GPLL0, 2.5, 0, 0),
1058 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1059 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1064 static struct clk_rcg2 axi_clk_src = {
1067 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1068 .freq_tbl = ftbl_axi_clk_src,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "axi_clk_src",
1071 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1073 .ops = &clk_rcg2_ops,
1077 static struct clk_rcg2 pclk0_clk_src = {
1081 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1082 .clkr.hw.init = &(struct clk_init_data){
1083 .name = "pclk0_clk_src",
1084 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1086 .ops = &clk_pixel_ops,
1087 .flags = CLK_SET_RATE_PARENT,
1091 static struct clk_rcg2 pclk1_clk_src = {
1095 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "pclk1_clk_src",
1098 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1100 .ops = &clk_pixel_ops,
1101 .flags = CLK_SET_RATE_PARENT,
1105 static const struct freq_tbl ftbl_rot_clk_src[] = {
1106 F(171428571, P_GPLL0, 3.5, 0, 0),
1107 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1108 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1109 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1113 static struct clk_rcg2 rot_clk_src = {
1116 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1117 .freq_tbl = ftbl_rot_clk_src,
1118 .clkr.hw.init = &(struct clk_init_data){
1119 .name = "rot_clk_src",
1120 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1122 .ops = &clk_rcg2_ops,
1126 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1129 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1130 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1131 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1135 static struct clk_rcg2 video_core_clk_src = {
1138 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1139 .freq_tbl = ftbl_video_core_clk_src,
1140 .clkr.hw.init = &(struct clk_init_data){
1141 .name = "video_core_clk_src",
1142 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1144 .ops = &clk_rcg2_ops,
1148 static struct clk_rcg2 video_subcore0_clk_src = {
1151 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1152 .freq_tbl = ftbl_video_core_clk_src,
1153 .clkr.hw.init = &(struct clk_init_data){
1154 .name = "video_subcore0_clk_src",
1155 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1157 .ops = &clk_rcg2_ops,
1161 static struct clk_rcg2 video_subcore1_clk_src = {
1164 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1165 .freq_tbl = ftbl_video_core_clk_src,
1166 .clkr.hw.init = &(struct clk_init_data){
1167 .name = "video_subcore1_clk_src",
1168 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1170 .ops = &clk_rcg2_ops,
1174 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1175 F(200000000, P_GPLL0, 3, 0, 0),
1176 F(300000000, P_GPLL0, 2, 0, 0),
1177 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1178 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1179 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1180 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1181 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1182 F(600000000, P_GPLL0, 1, 0, 0),
1186 static struct clk_rcg2 vfe0_clk_src = {
1189 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1190 .freq_tbl = ftbl_vfe_clk_src,
1191 .clkr.hw.init = &(struct clk_init_data){
1192 .name = "vfe0_clk_src",
1193 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1195 .ops = &clk_rcg2_ops,
1199 static struct clk_rcg2 vfe1_clk_src = {
1202 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1203 .freq_tbl = ftbl_vfe_clk_src,
1204 .clkr.hw.init = &(struct clk_init_data){
1205 .name = "vfe1_clk_src",
1206 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1208 .ops = &clk_rcg2_ops,
1212 static struct clk_branch misc_ahb_clk = {
1217 .enable_reg = 0x328,
1218 .enable_mask = BIT(0),
1219 .hw.init = &(struct clk_init_data){
1220 .name = "misc_ahb_clk",
1221 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1223 .ops = &clk_branch2_ops,
1224 .flags = CLK_SET_RATE_PARENT,
1229 static struct clk_branch video_core_clk = {
1232 .enable_reg = 0x1028,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "video_core_clk",
1236 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1238 .ops = &clk_branch2_ops,
1239 .flags = CLK_SET_RATE_PARENT,
1244 static struct clk_branch video_ahb_clk = {
1249 .enable_reg = 0x1030,
1250 .enable_mask = BIT(0),
1251 .hw.init = &(struct clk_init_data){
1252 .name = "video_ahb_clk",
1253 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1255 .ops = &clk_branch2_ops,
1256 .flags = CLK_SET_RATE_PARENT,
1261 static struct clk_branch video_axi_clk = {
1264 .enable_reg = 0x1034,
1265 .enable_mask = BIT(0),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "video_axi_clk",
1268 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1270 .ops = &clk_branch2_ops,
1275 static struct clk_branch video_maxi_clk = {
1278 .enable_reg = 0x1038,
1279 .enable_mask = BIT(0),
1280 .hw.init = &(struct clk_init_data){
1281 .name = "video_maxi_clk",
1282 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1284 .ops = &clk_branch2_ops,
1285 .flags = CLK_SET_RATE_PARENT,
1290 static struct clk_branch video_subcore0_clk = {
1293 .enable_reg = 0x1048,
1294 .enable_mask = BIT(0),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "video_subcore0_clk",
1297 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1299 .ops = &clk_branch2_ops,
1300 .flags = CLK_SET_RATE_PARENT,
1305 static struct clk_branch video_subcore1_clk = {
1308 .enable_reg = 0x104c,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "video_subcore1_clk",
1312 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1314 .ops = &clk_branch2_ops,
1315 .flags = CLK_SET_RATE_PARENT,
1320 static struct clk_branch mdss_ahb_clk = {
1325 .enable_reg = 0x2308,
1326 .enable_mask = BIT(0),
1327 .hw.init = &(struct clk_init_data){
1328 .name = "mdss_ahb_clk",
1329 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1331 .ops = &clk_branch2_ops,
1332 .flags = CLK_SET_RATE_PARENT,
1337 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1340 .enable_reg = 0x230c,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "mdss_hdmi_dp_ahb_clk",
1344 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1346 .ops = &clk_branch2_ops,
1347 .flags = CLK_SET_RATE_PARENT,
1352 static struct clk_branch mdss_axi_clk = {
1355 .enable_reg = 0x2310,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "mdss_axi_clk",
1359 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1361 .ops = &clk_branch2_ops,
1366 static struct clk_branch mdss_pclk0_clk = {
1369 .enable_reg = 0x2314,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(struct clk_init_data){
1372 .name = "mdss_pclk0_clk",
1373 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1375 .ops = &clk_branch2_ops,
1376 .flags = CLK_SET_RATE_PARENT,
1381 static struct clk_branch mdss_pclk1_clk = {
1384 .enable_reg = 0x2318,
1385 .enable_mask = BIT(0),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "mdss_pclk1_clk",
1388 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1390 .ops = &clk_branch2_ops,
1391 .flags = CLK_SET_RATE_PARENT,
1396 static struct clk_branch mdss_mdp_clk = {
1399 .enable_reg = 0x231c,
1400 .enable_mask = BIT(0),
1401 .hw.init = &(struct clk_init_data){
1402 .name = "mdss_mdp_clk",
1403 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1405 .ops = &clk_branch2_ops,
1406 .flags = CLK_SET_RATE_PARENT,
1411 static struct clk_branch mdss_mdp_lut_clk = {
1414 .enable_reg = 0x2320,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "mdss_mdp_lut_clk",
1418 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1420 .ops = &clk_branch2_ops,
1421 .flags = CLK_SET_RATE_PARENT,
1426 static struct clk_branch mdss_extpclk_clk = {
1429 .enable_reg = 0x2324,
1430 .enable_mask = BIT(0),
1431 .hw.init = &(struct clk_init_data){
1432 .name = "mdss_extpclk_clk",
1433 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1435 .ops = &clk_branch2_ops,
1436 .flags = CLK_SET_RATE_PARENT,
1441 static struct clk_branch mdss_vsync_clk = {
1444 .enable_reg = 0x2328,
1445 .enable_mask = BIT(0),
1446 .hw.init = &(struct clk_init_data){
1447 .name = "mdss_vsync_clk",
1448 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1450 .ops = &clk_branch2_ops,
1451 .flags = CLK_SET_RATE_PARENT,
1456 static struct clk_branch mdss_hdmi_clk = {
1459 .enable_reg = 0x2338,
1460 .enable_mask = BIT(0),
1461 .hw.init = &(struct clk_init_data){
1462 .name = "mdss_hdmi_clk",
1463 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1465 .ops = &clk_branch2_ops,
1466 .flags = CLK_SET_RATE_PARENT,
1471 static struct clk_branch mdss_byte0_clk = {
1474 .enable_reg = 0x233c,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "mdss_byte0_clk",
1478 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1480 .ops = &clk_branch2_ops,
1481 .flags = CLK_SET_RATE_PARENT,
1486 static struct clk_branch mdss_byte1_clk = {
1489 .enable_reg = 0x2340,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "mdss_byte1_clk",
1493 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1495 .ops = &clk_branch2_ops,
1496 .flags = CLK_SET_RATE_PARENT,
1501 static struct clk_branch mdss_esc0_clk = {
1504 .enable_reg = 0x2344,
1505 .enable_mask = BIT(0),
1506 .hw.init = &(struct clk_init_data){
1507 .name = "mdss_esc0_clk",
1508 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1510 .ops = &clk_branch2_ops,
1511 .flags = CLK_SET_RATE_PARENT,
1516 static struct clk_branch mdss_esc1_clk = {
1519 .enable_reg = 0x2348,
1520 .enable_mask = BIT(0),
1521 .hw.init = &(struct clk_init_data){
1522 .name = "mdss_esc1_clk",
1523 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1525 .ops = &clk_branch2_ops,
1526 .flags = CLK_SET_RATE_PARENT,
1531 static struct clk_branch mdss_rot_clk = {
1534 .enable_reg = 0x2350,
1535 .enable_mask = BIT(0),
1536 .hw.init = &(struct clk_init_data){
1537 .name = "mdss_rot_clk",
1538 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1540 .ops = &clk_branch2_ops,
1541 .flags = CLK_SET_RATE_PARENT,
1546 static struct clk_branch mdss_dp_link_clk = {
1549 .enable_reg = 0x2354,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "mdss_dp_link_clk",
1553 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1555 .ops = &clk_branch2_ops,
1556 .flags = CLK_SET_RATE_PARENT,
1561 static struct clk_branch mdss_dp_link_intf_clk = {
1564 .enable_reg = 0x2358,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "mdss_dp_link_intf_clk",
1568 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1570 .ops = &clk_branch2_ops,
1571 .flags = CLK_SET_RATE_PARENT,
1576 static struct clk_branch mdss_dp_crypto_clk = {
1579 .enable_reg = 0x235c,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "mdss_dp_crypto_clk",
1583 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1585 .ops = &clk_branch2_ops,
1586 .flags = CLK_SET_RATE_PARENT,
1591 static struct clk_branch mdss_dp_pixel_clk = {
1594 .enable_reg = 0x2360,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "mdss_dp_pixel_clk",
1598 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1600 .ops = &clk_branch2_ops,
1601 .flags = CLK_SET_RATE_PARENT,
1606 static struct clk_branch mdss_dp_aux_clk = {
1609 .enable_reg = 0x2364,
1610 .enable_mask = BIT(0),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "mdss_dp_aux_clk",
1613 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1615 .ops = &clk_branch2_ops,
1616 .flags = CLK_SET_RATE_PARENT,
1621 static struct clk_branch mdss_byte0_intf_clk = {
1624 .enable_reg = 0x2374,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "mdss_byte0_intf_clk",
1628 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1630 .ops = &clk_branch2_ops,
1631 .flags = CLK_SET_RATE_PARENT,
1636 static struct clk_branch mdss_byte1_intf_clk = {
1639 .enable_reg = 0x2378,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "mdss_byte1_intf_clk",
1643 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1645 .ops = &clk_branch2_ops,
1646 .flags = CLK_SET_RATE_PARENT,
1651 static struct clk_branch camss_csi0phytimer_clk = {
1654 .enable_reg = 0x3024,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data){
1657 .name = "camss_csi0phytimer_clk",
1658 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1660 .ops = &clk_branch2_ops,
1661 .flags = CLK_SET_RATE_PARENT,
1666 static struct clk_branch camss_csi1phytimer_clk = {
1669 .enable_reg = 0x3054,
1670 .enable_mask = BIT(0),
1671 .hw.init = &(struct clk_init_data){
1672 .name = "camss_csi1phytimer_clk",
1673 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1675 .ops = &clk_branch2_ops,
1676 .flags = CLK_SET_RATE_PARENT,
1681 static struct clk_branch camss_csi2phytimer_clk = {
1684 .enable_reg = 0x3084,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "camss_csi2phytimer_clk",
1688 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1690 .ops = &clk_branch2_ops,
1691 .flags = CLK_SET_RATE_PARENT,
1696 static struct clk_branch camss_csi0_clk = {
1699 .enable_reg = 0x30b4,
1700 .enable_mask = BIT(0),
1701 .hw.init = &(struct clk_init_data){
1702 .name = "camss_csi0_clk",
1703 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1705 .ops = &clk_branch2_ops,
1706 .flags = CLK_SET_RATE_PARENT,
1711 static struct clk_branch camss_csi0_ahb_clk = {
1714 .enable_reg = 0x30bc,
1715 .enable_mask = BIT(0),
1716 .hw.init = &(struct clk_init_data){
1717 .name = "camss_csi0_ahb_clk",
1718 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1720 .ops = &clk_branch2_ops,
1721 .flags = CLK_SET_RATE_PARENT,
1726 static struct clk_branch camss_csi0rdi_clk = {
1729 .enable_reg = 0x30d4,
1730 .enable_mask = BIT(0),
1731 .hw.init = &(struct clk_init_data){
1732 .name = "camss_csi0rdi_clk",
1733 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1735 .ops = &clk_branch2_ops,
1736 .flags = CLK_SET_RATE_PARENT,
1741 static struct clk_branch camss_csi0pix_clk = {
1744 .enable_reg = 0x30e4,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "camss_csi0pix_clk",
1748 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1750 .ops = &clk_branch2_ops,
1751 .flags = CLK_SET_RATE_PARENT,
1756 static struct clk_branch camss_csi1_clk = {
1759 .enable_reg = 0x3124,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "camss_csi1_clk",
1763 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1765 .ops = &clk_branch2_ops,
1766 .flags = CLK_SET_RATE_PARENT,
1771 static struct clk_branch camss_csi1_ahb_clk = {
1774 .enable_reg = 0x3128,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "camss_csi1_ahb_clk",
1778 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1780 .ops = &clk_branch2_ops,
1781 .flags = CLK_SET_RATE_PARENT,
1786 static struct clk_branch camss_csi1rdi_clk = {
1789 .enable_reg = 0x3144,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "camss_csi1rdi_clk",
1793 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1795 .ops = &clk_branch2_ops,
1796 .flags = CLK_SET_RATE_PARENT,
1801 static struct clk_branch camss_csi1pix_clk = {
1804 .enable_reg = 0x3154,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "camss_csi1pix_clk",
1808 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1810 .ops = &clk_branch2_ops,
1811 .flags = CLK_SET_RATE_PARENT,
1816 static struct clk_branch camss_csi2_clk = {
1819 .enable_reg = 0x3184,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "camss_csi2_clk",
1823 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1825 .ops = &clk_branch2_ops,
1826 .flags = CLK_SET_RATE_PARENT,
1831 static struct clk_branch camss_csi2_ahb_clk = {
1834 .enable_reg = 0x3188,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "camss_csi2_ahb_clk",
1838 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1840 .ops = &clk_branch2_ops,
1841 .flags = CLK_SET_RATE_PARENT,
1846 static struct clk_branch camss_csi2rdi_clk = {
1849 .enable_reg = 0x31a4,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "camss_csi2rdi_clk",
1853 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1855 .ops = &clk_branch2_ops,
1856 .flags = CLK_SET_RATE_PARENT,
1861 static struct clk_branch camss_csi2pix_clk = {
1864 .enable_reg = 0x31b4,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "camss_csi2pix_clk",
1868 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1870 .ops = &clk_branch2_ops,
1871 .flags = CLK_SET_RATE_PARENT,
1876 static struct clk_branch camss_csi3_clk = {
1879 .enable_reg = 0x31e4,
1880 .enable_mask = BIT(0),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "camss_csi3_clk",
1883 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1885 .ops = &clk_branch2_ops,
1886 .flags = CLK_SET_RATE_PARENT,
1891 static struct clk_branch camss_csi3_ahb_clk = {
1894 .enable_reg = 0x31e8,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "camss_csi3_ahb_clk",
1898 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1900 .ops = &clk_branch2_ops,
1901 .flags = CLK_SET_RATE_PARENT,
1906 static struct clk_branch camss_csi3rdi_clk = {
1909 .enable_reg = 0x3204,
1910 .enable_mask = BIT(0),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "camss_csi3rdi_clk",
1913 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1915 .ops = &clk_branch2_ops,
1916 .flags = CLK_SET_RATE_PARENT,
1921 static struct clk_branch camss_csi3pix_clk = {
1924 .enable_reg = 0x3214,
1925 .enable_mask = BIT(0),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "camss_csi3pix_clk",
1928 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1930 .ops = &clk_branch2_ops,
1931 .flags = CLK_SET_RATE_PARENT,
1936 static struct clk_branch camss_ispif_ahb_clk = {
1939 .enable_reg = 0x3224,
1940 .enable_mask = BIT(0),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "camss_ispif_ahb_clk",
1943 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1945 .ops = &clk_branch2_ops,
1946 .flags = CLK_SET_RATE_PARENT,
1951 static struct clk_branch camss_cci_clk = {
1954 .enable_reg = 0x3344,
1955 .enable_mask = BIT(0),
1956 .hw.init = &(struct clk_init_data){
1957 .name = "camss_cci_clk",
1958 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1960 .ops = &clk_branch2_ops,
1961 .flags = CLK_SET_RATE_PARENT,
1966 static struct clk_branch camss_cci_ahb_clk = {
1969 .enable_reg = 0x3348,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "camss_cci_ahb_clk",
1973 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1975 .ops = &clk_branch2_ops,
1976 .flags = CLK_SET_RATE_PARENT,
1981 static struct clk_branch camss_mclk0_clk = {
1984 .enable_reg = 0x3384,
1985 .enable_mask = BIT(0),
1986 .hw.init = &(struct clk_init_data){
1987 .name = "camss_mclk0_clk",
1988 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1990 .ops = &clk_branch2_ops,
1991 .flags = CLK_SET_RATE_PARENT,
1996 static struct clk_branch camss_mclk1_clk = {
1999 .enable_reg = 0x33b4,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "camss_mclk1_clk",
2003 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
2005 .ops = &clk_branch2_ops,
2006 .flags = CLK_SET_RATE_PARENT,
2011 static struct clk_branch camss_mclk2_clk = {
2014 .enable_reg = 0x33e4,
2015 .enable_mask = BIT(0),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "camss_mclk2_clk",
2018 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
2020 .ops = &clk_branch2_ops,
2021 .flags = CLK_SET_RATE_PARENT,
2026 static struct clk_branch camss_mclk3_clk = {
2029 .enable_reg = 0x3414,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "camss_mclk3_clk",
2033 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
2035 .ops = &clk_branch2_ops,
2036 .flags = CLK_SET_RATE_PARENT,
2041 static struct clk_branch camss_top_ahb_clk = {
2044 .enable_reg = 0x3484,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "camss_top_ahb_clk",
2048 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2050 .ops = &clk_branch2_ops,
2051 .flags = CLK_SET_RATE_PARENT,
2056 static struct clk_branch camss_ahb_clk = {
2059 .enable_reg = 0x348c,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "camss_ahb_clk",
2063 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2065 .ops = &clk_branch2_ops,
2066 .flags = CLK_SET_RATE_PARENT,
2071 static struct clk_branch camss_micro_ahb_clk = {
2074 .enable_reg = 0x3494,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "camss_micro_ahb_clk",
2078 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2080 .ops = &clk_branch2_ops,
2081 .flags = CLK_SET_RATE_PARENT,
2086 static struct clk_branch camss_jpeg0_clk = {
2089 .enable_reg = 0x35a8,
2090 .enable_mask = BIT(0),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "camss_jpeg0_clk",
2093 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2095 .ops = &clk_branch2_ops,
2096 .flags = CLK_SET_RATE_PARENT,
2101 static struct clk_branch camss_jpeg_ahb_clk = {
2104 .enable_reg = 0x35b4,
2105 .enable_mask = BIT(0),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "camss_jpeg_ahb_clk",
2108 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2110 .ops = &clk_branch2_ops,
2111 .flags = CLK_SET_RATE_PARENT,
2116 static struct clk_branch camss_jpeg_axi_clk = {
2119 .enable_reg = 0x35b8,
2120 .enable_mask = BIT(0),
2121 .hw.init = &(struct clk_init_data){
2122 .name = "camss_jpeg_axi_clk",
2123 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2125 .ops = &clk_branch2_ops,
2130 static struct clk_branch camss_vfe0_ahb_clk = {
2133 .enable_reg = 0x3668,
2134 .enable_mask = BIT(0),
2135 .hw.init = &(struct clk_init_data){
2136 .name = "camss_vfe0_ahb_clk",
2137 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2139 .ops = &clk_branch2_ops,
2140 .flags = CLK_SET_RATE_PARENT,
2145 static struct clk_branch camss_vfe1_ahb_clk = {
2148 .enable_reg = 0x3678,
2149 .enable_mask = BIT(0),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "camss_vfe1_ahb_clk",
2152 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2154 .ops = &clk_branch2_ops,
2155 .flags = CLK_SET_RATE_PARENT,
2160 static struct clk_branch camss_vfe0_clk = {
2163 .enable_reg = 0x36a8,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "camss_vfe0_clk",
2167 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2169 .ops = &clk_branch2_ops,
2170 .flags = CLK_SET_RATE_PARENT,
2175 static struct clk_branch camss_vfe1_clk = {
2178 .enable_reg = 0x36ac,
2179 .enable_mask = BIT(0),
2180 .hw.init = &(struct clk_init_data){
2181 .name = "camss_vfe1_clk",
2182 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2184 .ops = &clk_branch2_ops,
2185 .flags = CLK_SET_RATE_PARENT,
2190 static struct clk_branch camss_cpp_clk = {
2193 .enable_reg = 0x36b0,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "camss_cpp_clk",
2197 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2199 .ops = &clk_branch2_ops,
2200 .flags = CLK_SET_RATE_PARENT,
2205 static struct clk_branch camss_cpp_ahb_clk = {
2208 .enable_reg = 0x36b4,
2209 .enable_mask = BIT(0),
2210 .hw.init = &(struct clk_init_data){
2211 .name = "camss_cpp_ahb_clk",
2212 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2214 .ops = &clk_branch2_ops,
2215 .flags = CLK_SET_RATE_PARENT,
2220 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2223 .enable_reg = 0x36b8,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "camss_vfe_vbif_ahb_clk",
2227 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2229 .ops = &clk_branch2_ops,
2230 .flags = CLK_SET_RATE_PARENT,
2235 static struct clk_branch camss_vfe_vbif_axi_clk = {
2238 .enable_reg = 0x36bc,
2239 .enable_mask = BIT(0),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "camss_vfe_vbif_axi_clk",
2242 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2244 .ops = &clk_branch2_ops,
2249 static struct clk_branch camss_cpp_axi_clk = {
2252 .enable_reg = 0x36c4,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "camss_cpp_axi_clk",
2256 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2258 .ops = &clk_branch2_ops,
2263 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2266 .enable_reg = 0x36c8,
2267 .enable_mask = BIT(0),
2268 .hw.init = &(struct clk_init_data){
2269 .name = "camss_cpp_vbif_ahb_clk",
2270 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2272 .ops = &clk_branch2_ops,
2273 .flags = CLK_SET_RATE_PARENT,
2278 static struct clk_branch camss_csi_vfe0_clk = {
2281 .enable_reg = 0x3704,
2282 .enable_mask = BIT(0),
2283 .hw.init = &(struct clk_init_data){
2284 .name = "camss_csi_vfe0_clk",
2285 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2287 .ops = &clk_branch2_ops,
2288 .flags = CLK_SET_RATE_PARENT,
2293 static struct clk_branch camss_csi_vfe1_clk = {
2296 .enable_reg = 0x3714,
2297 .enable_mask = BIT(0),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "camss_csi_vfe1_clk",
2300 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2302 .ops = &clk_branch2_ops,
2303 .flags = CLK_SET_RATE_PARENT,
2308 static struct clk_branch camss_vfe0_stream_clk = {
2311 .enable_reg = 0x3720,
2312 .enable_mask = BIT(0),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "camss_vfe0_stream_clk",
2315 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2317 .ops = &clk_branch2_ops,
2318 .flags = CLK_SET_RATE_PARENT,
2323 static struct clk_branch camss_vfe1_stream_clk = {
2326 .enable_reg = 0x3724,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "camss_vfe1_stream_clk",
2330 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2332 .ops = &clk_branch2_ops,
2333 .flags = CLK_SET_RATE_PARENT,
2338 static struct clk_branch camss_cphy_csid0_clk = {
2341 .enable_reg = 0x3730,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "camss_cphy_csid0_clk",
2345 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2347 .ops = &clk_branch2_ops,
2348 .flags = CLK_SET_RATE_PARENT,
2353 static struct clk_branch camss_cphy_csid1_clk = {
2356 .enable_reg = 0x3734,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "camss_cphy_csid1_clk",
2360 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2362 .ops = &clk_branch2_ops,
2363 .flags = CLK_SET_RATE_PARENT,
2368 static struct clk_branch camss_cphy_csid2_clk = {
2371 .enable_reg = 0x3738,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "camss_cphy_csid2_clk",
2375 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2377 .ops = &clk_branch2_ops,
2378 .flags = CLK_SET_RATE_PARENT,
2383 static struct clk_branch camss_cphy_csid3_clk = {
2386 .enable_reg = 0x373c,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "camss_cphy_csid3_clk",
2390 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2392 .ops = &clk_branch2_ops,
2393 .flags = CLK_SET_RATE_PARENT,
2398 static struct clk_branch camss_csiphy0_clk = {
2401 .enable_reg = 0x3740,
2402 .enable_mask = BIT(0),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "camss_csiphy0_clk",
2405 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2407 .ops = &clk_branch2_ops,
2408 .flags = CLK_SET_RATE_PARENT,
2413 static struct clk_branch camss_csiphy1_clk = {
2416 .enable_reg = 0x3744,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "camss_csiphy1_clk",
2420 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2422 .ops = &clk_branch2_ops,
2423 .flags = CLK_SET_RATE_PARENT,
2428 static struct clk_branch camss_csiphy2_clk = {
2431 .enable_reg = 0x3748,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "camss_csiphy2_clk",
2435 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2437 .ops = &clk_branch2_ops,
2438 .flags = CLK_SET_RATE_PARENT,
2443 static struct clk_branch fd_core_clk = {
2446 .enable_reg = 0x3b68,
2447 .enable_mask = BIT(0),
2448 .hw.init = &(struct clk_init_data){
2449 .name = "fd_core_clk",
2450 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2452 .ops = &clk_branch2_ops,
2453 .flags = CLK_SET_RATE_PARENT,
2458 static struct clk_branch fd_core_uar_clk = {
2461 .enable_reg = 0x3b6c,
2462 .enable_mask = BIT(0),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "fd_core_uar_clk",
2465 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2467 .ops = &clk_branch2_ops,
2468 .flags = CLK_SET_RATE_PARENT,
2473 static struct clk_branch fd_ahb_clk = {
2476 .enable_reg = 0x3b74,
2477 .enable_mask = BIT(0),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "fd_ahb_clk",
2480 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2482 .ops = &clk_branch2_ops,
2483 .flags = CLK_SET_RATE_PARENT,
2488 static struct clk_branch mnoc_ahb_clk = {
2490 .halt_check = BRANCH_HALT_SKIP,
2492 .enable_reg = 0x5024,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mnoc_ahb_clk",
2496 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2498 .ops = &clk_branch2_ops,
2499 .flags = CLK_SET_RATE_PARENT,
2504 static struct clk_branch bimc_smmu_ahb_clk = {
2506 .halt_check = BRANCH_HALT_SKIP,
2510 .enable_reg = 0xe004,
2511 .enable_mask = BIT(0),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "bimc_smmu_ahb_clk",
2514 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2516 .ops = &clk_branch2_ops,
2517 .flags = CLK_SET_RATE_PARENT,
2522 static struct clk_branch bimc_smmu_axi_clk = {
2524 .halt_check = BRANCH_HALT_SKIP,
2528 .enable_reg = 0xe008,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "bimc_smmu_axi_clk",
2532 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2534 .ops = &clk_branch2_ops,
2539 static struct clk_branch mnoc_maxi_clk = {
2542 .enable_reg = 0xf004,
2543 .enable_mask = BIT(0),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "mnoc_maxi_clk",
2546 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2548 .ops = &clk_branch2_ops,
2549 .flags = CLK_SET_RATE_PARENT,
2554 static struct clk_branch vmem_maxi_clk = {
2557 .enable_reg = 0xf064,
2558 .enable_mask = BIT(0),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "vmem_maxi_clk",
2561 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2563 .ops = &clk_branch2_ops,
2564 .flags = CLK_SET_RATE_PARENT,
2569 static struct clk_branch vmem_ahb_clk = {
2572 .enable_reg = 0xf068,
2573 .enable_mask = BIT(0),
2574 .hw.init = &(struct clk_init_data){
2575 .name = "vmem_ahb_clk",
2576 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2578 .ops = &clk_branch2_ops,
2579 .flags = CLK_SET_RATE_PARENT,
2584 static struct clk_hw *mmcc_msm8998_hws[] = {
2588 static struct gdsc video_top_gdsc = {
2591 .name = "video_top",
2593 .pwrsts = PWRSTS_OFF_ON,
2596 static struct gdsc video_subcore0_gdsc = {
2599 .name = "video_subcore0",
2601 .parent = &video_top_gdsc.pd,
2602 .pwrsts = PWRSTS_OFF_ON,
2605 static struct gdsc video_subcore1_gdsc = {
2608 .name = "video_subcore1",
2610 .parent = &video_top_gdsc.pd,
2611 .pwrsts = PWRSTS_OFF_ON,
2614 static struct gdsc mdss_gdsc = {
2616 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2621 .pwrsts = PWRSTS_OFF_ON,
2624 static struct gdsc camss_top_gdsc = {
2626 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2630 .name = "camss_top",
2632 .pwrsts = PWRSTS_OFF_ON,
2635 static struct gdsc camss_vfe0_gdsc = {
2638 .name = "camss_vfe0",
2640 .parent = &camss_top_gdsc.pd,
2641 .pwrsts = PWRSTS_OFF_ON,
2644 static struct gdsc camss_vfe1_gdsc = {
2647 .name = "camss_vfe1_gdsc",
2649 .parent = &camss_top_gdsc.pd,
2650 .pwrsts = PWRSTS_OFF_ON,
2653 static struct gdsc camss_cpp_gdsc = {
2656 .name = "camss_cpp",
2658 .parent = &camss_top_gdsc.pd,
2659 .pwrsts = PWRSTS_OFF_ON,
2662 static struct gdsc bimc_smmu_gdsc = {
2664 .gds_hw_ctrl = 0xe024,
2665 .cxcs = (unsigned int []){ 0xe008 },
2668 .name = "bimc_smmu",
2670 .pwrsts = PWRSTS_OFF_ON,
2674 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2675 [MMPLL0] = &mmpll0.clkr,
2676 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2677 [MMPLL1] = &mmpll1.clkr,
2678 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2679 [MMPLL3] = &mmpll3.clkr,
2680 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2681 [MMPLL4] = &mmpll4.clkr,
2682 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2683 [MMPLL5] = &mmpll5.clkr,
2684 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2685 [MMPLL6] = &mmpll6.clkr,
2686 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2687 [MMPLL7] = &mmpll7.clkr,
2688 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2689 [MMPLL10] = &mmpll10.clkr,
2690 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2691 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2692 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2693 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2694 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2695 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2696 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2697 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2698 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2699 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2700 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2701 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2702 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2703 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2704 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2705 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2706 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2707 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2708 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2709 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2710 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2711 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2712 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2713 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2714 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2715 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2716 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2717 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2718 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2719 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2720 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2721 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2722 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2723 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2724 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2725 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2726 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2727 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2728 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2729 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2730 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2731 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2732 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2733 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2734 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2735 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2736 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2737 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2738 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2739 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2740 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2741 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2742 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2743 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2744 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2745 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2746 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2747 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2748 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2749 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2750 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2751 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2752 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2753 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2754 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2755 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2756 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2757 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2758 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2759 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2760 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2761 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2762 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2763 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2764 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2765 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2766 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2767 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2768 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2769 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2770 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2771 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2772 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2773 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2774 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2775 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2776 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2777 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2778 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2779 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2780 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2781 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2782 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2783 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2784 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2785 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2786 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2787 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2788 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2789 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2790 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2791 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2792 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2793 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2794 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2795 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2796 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2797 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2798 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2799 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2800 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2801 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2802 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2803 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2804 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2805 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2806 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2807 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2808 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2809 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2810 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2811 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2812 [FD_CORE_CLK] = &fd_core_clk.clkr,
2813 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2814 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2815 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2816 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2817 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2818 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2819 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2820 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2823 static struct gdsc *mmcc_msm8998_gdscs[] = {
2824 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2825 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2826 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2827 [MDSS_GDSC] = &mdss_gdsc,
2828 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2829 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2830 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2831 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2832 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2835 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2836 [SPDM_BCR] = { 0x200 },
2837 [SPDM_RM_BCR] = { 0x300 },
2838 [MISC_BCR] = { 0x320 },
2839 [VIDEO_TOP_BCR] = { 0x1020 },
2840 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2841 [MDSS_BCR] = { 0x2300 },
2842 [THROTTLE_MDSS_BCR] = { 0x2460 },
2843 [CAMSS_PHY0_BCR] = { 0x3020 },
2844 [CAMSS_PHY1_BCR] = { 0x3050 },
2845 [CAMSS_PHY2_BCR] = { 0x3080 },
2846 [CAMSS_CSI0_BCR] = { 0x30b0 },
2847 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2848 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2849 [CAMSS_CSI1_BCR] = { 0x3120 },
2850 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2851 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2852 [CAMSS_CSI2_BCR] = { 0x3180 },
2853 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2854 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2855 [CAMSS_CSI3_BCR] = { 0x31e0 },
2856 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2857 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2858 [CAMSS_ISPIF_BCR] = { 0x3220 },
2859 [CAMSS_CCI_BCR] = { 0x3340 },
2860 [CAMSS_TOP_BCR] = { 0x3480 },
2861 [CAMSS_AHB_BCR] = { 0x3488 },
2862 [CAMSS_MICRO_BCR] = { 0x3490 },
2863 [CAMSS_JPEG_BCR] = { 0x35a0 },
2864 [CAMSS_VFE0_BCR] = { 0x3660 },
2865 [CAMSS_VFE1_BCR] = { 0x3670 },
2866 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2867 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2868 [CAMSS_CPP_BCR] = { 0x36d0 },
2869 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2870 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2871 [CAMSS_FD_BCR] = { 0x3b60 },
2872 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2873 [MNOCAHB_BCR] = { 0x5020 },
2874 [MNOCAXI_BCR] = { 0xd020 },
2875 [BMIC_SMMU_BCR] = { 0xe000 },
2876 [MNOC_MAXI_BCR] = { 0xf000 },
2877 [VMEM_BCR] = { 0xf060 },
2878 [BTO_BCR] = { 0x10004 },
2881 static const struct regmap_config mmcc_msm8998_regmap_config = {
2885 .max_register = 0x10004,
2889 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2890 .config = &mmcc_msm8998_regmap_config,
2891 .clks = mmcc_msm8998_clocks,
2892 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2893 .resets = mmcc_msm8998_resets,
2894 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2895 .gdscs = mmcc_msm8998_gdscs,
2896 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2897 .clk_hws = mmcc_msm8998_hws,
2898 .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
2901 static const struct of_device_id mmcc_msm8998_match_table[] = {
2902 { .compatible = "qcom,mmcc-msm8998" },
2905 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2907 static int mmcc_msm8998_probe(struct platform_device *pdev)
2909 struct regmap *regmap;
2911 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2913 return PTR_ERR(regmap);
2915 return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2918 static struct platform_driver mmcc_msm8998_driver = {
2919 .probe = mmcc_msm8998_probe,
2921 .name = "mmcc-msm8998",
2922 .of_match_table = mmcc_msm8998_match_table,
2925 module_platform_driver(mmcc_msm8998_driver);
2927 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2928 MODULE_LICENSE("GPL v2");