drivers/clk/qcom/mmcc-msm8996.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*x
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/clk.h>
  17
  18 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-regmap-divider.h"
  23 #include "clk-alpha-pll.h"
  24 #include "clk-rcg.h"
  25 #include "clk-branch.h"
  26 #include "reset.h"
  27 #include "gdsc.h"
  28
  29 enum {
  30         P_XO,
  31         P_MMPLL0,
  32         P_GPLL0,
  33         P_GPLL0_DIV,
  34         P_MMPLL1,
  35         P_MMPLL9,
  36         P_MMPLL2,
  37         P_MMPLL8,
  38         P_MMPLL3,
  39         P_DSI0PLL,
  40         P_DSI1PLL,
  41         P_MMPLL5,
  42         P_HDMIPLL,
  43         P_DSI0PLL_BYTE,
  44         P_DSI1PLL_BYTE,
  45         P_MMPLL4,
  46 };
  47
  48 static struct clk_fixed_factor gpll0_div = {
  49         .mult = 1,
  50         .div = 2,
  51         .hw.init = &(struct clk_init_data){
  52                 .name = "gpll0_div",
  53                 .parent_data = (const struct clk_parent_data[]){
  54                         { .fw_name = "gpll0", .name = "gpll0" },
  55                 },
  56                 .num_parents = 1,
  57                 .ops = &clk_fixed_factor_ops,
  58         },
  59 };
  60
  61 static struct pll_vco mmpll_p_vco[] = {
  62         { 250000000, 500000000, 3 },
  63         { 500000000, 1000000000, 2 },
  64         { 1000000000, 1500000000, 1 },
  65         { 1500000000, 2000000000, 0 },
  66 };
  67
  68 static struct pll_vco mmpll_gfx_vco[] = {
  69         { 400000000, 1000000000, 2 },
  70         { 1000000000, 1500000000, 1 },
  71         { 1500000000, 2000000000, 0 },
  72 };
  73
  74 static struct pll_vco mmpll_t_vco[] = {
  75         { 500000000, 1500000000, 0 },
  76 };
  77
  78 static struct clk_alpha_pll mmpll0_early = {
  79         .offset = 0x0,
  80         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  81         .vco_table = mmpll_p_vco,
  82         .num_vco = ARRAY_SIZE(mmpll_p_vco),
  83         .clkr = {
  84                 .enable_reg = 0x100,
  85                 .enable_mask = BIT(0),
  86                 .hw.init = &(struct clk_init_data){
  87                         .name = "mmpll0_early",
  88                         .parent_data = (const struct clk_parent_data[]){
  89                                 { .fw_name = "xo", .name = "xo_board" },
  90                         },
  91                         .num_parents = 1,
  92                         .ops = &clk_alpha_pll_ops,
  93                 },
  94         },
  95 };
  96
  97 static struct clk_alpha_pll_postdiv mmpll0 = {
  98         .offset = 0x0,
  99         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 100         .width = 4,
 101         .clkr.hw.init = &(struct clk_init_data){
 102                 .name = "mmpll0",
 103                 .parent_hws = (const struct clk_hw*[]){
 104                         &mmpll0_early.clkr.hw
 105                 },
 106                 .num_parents = 1,
 107                 .ops = &clk_alpha_pll_postdiv_ops,
 108                 .flags = CLK_SET_RATE_PARENT,
 109         },
 110 };
 111
 112 static struct clk_alpha_pll mmpll1_early = {
 113         .offset = 0x30,
 114         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 115         .vco_table = mmpll_p_vco,
 116         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 117         .clkr = {
 118                 .enable_reg = 0x100,
 119                 .enable_mask = BIT(1),
 120                 .hw.init = &(struct clk_init_data){
 121                         .name = "mmpll1_early",
 122                         .parent_data = (const struct clk_parent_data[]){
 123                                 { .fw_name = "xo", .name = "xo_board" },
 124                         },
 125                         .num_parents = 1,
 126                         .ops = &clk_alpha_pll_ops,
 127                 }
 128         },
 129 };
 130
 131 static struct clk_alpha_pll_postdiv mmpll1 = {
 132         .offset = 0x30,
 133         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 134         .width = 4,
 135         .clkr.hw.init = &(struct clk_init_data){
 136                 .name = "mmpll1",
 137                 .parent_hws = (const struct clk_hw*[]){
 138                         &mmpll1_early.clkr.hw
 139                 },
 140                 .num_parents = 1,
 141                 .ops = &clk_alpha_pll_postdiv_ops,
 142                 .flags = CLK_SET_RATE_PARENT,
 143         },
 144 };
 145
 146 static struct clk_alpha_pll mmpll2_early = {
 147         .offset = 0x4100,
 148         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 149         .vco_table = mmpll_gfx_vco,
 150         .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 151         .clkr.hw.init = &(struct clk_init_data){
 152                 .name = "mmpll2_early",
 153                 .parent_data = (const struct clk_parent_data[]){
 154                         { .fw_name = "xo", .name = "xo_board" },
 155                 },
 156                 .num_parents = 1,
 157                 .ops = &clk_alpha_pll_ops,
 158         },
 159 };
 160
 161 static struct clk_alpha_pll_postdiv mmpll2 = {
 162         .offset = 0x4100,
 163         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 164         .width = 4,
 165         .clkr.hw.init = &(struct clk_init_data){
 166                 .name = "mmpll2",
 167                 .parent_hws = (const struct clk_hw*[]){
 168                         &mmpll2_early.clkr.hw
 169                 },
 170                 .num_parents = 1,
 171                 .ops = &clk_alpha_pll_postdiv_ops,
 172                 .flags = CLK_SET_RATE_PARENT,
 173         },
 174 };
 175
 176 static struct clk_alpha_pll mmpll3_early = {
 177         .offset = 0x60,
 178         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 179         .vco_table = mmpll_p_vco,
 180         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 181         .clkr.hw.init = &(struct clk_init_data){
 182                 .name = "mmpll3_early",
 183                 .parent_data = (const struct clk_parent_data[]){
 184                         { .fw_name = "xo", .name = "xo_board" },
 185                 },
 186                 .num_parents = 1,
 187                 .ops = &clk_alpha_pll_ops,
 188         },
 189 };
 190
 191 static struct clk_alpha_pll_postdiv mmpll3 = {
 192         .offset = 0x60,
 193         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 194         .width = 4,
 195         .clkr.hw.init = &(struct clk_init_data){
 196                 .name = "mmpll3",
 197                 .parent_hws = (const struct clk_hw*[]){
 198                         &mmpll3_early.clkr.hw
 199                 },
 200                 .num_parents = 1,
 201                 .ops = &clk_alpha_pll_postdiv_ops,
 202                 .flags = CLK_SET_RATE_PARENT,
 203         },
 204 };
 205
 206 static struct clk_alpha_pll mmpll4_early = {
 207         .offset = 0x90,
 208         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 209         .vco_table = mmpll_t_vco,
 210         .num_vco = ARRAY_SIZE(mmpll_t_vco),
 211         .clkr.hw.init = &(struct clk_init_data){
 212                 .name = "mmpll4_early",
 213                 .parent_data = (const struct clk_parent_data[]){
 214                         { .fw_name = "xo", .name = "xo_board" },
 215                 },
 216                 .num_parents = 1,
 217                 .ops = &clk_alpha_pll_ops,
 218         },
 219 };
 220
 221 static struct clk_alpha_pll_postdiv mmpll4 = {
 222         .offset = 0x90,
 223         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 224         .width = 2,
 225         .clkr.hw.init = &(struct clk_init_data){
 226                 .name = "mmpll4",
 227                 .parent_hws = (const struct clk_hw*[]){
 228                         &mmpll4_early.clkr.hw
 229                 },
 230                 .num_parents = 1,
 231                 .ops = &clk_alpha_pll_postdiv_ops,
 232                 .flags = CLK_SET_RATE_PARENT,
 233         },
 234 };
 235
 236 static struct clk_alpha_pll mmpll5_early = {
 237         .offset = 0xc0,
 238         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 239         .vco_table = mmpll_p_vco,
 240         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 241         .clkr.hw.init = &(struct clk_init_data){
 242                 .name = "mmpll5_early",
 243                 .parent_data = (const struct clk_parent_data[]){
 244                         { .fw_name = "xo", .name = "xo_board" },
 245                 },
 246                 .num_parents = 1,
 247                 .ops = &clk_alpha_pll_ops,
 248         },
 249 };
 250
 251 static struct clk_alpha_pll_postdiv mmpll5 = {
 252         .offset = 0xc0,
 253         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 254         .width = 4,
 255         .clkr.hw.init = &(struct clk_init_data){
 256                 .name = "mmpll5",
 257                 .parent_hws = (const struct clk_hw*[]){
 258                         &mmpll5_early.clkr.hw
 259                 },
 260                 .num_parents = 1,
 261                 .ops = &clk_alpha_pll_postdiv_ops,
 262                 .flags = CLK_SET_RATE_PARENT,
 263         },
 264 };
 265
 266 static struct clk_alpha_pll mmpll8_early = {
 267         .offset = 0x4130,
 268         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 269         .vco_table = mmpll_gfx_vco,
 270         .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 271         .clkr.hw.init = &(struct clk_init_data){
 272                 .name = "mmpll8_early",
 273                 .parent_data = (const struct clk_parent_data[]){
 274                         { .fw_name = "xo", .name = "xo_board" },
 275                 },
 276                 .num_parents = 1,
 277                 .ops = &clk_alpha_pll_ops,
 278         },
 279 };
 280
 281 static struct clk_alpha_pll_postdiv mmpll8 = {
 282         .offset = 0x4130,
 283         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 284         .width = 4,
 285         .clkr.hw.init = &(struct clk_init_data){
 286                 .name = "mmpll8",
 287                 .parent_hws = (const struct clk_hw*[]){
 288                         &mmpll8_early.clkr.hw
 289                 },
 290                 .num_parents = 1,
 291                 .ops = &clk_alpha_pll_postdiv_ops,
 292                 .flags = CLK_SET_RATE_PARENT,
 293         },
 294 };
 295
 296 static struct clk_alpha_pll mmpll9_early = {
 297         .offset = 0x4200,
 298         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 299         .vco_table = mmpll_t_vco,
 300         .num_vco = ARRAY_SIZE(mmpll_t_vco),
 301         .clkr.hw.init = &(struct clk_init_data){
 302                 .name = "mmpll9_early",
 303                 .parent_data = (const struct clk_parent_data[]){
 304                         { .fw_name = "xo", .name = "xo_board" },
 305                 },
 306                 .num_parents = 1,
 307                 .ops = &clk_alpha_pll_ops,
 308         },
 309 };
 310
 311 static struct clk_alpha_pll_postdiv mmpll9 = {
 312         .offset = 0x4200,
 313         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 314         .width = 2,
 315         .clkr.hw.init = &(struct clk_init_data){
 316                 .name = "mmpll9",
 317                 .parent_hws = (const struct clk_hw*[]){
 318                         &mmpll9_early.clkr.hw
 319                 },
 320                 .num_parents = 1,
 321                 .ops = &clk_alpha_pll_postdiv_ops,
 322                 .flags = CLK_SET_RATE_PARENT,
 323         },
 324 };
 325
 326 static const struct parent_map mmss_xo_hdmi_map[] = {
 327         { P_XO, 0 },
 328         { P_HDMIPLL, 1 }
 329 };
 330
 331 static const struct clk_parent_data mmss_xo_hdmi[] = {
 332         { .fw_name = "xo", .name = "xo_board" },
 333         { .fw_name = "hdmipll", .name = "hdmipll" }
 334 };
 335
 336 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
 337         { P_XO, 0 },
 338         { P_DSI0PLL, 1 },
 339         { P_DSI1PLL, 2 }
 340 };
 341
 342 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
 343         { .fw_name = "xo", .name = "xo_board" },
 344         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 345         { .fw_name = "dsi1pll", .name = "dsi1pll" }
 346 };
 347
 348 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
 349         { P_XO, 0 },
 350         { P_GPLL0, 5 },
 351         { P_GPLL0_DIV, 6 }
 352 };
 353
 354 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
 355         { .fw_name = "xo", .name = "xo_board" },
 356         { .fw_name = "gpll0", .name = "gpll0" },
 357         { .hw = &gpll0_div.hw }
 358 };
 359
 360 static const struct parent_map mmss_xo_dsibyte_map[] = {
 361         { P_XO, 0 },
 362         { P_DSI0PLL_BYTE, 1 },
 363         { P_DSI1PLL_BYTE, 2 }
 364 };
 365
 366 static const struct clk_parent_data mmss_xo_dsibyte[] = {
 367         { .fw_name = "xo", .name = "xo_board" },
 368         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 369         { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }
 370 };
 371
 372 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
 373         { P_XO, 0 },
 374         { P_MMPLL0, 1 },
 375         { P_GPLL0, 5 },
 376         { P_GPLL0_DIV, 6 }
 377 };
 378
 379 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
 380         { .fw_name = "xo", .name = "xo_board" },
 381         { .hw = &mmpll0.clkr.hw },
 382         { .fw_name = "gpll0", .name = "gpll0" },
 383         { .hw = &gpll0_div.hw }
 384 };
 385
 386 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
 387         { P_XO, 0 },
 388         { P_MMPLL0, 1 },
 389         { P_MMPLL1, 2 },
 390         { P_GPLL0, 5 },
 391         { P_GPLL0_DIV, 6 }
 392 };
 393
 394 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
 395         { .fw_name = "xo", .name = "xo_board" },
 396         { .hw = &mmpll0.clkr.hw },
 397         { .hw = &mmpll1.clkr.hw },
 398         { .fw_name = "gpll0", .name = "gpll0" },
 399         { .hw = &gpll0_div.hw }
 400 };
 401
 402 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
 403         { P_XO, 0 },
 404         { P_MMPLL0, 1 },
 405         { P_MMPLL3, 3 },
 406         { P_GPLL0, 5 },
 407         { P_GPLL0_DIV, 6 }
 408 };
 409
 410 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
 411         { .fw_name = "xo", .name = "xo_board" },
 412         { .hw = &mmpll0.clkr.hw },
 413         { .hw = &mmpll3.clkr.hw },
 414         { .fw_name = "gpll0", .name = "gpll0" },
 415         { .hw = &gpll0_div.hw }
 416 };
 417
 418 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
 419         { P_XO, 0 },
 420         { P_MMPLL0, 1 },
 421         { P_MMPLL5, 2 },
 422         { P_GPLL0, 5 },
 423         { P_GPLL0_DIV, 6 }
 424 };
 425
 426 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
 427         { .fw_name = "xo", .name = "xo_board" },
 428         { .hw = &mmpll0.clkr.hw },
 429         { .hw = &mmpll5.clkr.hw },
 430         { .fw_name = "gpll0", .name = "gpll0" },
 431         { .hw = &gpll0_div.hw }
 432 };
 433
 434 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
 435         { P_XO, 0 },
 436         { P_MMPLL0, 1 },
 437         { P_MMPLL4, 3 },
 438         { P_GPLL0, 5 },
 439         { P_GPLL0_DIV, 6 }
 440 };
 441
 442 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
 443         { .fw_name = "xo", .name = "xo_board" },
 444         { .hw = &mmpll0.clkr.hw },
 445         { .hw = &mmpll4.clkr.hw },
 446         { .fw_name = "gpll0", .name = "gpll0" },
 447         { .hw = &gpll0_div.hw }
 448 };
 449
 450 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
 451         { P_XO, 0 },
 452         { P_MMPLL0, 1 },
 453         { P_MMPLL9, 2 },
 454         { P_MMPLL2, 3 },
 455         { P_MMPLL8, 4 },
 456         { P_GPLL0, 5 }
 457 };
 458
 459 static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
 460         { .fw_name = "xo", .name = "xo_board" },
 461         { .hw = &mmpll0.clkr.hw },
 462         { .hw = &mmpll9.clkr.hw },
 463         { .hw = &mmpll2.clkr.hw },
 464         { .hw = &mmpll8.clkr.hw },
 465         { .fw_name = "gpll0", .name = "gpll0" },
 466 };
 467
 468 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
 469         { P_XO, 0 },
 470         { P_MMPLL0, 1 },
 471         { P_MMPLL9, 2 },
 472         { P_MMPLL2, 3 },
 473         { P_MMPLL8, 4 },
 474         { P_GPLL0, 5 },
 475         { P_GPLL0_DIV, 6 }
 476 };
 477
 478 static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
 479         { .fw_name = "xo", .name = "xo_board" },
 480         { .hw = &mmpll0.clkr.hw },
 481         { .hw = &mmpll9.clkr.hw },
 482         { .hw = &mmpll2.clkr.hw },
 483         { .hw = &mmpll8.clkr.hw },
 484         { .fw_name = "gpll0", .name = "gpll0" },
 485         { .hw = &gpll0_div.hw }
 486 };
 487
 488 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
 489         { P_XO, 0 },
 490         { P_MMPLL0, 1 },
 491         { P_MMPLL1, 2 },
 492         { P_MMPLL4, 3 },
 493         { P_MMPLL3, 4 },
 494         { P_GPLL0, 5 },
 495         { P_GPLL0_DIV, 6 }
 496 };
 497
 498 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
 499         { .fw_name = "xo", .name = "xo_board" },
 500         { .hw = &mmpll0.clkr.hw },
 501         { .hw = &mmpll1.clkr.hw },
 502         { .hw = &mmpll4.clkr.hw },
 503         { .hw = &mmpll3.clkr.hw },
 504         { .fw_name = "gpll0", .name = "gpll0" },
 505         { .hw = &gpll0_div.hw }
 506 };
 507
 508 static const struct freq_tbl ftbl_ahb_clk_src[] = {
 509         F(19200000, P_XO, 1, 0, 0),
 510         F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
 511         F(80000000, P_MMPLL0, 10, 0, 0),
 512         { }
 513 };
 514
 515 static struct clk_rcg2 ahb_clk_src = {
 516         .cmd_rcgr = 0x5000,
 517         .hid_width = 5,
 518         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 519         .freq_tbl = ftbl_ahb_clk_src,
 520         .clkr.hw.init = &(struct clk_init_data){
 521                 .name = "ahb_clk_src",
 522                 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 523                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 524                 .ops = &clk_rcg2_ops,
 525         },
 526 };
 527
 528 static const struct freq_tbl ftbl_axi_clk_src[] = {
 529         F(19200000, P_XO, 1, 0, 0),
 530         F(75000000, P_GPLL0_DIV, 4, 0, 0),
 531         F(100000000, P_GPLL0, 6, 0, 0),
 532         F(171430000, P_GPLL0, 3.5, 0, 0),
 533         F(200000000, P_GPLL0, 3, 0, 0),
 534         F(320000000, P_MMPLL0, 2.5, 0, 0),
 535         F(400000000, P_MMPLL0, 2, 0, 0),
 536         { }
 537 };
 538
 539 static struct clk_rcg2 axi_clk_src = {
 540         .cmd_rcgr = 0x5040,
 541         .hid_width = 5,
 542         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 543         .freq_tbl = ftbl_axi_clk_src,
 544         .clkr.hw.init = &(struct clk_init_data){
 545                 .name = "axi_clk_src",
 546                 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 547                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
 548                 .ops = &clk_rcg2_ops,
 549         },
 550 };
 551
 552 static struct clk_rcg2 maxi_clk_src = {
 553         .cmd_rcgr = 0x5090,
 554         .hid_width = 5,
 555         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 556         .freq_tbl = ftbl_axi_clk_src,
 557         .clkr.hw.init = &(struct clk_init_data){
 558                 .name = "maxi_clk_src",
 559                 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 560                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
 561                 .ops = &clk_rcg2_ops,
 562         },
 563 };
 564
 565 static struct clk_rcg2_gfx3d gfx3d_clk_src = {
 566         .rcg = {
 567                 .cmd_rcgr = 0x4000,
 568                 .hid_width = 5,
 569                 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
 570                 .clkr.hw.init = &(struct clk_init_data){
 571                         .name = "gfx3d_clk_src",
 572                         .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
 573                         .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0),
 574                         .ops = &clk_gfx3d_ops,
 575                         .flags = CLK_SET_RATE_PARENT,
 576                 },
 577         },
 578         .hws = (struct clk_hw*[]) {
 579                 &mmpll9.clkr.hw,
 580                 &mmpll2.clkr.hw,
 581                 &mmpll8.clkr.hw
 582         },
 583 };
 584
 585 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
 586         F(19200000, P_XO, 1, 0, 0),
 587         { }
 588 };
 589
 590 static struct clk_rcg2 rbbmtimer_clk_src = {
 591         .cmd_rcgr = 0x4090,
 592         .hid_width = 5,
 593         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 594         .freq_tbl = ftbl_rbbmtimer_clk_src,
 595         .clkr.hw.init = &(struct clk_init_data){
 596                 .name = "rbbmtimer_clk_src",
 597                 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 598                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 599                 .ops = &clk_rcg2_ops,
 600         },
 601 };
 602
 603 static struct clk_rcg2 isense_clk_src = {
 604         .cmd_rcgr = 0x4010,
 605         .hid_width = 5,
 606         .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "isense_clk_src",
 609                 .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
 610                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div),
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
 616         F(19200000, P_XO, 1, 0, 0),
 617         F(50000000, P_GPLL0, 12, 0, 0),
 618         { }
 619 };
 620
 621 static struct clk_rcg2 rbcpr_clk_src = {
 622         .cmd_rcgr = 0x4060,
 623         .hid_width = 5,
 624         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 625         .freq_tbl = ftbl_rbcpr_clk_src,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "rbcpr_clk_src",
 628                 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 629                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static const struct freq_tbl ftbl_video_core_clk_src[] = {
 635         F(75000000, P_GPLL0_DIV, 4, 0, 0),
 636         F(150000000, P_GPLL0, 4, 0, 0),
 637         F(346666667, P_MMPLL3, 3, 0, 0),
 638         F(520000000, P_MMPLL3, 2, 0, 0),
 639         { }
 640 };
 641
 642 static struct clk_rcg2 video_core_clk_src = {
 643         .cmd_rcgr = 0x1000,
 644         .mnd_width = 8,
 645         .hid_width = 5,
 646         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 647         .freq_tbl = ftbl_video_core_clk_src,
 648         .clkr.hw.init = &(struct clk_init_data){
 649                 .name = "video_core_clk_src",
 650                 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 651                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 652                 .ops = &clk_rcg2_ops,
 653         },
 654 };
 655
 656 static struct clk_rcg2 video_subcore0_clk_src = {
 657         .cmd_rcgr = 0x1060,
 658         .mnd_width = 8,
 659         .hid_width = 5,
 660         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 661         .freq_tbl = ftbl_video_core_clk_src,
 662         .clkr.hw.init = &(struct clk_init_data){
 663                 .name = "video_subcore0_clk_src",
 664                 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 665                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 666                 .ops = &clk_rcg2_ops,
 667         },
 668 };
 669
 670 static struct clk_rcg2 video_subcore1_clk_src = {
 671         .cmd_rcgr = 0x1080,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 675         .freq_tbl = ftbl_video_core_clk_src,
 676         .clkr.hw.init = &(struct clk_init_data){
 677                 .name = "video_subcore1_clk_src",
 678                 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 679                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 680                 .ops = &clk_rcg2_ops,
 681         },
 682 };
 683
 684 static struct clk_rcg2 pclk0_clk_src = {
 685         .cmd_rcgr = 0x2000,
 686         .mnd_width = 8,
 687         .hid_width = 5,
 688         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 689         .clkr.hw.init = &(struct clk_init_data){
 690                 .name = "pclk0_clk_src",
 691                 .parent_data = mmss_xo_dsi0pll_dsi1pll,
 692                 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
 693                 .ops = &clk_pixel_ops,
 694                 .flags = CLK_SET_RATE_PARENT,
 695         },
 696 };
 697
 698 static struct clk_rcg2 pclk1_clk_src = {
 699         .cmd_rcgr = 0x2020,
 700         .mnd_width = 8,
 701         .hid_width = 5,
 702         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 703         .clkr.hw.init = &(struct clk_init_data){
 704                 .name = "pclk1_clk_src",
 705                 .parent_data = mmss_xo_dsi0pll_dsi1pll,
 706                 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
 707                 .ops = &clk_pixel_ops,
 708                 .flags = CLK_SET_RATE_PARENT,
 709         },
 710 };
 711
 712 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 713         F(85714286, P_GPLL0, 7, 0, 0),
 714         F(100000000, P_GPLL0, 6, 0, 0),
 715         F(150000000, P_GPLL0, 4, 0, 0),
 716         F(171428571, P_GPLL0, 3.5, 0, 0),
 717         F(200000000, P_GPLL0, 3, 0, 0),
 718         F(275000000, P_MMPLL5, 3, 0, 0),
 719         F(300000000, P_GPLL0, 2, 0, 0),
 720         F(330000000, P_MMPLL5, 2.5, 0, 0),
 721         F(412500000, P_MMPLL5, 2, 0, 0),
 722         { }
 723 };
 724
 725 static struct clk_rcg2 mdp_clk_src = {
 726         .cmd_rcgr = 0x2040,
 727         .hid_width = 5,
 728         .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
 729         .freq_tbl = ftbl_mdp_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "mdp_clk_src",
 732                 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
 733                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
 734                 .ops = &clk_rcg2_ops,
 735         },
 736 };
 737
 738 static struct freq_tbl extpclk_freq_tbl[] = {
 739         { .src = P_HDMIPLL },
 740         { }
 741 };
 742
 743 static struct clk_rcg2 extpclk_clk_src = {
 744         .cmd_rcgr = 0x2060,
 745         .hid_width = 5,
 746         .parent_map = mmss_xo_hdmi_map,
 747         .freq_tbl = extpclk_freq_tbl,
 748         .clkr.hw.init = &(struct clk_init_data){
 749                 .name = "extpclk_clk_src",
 750                 .parent_data = mmss_xo_hdmi,
 751                 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
 752                 .ops = &clk_byte_ops,
 753                 .flags = CLK_SET_RATE_PARENT,
 754         },
 755 };
 756
 757 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 758         F(19200000, P_XO, 1, 0, 0),
 759         { }
 760 };
 761
 762 static struct clk_rcg2 vsync_clk_src = {
 763         .cmd_rcgr = 0x2080,
 764         .hid_width = 5,
 765         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 766         .freq_tbl = ftbl_mdss_vsync_clk,
 767         .clkr.hw.init = &(struct clk_init_data){
 768                 .name = "vsync_clk_src",
 769                 .parent_data = mmss_xo_gpll0_gpll0_div,
 770                 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
 771                 .ops = &clk_rcg2_ops,
 772         },
 773 };
 774
 775 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 776         F(19200000, P_XO, 1, 0, 0),
 777         { }
 778 };
 779
 780 static struct clk_rcg2 hdmi_clk_src = {
 781         .cmd_rcgr = 0x2100,
 782         .hid_width = 5,
 783         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 784         .freq_tbl = ftbl_mdss_hdmi_clk,
 785         .clkr.hw.init = &(struct clk_init_data){
 786                 .name = "hdmi_clk_src",
 787                 .parent_data = mmss_xo_gpll0_gpll0_div,
 788                 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
 789                 .ops = &clk_rcg2_ops,
 790         },
 791 };
 792
 793 static struct clk_rcg2 byte0_clk_src = {
 794         .cmd_rcgr = 0x2120,
 795         .hid_width = 5,
 796         .parent_map = mmss_xo_dsibyte_map,
 797         .clkr.hw.init = &(struct clk_init_data){
 798                 .name = "byte0_clk_src",
 799                 .parent_data = mmss_xo_dsibyte,
 800                 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 801                 .ops = &clk_byte2_ops,
 802                 .flags = CLK_SET_RATE_PARENT,
 803         },
 804 };
 805
 806 static struct clk_rcg2 byte1_clk_src = {
 807         .cmd_rcgr = 0x2140,
 808         .hid_width = 5,
 809         .parent_map = mmss_xo_dsibyte_map,
 810         .clkr.hw.init = &(struct clk_init_data){
 811                 .name = "byte1_clk_src",
 812                 .parent_data = mmss_xo_dsibyte,
 813                 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 814                 .ops = &clk_byte2_ops,
 815                 .flags = CLK_SET_RATE_PARENT,
 816         },
 817 };
 818
 819 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 820         F(19200000, P_XO, 1, 0, 0),
 821         { }
 822 };
 823
 824 static struct clk_rcg2 esc0_clk_src = {
 825         .cmd_rcgr = 0x2160,
 826         .hid_width = 5,
 827         .parent_map = mmss_xo_dsibyte_map,
 828         .freq_tbl = ftbl_mdss_esc0_1_clk,
 829         .clkr.hw.init = &(struct clk_init_data){
 830                 .name = "esc0_clk_src",
 831                 .parent_data = mmss_xo_dsibyte,
 832                 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 833                 .ops = &clk_rcg2_ops,
 834         },
 835 };
 836
 837 static struct clk_rcg2 esc1_clk_src = {
 838         .cmd_rcgr = 0x2180,
 839         .hid_width = 5,
 840         .parent_map = mmss_xo_dsibyte_map,
 841         .freq_tbl = ftbl_mdss_esc0_1_clk,
 842         .clkr.hw.init = &(struct clk_init_data){
 843                 .name = "esc1_clk_src",
 844                 .parent_data = mmss_xo_dsibyte,
 845                 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 846                 .ops = &clk_rcg2_ops,
 847         },
 848 };
 849
 850 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
 851         F(10000, P_XO, 16, 1, 120),
 852         F(24000, P_XO, 16, 1, 50),
 853         F(6000000, P_GPLL0_DIV, 10, 1, 5),
 854         F(12000000, P_GPLL0_DIV, 1, 1, 25),
 855         F(13000000, P_GPLL0_DIV, 2, 13, 150),
 856         F(24000000, P_GPLL0_DIV, 1, 2, 25),
 857         { }
 858 };
 859
 860 static struct clk_rcg2 camss_gp0_clk_src = {
 861         .cmd_rcgr = 0x3420,
 862         .mnd_width = 8,
 863         .hid_width = 5,
 864         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 865         .freq_tbl = ftbl_camss_gp0_clk_src,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "camss_gp0_clk_src",
 868                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 869                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 camss_gp1_clk_src = {
 875         .cmd_rcgr = 0x3450,
 876         .mnd_width = 8,
 877         .hid_width = 5,
 878         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 879         .freq_tbl = ftbl_camss_gp0_clk_src,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "camss_gp1_clk_src",
 882                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 883                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
 889         F(4800000, P_XO, 4, 0, 0),
 890         F(6000000, P_GPLL0_DIV, 10, 1, 5),
 891         F(8000000, P_GPLL0_DIV, 1, 2, 75),
 892         F(9600000, P_XO, 2, 0, 0),
 893         F(16666667, P_GPLL0_DIV, 2, 1, 9),
 894         F(19200000, P_XO, 1, 0, 0),
 895         F(24000000, P_GPLL0_DIV, 1, 2, 25),
 896         F(33333333, P_GPLL0_DIV, 1, 1, 9),
 897         F(48000000, P_GPLL0, 1, 2, 25),
 898         F(66666667, P_GPLL0, 1, 1, 9),
 899         { }
 900 };
 901
 902 static struct clk_rcg2 mclk0_clk_src = {
 903         .cmd_rcgr = 0x3360,
 904         .mnd_width = 8,
 905         .hid_width = 5,
 906         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 907         .freq_tbl = ftbl_mclk0_clk_src,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "mclk0_clk_src",
 910                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 911                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 mclk1_clk_src = {
 917         .cmd_rcgr = 0x3390,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 921         .freq_tbl = ftbl_mclk0_clk_src,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "mclk1_clk_src",
 924                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 925                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 926                 .ops = &clk_rcg2_ops,
 927         },
 928 };
 929
 930 static struct clk_rcg2 mclk2_clk_src = {
 931         .cmd_rcgr = 0x33c0,
 932         .mnd_width = 8,
 933         .hid_width = 5,
 934         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 935         .freq_tbl = ftbl_mclk0_clk_src,
 936         .clkr.hw.init = &(struct clk_init_data){
 937                 .name = "mclk2_clk_src",
 938                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 939                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 940                 .ops = &clk_rcg2_ops,
 941         },
 942 };
 943
 944 static struct clk_rcg2 mclk3_clk_src = {
 945         .cmd_rcgr = 0x33f0,
 946         .mnd_width = 8,
 947         .hid_width = 5,
 948         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 949         .freq_tbl = ftbl_mclk0_clk_src,
 950         .clkr.hw.init = &(struct clk_init_data){
 951                 .name = "mclk3_clk_src",
 952                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 953                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 954                 .ops = &clk_rcg2_ops,
 955         },
 956 };
 957
 958 static const struct freq_tbl ftbl_cci_clk_src[] = {
 959         F(19200000, P_XO, 1, 0, 0),
 960         F(37500000, P_GPLL0, 16, 0, 0),
 961         F(50000000, P_GPLL0, 12, 0, 0),
 962         F(100000000, P_GPLL0, 6, 0, 0),
 963         { }
 964 };
 965
 966 static struct clk_rcg2 cci_clk_src = {
 967         .cmd_rcgr = 0x3300,
 968         .mnd_width = 8,
 969         .hid_width = 5,
 970         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 971         .freq_tbl = ftbl_cci_clk_src,
 972         .clkr.hw.init = &(struct clk_init_data){
 973                 .name = "cci_clk_src",
 974                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 975                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 976                 .ops = &clk_rcg2_ops,
 977         },
 978 };
 979
 980 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
 981         F(100000000, P_GPLL0_DIV, 3, 0, 0),
 982         F(200000000, P_GPLL0, 3, 0, 0),
 983         F(266666667, P_MMPLL0, 3, 0, 0),
 984         { }
 985 };
 986
 987 static struct clk_rcg2 csi0phytimer_clk_src = {
 988         .cmd_rcgr = 0x3000,
 989         .hid_width = 5,
 990         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 991         .freq_tbl = ftbl_csi0phytimer_clk_src,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "csi0phytimer_clk_src",
 994                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 995                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
 996                 .ops = &clk_rcg2_ops,
 997         },
 998 };
 999
1000 static struct clk_rcg2 csi1phytimer_clk_src = {
1001         .cmd_rcgr = 0x3030,
1002         .hid_width = 5,
1003         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1004         .freq_tbl = ftbl_csi0phytimer_clk_src,
1005         .clkr.hw.init = &(struct clk_init_data){
1006                 .name = "csi1phytimer_clk_src",
1007                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1008                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1009                 .ops = &clk_rcg2_ops,
1010         },
1011 };
1012
1013 static struct clk_rcg2 csi2phytimer_clk_src = {
1014         .cmd_rcgr = 0x3060,
1015         .hid_width = 5,
1016         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1017         .freq_tbl = ftbl_csi0phytimer_clk_src,
1018         .clkr.hw.init = &(struct clk_init_data){
1019                 .name = "csi2phytimer_clk_src",
1020                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1021                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1022                 .ops = &clk_rcg2_ops,
1023         },
1024 };
1025
1026 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
1027         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1028         F(200000000, P_GPLL0, 3, 0, 0),
1029         F(320000000, P_MMPLL4, 3, 0, 0),
1030         F(384000000, P_MMPLL4, 2.5, 0, 0),
1031         { }
1032 };
1033
1034 static struct clk_rcg2 csiphy0_3p_clk_src = {
1035         .cmd_rcgr = 0x3240,
1036         .hid_width = 5,
1037         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1038         .freq_tbl = ftbl_csiphy0_3p_clk_src,
1039         .clkr.hw.init = &(struct clk_init_data){
1040                 .name = "csiphy0_3p_clk_src",
1041                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1042                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1043                 .ops = &clk_rcg2_ops,
1044         },
1045 };
1046
1047 static struct clk_rcg2 csiphy1_3p_clk_src = {
1048         .cmd_rcgr = 0x3260,
1049         .hid_width = 5,
1050         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1051         .freq_tbl = ftbl_csiphy0_3p_clk_src,
1052         .clkr.hw.init = &(struct clk_init_data){
1053                 .name = "csiphy1_3p_clk_src",
1054                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1055                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1056                 .ops = &clk_rcg2_ops,
1057         },
1058 };
1059
1060 static struct clk_rcg2 csiphy2_3p_clk_src = {
1061         .cmd_rcgr = 0x3280,
1062         .hid_width = 5,
1063         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1064         .freq_tbl = ftbl_csiphy0_3p_clk_src,
1065         .clkr.hw.init = &(struct clk_init_data){
1066                 .name = "csiphy2_3p_clk_src",
1067                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1068                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1069                 .ops = &clk_rcg2_ops,
1070         },
1071 };
1072
1073 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1074         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1075         F(150000000, P_GPLL0, 4, 0, 0),
1076         F(228571429, P_MMPLL0, 3.5, 0, 0),
1077         F(266666667, P_MMPLL0, 3, 0, 0),
1078         F(320000000, P_MMPLL0, 2.5, 0, 0),
1079         F(480000000, P_MMPLL4, 2, 0, 0),
1080         { }
1081 };
1082
1083 static struct clk_rcg2 jpeg0_clk_src = {
1084         .cmd_rcgr = 0x3500,
1085         .hid_width = 5,
1086         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1087         .freq_tbl = ftbl_jpeg0_clk_src,
1088         .clkr.hw.init = &(struct clk_init_data){
1089                 .name = "jpeg0_clk_src",
1090                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1091                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1092                 .ops = &clk_rcg2_ops,
1093         },
1094 };
1095
1096 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1097         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1098         F(150000000, P_GPLL0, 4, 0, 0),
1099         F(228571429, P_MMPLL0, 3.5, 0, 0),
1100         F(266666667, P_MMPLL0, 3, 0, 0),
1101         F(320000000, P_MMPLL0, 2.5, 0, 0),
1102         { }
1103 };
1104
1105 static struct clk_rcg2 jpeg2_clk_src = {
1106         .cmd_rcgr = 0x3540,
1107         .hid_width = 5,
1108         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1109         .freq_tbl = ftbl_jpeg2_clk_src,
1110         .clkr.hw.init = &(struct clk_init_data){
1111                 .name = "jpeg2_clk_src",
1112                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1113                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1114                 .ops = &clk_rcg2_ops,
1115         },
1116 };
1117
1118 static struct clk_rcg2 jpeg_dma_clk_src = {
1119         .cmd_rcgr = 0x3560,
1120         .hid_width = 5,
1121         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1122         .freq_tbl = ftbl_jpeg0_clk_src,
1123         .clkr.hw.init = &(struct clk_init_data){
1124                 .name = "jpeg_dma_clk_src",
1125                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1126                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1127                 .ops = &clk_rcg2_ops,
1128         },
1129 };
1130
1131 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1132         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1133         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1134         F(300000000, P_GPLL0, 2, 0, 0),
1135         F(320000000, P_MMPLL0, 2.5, 0, 0),
1136         F(480000000, P_MMPLL4, 2, 0, 0),
1137         F(600000000, P_GPLL0, 1, 0, 0),
1138         { }
1139 };
1140
1141 static struct clk_rcg2 vfe0_clk_src = {
1142         .cmd_rcgr = 0x3600,
1143         .hid_width = 5,
1144         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1145         .freq_tbl = ftbl_vfe0_clk_src,
1146         .clkr.hw.init = &(struct clk_init_data){
1147                 .name = "vfe0_clk_src",
1148                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1149                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1150                 .ops = &clk_rcg2_ops,
1151         },
1152 };
1153
1154 static struct clk_rcg2 vfe1_clk_src = {
1155         .cmd_rcgr = 0x3620,
1156         .hid_width = 5,
1157         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1158         .freq_tbl = ftbl_vfe0_clk_src,
1159         .clkr.hw.init = &(struct clk_init_data){
1160                 .name = "vfe1_clk_src",
1161                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1162                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1163                 .ops = &clk_rcg2_ops,
1164         },
1165 };
1166
1167 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1168         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1169         F(200000000, P_GPLL0, 3, 0, 0),
1170         F(320000000, P_MMPLL0, 2.5, 0, 0),
1171         F(480000000, P_MMPLL4, 2, 0, 0),
1172         F(640000000, P_MMPLL4, 1.5, 0, 0),
1173         { }
1174 };
1175
1176 static struct clk_rcg2 cpp_clk_src = {
1177         .cmd_rcgr = 0x3640,
1178         .hid_width = 5,
1179         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1180         .freq_tbl = ftbl_cpp_clk_src,
1181         .clkr.hw.init = &(struct clk_init_data){
1182                 .name = "cpp_clk_src",
1183                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1184                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1185                 .ops = &clk_rcg2_ops,
1186         },
1187 };
1188
1189 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1190         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1191         F(200000000, P_GPLL0, 3, 0, 0),
1192         F(266666667, P_MMPLL0, 3, 0, 0),
1193         F(480000000, P_MMPLL4, 2, 0, 0),
1194         F(600000000, P_GPLL0, 1, 0, 0),
1195         { }
1196 };
1197
1198 static struct clk_rcg2 csi0_clk_src = {
1199         .cmd_rcgr = 0x3090,
1200         .hid_width = 5,
1201         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1202         .freq_tbl = ftbl_csi0_clk_src,
1203         .clkr.hw.init = &(struct clk_init_data){
1204                 .name = "csi0_clk_src",
1205                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1206                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1207                 .ops = &clk_rcg2_ops,
1208         },
1209 };
1210
1211 static struct clk_rcg2 csi1_clk_src = {
1212         .cmd_rcgr = 0x3100,
1213         .hid_width = 5,
1214         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1215         .freq_tbl = ftbl_csi0_clk_src,
1216         .clkr.hw.init = &(struct clk_init_data){
1217                 .name = "csi1_clk_src",
1218                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1219                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1220                 .ops = &clk_rcg2_ops,
1221         },
1222 };
1223
1224 static struct clk_rcg2 csi2_clk_src = {
1225         .cmd_rcgr = 0x3160,
1226         .hid_width = 5,
1227         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1228         .freq_tbl = ftbl_csi0_clk_src,
1229         .clkr.hw.init = &(struct clk_init_data){
1230                 .name = "csi2_clk_src",
1231                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1232                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1233                 .ops = &clk_rcg2_ops,
1234         },
1235 };
1236
1237 static struct clk_rcg2 csi3_clk_src = {
1238         .cmd_rcgr = 0x31c0,
1239         .hid_width = 5,
1240         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1241         .freq_tbl = ftbl_csi0_clk_src,
1242         .clkr.hw.init = &(struct clk_init_data){
1243                 .name = "csi3_clk_src",
1244                 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1245                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1246                 .ops = &clk_rcg2_ops,
1247         },
1248 };
1249
1250 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1251         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1252         F(200000000, P_GPLL0, 3, 0, 0),
1253         F(400000000, P_MMPLL0, 2, 0, 0),
1254         { }
1255 };
1256
1257 static struct clk_rcg2 fd_core_clk_src = {
1258         .cmd_rcgr = 0x3b00,
1259         .hid_width = 5,
1260         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1261         .freq_tbl = ftbl_fd_core_clk_src,
1262         .clkr.hw.init = &(struct clk_init_data){
1263                 .name = "fd_core_clk_src",
1264                 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1265                 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
1266                 .ops = &clk_rcg2_ops,
1267         },
1268 };
1269
1270 static struct clk_branch mmss_mmagic_ahb_clk = {
1271         .halt_reg = 0x5024,
1272         .clkr = {
1273                 .enable_reg = 0x5024,
1274                 .enable_mask = BIT(0),
1275                 .hw.init = &(struct clk_init_data){
1276                         .name = "mmss_mmagic_ahb_clk",
1277                         .parent_hws = (const struct clk_hw*[]){
1278                                 &ahb_clk_src.clkr.hw
1279                         },
1280                         .num_parents = 1,
1281                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1282                         .ops = &clk_branch2_ops,
1283                 },
1284         },
1285 };
1286
1287 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1288         .halt_reg = 0x5054,
1289         .clkr = {
1290                 .enable_reg = 0x5054,
1291                 .enable_mask = BIT(0),
1292                 .hw.init = &(struct clk_init_data){
1293                         .name = "mmss_mmagic_cfg_ahb_clk",
1294                         .parent_hws = (const struct clk_hw*[]){
1295                                 &ahb_clk_src.clkr.hw
1296                         },
1297                         .num_parents = 1,
1298                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1299                         .ops = &clk_branch2_ops,
1300                 },
1301         },
1302 };
1303
1304 static struct clk_branch mmss_misc_ahb_clk = {
1305         .halt_reg = 0x5018,
1306         .clkr = {
1307                 .enable_reg = 0x5018,
1308                 .enable_mask = BIT(0),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "mmss_misc_ahb_clk",
1311                         .parent_hws = (const struct clk_hw*[]){
1312                                 &ahb_clk_src.clkr.hw
1313                         },
1314                         .num_parents = 1,
1315                         .flags = CLK_SET_RATE_PARENT,
1316                         .ops = &clk_branch2_ops,
1317                 },
1318         },
1319 };
1320
1321 static struct clk_branch mmss_misc_cxo_clk = {
1322         .halt_reg = 0x5014,
1323         .clkr = {
1324                 .enable_reg = 0x5014,
1325                 .enable_mask = BIT(0),
1326                 .hw.init = &(struct clk_init_data){
1327                         .name = "mmss_misc_cxo_clk",
1328                         .parent_data = (const struct clk_parent_data[]){
1329                                 { .fw_name = "xo", .name = "xo_board" },
1330                         },
1331                         .num_parents = 1,
1332                         .ops = &clk_branch2_ops,
1333                 },
1334         },
1335 };
1336
1337 static struct clk_branch mmss_mmagic_maxi_clk = {
1338         .halt_reg = 0x5074,
1339         .clkr = {
1340                 .enable_reg = 0x5074,
1341                 .enable_mask = BIT(0),
1342                 .hw.init = &(struct clk_init_data){
1343                         .name = "mmss_mmagic_maxi_clk",
1344                         .parent_hws = (const struct clk_hw*[]){
1345                                 &maxi_clk_src.clkr.hw
1346                         },
1347                         .num_parents = 1,
1348                         .flags = CLK_SET_RATE_PARENT,
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch mmagic_camss_axi_clk = {
1355         .halt_reg = 0x3c44,
1356         .clkr = {
1357                 .enable_reg = 0x3c44,
1358                 .enable_mask = BIT(0),
1359                 .hw.init = &(struct clk_init_data){
1360                         .name = "mmagic_camss_axi_clk",
1361                         .parent_hws = (const struct clk_hw*[]){
1362                                 &axi_clk_src.clkr.hw
1363                         },
1364                         .num_parents = 1,
1365                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1366                         .ops = &clk_branch2_ops,
1367                 },
1368         },
1369 };
1370
1371 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1372         .halt_reg = 0x3c48,
1373         .clkr = {
1374                 .enable_reg = 0x3c48,
1375                 .enable_mask = BIT(0),
1376                 .hw.init = &(struct clk_init_data){
1377                         .name = "mmagic_camss_noc_cfg_ahb_clk",
1378                         .parent_data = (const struct clk_parent_data[]){
1379                                 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1380                         },
1381                         .num_parents = 1,
1382                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1383                         .ops = &clk_branch2_ops,
1384                 },
1385         },
1386 };
1387
1388 static struct clk_branch smmu_vfe_ahb_clk = {
1389         .halt_reg = 0x3c04,
1390         .clkr = {
1391                 .enable_reg = 0x3c04,
1392                 .enable_mask = BIT(0),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "smmu_vfe_ahb_clk",
1395                         .parent_hws = (const struct clk_hw*[]){
1396                                 &ahb_clk_src.clkr.hw
1397                         },
1398                         .num_parents = 1,
1399                         .flags = CLK_SET_RATE_PARENT,
1400                         .ops = &clk_branch2_ops,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_branch smmu_vfe_axi_clk = {
1406         .halt_reg = 0x3c08,
1407         .clkr = {
1408                 .enable_reg = 0x3c08,
1409                 .enable_mask = BIT(0),
1410                 .hw.init = &(struct clk_init_data){
1411                         .name = "smmu_vfe_axi_clk",
1412                         .parent_hws = (const struct clk_hw*[]){
1413                                 &axi_clk_src.clkr.hw
1414                         },
1415                         .num_parents = 1,
1416                         .flags = CLK_SET_RATE_PARENT,
1417                         .ops = &clk_branch2_ops,
1418                 },
1419         },
1420 };
1421
1422 static struct clk_branch smmu_cpp_ahb_clk = {
1423         .halt_reg = 0x3c14,
1424         .clkr = {
1425                 .enable_reg = 0x3c14,
1426                 .enable_mask = BIT(0),
1427                 .hw.init = &(struct clk_init_data){
1428                         .name = "smmu_cpp_ahb_clk",
1429                         .parent_hws = (const struct clk_hw*[]){
1430                                 &ahb_clk_src.clkr.hw
1431                         },
1432                         .num_parents = 1,
1433                         .flags = CLK_SET_RATE_PARENT,
1434                         .ops = &clk_branch2_ops,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_branch smmu_cpp_axi_clk = {
1440         .halt_reg = 0x3c18,
1441         .clkr = {
1442                 .enable_reg = 0x3c18,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "smmu_cpp_axi_clk",
1446                         .parent_hws = (const struct clk_hw*[]){
1447                                 &axi_clk_src.clkr.hw
1448                         },
1449                         .num_parents = 1,
1450                         .flags = CLK_SET_RATE_PARENT,
1451                         .ops = &clk_branch2_ops,
1452                 },
1453         },
1454 };
1455
1456 static struct clk_branch smmu_jpeg_ahb_clk = {
1457         .halt_reg = 0x3c24,
1458         .clkr = {
1459                 .enable_reg = 0x3c24,
1460                 .enable_mask = BIT(0),
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "smmu_jpeg_ahb_clk",
1463                         .parent_hws = (const struct clk_hw*[]){
1464                                 &ahb_clk_src.clkr.hw
1465                         },
1466                         .num_parents = 1,
1467                         .flags = CLK_SET_RATE_PARENT,
1468                         .ops = &clk_branch2_ops,
1469                 },
1470         },
1471 };
1472
1473 static struct clk_branch smmu_jpeg_axi_clk = {
1474         .halt_reg = 0x3c28,
1475         .clkr = {
1476                 .enable_reg = 0x3c28,
1477                 .enable_mask = BIT(0),
1478                 .hw.init = &(struct clk_init_data){
1479                         .name = "smmu_jpeg_axi_clk",
1480                         .parent_hws = (const struct clk_hw*[]){
1481                                 &axi_clk_src.clkr.hw
1482                         },
1483                         .num_parents = 1,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                         .ops = &clk_branch2_ops,
1486                 },
1487         },
1488 };
1489
1490 static struct clk_branch mmagic_mdss_axi_clk = {
1491         .halt_reg = 0x2474,
1492         .clkr = {
1493                 .enable_reg = 0x2474,
1494                 .enable_mask = BIT(0),
1495                 .hw.init = &(struct clk_init_data){
1496                         .name = "mmagic_mdss_axi_clk",
1497                         .parent_hws = (const struct clk_hw*[]){
1498                                 &axi_clk_src.clkr.hw
1499                         },
1500                         .num_parents = 1,
1501                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1502                         .ops = &clk_branch2_ops,
1503                 },
1504         },
1505 };
1506
1507 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1508         .halt_reg = 0x2478,
1509         .clkr = {
1510                 .enable_reg = 0x2478,
1511                 .enable_mask = BIT(0),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "mmagic_mdss_noc_cfg_ahb_clk",
1514                         .parent_data = (const struct clk_parent_data[]){
1515                                 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1516                         },
1517                         .num_parents = 1,
1518                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1519                         .ops = &clk_branch2_ops,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch smmu_rot_ahb_clk = {
1525         .halt_reg = 0x2444,
1526         .clkr = {
1527                 .enable_reg = 0x2444,
1528                 .enable_mask = BIT(0),
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "smmu_rot_ahb_clk",
1531                         .parent_hws = (const struct clk_hw*[]){
1532                                 &ahb_clk_src.clkr.hw
1533                         },
1534                         .num_parents = 1,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch smmu_rot_axi_clk = {
1542         .halt_reg = 0x2448,
1543         .clkr = {
1544                 .enable_reg = 0x2448,
1545                 .enable_mask = BIT(0),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "smmu_rot_axi_clk",
1548                         .parent_hws = (const struct clk_hw*[]){
1549                                 &axi_clk_src.clkr.hw
1550                         },
1551                         .num_parents = 1,
1552                         .flags = CLK_SET_RATE_PARENT,
1553                         .ops = &clk_branch2_ops,
1554                 },
1555         },
1556 };
1557
1558 static struct clk_branch smmu_mdp_ahb_clk = {
1559         .halt_reg = 0x2454,
1560         .clkr = {
1561                 .enable_reg = 0x2454,
1562                 .enable_mask = BIT(0),
1563                 .hw.init = &(struct clk_init_data){
1564                         .name = "smmu_mdp_ahb_clk",
1565                         .parent_hws = (const struct clk_hw*[]){
1566                                 &ahb_clk_src.clkr.hw
1567                         },
1568                         .num_parents = 1,
1569                         .flags = CLK_SET_RATE_PARENT,
1570                         .ops = &clk_branch2_ops,
1571                 },
1572         },
1573 };
1574
1575 static struct clk_branch smmu_mdp_axi_clk = {
1576         .halt_reg = 0x2458,
1577         .clkr = {
1578                 .enable_reg = 0x2458,
1579                 .enable_mask = BIT(0),
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "smmu_mdp_axi_clk",
1582                         .parent_hws = (const struct clk_hw*[]){
1583                                 &axi_clk_src.clkr.hw
1584                         },
1585                         .num_parents = 1,
1586                         .flags = CLK_SET_RATE_PARENT,
1587                         .ops = &clk_branch2_ops,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_branch mmagic_video_axi_clk = {
1593         .halt_reg = 0x1194,
1594         .clkr = {
1595                 .enable_reg = 0x1194,
1596                 .enable_mask = BIT(0),
1597                 .hw.init = &(struct clk_init_data){
1598                         .name = "mmagic_video_axi_clk",
1599                         .parent_hws = (const struct clk_hw*[]){
1600                                 &axi_clk_src.clkr.hw
1601                         },
1602                         .num_parents = 1,
1603                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1604                         .ops = &clk_branch2_ops,
1605                 },
1606         },
1607 };
1608
1609 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1610         .halt_reg = 0x1198,
1611         .clkr = {
1612                 .enable_reg = 0x1198,
1613                 .enable_mask = BIT(0),
1614                 .hw.init = &(struct clk_init_data){
1615                         .name = "mmagic_video_noc_cfg_ahb_clk",
1616                         .parent_data = (const struct clk_parent_data[]){
1617                                 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1618                         },
1619                         .num_parents = 1,
1620                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1621                         .ops = &clk_branch2_ops,
1622                 },
1623         },
1624 };
1625
1626 static struct clk_branch smmu_video_ahb_clk = {
1627         .halt_reg = 0x1174,
1628         .clkr = {
1629                 .enable_reg = 0x1174,
1630                 .enable_mask = BIT(0),
1631                 .hw.init = &(struct clk_init_data){
1632                         .name = "smmu_video_ahb_clk",
1633                         .parent_hws = (const struct clk_hw*[]){
1634                                 &ahb_clk_src.clkr.hw
1635                         },
1636                         .num_parents = 1,
1637                         .flags = CLK_SET_RATE_PARENT,
1638                         .ops = &clk_branch2_ops,
1639                 },
1640         },
1641 };
1642
1643 static struct clk_branch smmu_video_axi_clk = {
1644         .halt_reg = 0x1178,
1645         .clkr = {
1646                 .enable_reg = 0x1178,
1647                 .enable_mask = BIT(0),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "smmu_video_axi_clk",
1650                         .parent_hws = (const struct clk_hw*[]){
1651                                 &axi_clk_src.clkr.hw
1652                         },
1653                         .num_parents = 1,
1654                         .flags = CLK_SET_RATE_PARENT,
1655                         .ops = &clk_branch2_ops,
1656                 },
1657         },
1658 };
1659
1660 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1661         .halt_reg = 0x5298,
1662         .clkr = {
1663                 .enable_reg = 0x5298,
1664                 .enable_mask = BIT(0),
1665                 .hw.init = &(struct clk_init_data){
1666                         .name = "mmagic_bimc_noc_cfg_ahb_clk",
1667                         .parent_data = (const struct clk_parent_data[]){
1668                                 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1669                         },
1670                         .num_parents = 1,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                         .ops = &clk_branch2_ops,
1673                 },
1674         },
1675 };
1676
1677 static struct clk_branch gpu_gx_gfx3d_clk = {
1678         .halt_reg = 0x4028,
1679         .clkr = {
1680                 .enable_reg = 0x4028,
1681                 .enable_mask = BIT(0),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "gpu_gx_gfx3d_clk",
1684                         .parent_hws = (const struct clk_hw*[]){
1685                                 &gfx3d_clk_src.rcg.clkr.hw
1686                         },
1687                         .num_parents = 1,
1688                         .flags = CLK_SET_RATE_PARENT,
1689                         .ops = &clk_branch2_ops,
1690                 },
1691         },
1692 };
1693
1694 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1695         .halt_reg = 0x40b0,
1696         .clkr = {
1697                 .enable_reg = 0x40b0,
1698                 .enable_mask = BIT(0),
1699                 .hw.init = &(struct clk_init_data){
1700                         .name = "gpu_gx_rbbmtimer_clk",
1701                         .parent_hws = (const struct clk_hw*[]){
1702                                 &rbbmtimer_clk_src.clkr.hw
1703                         },
1704                         .num_parents = 1,
1705                         .flags = CLK_SET_RATE_PARENT,
1706                         .ops = &clk_branch2_ops,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch gpu_ahb_clk = {
1712         .halt_reg = 0x403c,
1713         .clkr = {
1714                 .enable_reg = 0x403c,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "gpu_ahb_clk",
1718                         .parent_hws = (const struct clk_hw*[]){
1719                                 &ahb_clk_src.clkr.hw
1720                         },
1721                         .num_parents = 1,
1722                         .flags = CLK_SET_RATE_PARENT,
1723                         .ops = &clk_branch2_ops,
1724                 },
1725         },
1726 };
1727
1728 static struct clk_branch gpu_aon_isense_clk = {
1729         .halt_reg = 0x4044,
1730         .clkr = {
1731                 .enable_reg = 0x4044,
1732                 .enable_mask = BIT(0),
1733                 .hw.init = &(struct clk_init_data){
1734                         .name = "gpu_aon_isense_clk",
1735                         .parent_hws = (const struct clk_hw*[]){
1736                                 &isense_clk_src.clkr.hw
1737                         },
1738                         .num_parents = 1,
1739                         .flags = CLK_SET_RATE_PARENT,
1740                         .ops = &clk_branch2_ops,
1741                 },
1742         },
1743 };
1744
1745 static struct clk_branch vmem_maxi_clk = {
1746         .halt_reg = 0x1204,
1747         .clkr = {
1748                 .enable_reg = 0x1204,
1749                 .enable_mask = BIT(0),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "vmem_maxi_clk",
1752                         .parent_hws = (const struct clk_hw*[]){
1753                                 &maxi_clk_src.clkr.hw
1754                         },
1755                         .num_parents = 1,
1756                         .flags = CLK_SET_RATE_PARENT,
1757                         .ops = &clk_branch2_ops,
1758                 },
1759         },
1760 };
1761
1762 static struct clk_branch vmem_ahb_clk = {
1763         .halt_reg = 0x1208,
1764         .clkr = {
1765                 .enable_reg = 0x1208,
1766                 .enable_mask = BIT(0),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "vmem_ahb_clk",
1769                         .parent_hws = (const struct clk_hw*[]){
1770                                 &ahb_clk_src.clkr.hw
1771                         },
1772                         .num_parents = 1,
1773                         .flags = CLK_SET_RATE_PARENT,
1774                         .ops = &clk_branch2_ops,
1775                 },
1776         },
1777 };
1778
1779 static struct clk_branch mmss_rbcpr_clk = {
1780         .halt_reg = 0x4084,
1781         .clkr = {
1782                 .enable_reg = 0x4084,
1783                 .enable_mask = BIT(0),
1784                 .hw.init = &(struct clk_init_data){
1785                         .name = "mmss_rbcpr_clk",
1786                         .parent_hws = (const struct clk_hw*[]){
1787                                 &rbcpr_clk_src.clkr.hw
1788                         },
1789                         .num_parents = 1,
1790                         .flags = CLK_SET_RATE_PARENT,
1791                         .ops = &clk_branch2_ops,
1792                 },
1793         },
1794 };
1795
1796 static struct clk_branch mmss_rbcpr_ahb_clk = {
1797         .halt_reg = 0x4088,
1798         .clkr = {
1799                 .enable_reg = 0x4088,
1800                 .enable_mask = BIT(0),
1801                 .hw.init = &(struct clk_init_data){
1802                         .name = "mmss_rbcpr_ahb_clk",
1803                         .parent_hws = (const struct clk_hw*[]){
1804                                 &ahb_clk_src.clkr.hw
1805                         },
1806                         .num_parents = 1,
1807                         .flags = CLK_SET_RATE_PARENT,
1808                         .ops = &clk_branch2_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch video_core_clk = {
1814         .halt_reg = 0x1028,
1815         .clkr = {
1816                 .enable_reg = 0x1028,
1817                 .enable_mask = BIT(0),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "video_core_clk",
1820                         .parent_hws = (const struct clk_hw*[]){
1821                                 &video_core_clk_src.clkr.hw
1822                         },
1823                         .num_parents = 1,
1824                         .flags = CLK_SET_RATE_PARENT,
1825                         .ops = &clk_branch2_ops,
1826                 },
1827         },
1828 };
1829
1830 static struct clk_branch video_axi_clk = {
1831         .halt_reg = 0x1034,
1832         .clkr = {
1833                 .enable_reg = 0x1034,
1834                 .enable_mask = BIT(0),
1835                 .hw.init = &(struct clk_init_data){
1836                         .name = "video_axi_clk",
1837                         .parent_hws = (const struct clk_hw*[]){
1838                                 &axi_clk_src.clkr.hw
1839                         },
1840                         .num_parents = 1,
1841                         .flags = CLK_SET_RATE_PARENT,
1842                         .ops = &clk_branch2_ops,
1843                 },
1844         },
1845 };
1846
1847 static struct clk_branch video_maxi_clk = {
1848         .halt_reg = 0x1038,
1849         .clkr = {
1850                 .enable_reg = 0x1038,
1851                 .enable_mask = BIT(0),
1852                 .hw.init = &(struct clk_init_data){
1853                         .name = "video_maxi_clk",
1854                         .parent_hws = (const struct clk_hw*[]){
1855                                 &maxi_clk_src.clkr.hw
1856                         },
1857                         .num_parents = 1,
1858                         .flags = CLK_SET_RATE_PARENT,
1859                         .ops = &clk_branch2_ops,
1860                 },
1861         },
1862 };
1863
1864 static struct clk_branch video_ahb_clk = {
1865         .halt_reg = 0x1030,
1866         .clkr = {
1867                 .enable_reg = 0x1030,
1868                 .enable_mask = BIT(0),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "video_ahb_clk",
1871                         .parent_hws = (const struct clk_hw*[]){
1872                                 &ahb_clk_src.clkr.hw
1873                         },
1874                         .num_parents = 1,
1875                         .flags = CLK_SET_RATE_PARENT,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch video_subcore0_clk = {
1882         .halt_reg = 0x1048,
1883         .clkr = {
1884                 .enable_reg = 0x1048,
1885                 .enable_mask = BIT(0),
1886                 .hw.init = &(struct clk_init_data){
1887                         .name = "video_subcore0_clk",
1888                         .parent_hws = (const struct clk_hw*[]){
1889                                 &video_subcore0_clk_src.clkr.hw
1890                         },
1891                         .num_parents = 1,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                         .ops = &clk_branch2_ops,
1894                 },
1895         },
1896 };
1897
1898 static struct clk_branch video_subcore1_clk = {
1899         .halt_reg = 0x104c,
1900         .clkr = {
1901                 .enable_reg = 0x104c,
1902                 .enable_mask = BIT(0),
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "video_subcore1_clk",
1905                         .parent_hws = (const struct clk_hw*[]){
1906                                 &video_subcore1_clk_src.clkr.hw
1907                         },
1908                         .num_parents = 1,
1909                         .flags = CLK_SET_RATE_PARENT,
1910                         .ops = &clk_branch2_ops,
1911                 },
1912         },
1913 };
1914
1915 static struct clk_branch mdss_ahb_clk = {
1916         .halt_reg = 0x2308,
1917         .clkr = {
1918                 .enable_reg = 0x2308,
1919                 .enable_mask = BIT(0),
1920                 .hw.init = &(struct clk_init_data){
1921                         .name = "mdss_ahb_clk",
1922                         .parent_hws = (const struct clk_hw*[]){
1923                                 &ahb_clk_src.clkr.hw
1924                         },
1925                         .num_parents = 1,
1926                         .flags = CLK_SET_RATE_PARENT,
1927                         .ops = &clk_branch2_ops,
1928                 },
1929         },
1930 };
1931
1932 static struct clk_branch mdss_hdmi_ahb_clk = {
1933         .halt_reg = 0x230c,
1934         .clkr = {
1935                 .enable_reg = 0x230c,
1936                 .enable_mask = BIT(0),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "mdss_hdmi_ahb_clk",
1939                         .parent_hws = (const struct clk_hw*[]){
1940                                 &ahb_clk_src.clkr.hw
1941                         },
1942                         .num_parents = 1,
1943                         .flags = CLK_SET_RATE_PARENT,
1944                         .ops = &clk_branch2_ops,
1945                 },
1946         },
1947 };
1948
1949 static struct clk_branch mdss_axi_clk = {
1950         .halt_reg = 0x2310,
1951         .clkr = {
1952                 .enable_reg = 0x2310,
1953                 .enable_mask = BIT(0),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "mdss_axi_clk",
1956                         .parent_hws = (const struct clk_hw*[]){
1957                                 &axi_clk_src.clkr.hw
1958                         },
1959                         .num_parents = 1,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch mdss_pclk0_clk = {
1967         .halt_reg = 0x2314,
1968         .clkr = {
1969                 .enable_reg = 0x2314,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data){
1972                         .name = "mdss_pclk0_clk",
1973                         .parent_hws = (const struct clk_hw*[]){
1974                                 &pclk0_clk_src.clkr.hw
1975                         },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch mdss_pclk1_clk = {
1984         .halt_reg = 0x2318,
1985         .clkr = {
1986                 .enable_reg = 0x2318,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "mdss_pclk1_clk",
1990                         .parent_hws = (const struct clk_hw*[]){
1991                                 &pclk1_clk_src.clkr.hw
1992                         },
1993                         .num_parents = 1,
1994                         .flags = CLK_SET_RATE_PARENT,
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch mdss_mdp_clk = {
2001         .halt_reg = 0x231c,
2002         .clkr = {
2003                 .enable_reg = 0x231c,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "mdss_mdp_clk",
2007                         .parent_hws = (const struct clk_hw*[]){
2008                                 &mdp_clk_src.clkr.hw
2009                         },
2010                         .num_parents = 1,
2011                         .flags = CLK_SET_RATE_PARENT,
2012                         .ops = &clk_branch2_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch mdss_extpclk_clk = {
2018         .halt_reg = 0x2324,
2019         .clkr = {
2020                 .enable_reg = 0x2324,
2021                 .enable_mask = BIT(0),
2022                 .hw.init = &(struct clk_init_data){
2023                         .name = "mdss_extpclk_clk",
2024                         .parent_hws = (const struct clk_hw*[]){
2025                                 &extpclk_clk_src.clkr.hw
2026                         },
2027                         .num_parents = 1,
2028                         .flags = CLK_SET_RATE_PARENT,
2029                         .ops = &clk_branch2_ops,
2030                 },
2031         },
2032 };
2033
2034 static struct clk_branch mdss_vsync_clk = {
2035         .halt_reg = 0x2328,
2036         .clkr = {
2037                 .enable_reg = 0x2328,
2038                 .enable_mask = BIT(0),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "mdss_vsync_clk",
2041                         .parent_hws = (const struct clk_hw*[]){
2042                                 &vsync_clk_src.clkr.hw
2043                         },
2044                         .num_parents = 1,
2045                         .flags = CLK_SET_RATE_PARENT,
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch mdss_hdmi_clk = {
2052         .halt_reg = 0x2338,
2053         .clkr = {
2054                 .enable_reg = 0x2338,
2055                 .enable_mask = BIT(0),
2056                 .hw.init = &(struct clk_init_data){
2057                         .name = "mdss_hdmi_clk",
2058                         .parent_hws = (const struct clk_hw*[]){
2059                                 &hdmi_clk_src.clkr.hw
2060                         },
2061                         .num_parents = 1,
2062                         .flags = CLK_SET_RATE_PARENT,
2063                         .ops = &clk_branch2_ops,
2064                 },
2065         },
2066 };
2067
2068 static struct clk_branch mdss_byte0_clk = {
2069         .halt_reg = 0x233c,
2070         .clkr = {
2071                 .enable_reg = 0x233c,
2072                 .enable_mask = BIT(0),
2073                 .hw.init = &(struct clk_init_data){
2074                         .name = "mdss_byte0_clk",
2075                         .parent_hws = (const struct clk_hw*[]){
2076                                 &byte0_clk_src.clkr.hw
2077                         },
2078                         .num_parents = 1,
2079                         .flags = CLK_SET_RATE_PARENT,
2080                         .ops = &clk_branch2_ops,
2081                 },
2082         },
2083 };
2084
2085 static struct clk_branch mdss_byte1_clk = {
2086         .halt_reg = 0x2340,
2087         .clkr = {
2088                 .enable_reg = 0x2340,
2089                 .enable_mask = BIT(0),
2090                 .hw.init = &(struct clk_init_data){
2091                         .name = "mdss_byte1_clk",
2092                         .parent_hws = (const struct clk_hw*[]){
2093                                 &byte1_clk_src.clkr.hw
2094                         },
2095                         .num_parents = 1,
2096                         .flags = CLK_SET_RATE_PARENT,
2097                         .ops = &clk_branch2_ops,
2098                 },
2099         },
2100 };
2101
2102 static struct clk_branch mdss_esc0_clk = {
2103         .halt_reg = 0x2344,
2104         .clkr = {
2105                 .enable_reg = 0x2344,
2106                 .enable_mask = BIT(0),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "mdss_esc0_clk",
2109                         .parent_hws = (const struct clk_hw*[]){
2110                                 &esc0_clk_src.clkr.hw
2111                         },
2112                         .num_parents = 1,
2113                         .flags = CLK_SET_RATE_PARENT,
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch mdss_esc1_clk = {
2120         .halt_reg = 0x2348,
2121         .clkr = {
2122                 .enable_reg = 0x2348,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "mdss_esc1_clk",
2126                         .parent_hws = (const struct clk_hw*[]){
2127                                 &esc1_clk_src.clkr.hw
2128                         },
2129                         .num_parents = 1,
2130                         .flags = CLK_SET_RATE_PARENT,
2131                         .ops = &clk_branch2_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch camss_top_ahb_clk = {
2137         .halt_reg = 0x3484,
2138         .clkr = {
2139                 .enable_reg = 0x3484,
2140                 .enable_mask = BIT(0),
2141                 .hw.init = &(struct clk_init_data){
2142                         .name = "camss_top_ahb_clk",
2143                         .parent_hws = (const struct clk_hw*[]){
2144                                 &ahb_clk_src.clkr.hw
2145                         },
2146                         .num_parents = 1,
2147                         .flags = CLK_SET_RATE_PARENT,
2148                         .ops = &clk_branch2_ops,
2149                 },
2150         },
2151 };
2152
2153 static struct clk_branch camss_ahb_clk = {
2154         .halt_reg = 0x348c,
2155         .clkr = {
2156                 .enable_reg = 0x348c,
2157                 .enable_mask = BIT(0),
2158                 .hw.init = &(struct clk_init_data){
2159                         .name = "camss_ahb_clk",
2160                         .parent_hws = (const struct clk_hw*[]){
2161                                 &ahb_clk_src.clkr.hw
2162                         },
2163                         .num_parents = 1,
2164                         .flags = CLK_SET_RATE_PARENT,
2165                         .ops = &clk_branch2_ops,
2166                 },
2167         },
2168 };
2169
2170 static struct clk_branch camss_micro_ahb_clk = {
2171         .halt_reg = 0x3494,
2172         .clkr = {
2173                 .enable_reg = 0x3494,
2174                 .enable_mask = BIT(0),
2175                 .hw.init = &(struct clk_init_data){
2176                         .name = "camss_micro_ahb_clk",
2177                         .parent_hws = (const struct clk_hw*[]){
2178                                 &ahb_clk_src.clkr.hw
2179                         },
2180                         .num_parents = 1,
2181                         .flags = CLK_SET_RATE_PARENT,
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch camss_gp0_clk = {
2188         .halt_reg = 0x3444,
2189         .clkr = {
2190                 .enable_reg = 0x3444,
2191                 .enable_mask = BIT(0),
2192                 .hw.init = &(struct clk_init_data){
2193                         .name = "camss_gp0_clk",
2194                         .parent_hws = (const struct clk_hw*[]){
2195                                 &camss_gp0_clk_src.clkr.hw
2196                         },
2197                         .num_parents = 1,
2198                         .flags = CLK_SET_RATE_PARENT,
2199                         .ops = &clk_branch2_ops,
2200                 },
2201         },
2202 };
2203
2204 static struct clk_branch camss_gp1_clk = {
2205         .halt_reg = 0x3474,
2206         .clkr = {
2207                 .enable_reg = 0x3474,
2208                 .enable_mask = BIT(0),
2209                 .hw.init = &(struct clk_init_data){
2210                         .name = "camss_gp1_clk",
2211                         .parent_hws = (const struct clk_hw*[]){
2212                                 &camss_gp1_clk_src.clkr.hw
2213                         },
2214                         .num_parents = 1,
2215                         .flags = CLK_SET_RATE_PARENT,
2216                         .ops = &clk_branch2_ops,
2217                 },
2218         },
2219 };
2220
2221 static struct clk_branch camss_mclk0_clk = {
2222         .halt_reg = 0x3384,
2223         .clkr = {
2224                 .enable_reg = 0x3384,
2225                 .enable_mask = BIT(0),
2226                 .hw.init = &(struct clk_init_data){
2227                         .name = "camss_mclk0_clk",
2228                         .parent_hws = (const struct clk_hw*[]){
2229                                 &mclk0_clk_src.clkr.hw
2230                         },
2231                         .num_parents = 1,
2232                         .flags = CLK_SET_RATE_PARENT,
2233                         .ops = &clk_branch2_ops,
2234                 },
2235         },
2236 };
2237
2238 static struct clk_branch camss_mclk1_clk = {
2239         .halt_reg = 0x33b4,
2240         .clkr = {
2241                 .enable_reg = 0x33b4,
2242                 .enable_mask = BIT(0),
2243                 .hw.init = &(struct clk_init_data){
2244                         .name = "camss_mclk1_clk",
2245                         .parent_hws = (const struct clk_hw*[]){
2246                                 &mclk1_clk_src.clkr.hw
2247                         },
2248                         .num_parents = 1,
2249                         .flags = CLK_SET_RATE_PARENT,
2250                         .ops = &clk_branch2_ops,
2251                 },
2252         },
2253 };
2254
2255 static struct clk_branch camss_mclk2_clk = {
2256         .halt_reg = 0x33e4,
2257         .clkr = {
2258                 .enable_reg = 0x33e4,
2259                 .enable_mask = BIT(0),
2260                 .hw.init = &(struct clk_init_data){
2261                         .name = "camss_mclk2_clk",
2262                         .parent_hws = (const struct clk_hw*[]){
2263                                 &mclk2_clk_src.clkr.hw
2264                         },
2265                         .num_parents = 1,
2266                         .flags = CLK_SET_RATE_PARENT,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch camss_mclk3_clk = {
2273         .halt_reg = 0x3414,
2274         .clkr = {
2275                 .enable_reg = 0x3414,
2276                 .enable_mask = BIT(0),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "camss_mclk3_clk",
2279                         .parent_hws = (const struct clk_hw*[]){
2280                                 &mclk3_clk_src.clkr.hw
2281                         },
2282                         .num_parents = 1,
2283                         .flags = CLK_SET_RATE_PARENT,
2284                         .ops = &clk_branch2_ops,
2285                 },
2286         },
2287 };
2288
2289 static struct clk_branch camss_cci_clk = {
2290         .halt_reg = 0x3344,
2291         .clkr = {
2292                 .enable_reg = 0x3344,
2293                 .enable_mask = BIT(0),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "camss_cci_clk",
2296                         .parent_hws = (const struct clk_hw*[]){
2297                                 &cci_clk_src.clkr.hw
2298                         },
2299                         .num_parents = 1,
2300                         .flags = CLK_SET_RATE_PARENT,
2301                         .ops = &clk_branch2_ops,
2302                 },
2303         },
2304 };
2305
2306 static struct clk_branch camss_cci_ahb_clk = {
2307         .halt_reg = 0x3348,
2308         .clkr = {
2309                 .enable_reg = 0x3348,
2310                 .enable_mask = BIT(0),
2311                 .hw.init = &(struct clk_init_data){
2312                         .name = "camss_cci_ahb_clk",
2313                         .parent_hws = (const struct clk_hw*[]){
2314                                 &ahb_clk_src.clkr.hw
2315                         },
2316                         .num_parents = 1,
2317                         .flags = CLK_SET_RATE_PARENT,
2318                         .ops = &clk_branch2_ops,
2319                 },
2320         },
2321 };
2322
2323 static struct clk_branch camss_csi0phytimer_clk = {
2324         .halt_reg = 0x3024,
2325         .clkr = {
2326                 .enable_reg = 0x3024,
2327                 .enable_mask = BIT(0),
2328                 .hw.init = &(struct clk_init_data){
2329                         .name = "camss_csi0phytimer_clk",
2330                         .parent_hws = (const struct clk_hw*[]){
2331                                 &csi0phytimer_clk_src.clkr.hw
2332                         },
2333                         .num_parents = 1,
2334                         .flags = CLK_SET_RATE_PARENT,
2335                         .ops = &clk_branch2_ops,
2336                 },
2337         },
2338 };
2339
2340 static struct clk_branch camss_csi1phytimer_clk = {
2341         .halt_reg = 0x3054,
2342         .clkr = {
2343                 .enable_reg = 0x3054,
2344                 .enable_mask = BIT(0),
2345                 .hw.init = &(struct clk_init_data){
2346                         .name = "camss_csi1phytimer_clk",
2347                         .parent_hws = (const struct clk_hw*[]){
2348                                 &csi1phytimer_clk_src.clkr.hw
2349                         },
2350                         .num_parents = 1,
2351                         .flags = CLK_SET_RATE_PARENT,
2352                         .ops = &clk_branch2_ops,
2353                 },
2354         },
2355 };
2356
2357 static struct clk_branch camss_csi2phytimer_clk = {
2358         .halt_reg = 0x3084,
2359         .clkr = {
2360                 .enable_reg = 0x3084,
2361                 .enable_mask = BIT(0),
2362                 .hw.init = &(struct clk_init_data){
2363                         .name = "camss_csi2phytimer_clk",
2364                         .parent_hws = (const struct clk_hw*[]){
2365                                 &csi2phytimer_clk_src.clkr.hw
2366                         },
2367                         .num_parents = 1,
2368                         .flags = CLK_SET_RATE_PARENT,
2369                         .ops = &clk_branch2_ops,
2370                 },
2371         },
2372 };
2373
2374 static struct clk_branch camss_csiphy0_3p_clk = {
2375         .halt_reg = 0x3234,
2376         .clkr = {
2377                 .enable_reg = 0x3234,
2378                 .enable_mask = BIT(0),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "camss_csiphy0_3p_clk",
2381                         .parent_hws = (const struct clk_hw*[]){
2382                                 &csiphy0_3p_clk_src.clkr.hw
2383                         },
2384                         .num_parents = 1,
2385                         .flags = CLK_SET_RATE_PARENT,
2386                         .ops = &clk_branch2_ops,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_branch camss_csiphy1_3p_clk = {
2392         .halt_reg = 0x3254,
2393         .clkr = {
2394                 .enable_reg = 0x3254,
2395                 .enable_mask = BIT(0),
2396                 .hw.init = &(struct clk_init_data){
2397                         .name = "camss_csiphy1_3p_clk",
2398                         .parent_hws = (const struct clk_hw*[]){
2399                                 &csiphy1_3p_clk_src.clkr.hw
2400                         },
2401                         .num_parents = 1,
2402                         .flags = CLK_SET_RATE_PARENT,
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch camss_csiphy2_3p_clk = {
2409         .halt_reg = 0x3274,
2410         .clkr = {
2411                 .enable_reg = 0x3274,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "camss_csiphy2_3p_clk",
2415                         .parent_hws = (const struct clk_hw*[]){
2416                                 &csiphy2_3p_clk_src.clkr.hw
2417                         },
2418                         .num_parents = 1,
2419                         .flags = CLK_SET_RATE_PARENT,
2420                         .ops = &clk_branch2_ops,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_branch camss_jpeg0_clk = {
2426         .halt_reg = 0x35a8,
2427         .clkr = {
2428                 .enable_reg = 0x35a8,
2429                 .enable_mask = BIT(0),
2430                 .hw.init = &(struct clk_init_data){
2431                         .name = "camss_jpeg0_clk",
2432                         .parent_hws = (const struct clk_hw*[]){
2433                                 &jpeg0_clk_src.clkr.hw
2434                         },
2435                         .num_parents = 1,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch camss_jpeg2_clk = {
2443         .halt_reg = 0x35b0,
2444         .clkr = {
2445                 .enable_reg = 0x35b0,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "camss_jpeg2_clk",
2449                         .parent_hws = (const struct clk_hw*[]){
2450                                 &jpeg2_clk_src.clkr.hw
2451                         },
2452                         .num_parents = 1,
2453                         .flags = CLK_SET_RATE_PARENT,
2454                         .ops = &clk_branch2_ops,
2455                 },
2456         },
2457 };
2458
2459 static struct clk_branch camss_jpeg_dma_clk = {
2460         .halt_reg = 0x35c0,
2461         .clkr = {
2462                 .enable_reg = 0x35c0,
2463                 .enable_mask = BIT(0),
2464                 .hw.init = &(struct clk_init_data){
2465                         .name = "camss_jpeg_dma_clk",
2466                         .parent_hws = (const struct clk_hw*[]){
2467                                 &jpeg_dma_clk_src.clkr.hw
2468                         },
2469                         .num_parents = 1,
2470                         .flags = CLK_SET_RATE_PARENT,
2471                         .ops = &clk_branch2_ops,
2472                 },
2473         },
2474 };
2475
2476 static struct clk_branch camss_jpeg_ahb_clk = {
2477         .halt_reg = 0x35b4,
2478         .clkr = {
2479                 .enable_reg = 0x35b4,
2480                 .enable_mask = BIT(0),
2481                 .hw.init = &(struct clk_init_data){
2482                         .name = "camss_jpeg_ahb_clk",
2483                         .parent_hws = (const struct clk_hw*[]){
2484                                 &ahb_clk_src.clkr.hw
2485                         },
2486                         .num_parents = 1,
2487                         .flags = CLK_SET_RATE_PARENT,
2488                         .ops = &clk_branch2_ops,
2489                 },
2490         },
2491 };
2492
2493 static struct clk_branch camss_jpeg_axi_clk = {
2494         .halt_reg = 0x35b8,
2495         .clkr = {
2496                 .enable_reg = 0x35b8,
2497                 .enable_mask = BIT(0),
2498                 .hw.init = &(struct clk_init_data){
2499                         .name = "camss_jpeg_axi_clk",
2500                         .parent_hws = (const struct clk_hw*[]){
2501                                 &axi_clk_src.clkr.hw
2502                         },
2503                         .num_parents = 1,
2504                         .flags = CLK_SET_RATE_PARENT,
2505                         .ops = &clk_branch2_ops,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch camss_vfe_ahb_clk = {
2511         .halt_reg = 0x36b8,
2512         .clkr = {
2513                 .enable_reg = 0x36b8,
2514                 .enable_mask = BIT(0),
2515                 .hw.init = &(struct clk_init_data){
2516                         .name = "camss_vfe_ahb_clk",
2517                         .parent_hws = (const struct clk_hw*[]){
2518                                 &ahb_clk_src.clkr.hw
2519                         },
2520                         .num_parents = 1,
2521                         .flags = CLK_SET_RATE_PARENT,
2522                         .ops = &clk_branch2_ops,
2523                 },
2524         },
2525 };
2526
2527 static struct clk_branch camss_vfe_axi_clk = {
2528         .halt_reg = 0x36bc,
2529         .clkr = {
2530                 .enable_reg = 0x36bc,
2531                 .enable_mask = BIT(0),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "camss_vfe_axi_clk",
2534                         .parent_hws = (const struct clk_hw*[]){
2535                                 &axi_clk_src.clkr.hw
2536                         },
2537                         .num_parents = 1,
2538                         .flags = CLK_SET_RATE_PARENT,
2539                         .ops = &clk_branch2_ops,
2540                 },
2541         },
2542 };
2543
2544 static struct clk_branch camss_vfe0_clk = {
2545         .halt_reg = 0x36a8,
2546         .clkr = {
2547                 .enable_reg = 0x36a8,
2548                 .enable_mask = BIT(0),
2549                 .hw.init = &(struct clk_init_data){
2550                         .name = "camss_vfe0_clk",
2551                         .parent_hws = (const struct clk_hw*[]){
2552                                 &vfe0_clk_src.clkr.hw
2553                         },
2554                         .num_parents = 1,
2555                         .flags = CLK_SET_RATE_PARENT,
2556                         .ops = &clk_branch2_ops,
2557                 },
2558         },
2559 };
2560
2561 static struct clk_branch camss_vfe0_stream_clk = {
2562         .halt_reg = 0x3720,
2563         .clkr = {
2564                 .enable_reg = 0x3720,
2565                 .enable_mask = BIT(0),
2566                 .hw.init = &(struct clk_init_data){
2567                         .name = "camss_vfe0_stream_clk",
2568                         .parent_hws = (const struct clk_hw*[]){
2569                                 &vfe0_clk_src.clkr.hw
2570                         },
2571                         .num_parents = 1,
2572                         .flags = CLK_SET_RATE_PARENT,
2573                         .ops = &clk_branch2_ops,
2574                 },
2575         },
2576 };
2577
2578 static struct clk_branch camss_vfe0_ahb_clk = {
2579         .halt_reg = 0x3668,
2580         .clkr = {
2581                 .enable_reg = 0x3668,
2582                 .enable_mask = BIT(0),
2583                 .hw.init = &(struct clk_init_data){
2584                         .name = "camss_vfe0_ahb_clk",
2585                         .parent_hws = (const struct clk_hw*[]){
2586                                 &ahb_clk_src.clkr.hw
2587                         },
2588                         .num_parents = 1,
2589                         .flags = CLK_SET_RATE_PARENT,
2590                         .ops = &clk_branch2_ops,
2591                 },
2592         },
2593 };
2594
2595 static struct clk_branch camss_vfe1_clk = {
2596         .halt_reg = 0x36ac,
2597         .clkr = {
2598                 .enable_reg = 0x36ac,
2599                 .enable_mask = BIT(0),
2600                 .hw.init = &(struct clk_init_data){
2601                         .name = "camss_vfe1_clk",
2602                         .parent_hws = (const struct clk_hw*[]){
2603                                 &vfe1_clk_src.clkr.hw
2604                         },
2605                         .num_parents = 1,
2606                         .flags = CLK_SET_RATE_PARENT,
2607                         .ops = &clk_branch2_ops,
2608                 },
2609         },
2610 };
2611
2612 static struct clk_branch camss_vfe1_stream_clk = {
2613         .halt_reg = 0x3724,
2614         .clkr = {
2615                 .enable_reg = 0x3724,
2616                 .enable_mask = BIT(0),
2617                 .hw.init = &(struct clk_init_data){
2618                         .name = "camss_vfe1_stream_clk",
2619                         .parent_hws = (const struct clk_hw*[]){
2620                                 &vfe1_clk_src.clkr.hw
2621                         },
2622                         .num_parents = 1,
2623                         .flags = CLK_SET_RATE_PARENT,
2624                         .ops = &clk_branch2_ops,
2625                 },
2626         },
2627 };
2628
2629 static struct clk_branch camss_vfe1_ahb_clk = {
2630         .halt_reg = 0x3678,
2631         .clkr = {
2632                 .enable_reg = 0x3678,
2633                 .enable_mask = BIT(0),
2634                 .hw.init = &(struct clk_init_data){
2635                         .name = "camss_vfe1_ahb_clk",
2636                         .parent_hws = (const struct clk_hw*[]){
2637                                 &ahb_clk_src.clkr.hw
2638                         },
2639                         .num_parents = 1,
2640                         .flags = CLK_SET_RATE_PARENT,
2641                         .ops = &clk_branch2_ops,
2642                 },
2643         },
2644 };
2645
2646 static struct clk_branch camss_csi_vfe0_clk = {
2647         .halt_reg = 0x3704,
2648         .clkr = {
2649                 .enable_reg = 0x3704,
2650                 .enable_mask = BIT(0),
2651                 .hw.init = &(struct clk_init_data){
2652                         .name = "camss_csi_vfe0_clk",
2653                         .parent_hws = (const struct clk_hw*[]){
2654                                 &vfe0_clk_src.clkr.hw
2655                         },
2656                         .num_parents = 1,
2657                         .flags = CLK_SET_RATE_PARENT,
2658                         .ops = &clk_branch2_ops,
2659                 },
2660         },
2661 };
2662
2663 static struct clk_branch camss_csi_vfe1_clk = {
2664         .halt_reg = 0x3714,
2665         .clkr = {
2666                 .enable_reg = 0x3714,
2667                 .enable_mask = BIT(0),
2668                 .hw.init = &(struct clk_init_data){
2669                         .name = "camss_csi_vfe1_clk",
2670                         .parent_hws = (const struct clk_hw*[]){
2671                                 &vfe1_clk_src.clkr.hw
2672                         },
2673                         .num_parents = 1,
2674                         .flags = CLK_SET_RATE_PARENT,
2675                         .ops = &clk_branch2_ops,
2676                 },
2677         },
2678 };
2679
2680 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2681         .halt_reg = 0x36c8,
2682         .clkr = {
2683                 .enable_reg = 0x36c8,
2684                 .enable_mask = BIT(0),
2685                 .hw.init = &(struct clk_init_data){
2686                         .name = "camss_cpp_vbif_ahb_clk",
2687                         .parent_hws = (const struct clk_hw*[]){
2688                                 &ahb_clk_src.clkr.hw
2689                         },
2690                         .num_parents = 1,
2691                         .flags = CLK_SET_RATE_PARENT,
2692                         .ops = &clk_branch2_ops,
2693                 },
2694         },
2695 };
2696
2697 static struct clk_branch camss_cpp_axi_clk = {
2698         .halt_reg = 0x36c4,
2699         .clkr = {
2700                 .enable_reg = 0x36c4,
2701                 .enable_mask = BIT(0),
2702                 .hw.init = &(struct clk_init_data){
2703                         .name = "camss_cpp_axi_clk",
2704                         .parent_hws = (const struct clk_hw*[]){
2705                                 &axi_clk_src.clkr.hw
2706                         },
2707                         .num_parents = 1,
2708                         .flags = CLK_SET_RATE_PARENT,
2709                         .ops = &clk_branch2_ops,
2710                 },
2711         },
2712 };
2713
2714 static struct clk_branch camss_cpp_clk = {
2715         .halt_reg = 0x36b0,
2716         .clkr = {
2717                 .enable_reg = 0x36b0,
2718                 .enable_mask = BIT(0),
2719                 .hw.init = &(struct clk_init_data){
2720                         .name = "camss_cpp_clk",
2721                         .parent_hws = (const struct clk_hw*[]){
2722                                 &cpp_clk_src.clkr.hw
2723                         },
2724                         .num_parents = 1,
2725                         .flags = CLK_SET_RATE_PARENT,
2726                         .ops = &clk_branch2_ops,
2727                 },
2728         },
2729 };
2730
2731 static struct clk_branch camss_cpp_ahb_clk = {
2732         .halt_reg = 0x36b4,
2733         .clkr = {
2734                 .enable_reg = 0x36b4,
2735                 .enable_mask = BIT(0),
2736                 .hw.init = &(struct clk_init_data){
2737                         .name = "camss_cpp_ahb_clk",
2738                         .parent_hws = (const struct clk_hw*[]){
2739                                 &ahb_clk_src.clkr.hw
2740                         },
2741                         .num_parents = 1,
2742                         .flags = CLK_SET_RATE_PARENT,
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch camss_csi0_clk = {
2749         .halt_reg = 0x30b4,
2750         .clkr = {
2751                 .enable_reg = 0x30b4,
2752                 .enable_mask = BIT(0),
2753                 .hw.init = &(struct clk_init_data){
2754                         .name = "camss_csi0_clk",
2755                         .parent_hws = (const struct clk_hw*[]){
2756                                 &csi0_clk_src.clkr.hw
2757                         },
2758                         .num_parents = 1,
2759                         .flags = CLK_SET_RATE_PARENT,
2760                         .ops = &clk_branch2_ops,
2761                 },
2762         },
2763 };
2764
2765 static struct clk_branch camss_csi0_ahb_clk = {
2766         .halt_reg = 0x30bc,
2767         .clkr = {
2768                 .enable_reg = 0x30bc,
2769                 .enable_mask = BIT(0),
2770                 .hw.init = &(struct clk_init_data){
2771                         .name = "camss_csi0_ahb_clk",
2772                         .parent_hws = (const struct clk_hw*[]){
2773                                 &ahb_clk_src.clkr.hw
2774                         },
2775                         .num_parents = 1,
2776                         .flags = CLK_SET_RATE_PARENT,
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch camss_csi0phy_clk = {
2783         .halt_reg = 0x30c4,
2784         .clkr = {
2785                 .enable_reg = 0x30c4,
2786                 .enable_mask = BIT(0),
2787                 .hw.init = &(struct clk_init_data){
2788                         .name = "camss_csi0phy_clk",
2789                         .parent_hws = (const struct clk_hw*[]){
2790                                 &csi0_clk_src.clkr.hw
2791                         },
2792                         .num_parents = 1,
2793                         .flags = CLK_SET_RATE_PARENT,
2794                         .ops = &clk_branch2_ops,
2795                 },
2796         },
2797 };
2798
2799 static struct clk_branch camss_csi0rdi_clk = {
2800         .halt_reg = 0x30d4,
2801         .clkr = {
2802                 .enable_reg = 0x30d4,
2803                 .enable_mask = BIT(0),
2804                 .hw.init = &(struct clk_init_data){
2805                         .name = "camss_csi0rdi_clk",
2806                         .parent_hws = (const struct clk_hw*[]){
2807                                 &csi0_clk_src.clkr.hw
2808                         },
2809                         .num_parents = 1,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch camss_csi0pix_clk = {
2817         .halt_reg = 0x30e4,
2818         .clkr = {
2819                 .enable_reg = 0x30e4,
2820                 .enable_mask = BIT(0),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "camss_csi0pix_clk",
2823                         .parent_hws = (const struct clk_hw*[]){
2824                                 &csi0_clk_src.clkr.hw
2825                         },
2826                         .num_parents = 1,
2827                         .flags = CLK_SET_RATE_PARENT,
2828                         .ops = &clk_branch2_ops,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch camss_csi1_clk = {
2834         .halt_reg = 0x3124,
2835         .clkr = {
2836                 .enable_reg = 0x3124,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data){
2839                         .name = "camss_csi1_clk",
2840                         .parent_hws = (const struct clk_hw*[]){
2841                                 &csi1_clk_src.clkr.hw
2842                         },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch camss_csi1_ahb_clk = {
2851         .halt_reg = 0x3128,
2852         .clkr = {
2853                 .enable_reg = 0x3128,
2854                 .enable_mask = BIT(0),
2855                 .hw.init = &(struct clk_init_data){
2856                         .name = "camss_csi1_ahb_clk",
2857                         .parent_hws = (const struct clk_hw*[]){
2858                                 &ahb_clk_src.clkr.hw
2859                         },
2860                         .num_parents = 1,
2861                         .flags = CLK_SET_RATE_PARENT,
2862                         .ops = &clk_branch2_ops,
2863                 },
2864         },
2865 };
2866
2867 static struct clk_branch camss_csi1phy_clk = {
2868         .halt_reg = 0x3134,
2869         .clkr = {
2870                 .enable_reg = 0x3134,
2871                 .enable_mask = BIT(0),
2872                 .hw.init = &(struct clk_init_data){
2873                         .name = "camss_csi1phy_clk",
2874                         .parent_hws = (const struct clk_hw*[]){
2875                                 &csi1_clk_src.clkr.hw
2876                         },
2877                         .num_parents = 1,
2878                         .flags = CLK_SET_RATE_PARENT,
2879                         .ops = &clk_branch2_ops,
2880                 },
2881         },
2882 };
2883
2884 static struct clk_branch camss_csi1rdi_clk = {
2885         .halt_reg = 0x3144,
2886         .clkr = {
2887                 .enable_reg = 0x3144,
2888                 .enable_mask = BIT(0),
2889                 .hw.init = &(struct clk_init_data){
2890                         .name = "camss_csi1rdi_clk",
2891                         .parent_hws = (const struct clk_hw*[]){
2892                                 &csi1_clk_src.clkr.hw
2893                         },
2894                         .num_parents = 1,
2895                         .flags = CLK_SET_RATE_PARENT,
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch camss_csi1pix_clk = {
2902         .halt_reg = 0x3154,
2903         .clkr = {
2904                 .enable_reg = 0x3154,
2905                 .enable_mask = BIT(0),
2906                 .hw.init = &(struct clk_init_data){
2907                         .name = "camss_csi1pix_clk",
2908                         .parent_hws = (const struct clk_hw*[]){
2909                                 &csi1_clk_src.clkr.hw
2910                         },
2911                         .num_parents = 1,
2912                         .flags = CLK_SET_RATE_PARENT,
2913                         .ops = &clk_branch2_ops,
2914                 },
2915         },
2916 };
2917
2918 static struct clk_branch camss_csi2_clk = {
2919         .halt_reg = 0x3184,
2920         .clkr = {
2921                 .enable_reg = 0x3184,
2922                 .enable_mask = BIT(0),
2923                 .hw.init = &(struct clk_init_data){
2924                         .name = "camss_csi2_clk",
2925                         .parent_hws = (const struct clk_hw*[]){
2926                                 &csi2_clk_src.clkr.hw
2927                         },
2928                         .num_parents = 1,
2929                         .flags = CLK_SET_RATE_PARENT,
2930                         .ops = &clk_branch2_ops,
2931                 },
2932         },
2933 };
2934
2935 static struct clk_branch camss_csi2_ahb_clk = {
2936         .halt_reg = 0x3188,
2937         .clkr = {
2938                 .enable_reg = 0x3188,
2939                 .enable_mask = BIT(0),
2940                 .hw.init = &(struct clk_init_data){
2941                         .name = "camss_csi2_ahb_clk",
2942                         .parent_hws = (const struct clk_hw*[]){
2943                                 &ahb_clk_src.clkr.hw
2944                         },
2945                         .num_parents = 1,
2946                         .flags = CLK_SET_RATE_PARENT,
2947                         .ops = &clk_branch2_ops,
2948                 },
2949         },
2950 };
2951
2952 static struct clk_branch camss_csi2phy_clk = {
2953         .halt_reg = 0x3194,
2954         .clkr = {
2955                 .enable_reg = 0x3194,
2956                 .enable_mask = BIT(0),
2957                 .hw.init = &(struct clk_init_data){
2958                         .name = "camss_csi2phy_clk",
2959                         .parent_hws = (const struct clk_hw*[]){
2960                                 &csi2_clk_src.clkr.hw
2961                         },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch camss_csi2rdi_clk = {
2970         .halt_reg = 0x31a4,
2971         .clkr = {
2972                 .enable_reg = 0x31a4,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "camss_csi2rdi_clk",
2976                         .parent_hws = (const struct clk_hw*[]){
2977                                 &csi2_clk_src.clkr.hw
2978                         },
2979                         .num_parents = 1,
2980                         .flags = CLK_SET_RATE_PARENT,
2981                         .ops = &clk_branch2_ops,
2982                 },
2983         },
2984 };
2985
2986 static struct clk_branch camss_csi2pix_clk = {
2987         .halt_reg = 0x31b4,
2988         .clkr = {
2989                 .enable_reg = 0x31b4,
2990                 .enable_mask = BIT(0),
2991                 .hw.init = &(struct clk_init_data){
2992                         .name = "camss_csi2pix_clk",
2993                         .parent_hws = (const struct clk_hw*[]){
2994                                 &csi2_clk_src.clkr.hw
2995                         },
2996                         .num_parents = 1,
2997                         .flags = CLK_SET_RATE_PARENT,
2998                         .ops = &clk_branch2_ops,
2999                 },
3000         },
3001 };
3002
3003 static struct clk_branch camss_csi3_clk = {
3004         .halt_reg = 0x31e4,
3005         .clkr = {
3006                 .enable_reg = 0x31e4,
3007                 .enable_mask = BIT(0),
3008                 .hw.init = &(struct clk_init_data){
3009                         .name = "camss_csi3_clk",
3010                         .parent_hws = (const struct clk_hw*[]){
3011                                 &csi3_clk_src.clkr.hw
3012                         },
3013                         .num_parents = 1,
3014                         .flags = CLK_SET_RATE_PARENT,
3015                         .ops = &clk_branch2_ops,
3016                 },
3017         },
3018 };
3019
3020 static struct clk_branch camss_csi3_ahb_clk = {
3021         .halt_reg = 0x31e8,
3022         .clkr = {
3023                 .enable_reg = 0x31e8,
3024                 .enable_mask = BIT(0),
3025                 .hw.init = &(struct clk_init_data){
3026                         .name = "camss_csi3_ahb_clk",
3027                         .parent_hws = (const struct clk_hw*[]){
3028                                 &ahb_clk_src.clkr.hw
3029                         },
3030                         .num_parents = 1,
3031                         .flags = CLK_SET_RATE_PARENT,
3032                         .ops = &clk_branch2_ops,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_branch camss_csi3phy_clk = {
3038         .halt_reg = 0x31f4,
3039         .clkr = {
3040                 .enable_reg = 0x31f4,
3041                 .enable_mask = BIT(0),
3042                 .hw.init = &(struct clk_init_data){
3043                         .name = "camss_csi3phy_clk",
3044                         .parent_hws = (const struct clk_hw*[]){
3045                                 &csi3_clk_src.clkr.hw
3046                         },
3047                         .num_parents = 1,
3048                         .flags = CLK_SET_RATE_PARENT,
3049                         .ops = &clk_branch2_ops,
3050                 },
3051         },
3052 };
3053
3054 static struct clk_branch camss_csi3rdi_clk = {
3055         .halt_reg = 0x3204,
3056         .clkr = {
3057                 .enable_reg = 0x3204,
3058                 .enable_mask = BIT(0),
3059                 .hw.init = &(struct clk_init_data){
3060                         .name = "camss_csi3rdi_clk",
3061                         .parent_hws = (const struct clk_hw*[]){
3062                                 &csi3_clk_src.clkr.hw
3063                         },
3064                         .num_parents = 1,
3065                         .flags = CLK_SET_RATE_PARENT,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch camss_csi3pix_clk = {
3072         .halt_reg = 0x3214,
3073         .clkr = {
3074                 .enable_reg = 0x3214,
3075                 .enable_mask = BIT(0),
3076                 .hw.init = &(struct clk_init_data){
3077                         .name = "camss_csi3pix_clk",
3078                         .parent_hws = (const struct clk_hw*[]){
3079                                 &csi3_clk_src.clkr.hw
3080                         },
3081                         .num_parents = 1,
3082                         .flags = CLK_SET_RATE_PARENT,
3083                         .ops = &clk_branch2_ops,
3084                 },
3085         },
3086 };
3087
3088 static struct clk_branch camss_ispif_ahb_clk = {
3089         .halt_reg = 0x3224,
3090         .clkr = {
3091                 .enable_reg = 0x3224,
3092                 .enable_mask = BIT(0),
3093                 .hw.init = &(struct clk_init_data){
3094                         .name = "camss_ispif_ahb_clk",
3095                         .parent_hws = (const struct clk_hw*[]){
3096                                 &ahb_clk_src.clkr.hw
3097                         },
3098                         .num_parents = 1,
3099                         .flags = CLK_SET_RATE_PARENT,
3100                         .ops = &clk_branch2_ops,
3101                 },
3102         },
3103 };
3104
3105 static struct clk_branch fd_core_clk = {
3106         .halt_reg = 0x3b68,
3107         .clkr = {
3108                 .enable_reg = 0x3b68,
3109                 .enable_mask = BIT(0),
3110                 .hw.init = &(struct clk_init_data){
3111                         .name = "fd_core_clk",
3112                         .parent_hws = (const struct clk_hw*[]){
3113                                 &fd_core_clk_src.clkr.hw
3114                         },
3115                         .num_parents = 1,
3116                         .flags = CLK_SET_RATE_PARENT,
3117                         .ops = &clk_branch2_ops,
3118                 },
3119         },
3120 };
3121
3122 static struct clk_branch fd_core_uar_clk = {
3123         .halt_reg = 0x3b6c,
3124         .clkr = {
3125                 .enable_reg = 0x3b6c,
3126                 .enable_mask = BIT(0),
3127                 .hw.init = &(struct clk_init_data){
3128                         .name = "fd_core_uar_clk",
3129                         .parent_hws = (const struct clk_hw*[]){
3130                                 &fd_core_clk_src.clkr.hw
3131                         },
3132                         .num_parents = 1,
3133                         .flags = CLK_SET_RATE_PARENT,
3134                         .ops = &clk_branch2_ops,
3135                 },
3136         },
3137 };
3138
3139 static struct clk_branch fd_ahb_clk = {
3140         .halt_reg = 0x3ba74,
3141         .clkr = {
3142                 .enable_reg = 0x3ba74,
3143                 .enable_mask = BIT(0),
3144                 .hw.init = &(struct clk_init_data){
3145                         .name = "fd_ahb_clk",
3146                         .parent_hws = (const struct clk_hw*[]){
3147                                 &ahb_clk_src.clkr.hw
3148                         },
3149                         .num_parents = 1,
3150                         .flags = CLK_SET_RATE_PARENT,
3151                         .ops = &clk_branch2_ops,
3152                 },
3153         },
3154 };
3155
3156 static struct clk_hw *mmcc_msm8996_hws[] = {
3157         &gpll0_div.hw,
3158 };
3159
3160 static struct gdsc mmagic_bimc_gdsc = {
3161         .gdscr = 0x529c,
3162         .pd = {
3163                 .name = "mmagic_bimc",
3164         },
3165         .pwrsts = PWRSTS_OFF_ON,
3166         .flags = ALWAYS_ON,
3167 };
3168
3169 static struct gdsc mmagic_video_gdsc = {
3170         .gdscr = 0x119c,
3171         .gds_hw_ctrl = 0x120c,
3172         .pd = {
3173                 .name = "mmagic_video",
3174         },
3175         .pwrsts = PWRSTS_OFF_ON,
3176         .flags = VOTABLE | ALWAYS_ON,
3177 };
3178
3179 static struct gdsc mmagic_mdss_gdsc = {
3180         .gdscr = 0x247c,
3181         .gds_hw_ctrl = 0x2480,
3182         .pd = {
3183                 .name = "mmagic_mdss",
3184         },
3185         .pwrsts = PWRSTS_OFF_ON,
3186         .flags = VOTABLE | ALWAYS_ON,
3187 };
3188
3189 static struct gdsc mmagic_camss_gdsc = {
3190         .gdscr = 0x3c4c,
3191         .gds_hw_ctrl = 0x3c50,
3192         .pd = {
3193                 .name = "mmagic_camss",
3194         },
3195         .pwrsts = PWRSTS_OFF_ON,
3196         .flags = VOTABLE | ALWAYS_ON,
3197 };
3198
3199 static struct gdsc venus_gdsc = {
3200         .gdscr = 0x1024,
3201         .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3202         .cxc_count = 3,
3203         .pd = {
3204                 .name = "venus",
3205         },
3206         .parent = &mmagic_video_gdsc.pd,
3207         .pwrsts = PWRSTS_OFF_ON,
3208 };
3209
3210 static struct gdsc venus_core0_gdsc = {
3211         .gdscr = 0x1040,
3212         .cxcs = (unsigned int []){ 0x1048 },
3213         .cxc_count = 1,
3214         .pd = {
3215                 .name = "venus_core0",
3216         },
3217         .parent = &venus_gdsc.pd,
3218         .pwrsts = PWRSTS_OFF_ON,
3219         .flags = HW_CTRL,
3220 };
3221
3222 static struct gdsc venus_core1_gdsc = {
3223         .gdscr = 0x1044,
3224         .cxcs = (unsigned int []){ 0x104c },
3225         .cxc_count = 1,
3226         .pd = {
3227                 .name = "venus_core1",
3228         },
3229         .parent = &venus_gdsc.pd,
3230         .pwrsts = PWRSTS_OFF_ON,
3231         .flags = HW_CTRL,
3232 };
3233
3234 static struct gdsc camss_gdsc = {
3235         .gdscr = 0x34a0,
3236         .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3237         .cxc_count = 2,
3238         .pd = {
3239                 .name = "camss",
3240         },
3241         .parent = &mmagic_camss_gdsc.pd,
3242         .pwrsts = PWRSTS_OFF_ON,
3243 };
3244
3245 static struct gdsc vfe0_gdsc = {
3246         .gdscr = 0x3664,
3247         .cxcs = (unsigned int []){ 0x36a8 },
3248         .cxc_count = 1,
3249         .pd = {
3250                 .name = "vfe0",
3251         },
3252         .parent = &camss_gdsc.pd,
3253         .pwrsts = PWRSTS_OFF_ON,
3254 };
3255
3256 static struct gdsc vfe1_gdsc = {
3257         .gdscr = 0x3674,
3258         .cxcs = (unsigned int []){ 0x36ac },
3259         .cxc_count = 1,
3260         .pd = {
3261                 .name = "vfe1",
3262         },
3263         .parent = &camss_gdsc.pd,
3264         .pwrsts = PWRSTS_OFF_ON,
3265 };
3266
3267 static struct gdsc jpeg_gdsc = {
3268         .gdscr = 0x35a4,
3269         .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3270         .cxc_count = 4,
3271         .pd = {
3272                 .name = "jpeg",
3273         },
3274         .parent = &camss_gdsc.pd,
3275         .pwrsts = PWRSTS_OFF_ON,
3276 };
3277
3278 static struct gdsc cpp_gdsc = {
3279         .gdscr = 0x36d4,
3280         .cxcs = (unsigned int []){ 0x36b0 },
3281         .cxc_count = 1,
3282         .pd = {
3283                 .name = "cpp",
3284         },
3285         .parent = &camss_gdsc.pd,
3286         .pwrsts = PWRSTS_OFF_ON,
3287 };
3288
3289 static struct gdsc fd_gdsc = {
3290         .gdscr = 0x3b64,
3291         .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3292         .cxc_count = 2,
3293         .pd = {
3294                 .name = "fd",
3295         },
3296         .parent = &camss_gdsc.pd,
3297         .pwrsts = PWRSTS_OFF_ON,
3298 };
3299
3300 static struct gdsc mdss_gdsc = {
3301         .gdscr = 0x2304,
3302         .cxcs = (unsigned int []){ 0x2310, 0x231c },
3303         .cxc_count = 2,
3304         .pd = {
3305                 .name = "mdss",
3306         },
3307         .parent = &mmagic_mdss_gdsc.pd,
3308         .pwrsts = PWRSTS_OFF_ON,
3309 };
3310
3311 static struct gdsc gpu_gdsc = {
3312         .gdscr = 0x4034,
3313         .gds_hw_ctrl = 0x4038,
3314         .pd = {
3315                 .name = "gpu",
3316         },
3317         .pwrsts = PWRSTS_OFF_ON,
3318         .flags = VOTABLE,
3319 };
3320
3321 static struct gdsc gpu_gx_gdsc = {
3322         .gdscr = 0x4024,
3323         .clamp_io_ctrl = 0x4300,
3324         .cxcs = (unsigned int []){ 0x4028 },
3325         .cxc_count = 1,
3326         .pd = {
3327                 .name = "gpu_gx",
3328         },
3329         .pwrsts = PWRSTS_OFF_ON,
3330         .parent = &gpu_gdsc.pd,
3331         .flags = CLAMP_IO,
3332         .supply = "vdd-gfx",
3333 };
3334
3335 static struct clk_regmap *mmcc_msm8996_clocks[] = {
3336         [MMPLL0_EARLY] = &mmpll0_early.clkr,
3337         [MMPLL0_PLL] = &mmpll0.clkr,
3338         [MMPLL1_EARLY] = &mmpll1_early.clkr,
3339         [MMPLL1_PLL] = &mmpll1.clkr,
3340         [MMPLL2_EARLY] = &mmpll2_early.clkr,
3341         [MMPLL2_PLL] = &mmpll2.clkr,
3342         [MMPLL3_EARLY] = &mmpll3_early.clkr,
3343         [MMPLL3_PLL] = &mmpll3.clkr,
3344         [MMPLL4_EARLY] = &mmpll4_early.clkr,
3345         [MMPLL4_PLL] = &mmpll4.clkr,
3346         [MMPLL5_EARLY] = &mmpll5_early.clkr,
3347         [MMPLL5_PLL] = &mmpll5.clkr,
3348         [MMPLL8_EARLY] = &mmpll8_early.clkr,
3349         [MMPLL8_PLL] = &mmpll8.clkr,
3350         [MMPLL9_EARLY] = &mmpll9_early.clkr,
3351         [MMPLL9_PLL] = &mmpll9.clkr,
3352         [AHB_CLK_SRC] = &ahb_clk_src.clkr,
3353         [AXI_CLK_SRC] = &axi_clk_src.clkr,
3354         [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3355         [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
3356         [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3357         [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3358         [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3359         [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3360         [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3361         [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3362         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3363         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3364         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3365         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3366         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3367         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3368         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3369         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3370         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3371         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3372         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3373         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3374         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3375         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3376         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3377         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3378         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3379         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3380         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3381         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3382         [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3383         [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3384         [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3385         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3386         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3387         [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3388         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3389         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3390         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3391         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3392         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3393         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3394         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3395         [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3396         [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3397         [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3398         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3399         [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3400         [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3401         [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3402         [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3403         [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3404         [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3405         [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3406         [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3407         [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3408         [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3409         [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3410         [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3411         [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3412         [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3413         [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3414         [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3415         [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3416         [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3417         [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3418         [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3419         [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3420         [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3421         [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3422         [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3423         [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3424         [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3425         [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3426         [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3427         [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3428         [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3429         [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3430         [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3431         [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3432         [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3433         [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3434         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3435         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3436         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3437         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3438         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3439         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3440         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3441         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3442         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3443         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3444         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3445         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3446         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3447         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3448         [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3449         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3450         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3451         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3452         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3453         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3454         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3455         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3456         [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3457         [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3458         [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3459         [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3460         [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3461         [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3462         [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3463         [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3464         [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3465         [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3466         [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3467         [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3468         [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3469         [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3470         [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3471         [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3472         [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3473         [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3474         [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3475         [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3476         [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3477         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3478         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3479         [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3480         [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3481         [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3482         [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3483         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3484         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3485         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3486         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3487         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3488         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3489         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3490         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3491         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3492         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3493         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3494         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3495         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3496         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3497         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3498         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3499         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3500         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3501         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3502         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3503         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3504         [FD_CORE_CLK] = &fd_core_clk.clkr,
3505         [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3506         [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3507 };
3508
3509 static struct gdsc *mmcc_msm8996_gdscs[] = {
3510         [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3511         [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3512         [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3513         [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3514         [VENUS_GDSC] = &venus_gdsc,
3515         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3516         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3517         [CAMSS_GDSC] = &camss_gdsc,
3518         [VFE0_GDSC] = &vfe0_gdsc,
3519         [VFE1_GDSC] = &vfe1_gdsc,
3520         [JPEG_GDSC] = &jpeg_gdsc,
3521         [CPP_GDSC] = &cpp_gdsc,
3522         [FD_GDSC] = &fd_gdsc,
3523         [MDSS_GDSC] = &mdss_gdsc,
3524         [GPU_GDSC] = &gpu_gdsc,
3525         [GPU_GX_GDSC] = &gpu_gx_gdsc,
3526 };
3527
3528 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3529         [MMAGICAHB_BCR] = { 0x5020 },
3530         [MMAGIC_CFG_BCR] = { 0x5050 },
3531         [MISC_BCR] = { 0x5010 },
3532         [BTO_BCR] = { 0x5030 },
3533         [MMAGICAXI_BCR] = { 0x5060 },
3534         [MMAGICMAXI_BCR] = { 0x5070 },
3535         [DSA_BCR] = { 0x50a0 },
3536         [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3537         [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3538         [SMMU_VFE_BCR] = { 0x3c00 },
3539         [SMMU_CPP_BCR] = { 0x3c10 },
3540         [SMMU_JPEG_BCR] = { 0x3c20 },
3541         [MMAGIC_MDSS_BCR] = { 0x2470 },
3542         [THROTTLE_MDSS_BCR] = { 0x2460 },
3543         [SMMU_ROT_BCR] = { 0x2440 },
3544         [SMMU_MDP_BCR] = { 0x2450 },
3545         [MMAGIC_VIDEO_BCR] = { 0x1190 },
3546         [THROTTLE_VIDEO_BCR] = { 0x1180 },
3547         [SMMU_VIDEO_BCR] = { 0x1170 },
3548         [MMAGIC_BIMC_BCR] = { 0x5290 },
3549         [GPU_GX_BCR] = { 0x4020 },
3550         [GPU_BCR] = { 0x4030 },
3551         [GPU_AON_BCR] = { 0x4040 },
3552         [VMEM_BCR] = { 0x1200 },
3553         [MMSS_RBCPR_BCR] = { 0x4080 },
3554         [VIDEO_BCR] = { 0x1020 },
3555         [MDSS_BCR] = { 0x2300 },
3556         [CAMSS_TOP_BCR] = { 0x3480 },
3557         [CAMSS_AHB_BCR] = { 0x3488 },
3558         [CAMSS_MICRO_BCR] = { 0x3490 },
3559         [CAMSS_CCI_BCR] = { 0x3340 },
3560         [CAMSS_PHY0_BCR] = { 0x3020 },
3561         [CAMSS_PHY1_BCR] = { 0x3050 },
3562         [CAMSS_PHY2_BCR] = { 0x3080 },
3563         [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3564         [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3565         [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3566         [CAMSS_JPEG_BCR] = { 0x35a0 },
3567         [CAMSS_VFE_BCR] = { 0x36a0 },
3568         [CAMSS_VFE0_BCR] = { 0x3660 },
3569         [CAMSS_VFE1_BCR] = { 0x3670 },
3570         [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3571         [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3572         [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3573         [CAMSS_CPP_BCR] = { 0x36d0 },
3574         [CAMSS_CSI0_BCR] = { 0x30b0 },
3575         [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3576         [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3577         [CAMSS_CSI1_BCR] = { 0x3120 },
3578         [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3579         [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3580         [CAMSS_CSI2_BCR] = { 0x3180 },
3581         [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3582         [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3583         [CAMSS_CSI3_BCR] = { 0x31e0 },
3584         [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3585         [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3586         [CAMSS_ISPIF_BCR] = { 0x3220 },
3587         [FD_BCR] = { 0x3b60 },
3588         [MMSS_SPDM_RM_BCR] = { 0x300 },
3589 };
3590
3591 static const struct regmap_config mmcc_msm8996_regmap_config = {
3592         .reg_bits       = 32,
3593         .reg_stride     = 4,
3594         .val_bits       = 32,
3595         .max_register   = 0xb008,
3596         .fast_io        = true,
3597 };
3598
3599 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3600         .config = &mmcc_msm8996_regmap_config,
3601         .clks = mmcc_msm8996_clocks,
3602         .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3603         .resets = mmcc_msm8996_resets,
3604         .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3605         .gdscs = mmcc_msm8996_gdscs,
3606         .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3607         .clk_hws = mmcc_msm8996_hws,
3608         .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
3609 };
3610
3611 static const struct of_device_id mmcc_msm8996_match_table[] = {
3612         { .compatible = "qcom,mmcc-msm8996" },
3613         { }
3614 };
3615 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3616
3617 static int mmcc_msm8996_probe(struct platform_device *pdev)
3618 {
3619         struct regmap *regmap;
3620
3621         regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3622         if (IS_ERR(regmap))
3623                 return PTR_ERR(regmap);
3624
3625         /* Disable the AHB DCD */
3626         regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3627         /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3628         regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3629
3630         return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3631 }
3632
3633 static struct platform_driver mmcc_msm8996_driver = {
3634         .probe          = mmcc_msm8996_probe,
3635         .driver         = {
3636                 .name   = "mmcc-msm8996",
3637                 .of_match_table = mmcc_msm8996_match_table,
3638         },
3639 };
3640 module_platform_driver(mmcc_msm8996_driver);
3641
3642 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3643 MODULE_LICENSE("GPL v2");
3644 MODULE_ALIAS("platform:mmcc-msm8996");