1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16 #include <linux/clk.h>
18 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
21 #include "clk-regmap.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-alpha-pll.h"
25 #include "clk-branch.h"
37 P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
44 static const struct parent_map mmcc_xo_gpll0_map[] = {
49 static const struct clk_parent_data mmcc_xo_gpll0[] = {
51 { .fw_name = "gpll0" },
54 static const struct parent_map mmss_xo_hdmi_map[] = {
59 static const struct clk_parent_data mmss_xo_hdmi[] = {
61 { .fw_name = "hdmipll" },
64 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
70 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
72 { .fw_name = "dsi0pll" },
73 { .fw_name = "dsi1pll" },
76 static const struct parent_map mmcc_xo_dsibyte_map[] = {
78 { P_DSI0PLL_BYTE, 1 },
82 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
84 { .fw_name = "dsi0pllbyte" },
85 { .fw_name = "dsi1pllbyte" },
88 static struct pll_vco mmpll_p_vco[] = {
89 { 250000000, 500000000, 3 },
90 { 500000000, 1000000000, 2 },
91 { 1000000000, 1500000000, 1 },
92 { 1500000000, 2000000000, 0 },
95 static struct pll_vco mmpll_t_vco[] = {
96 { 500000000, 1500000000, 0 },
99 static const struct alpha_pll_config mmpll_p_config = {
100 .post_div_mask = 0xf00,
103 static struct clk_alpha_pll mmpll0_early = {
105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
106 .vco_table = mmpll_p_vco,
107 .num_vco = ARRAY_SIZE(mmpll_p_vco),
110 .enable_mask = BIT(0),
111 .hw.init = &(struct clk_init_data){
112 .name = "mmpll0_early",
113 .parent_data = &(const struct clk_parent_data){
117 .ops = &clk_alpha_pll_ops,
122 static struct clk_alpha_pll_postdiv mmpll0 = {
124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
126 .clkr.hw.init = &(struct clk_init_data){
128 .parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
130 .ops = &clk_alpha_pll_postdiv_ops,
131 .flags = CLK_SET_RATE_PARENT,
135 static struct clk_alpha_pll mmpll1_early = {
137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
138 .vco_table = mmpll_p_vco,
139 .num_vco = ARRAY_SIZE(mmpll_p_vco),
142 .enable_mask = BIT(1),
143 .hw.init = &(struct clk_init_data){
144 .name = "mmpll1_early",
145 .parent_data = &(const struct clk_parent_data){
149 .ops = &clk_alpha_pll_ops,
154 static struct clk_alpha_pll_postdiv mmpll1 = {
156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
158 .clkr.hw.init = &(struct clk_init_data){
160 .parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
162 .ops = &clk_alpha_pll_postdiv_ops,
163 .flags = CLK_SET_RATE_PARENT,
167 static struct clk_alpha_pll mmpll3_early = {
169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
170 .vco_table = mmpll_p_vco,
171 .num_vco = ARRAY_SIZE(mmpll_p_vco),
172 .clkr.hw.init = &(struct clk_init_data){
173 .name = "mmpll3_early",
174 .parent_data = &(const struct clk_parent_data){
178 .ops = &clk_alpha_pll_ops,
182 static struct clk_alpha_pll_postdiv mmpll3 = {
184 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
186 .clkr.hw.init = &(struct clk_init_data){
188 .parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
190 .ops = &clk_alpha_pll_postdiv_ops,
191 .flags = CLK_SET_RATE_PARENT,
195 static struct clk_alpha_pll mmpll4_early = {
197 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
198 .vco_table = mmpll_t_vco,
199 .num_vco = ARRAY_SIZE(mmpll_t_vco),
200 .clkr.hw.init = &(struct clk_init_data){
201 .name = "mmpll4_early",
202 .parent_data = &(const struct clk_parent_data){
206 .ops = &clk_alpha_pll_ops,
210 static struct clk_alpha_pll_postdiv mmpll4 = {
212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
214 .clkr.hw.init = &(struct clk_init_data){
216 .parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
218 .ops = &clk_alpha_pll_postdiv_ops,
219 .flags = CLK_SET_RATE_PARENT,
223 static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
229 static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
231 { .fw_name = "gpll0" },
232 { .hw = &mmpll1.clkr.hw },
235 static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
241 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
243 { .fw_name = "gpll0" },
244 { .hw = &mmpll0.clkr.hw },
247 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
254 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
256 { .fw_name = "gpll0" },
257 { .hw = &mmpll0.clkr.hw },
258 { .hw = &mmpll3.clkr.hw },
261 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
268 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
270 { .fw_name = "gpll0" },
271 { .hw = &mmpll0.clkr.hw },
272 { .hw = &mmpll4.clkr.hw },
275 static struct clk_alpha_pll mmpll5_early = {
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
278 .vco_table = mmpll_p_vco,
279 .num_vco = ARRAY_SIZE(mmpll_p_vco),
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "mmpll5_early",
282 .parent_data = &(const struct clk_parent_data){
286 .ops = &clk_alpha_pll_ops,
290 static struct clk_alpha_pll_postdiv mmpll5 = {
292 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
294 .clkr.hw.init = &(struct clk_init_data){
296 .parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
298 .ops = &clk_alpha_pll_postdiv_ops,
299 .flags = CLK_SET_RATE_PARENT,
303 static const struct freq_tbl ftbl_ahb_clk_src[] = {
304 /* Note: There might be more frequencies desired here. */
305 F(19200000, P_XO, 1, 0, 0),
306 F(40000000, P_GPLL0, 15, 0, 0),
307 F(80000000, P_MMPLL0, 10, 0, 0),
311 static struct clk_rcg2 ahb_clk_src = {
314 .parent_map = mmcc_xo_gpll0_mmpll0_map,
315 .freq_tbl = ftbl_ahb_clk_src,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "ahb_clk_src",
318 .parent_data = mmcc_xo_gpll0_mmpll0,
319 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
320 .ops = &clk_rcg2_ops,
324 static const struct freq_tbl ftbl_axi_clk_src[] = {
325 F(75000000, P_GPLL0, 8, 0, 0),
326 F(150000000, P_GPLL0, 4, 0, 0),
327 F(333430000, P_MMPLL1, 3.5, 0, 0),
328 F(466800000, P_MMPLL1, 2.5, 0, 0),
332 static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
333 F(75000000, P_GPLL0, 8, 0, 0),
334 F(150000000, P_GPLL0, 4, 0, 0),
335 F(300000000, P_GPLL0, 2, 0, 0),
336 F(404000000, P_MMPLL1, 2, 0, 0),
340 static struct clk_rcg2 axi_clk_src = {
343 .parent_map = mmcc_xo_gpll0_mmpll1_map,
344 .freq_tbl = ftbl_axi_clk_src,
345 .clkr.hw.init = &(struct clk_init_data){
346 .name = "axi_clk_src",
347 .parent_data = mmcc_xo_gpll0_mmpll1,
348 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
349 .ops = &clk_rcg2_ops,
353 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
354 F(100000000, P_GPLL0, 6, 0, 0),
355 F(240000000, P_GPLL0, 2.5, 0, 0),
356 F(266670000, P_MMPLL0, 3, 0, 0),
360 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
361 F(100000000, P_GPLL0, 6, 0, 0),
362 F(266670000, P_MMPLL0, 3, 0, 0),
366 static struct clk_rcg2 csi0_clk_src = {
369 .parent_map = mmcc_xo_gpll0_mmpll0_map,
370 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
371 .clkr.hw.init = &(struct clk_init_data){
372 .name = "csi0_clk_src",
373 .parent_data = mmcc_xo_gpll0_mmpll0,
374 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
375 .ops = &clk_rcg2_ops,
379 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
380 F(66670000, P_GPLL0, 9, 0, 0),
381 F(100000000, P_GPLL0, 6, 0, 0),
382 F(133330000, P_GPLL0, 4.5, 0, 0),
383 F(150000000, P_GPLL0, 4, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
385 F(240000000, P_GPLL0, 2.5, 0, 0),
386 F(266670000, P_MMPLL0, 3, 0, 0),
387 F(320000000, P_MMPLL0, 2.5, 0, 0),
388 F(510000000, P_MMPLL3, 2, 0, 0),
392 static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
393 F(66670000, P_GPLL0, 9, 0, 0),
394 F(100000000, P_GPLL0, 6, 0, 0),
395 F(133330000, P_GPLL0, 4.5, 0, 0),
396 F(200000000, P_MMPLL0, 4, 0, 0),
397 F(320000000, P_MMPLL0, 2.5, 0, 0),
398 F(510000000, P_MMPLL3, 2, 0, 0),
402 static struct clk_rcg2 vcodec0_clk_src = {
406 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
407 .freq_tbl = ftbl_vcodec0_clk_src,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "vcodec0_clk_src",
410 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
411 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
412 .ops = &clk_rcg2_ops,
416 static struct clk_rcg2 csi1_clk_src = {
419 .parent_map = mmcc_xo_gpll0_mmpll0_map,
420 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "csi1_clk_src",
423 .parent_data = mmcc_xo_gpll0_mmpll0,
424 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
425 .ops = &clk_rcg2_ops,
429 static struct clk_rcg2 csi2_clk_src = {
432 .parent_map = mmcc_xo_gpll0_mmpll0_map,
433 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "csi2_clk_src",
436 .parent_data = mmcc_xo_gpll0_mmpll0,
437 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
438 .ops = &clk_rcg2_ops,
442 static struct clk_rcg2 csi3_clk_src = {
445 .parent_map = mmcc_xo_gpll0_mmpll0_map,
446 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "csi3_clk_src",
449 .parent_data = mmcc_xo_gpll0_mmpll0,
450 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
451 .ops = &clk_rcg2_ops,
455 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
456 F(80000000, P_GPLL0, 7.5, 0, 0),
457 F(100000000, P_GPLL0, 6, 0, 0),
458 F(200000000, P_GPLL0, 3, 0, 0),
459 F(320000000, P_MMPLL0, 2.5, 0, 0),
460 F(400000000, P_MMPLL0, 2, 0, 0),
461 F(480000000, P_MMPLL4, 2, 0, 0),
462 F(533330000, P_MMPLL0, 1.5, 0, 0),
463 F(600000000, P_GPLL0, 1, 0, 0),
467 static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
468 F(80000000, P_GPLL0, 7.5, 0, 0),
469 F(100000000, P_GPLL0, 6, 0, 0),
470 F(200000000, P_GPLL0, 3, 0, 0),
471 F(320000000, P_MMPLL0, 2.5, 0, 0),
472 F(480000000, P_MMPLL4, 2, 0, 0),
473 F(600000000, P_GPLL0, 1, 0, 0),
477 static struct clk_rcg2 vfe0_clk_src = {
480 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
481 .freq_tbl = ftbl_vfe0_clk_src,
482 .clkr.hw.init = &(struct clk_init_data){
483 .name = "vfe0_clk_src",
484 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
485 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
486 .ops = &clk_rcg2_ops,
490 static const struct freq_tbl ftbl_vfe1_clk_src[] = {
491 F(80000000, P_GPLL0, 7.5, 0, 0),
492 F(100000000, P_GPLL0, 6, 0, 0),
493 F(200000000, P_GPLL0, 3, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 F(400000000, P_MMPLL0, 2, 0, 0),
496 F(533330000, P_MMPLL0, 1.5, 0, 0),
500 static struct clk_rcg2 vfe1_clk_src = {
503 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
504 .freq_tbl = ftbl_vfe1_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "vfe1_clk_src",
507 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
508 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
509 .ops = &clk_rcg2_ops,
513 static const struct freq_tbl ftbl_cpp_clk_src[] = {
514 F(100000000, P_GPLL0, 6, 0, 0),
515 F(200000000, P_GPLL0, 3, 0, 0),
516 F(320000000, P_MMPLL0, 2.5, 0, 0),
517 F(480000000, P_MMPLL4, 2, 0, 0),
518 F(600000000, P_GPLL0, 1, 0, 0),
519 F(640000000, P_MMPLL4, 1.5, 0, 0),
523 static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
524 F(100000000, P_GPLL0, 6, 0, 0),
525 F(200000000, P_GPLL0, 3, 0, 0),
526 F(320000000, P_MMPLL0, 2.5, 0, 0),
527 F(480000000, P_MMPLL4, 2, 0, 0),
528 F(640000000, P_MMPLL4, 1.5, 0, 0),
532 static struct clk_rcg2 cpp_clk_src = {
535 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
536 .freq_tbl = ftbl_cpp_clk_src,
537 .clkr.hw.init = &(struct clk_init_data){
538 .name = "cpp_clk_src",
539 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
540 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
541 .ops = &clk_rcg2_ops,
545 static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
546 F(75000000, P_GPLL0, 8, 0, 0),
547 F(150000000, P_GPLL0, 4, 0, 0),
548 F(228570000, P_MMPLL0, 3.5, 0, 0),
549 F(266670000, P_MMPLL0, 3, 0, 0),
550 F(320000000, P_MMPLL0, 2.5, 0, 0),
551 F(480000000, P_MMPLL4, 2, 0, 0),
555 static struct clk_rcg2 jpeg1_clk_src = {
558 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
559 .freq_tbl = ftbl_jpeg0_1_clk_src,
560 .clkr.hw.init = &(struct clk_init_data){
561 .name = "jpeg1_clk_src",
562 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
563 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
564 .ops = &clk_rcg2_ops,
568 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
569 F(75000000, P_GPLL0, 8, 0, 0),
570 F(133330000, P_GPLL0, 4.5, 0, 0),
571 F(150000000, P_GPLL0, 4, 0, 0),
572 F(228570000, P_MMPLL0, 3.5, 0, 0),
573 F(266670000, P_MMPLL0, 3, 0, 0),
574 F(320000000, P_MMPLL0, 2.5, 0, 0),
578 static struct clk_rcg2 jpeg2_clk_src = {
581 .parent_map = mmcc_xo_gpll0_mmpll0_map,
582 .freq_tbl = ftbl_jpeg2_clk_src,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "jpeg2_clk_src",
585 .parent_data = mmcc_xo_gpll0_mmpll0,
586 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
587 .ops = &clk_rcg2_ops,
591 static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
592 F(50000000, P_GPLL0, 12, 0, 0),
593 F(100000000, P_GPLL0, 6, 0, 0),
594 F(200000000, P_MMPLL0, 4, 0, 0),
598 static struct clk_rcg2 csi2phytimer_clk_src = {
601 .parent_map = mmcc_xo_gpll0_mmpll0_map,
602 .freq_tbl = ftbl_csi2phytimer_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "csi2phytimer_clk_src",
605 .parent_data = mmcc_xo_gpll0_mmpll0,
606 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
607 .ops = &clk_rcg2_ops,
611 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
612 F(60000000, P_GPLL0, 10, 0, 0),
613 F(200000000, P_GPLL0, 3, 0, 0),
614 F(320000000, P_MMPLL0, 2.5, 0, 0),
615 F(400000000, P_MMPLL0, 2, 0, 0),
619 static struct clk_rcg2 fd_core_clk_src = {
622 .parent_map = mmcc_xo_gpll0_mmpll0_map,
623 .freq_tbl = ftbl_fd_core_clk_src,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "fd_core_clk_src",
626 .parent_data = mmcc_xo_gpll0_mmpll0,
627 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
628 .ops = &clk_rcg2_ops,
632 static const struct freq_tbl ftbl_mdp_clk_src[] = {
633 F(85710000, P_GPLL0, 7, 0, 0),
634 F(100000000, P_GPLL0, 6, 0, 0),
635 F(120000000, P_GPLL0, 5, 0, 0),
636 F(150000000, P_GPLL0, 4, 0, 0),
637 F(171430000, P_GPLL0, 3.5, 0, 0),
638 F(200000000, P_GPLL0, 3, 0, 0),
639 F(240000000, P_GPLL0, 2.5, 0, 0),
640 F(266670000, P_MMPLL0, 3, 0, 0),
641 F(300000000, P_GPLL0, 2, 0, 0),
642 F(320000000, P_MMPLL0, 2.5, 0, 0),
643 F(400000000, P_MMPLL0, 2, 0, 0),
647 static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
648 F(85710000, P_GPLL0, 7, 0, 0),
649 F(171430000, P_GPLL0, 3.5, 0, 0),
650 F(200000000, P_GPLL0, 3, 0, 0),
651 F(240000000, P_GPLL0, 2.5, 0, 0),
652 F(266670000, P_MMPLL0, 3, 0, 0),
653 F(320000000, P_MMPLL0, 2.5, 0, 0),
654 F(400000000, P_MMPLL0, 2, 0, 0),
658 static struct clk_rcg2 mdp_clk_src = {
661 .parent_map = mmcc_xo_gpll0_mmpll0_map,
662 .freq_tbl = ftbl_mdp_clk_src,
663 .clkr.hw.init = &(struct clk_init_data){
664 .name = "mdp_clk_src",
665 .parent_data = mmcc_xo_gpll0_mmpll0,
666 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
667 .ops = &clk_rcg2_ops,
671 static struct clk_rcg2 pclk0_clk_src = {
675 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
676 .clkr.hw.init = &(struct clk_init_data){
677 .name = "pclk0_clk_src",
678 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
679 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
680 .ops = &clk_pixel_ops,
681 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
685 static struct clk_rcg2 pclk1_clk_src = {
689 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "pclk1_clk_src",
692 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
693 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
694 .ops = &clk_pixel_ops,
695 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
699 static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
700 F(19200000, P_XO, 1, 0, 0),
701 F(75000000, P_GPLL0, 8, 0, 0),
702 F(100000000, P_GPLL0, 6, 0, 0),
703 F(150000000, P_GPLL0, 4, 0, 0),
704 F(228570000, P_MMPLL0, 3.5, 0, 0),
705 F(266670000, P_MMPLL0, 3, 0, 0),
706 F(320000000, P_MMPLL0, 2.5, 0, 0),
707 F(400000000, P_MMPLL0, 2, 0, 0),
711 static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
712 F(19200000, P_XO, 1, 0, 0),
713 F(75000000, P_GPLL0, 8, 0, 0),
714 F(100000000, P_GPLL0, 6, 0, 0),
715 F(150000000, P_GPLL0, 4, 0, 0),
716 F(320000000, P_MMPLL0, 2.5, 0, 0),
717 F(400000000, P_MMPLL0, 2, 0, 0),
721 static struct clk_rcg2 ocmemnoc_clk_src = {
724 .parent_map = mmcc_xo_gpll0_mmpll0_map,
725 .freq_tbl = ftbl_ocmemnoc_clk_src,
726 .clkr.hw.init = &(struct clk_init_data){
727 .name = "ocmemnoc_clk_src",
728 .parent_data = mmcc_xo_gpll0_mmpll0,
729 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
730 .ops = &clk_rcg2_ops,
734 static const struct freq_tbl ftbl_cci_clk_src[] = {
735 F(19200000, P_XO, 1, 0, 0),
736 F(37500000, P_GPLL0, 16, 0, 0),
737 F(50000000, P_GPLL0, 12, 0, 0),
738 F(100000000, P_GPLL0, 6, 0, 0),
742 static struct clk_rcg2 cci_clk_src = {
746 .parent_map = mmcc_xo_gpll0_map,
747 .freq_tbl = ftbl_cci_clk_src,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "cci_clk_src",
750 .parent_data = mmcc_xo_gpll0,
751 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
752 .ops = &clk_rcg2_ops,
756 static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
757 F(10000, P_XO, 16, 10, 120),
758 F(24000, P_GPLL0, 16, 1, 50),
759 F(6000000, P_GPLL0, 10, 1, 10),
760 F(12000000, P_GPLL0, 10, 1, 5),
761 F(13000000, P_GPLL0, 4, 13, 150),
762 F(24000000, P_GPLL0, 5, 1, 5),
766 static struct clk_rcg2 mmss_gp0_clk_src = {
770 .parent_map = mmcc_xo_gpll0_map,
771 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
772 .clkr.hw.init = &(struct clk_init_data){
773 .name = "mmss_gp0_clk_src",
774 .parent_data = mmcc_xo_gpll0,
775 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
776 .ops = &clk_rcg2_ops,
780 static struct clk_rcg2 mmss_gp1_clk_src = {
784 .parent_map = mmcc_xo_gpll0_map,
785 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "mmss_gp1_clk_src",
788 .parent_data = mmcc_xo_gpll0,
789 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
790 .ops = &clk_rcg2_ops,
794 static struct clk_rcg2 jpeg0_clk_src = {
797 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
798 .freq_tbl = ftbl_jpeg0_1_clk_src,
799 .clkr.hw.init = &(struct clk_init_data){
800 .name = "jpeg0_clk_src",
801 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
802 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
803 .ops = &clk_rcg2_ops,
807 static struct clk_rcg2 jpeg_dma_clk_src = {
810 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
811 .freq_tbl = ftbl_jpeg0_1_clk_src,
812 .clkr.hw.init = &(struct clk_init_data){
813 .name = "jpeg_dma_clk_src",
814 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
815 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
816 .ops = &clk_rcg2_ops,
820 static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
821 F(4800000, P_XO, 4, 0, 0),
822 F(6000000, P_GPLL0, 10, 1, 10),
823 F(8000000, P_GPLL0, 15, 1, 5),
824 F(9600000, P_XO, 2, 0, 0),
825 F(16000000, P_MMPLL0, 10, 1, 5),
826 F(19200000, P_XO, 1, 0, 0),
827 F(24000000, P_GPLL0, 5, 1, 5),
828 F(32000000, P_MMPLL0, 5, 1, 5),
829 F(48000000, P_GPLL0, 12.5, 0, 0),
830 F(64000000, P_MMPLL0, 12.5, 0, 0),
834 static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
835 F(4800000, P_XO, 4, 0, 0),
836 F(6000000, P_MMPLL4, 10, 1, 16),
837 F(8000000, P_MMPLL4, 10, 1, 12),
838 F(9600000, P_XO, 2, 0, 0),
839 F(12000000, P_MMPLL4, 10, 1, 8),
840 F(16000000, P_MMPLL4, 10, 1, 6),
841 F(19200000, P_XO, 1, 0, 0),
842 F(24000000, P_MMPLL4, 10, 1, 4),
843 F(32000000, P_MMPLL4, 10, 1, 3),
844 F(48000000, P_MMPLL4, 10, 1, 2),
845 F(64000000, P_MMPLL4, 15, 0, 0),
849 static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
850 F(4800000, P_XO, 4, 0, 0),
851 F(6000000, P_MMPLL4, 10, 1, 16),
852 F(8000000, P_MMPLL4, 10, 1, 12),
853 F(9600000, P_XO, 2, 0, 0),
854 F(16000000, P_MMPLL4, 10, 1, 6),
855 F(19200000, P_XO, 1, 0, 0),
856 F(24000000, P_MMPLL4, 10, 1, 4),
857 F(32000000, P_MMPLL4, 10, 1, 3),
858 F(48000000, P_MMPLL4, 10, 1, 2),
859 F(64000000, P_MMPLL4, 15, 0, 0),
863 static struct clk_rcg2 mclk0_clk_src = {
867 .parent_map = mmcc_xo_gpll0_mmpll0_map,
868 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "mclk0_clk_src",
871 .parent_data = mmcc_xo_gpll0_mmpll0,
872 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
873 .ops = &clk_rcg2_ops,
877 static struct clk_rcg2 mclk1_clk_src = {
881 .parent_map = mmcc_xo_gpll0_mmpll0_map,
882 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "mclk1_clk_src",
885 .parent_data = mmcc_xo_gpll0_mmpll0,
886 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
887 .ops = &clk_rcg2_ops,
891 static struct clk_rcg2 mclk2_clk_src = {
895 .parent_map = mmcc_xo_gpll0_mmpll0_map,
896 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "mclk2_clk_src",
899 .parent_data = mmcc_xo_gpll0_mmpll0,
900 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
901 .ops = &clk_rcg2_ops,
905 static struct clk_rcg2 mclk3_clk_src = {
909 .parent_map = mmcc_xo_gpll0_mmpll0_map,
910 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "mclk3_clk_src",
913 .parent_data = mmcc_xo_gpll0_mmpll0,
914 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
915 .ops = &clk_rcg2_ops,
919 static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
920 F(50000000, P_GPLL0, 12, 0, 0),
921 F(100000000, P_GPLL0, 6, 0, 0),
922 F(200000000, P_MMPLL0, 4, 0, 0),
926 static struct clk_rcg2 csi0phytimer_clk_src = {
929 .parent_map = mmcc_xo_gpll0_mmpll0_map,
930 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
931 .clkr.hw.init = &(struct clk_init_data){
932 .name = "csi0phytimer_clk_src",
933 .parent_data = mmcc_xo_gpll0_mmpll0,
934 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
935 .ops = &clk_rcg2_ops,
939 static struct clk_rcg2 csi1phytimer_clk_src = {
942 .parent_map = mmcc_xo_gpll0_mmpll0_map,
943 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
944 .clkr.hw.init = &(struct clk_init_data){
945 .name = "csi1phytimer_clk_src",
946 .parent_data = mmcc_xo_gpll0_mmpll0,
947 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
948 .ops = &clk_rcg2_ops,
952 static struct clk_rcg2 byte0_clk_src = {
955 .parent_map = mmcc_xo_dsibyte_map,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "byte0_clk_src",
958 .parent_data = mmcc_xo_dsibyte,
959 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
960 .ops = &clk_byte2_ops,
961 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
965 static struct clk_rcg2 byte1_clk_src = {
968 .parent_map = mmcc_xo_dsibyte_map,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "byte1_clk_src",
971 .parent_data = mmcc_xo_dsibyte,
972 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
973 .ops = &clk_byte2_ops,
974 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
978 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
979 F(19200000, P_XO, 1, 0, 0),
983 static struct clk_rcg2 esc0_clk_src = {
986 .parent_map = mmcc_xo_dsibyte_map,
987 .freq_tbl = ftbl_mdss_esc0_1_clk,
988 .clkr.hw.init = &(struct clk_init_data){
989 .name = "esc0_clk_src",
990 .parent_data = mmcc_xo_dsibyte,
991 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
992 .ops = &clk_rcg2_ops,
996 static struct clk_rcg2 esc1_clk_src = {
999 .parent_map = mmcc_xo_dsibyte_map,
1000 .freq_tbl = ftbl_mdss_esc0_1_clk,
1001 .clkr.hw.init = &(struct clk_init_data){
1002 .name = "esc1_clk_src",
1003 .parent_data = mmcc_xo_dsibyte,
1004 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
1005 .ops = &clk_rcg2_ops,
1009 static struct freq_tbl extpclk_freq_tbl[] = {
1010 { .src = P_HDMIPLL },
1014 static struct clk_rcg2 extpclk_clk_src = {
1017 .parent_map = mmss_xo_hdmi_map,
1018 .freq_tbl = extpclk_freq_tbl,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "extpclk_clk_src",
1021 .parent_data = mmss_xo_hdmi,
1022 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
1023 .ops = &clk_rcg2_ops,
1024 .flags = CLK_SET_RATE_PARENT,
1028 static struct freq_tbl ftbl_hdmi_clk_src[] = {
1029 F(19200000, P_XO, 1, 0, 0),
1033 static struct clk_rcg2 hdmi_clk_src = {
1036 .parent_map = mmcc_xo_gpll0_map,
1037 .freq_tbl = ftbl_hdmi_clk_src,
1038 .clkr.hw.init = &(struct clk_init_data){
1039 .name = "hdmi_clk_src",
1040 .parent_data = mmcc_xo_gpll0,
1041 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1042 .ops = &clk_rcg2_ops,
1046 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1047 F(19200000, P_XO, 1, 0, 0),
1051 static struct clk_rcg2 vsync_clk_src = {
1054 .parent_map = mmcc_xo_gpll0_map,
1055 .freq_tbl = ftbl_mdss_vsync_clk,
1056 .clkr.hw.init = &(struct clk_init_data){
1057 .name = "vsync_clk_src",
1058 .parent_data = mmcc_xo_gpll0,
1059 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1060 .ops = &clk_rcg2_ops,
1064 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1065 F(19200000, P_XO, 1, 0, 0),
1069 static struct clk_rcg2 rbbmtimer_clk_src = {
1072 .parent_map = mmcc_xo_gpll0_map,
1073 .freq_tbl = ftbl_rbbmtimer_clk_src,
1074 .clkr.hw.init = &(struct clk_init_data){
1075 .name = "rbbmtimer_clk_src",
1076 .parent_data = mmcc_xo_gpll0,
1077 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1078 .ops = &clk_rcg2_ops,
1082 static struct clk_branch camss_ahb_clk = {
1085 .enable_reg = 0x348c,
1086 .enable_mask = BIT(0),
1087 .hw.init = &(struct clk_init_data){
1088 .name = "camss_ahb_clk",
1089 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1091 .flags = CLK_SET_RATE_PARENT,
1092 .ops = &clk_branch2_ops,
1097 static struct clk_branch camss_cci_cci_ahb_clk = {
1100 .enable_reg = 0x3348,
1101 .enable_mask = BIT(0),
1102 .hw.init = &(struct clk_init_data){
1103 .name = "camss_cci_cci_ahb_clk",
1104 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1106 .flags = CLK_SET_RATE_PARENT,
1107 .ops = &clk_branch2_ops,
1112 static struct clk_branch camss_cci_cci_clk = {
1115 .enable_reg = 0x3344,
1116 .enable_mask = BIT(0),
1117 .hw.init = &(struct clk_init_data){
1118 .name = "camss_cci_cci_clk",
1119 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1121 .ops = &clk_branch2_ops,
1126 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1129 .enable_reg = 0x36b4,
1130 .enable_mask = BIT(0),
1131 .hw.init = &(struct clk_init_data){
1132 .name = "camss_vfe_cpp_ahb_clk",
1133 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1135 .flags = CLK_SET_RATE_PARENT,
1136 .ops = &clk_branch2_ops,
1141 static struct clk_branch camss_vfe_cpp_axi_clk = {
1144 .enable_reg = 0x36c4,
1145 .enable_mask = BIT(0),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "camss_vfe_cpp_axi_clk",
1148 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1150 .ops = &clk_branch2_ops,
1155 static struct clk_branch camss_vfe_cpp_clk = {
1158 .enable_reg = 0x36b0,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "camss_vfe_cpp_clk",
1162 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1164 .ops = &clk_branch2_ops,
1169 static struct clk_branch camss_csi0_ahb_clk = {
1172 .enable_reg = 0x30bc,
1173 .enable_mask = BIT(0),
1174 .hw.init = &(struct clk_init_data){
1175 .name = "camss_csi0_ahb_clk",
1176 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1178 .flags = CLK_SET_RATE_PARENT,
1179 .ops = &clk_branch2_ops,
1184 static struct clk_branch camss_csi0_clk = {
1187 .enable_reg = 0x30b4,
1188 .enable_mask = BIT(0),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "camss_csi0_clk",
1191 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1193 .ops = &clk_branch2_ops,
1198 static struct clk_branch camss_csi0phy_clk = {
1201 .enable_reg = 0x30c4,
1202 .enable_mask = BIT(0),
1203 .hw.init = &(struct clk_init_data){
1204 .name = "camss_csi0phy_clk",
1205 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1207 .ops = &clk_branch2_ops,
1212 static struct clk_branch camss_csi0pix_clk = {
1215 .enable_reg = 0x30e4,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "camss_csi0pix_clk",
1219 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1221 .ops = &clk_branch2_ops,
1226 static struct clk_branch camss_csi0rdi_clk = {
1229 .enable_reg = 0x30d4,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "camss_csi0rdi_clk",
1233 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch camss_csi1_ahb_clk = {
1243 .enable_reg = 0x3128,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "camss_csi1_ahb_clk",
1247 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1255 static struct clk_branch camss_csi1_clk = {
1258 .enable_reg = 0x3124,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "camss_csi1_clk",
1262 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1264 .ops = &clk_branch2_ops,
1269 static struct clk_branch camss_csi1phy_clk = {
1272 .enable_reg = 0x3134,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "camss_csi1phy_clk",
1276 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch camss_csi1pix_clk = {
1286 .enable_reg = 0x3154,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data){
1289 .name = "camss_csi1pix_clk",
1290 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1292 .ops = &clk_branch2_ops,
1297 static struct clk_branch camss_csi1rdi_clk = {
1300 .enable_reg = 0x3144,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "camss_csi1rdi_clk",
1304 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1306 .ops = &clk_branch2_ops,
1311 static struct clk_branch camss_csi2_ahb_clk = {
1314 .enable_reg = 0x3188,
1315 .enable_mask = BIT(0),
1316 .hw.init = &(struct clk_init_data){
1317 .name = "camss_csi2_ahb_clk",
1318 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1320 .flags = CLK_SET_RATE_PARENT,
1321 .ops = &clk_branch2_ops,
1326 static struct clk_branch camss_csi2_clk = {
1329 .enable_reg = 0x3184,
1330 .enable_mask = BIT(0),
1331 .hw.init = &(struct clk_init_data){
1332 .name = "camss_csi2_clk",
1333 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1335 .ops = &clk_branch2_ops,
1340 static struct clk_branch camss_csi2phy_clk = {
1343 .enable_reg = 0x3194,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "camss_csi2phy_clk",
1347 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1349 .ops = &clk_branch2_ops,
1354 static struct clk_branch camss_csi2pix_clk = {
1357 .enable_reg = 0x31b4,
1358 .enable_mask = BIT(0),
1359 .hw.init = &(struct clk_init_data){
1360 .name = "camss_csi2pix_clk",
1361 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1363 .ops = &clk_branch2_ops,
1368 static struct clk_branch camss_csi2rdi_clk = {
1371 .enable_reg = 0x31a4,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "camss_csi2rdi_clk",
1375 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1377 .ops = &clk_branch2_ops,
1382 static struct clk_branch camss_csi3_ahb_clk = {
1385 .enable_reg = 0x31e8,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "camss_csi3_ahb_clk",
1389 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1391 .flags = CLK_SET_RATE_PARENT,
1392 .ops = &clk_branch2_ops,
1397 static struct clk_branch camss_csi3_clk = {
1400 .enable_reg = 0x31e4,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(struct clk_init_data){
1403 .name = "camss_csi3_clk",
1404 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1406 .ops = &clk_branch2_ops,
1411 static struct clk_branch camss_csi3phy_clk = {
1414 .enable_reg = 0x31f4,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "camss_csi3phy_clk",
1418 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1420 .ops = &clk_branch2_ops,
1425 static struct clk_branch camss_csi3pix_clk = {
1428 .enable_reg = 0x3214,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "camss_csi3pix_clk",
1432 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1434 .ops = &clk_branch2_ops,
1439 static struct clk_branch camss_csi3rdi_clk = {
1442 .enable_reg = 0x3204,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "camss_csi3rdi_clk",
1446 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1448 .ops = &clk_branch2_ops,
1453 static struct clk_branch camss_csi_vfe0_clk = {
1456 .enable_reg = 0x3704,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "camss_csi_vfe0_clk",
1460 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1462 .ops = &clk_branch2_ops,
1467 static struct clk_branch camss_csi_vfe1_clk = {
1470 .enable_reg = 0x3714,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "camss_csi_vfe1_clk",
1474 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1476 .ops = &clk_branch2_ops,
1481 static struct clk_branch camss_gp0_clk = {
1484 .enable_reg = 0x3444,
1485 .enable_mask = BIT(0),
1486 .hw.init = &(struct clk_init_data){
1487 .name = "camss_gp0_clk",
1488 .parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1490 .ops = &clk_branch2_ops,
1495 static struct clk_branch camss_gp1_clk = {
1498 .enable_reg = 0x3474,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "camss_gp1_clk",
1502 .parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1504 .ops = &clk_branch2_ops,
1509 static struct clk_branch camss_ispif_ahb_clk = {
1512 .enable_reg = 0x3224,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "camss_ispif_ahb_clk",
1516 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1524 static struct clk_branch camss_jpeg_dma_clk = {
1527 .enable_reg = 0x35c0,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "camss_jpeg_dma_clk",
1531 .parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1533 .ops = &clk_branch2_ops,
1538 static struct clk_branch camss_jpeg_jpeg0_clk = {
1541 .enable_reg = 0x35a8,
1542 .enable_mask = BIT(0),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "camss_jpeg_jpeg0_clk",
1545 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch camss_jpeg_jpeg1_clk = {
1555 .enable_reg = 0x35ac,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "camss_jpeg_jpeg1_clk",
1559 .parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1561 .ops = &clk_branch2_ops,
1566 static struct clk_branch camss_jpeg_jpeg2_clk = {
1569 .enable_reg = 0x35b0,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "camss_jpeg_jpeg2_clk",
1573 .parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1575 .ops = &clk_branch2_ops,
1580 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1583 .enable_reg = 0x35b4,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "camss_jpeg_jpeg_ahb_clk",
1587 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1598 .enable_reg = 0x35b8,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camss_jpeg_jpeg_axi_clk",
1602 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1604 .ops = &clk_branch2_ops,
1609 static struct clk_branch camss_mclk0_clk = {
1612 .enable_reg = 0x3384,
1613 .enable_mask = BIT(0),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "camss_mclk0_clk",
1616 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch camss_mclk1_clk = {
1626 .enable_reg = 0x33b4,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "camss_mclk1_clk",
1630 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1632 .ops = &clk_branch2_ops,
1637 static struct clk_branch camss_mclk2_clk = {
1640 .enable_reg = 0x33e4,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data){
1643 .name = "camss_mclk2_clk",
1644 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1646 .ops = &clk_branch2_ops,
1651 static struct clk_branch camss_mclk3_clk = {
1654 .enable_reg = 0x3414,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data){
1657 .name = "camss_mclk3_clk",
1658 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1660 .ops = &clk_branch2_ops,
1665 static struct clk_branch camss_micro_ahb_clk = {
1668 .enable_reg = 0x3494,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "camss_micro_ahb_clk",
1672 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1683 .enable_reg = 0x3024,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "camss_phy0_csi0phytimer_clk",
1687 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1689 .ops = &clk_branch2_ops,
1694 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1697 .enable_reg = 0x3054,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "camss_phy1_csi1phytimer_clk",
1701 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1703 .ops = &clk_branch2_ops,
1708 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1711 .enable_reg = 0x3084,
1712 .enable_mask = BIT(0),
1713 .hw.init = &(struct clk_init_data){
1714 .name = "camss_phy2_csi2phytimer_clk",
1715 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1717 .ops = &clk_branch2_ops,
1722 static struct clk_branch camss_top_ahb_clk = {
1725 .enable_reg = 0x3484,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "camss_top_ahb_clk",
1729 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1731 .flags = CLK_SET_RATE_PARENT,
1732 .ops = &clk_branch2_ops,
1737 static struct clk_branch camss_vfe_vfe0_clk = {
1740 .enable_reg = 0x36a8,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "camss_vfe_vfe0_clk",
1744 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1746 .ops = &clk_branch2_ops,
1751 static struct clk_branch camss_vfe_vfe1_clk = {
1754 .enable_reg = 0x36ac,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "camss_vfe_vfe1_clk",
1758 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1760 .ops = &clk_branch2_ops,
1765 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1768 .enable_reg = 0x36b8,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "camss_vfe_vfe_ahb_clk",
1772 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_branch2_ops,
1780 static struct clk_branch camss_vfe_vfe_axi_clk = {
1783 .enable_reg = 0x36bc,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "camss_vfe_vfe_axi_clk",
1787 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch fd_ahb_clk = {
1797 .enable_reg = 0x3b74,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "fd_ahb_clk",
1801 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1803 .ops = &clk_branch2_ops,
1808 static struct clk_branch fd_axi_clk = {
1811 .enable_reg = 0x3b70,
1812 .enable_mask = BIT(0),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "fd_axi_clk",
1815 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1817 .ops = &clk_branch2_ops,
1822 static struct clk_branch fd_core_clk = {
1825 .enable_reg = 0x3b68,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "fd_core_clk",
1829 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch fd_core_uar_clk = {
1839 .enable_reg = 0x3b6c,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "fd_core_uar_clk",
1843 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1845 .ops = &clk_branch2_ops,
1850 static struct clk_branch mdss_ahb_clk = {
1852 .halt_check = BRANCH_HALT,
1854 .enable_reg = 0x2308,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "mdss_ahb_clk",
1858 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch mdss_axi_clk = {
1869 .enable_reg = 0x2310,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "mdss_axi_clk",
1873 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1875 .flags = CLK_SET_RATE_PARENT,
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch mdss_byte0_clk = {
1884 .enable_reg = 0x233c,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "mdss_byte0_clk",
1888 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch mdss_byte1_clk = {
1899 .enable_reg = 0x2340,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_byte1_clk",
1903 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1911 static struct clk_branch mdss_esc0_clk = {
1914 .enable_reg = 0x2344,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "mdss_esc0_clk",
1918 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1926 static struct clk_branch mdss_esc1_clk = {
1929 .enable_reg = 0x2348,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "mdss_esc1_clk",
1933 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1941 static struct clk_branch mdss_extpclk_clk = {
1944 .enable_reg = 0x2324,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "mdss_extpclk_clk",
1948 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1956 static struct clk_branch mdss_hdmi_ahb_clk = {
1959 .enable_reg = 0x230c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "mdss_hdmi_ahb_clk",
1963 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1965 .flags = CLK_SET_RATE_PARENT,
1966 .ops = &clk_branch2_ops,
1971 static struct clk_branch mdss_hdmi_clk = {
1974 .enable_reg = 0x2338,
1975 .enable_mask = BIT(0),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "mdss_hdmi_clk",
1978 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1980 .flags = CLK_SET_RATE_PARENT,
1981 .ops = &clk_branch2_ops,
1986 static struct clk_branch mdss_mdp_clk = {
1989 .enable_reg = 0x231c,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "mdss_mdp_clk",
1993 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
2001 static struct clk_branch mdss_pclk0_clk = {
2004 .enable_reg = 0x2314,
2005 .enable_mask = BIT(0),
2006 .hw.init = &(struct clk_init_data){
2007 .name = "mdss_pclk0_clk",
2008 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2016 static struct clk_branch mdss_pclk1_clk = {
2019 .enable_reg = 0x2318,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "mdss_pclk1_clk",
2023 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2031 static struct clk_branch mdss_vsync_clk = {
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "mdss_vsync_clk",
2038 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2046 static struct clk_branch mmss_misc_ahb_clk = {
2049 .enable_reg = 0x502c,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "mmss_misc_ahb_clk",
2053 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2061 static struct clk_branch mmss_mmssnoc_axi_clk = {
2064 .enable_reg = 0x506c,
2065 .enable_mask = BIT(0),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "mmss_mmssnoc_axi_clk",
2068 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2070 /* Gating this clock will wreck havoc among MMSS! */
2071 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2072 .ops = &clk_branch2_ops,
2077 static struct clk_branch mmss_s0_axi_clk = {
2080 .enable_reg = 0x5064,
2081 .enable_mask = BIT(0),
2082 .hw.init = &(struct clk_init_data){
2083 .name = "mmss_s0_axi_clk",
2084 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
2086 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2095 .enable_reg = 0x4058,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "ocmemcx_ocmemnoc_clk",
2099 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2101 .flags = CLK_SET_RATE_PARENT,
2102 .ops = &clk_branch2_ops,
2107 static struct clk_branch oxili_gfx3d_clk = {
2110 .enable_reg = 0x4028,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "oxili_gfx3d_clk",
2114 .parent_data = &(const struct clk_parent_data){
2115 .fw_name = "oxili_gfx3d_clk_src",
2116 .name = "oxili_gfx3d_clk_src"
2119 .flags = CLK_SET_RATE_PARENT,
2120 .ops = &clk_branch2_ops,
2125 static struct clk_branch oxili_rbbmtimer_clk = {
2128 .enable_reg = 0x40b0,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "oxili_rbbmtimer_clk",
2132 .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_branch2_ops,
2140 static struct clk_branch oxilicx_ahb_clk = {
2143 .enable_reg = 0x403c,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "oxilicx_ahb_clk",
2147 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2149 .flags = CLK_SET_RATE_PARENT,
2150 .ops = &clk_branch2_ops,
2155 static struct clk_branch venus0_ahb_clk = {
2158 .enable_reg = 0x1030,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "venus0_ahb_clk",
2162 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2164 .flags = CLK_SET_RATE_PARENT,
2165 .ops = &clk_branch2_ops,
2170 static struct clk_branch venus0_axi_clk = {
2173 .enable_reg = 0x1034,
2174 .enable_mask = BIT(0),
2175 .hw.init = &(struct clk_init_data){
2176 .name = "venus0_axi_clk",
2177 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2179 .ops = &clk_branch2_ops,
2184 static struct clk_branch venus0_ocmemnoc_clk = {
2187 .enable_reg = 0x1038,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "venus0_ocmemnoc_clk",
2191 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2199 static struct clk_branch venus0_vcodec0_clk = {
2202 .enable_reg = 0x1028,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "venus0_vcodec0_clk",
2206 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2208 .flags = CLK_SET_RATE_PARENT,
2209 .ops = &clk_branch2_ops,
2214 static struct clk_branch venus0_core0_vcodec_clk = {
2217 .enable_reg = 0x1048,
2218 .enable_mask = BIT(0),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "venus0_core0_vcodec_clk",
2221 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2223 .flags = CLK_SET_RATE_PARENT,
2224 .ops = &clk_branch2_ops,
2229 static struct clk_branch venus0_core1_vcodec_clk = {
2232 .enable_reg = 0x104c,
2233 .enable_mask = BIT(0),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "venus0_core1_vcodec_clk",
2236 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2238 .flags = CLK_SET_RATE_PARENT,
2239 .ops = &clk_branch2_ops,
2244 static struct clk_branch venus0_core2_vcodec_clk = {
2247 .enable_reg = 0x1054,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "venus0_core2_vcodec_clk",
2251 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2253 .flags = CLK_SET_RATE_PARENT,
2254 .ops = &clk_branch2_ops,
2259 static struct gdsc venus_gdsc = {
2261 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2264 .name = "venus_gdsc",
2266 .pwrsts = PWRSTS_OFF_ON,
2269 static struct gdsc venus_core0_gdsc = {
2271 .cxcs = (unsigned int []){ 0x1048 },
2274 .name = "venus_core0_gdsc",
2276 .pwrsts = PWRSTS_OFF_ON,
2280 static struct gdsc venus_core1_gdsc = {
2282 .cxcs = (unsigned int []){ 0x104c },
2285 .name = "venus_core1_gdsc",
2287 .pwrsts = PWRSTS_OFF_ON,
2291 static struct gdsc venus_core2_gdsc = {
2293 .cxcs = (unsigned int []){ 0x1054 },
2296 .name = "venus_core2_gdsc",
2298 .pwrsts = PWRSTS_OFF_ON,
2302 static struct gdsc mdss_gdsc = {
2304 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2307 .name = "mdss_gdsc",
2309 .pwrsts = PWRSTS_OFF_ON,
2312 static struct gdsc camss_top_gdsc = {
2314 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2317 .name = "camss_top_gdsc",
2319 .pwrsts = PWRSTS_OFF_ON,
2322 static struct gdsc jpeg_gdsc = {
2324 .cxcs = (unsigned int []){ 0x35a8 },
2327 .name = "jpeg_gdsc",
2329 .parent = &camss_top_gdsc.pd,
2330 .pwrsts = PWRSTS_OFF_ON,
2333 static struct gdsc vfe_gdsc = {
2335 .cxcs = (unsigned int []){ 0x36bc },
2340 .parent = &camss_top_gdsc.pd,
2341 .pwrsts = PWRSTS_OFF_ON,
2344 static struct gdsc cpp_gdsc = {
2346 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2351 .parent = &camss_top_gdsc.pd,
2352 .pwrsts = PWRSTS_OFF_ON,
2355 static struct gdsc fd_gdsc = {
2357 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2361 .pwrsts = PWRSTS_OFF_ON,
2364 static struct gdsc oxili_cx_gdsc = {
2367 .name = "oxili_cx_gdsc",
2369 .pwrsts = PWRSTS_OFF_ON,
2373 static struct gdsc oxili_gx_gdsc = {
2375 .cxcs = (unsigned int []){ 0x4028 },
2378 .name = "oxili_gx_gdsc",
2380 .pwrsts = PWRSTS_OFF_ON,
2381 .parent = &oxili_cx_gdsc.pd,
2383 .supply = "VDD_GFX",
2386 static struct clk_regmap *mmcc_msm8994_clocks[] = {
2387 [MMPLL0_EARLY] = &mmpll0_early.clkr,
2388 [MMPLL0_PLL] = &mmpll0.clkr,
2389 [MMPLL1_EARLY] = &mmpll1_early.clkr,
2390 [MMPLL1_PLL] = &mmpll1.clkr,
2391 [MMPLL3_EARLY] = &mmpll3_early.clkr,
2392 [MMPLL3_PLL] = &mmpll3.clkr,
2393 [MMPLL4_EARLY] = &mmpll4_early.clkr,
2394 [MMPLL4_PLL] = &mmpll4.clkr,
2395 [MMPLL5_EARLY] = &mmpll5_early.clkr,
2396 [MMPLL5_PLL] = &mmpll5.clkr,
2397 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2398 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2399 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2400 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2401 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2402 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2403 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2404 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2405 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2406 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2407 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2408 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2409 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2410 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2411 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2412 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2413 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2414 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2415 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2416 [MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2417 [MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2418 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2419 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2420 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2421 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2422 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2423 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2424 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2425 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2426 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2427 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2428 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2429 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2430 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2431 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2432 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2433 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2434 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2435 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2436 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2437 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2438 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2439 [CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2440 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2441 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2442 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2443 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2444 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2445 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2446 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2447 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2448 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2449 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2450 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2451 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2452 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2453 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2454 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2455 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2456 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2457 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2458 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2459 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2460 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2461 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2462 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2463 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2464 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2465 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2466 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2467 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2468 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2469 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2470 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2471 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2472 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2473 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2474 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2475 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2476 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2477 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2478 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2479 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2480 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2481 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2482 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2483 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2484 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2485 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2486 [FD_AXI_CLK] = &fd_axi_clk.clkr,
2487 [FD_CORE_CLK] = &fd_core_clk.clkr,
2488 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2489 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2490 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2491 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2492 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2493 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2494 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2495 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2496 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2497 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2498 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2499 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2500 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2501 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2502 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2503 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2504 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2505 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2506 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2507 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2508 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2509 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2510 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2511 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2512 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2513 [VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2516 static struct gdsc *mmcc_msm8994_gdscs[] = {
2517 [VENUS_GDSC] = &venus_gdsc,
2518 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2519 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2520 [VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2521 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2522 [MDSS_GDSC] = &mdss_gdsc,
2523 [JPEG_GDSC] = &jpeg_gdsc,
2524 [VFE_GDSC] = &vfe_gdsc,
2525 [CPP_GDSC] = &cpp_gdsc,
2526 [OXILI_GX_GDSC] = &oxili_gx_gdsc,
2527 [OXILI_CX_GDSC] = &oxili_cx_gdsc,
2528 [FD_GDSC] = &fd_gdsc,
2531 static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2532 [CAMSS_MICRO_BCR] = { 0x3490 },
2535 static const struct regmap_config mmcc_msm8994_regmap_config = {
2539 .max_register = 0x5200,
2543 static const struct qcom_cc_desc mmcc_msm8994_desc = {
2544 .config = &mmcc_msm8994_regmap_config,
2545 .clks = mmcc_msm8994_clocks,
2546 .num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2547 .resets = mmcc_msm8994_resets,
2548 .num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2549 .gdscs = mmcc_msm8994_gdscs,
2550 .num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2553 static const struct of_device_id mmcc_msm8994_match_table[] = {
2554 { .compatible = "qcom,mmcc-msm8992" },
2555 { .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2558 MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2560 static int mmcc_msm8994_probe(struct platform_device *pdev)
2562 struct regmap *regmap;
2564 if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
2565 /* MSM8992 features less clocks and some have different freq tables */
2566 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
2567 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
2568 mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
2569 mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
2570 mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
2571 mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
2572 mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
2573 mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
2574 mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
2575 mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
2577 mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
2578 mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
2580 axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
2581 cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
2582 csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2583 csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2584 csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2585 csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2586 mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
2587 mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2588 mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2589 mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2590 mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
2591 ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
2592 vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
2593 vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2594 vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2597 regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2599 return PTR_ERR(regmap);
2601 clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2602 clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2603 clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2604 clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2606 return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
2609 static struct platform_driver mmcc_msm8994_driver = {
2610 .probe = mmcc_msm8994_probe,
2612 .name = "mmcc-msm8994",
2613 .of_match_table = mmcc_msm8994_match_table,
2616 module_platform_driver(mmcc_msm8994_driver);
2618 MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2619 MODULE_LICENSE("GPL v2");
2620 MODULE_ALIAS("platform:mmcc-msm8994");