1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
18 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
45 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
52 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
59 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
68 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
77 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
85 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
93 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
101 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
109 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
117 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
125 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
134 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
143 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
152 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
161 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
166 { P_DSI0PLL_BYTE, 1 },
167 { P_DSI1PLL_BYTE, 2 }
170 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
179 static struct clk_pll mmpll0 = {
183 .config_reg = 0x0014,
185 .status_reg = 0x001c,
187 .clkr.hw.init = &(struct clk_init_data){
189 .parent_names = (const char *[]){ "xo" },
195 static struct clk_regmap mmpll0_vote = {
196 .enable_reg = 0x0100,
197 .enable_mask = BIT(0),
198 .hw.init = &(struct clk_init_data){
199 .name = "mmpll0_vote",
200 .parent_names = (const char *[]){ "mmpll0" },
202 .ops = &clk_pll_vote_ops,
206 static struct clk_pll mmpll1 = {
210 .config_reg = 0x0050,
212 .status_reg = 0x005c,
214 .clkr.hw.init = &(struct clk_init_data){
216 .parent_names = (const char *[]){ "xo" },
222 static struct clk_regmap mmpll1_vote = {
223 .enable_reg = 0x0100,
224 .enable_mask = BIT(1),
225 .hw.init = &(struct clk_init_data){
226 .name = "mmpll1_vote",
227 .parent_names = (const char *[]){ "mmpll1" },
229 .ops = &clk_pll_vote_ops,
233 static struct clk_pll mmpll2 = {
237 .config_reg = 0x4110,
239 .status_reg = 0x411c,
240 .clkr.hw.init = &(struct clk_init_data){
242 .parent_names = (const char *[]){ "xo" },
248 static struct clk_pll mmpll3 = {
252 .config_reg = 0x0090,
254 .status_reg = 0x009c,
256 .clkr.hw.init = &(struct clk_init_data){
258 .parent_names = (const char *[]){ "xo" },
264 static struct clk_rcg2 mmss_ahb_clk_src = {
267 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
268 .clkr.hw.init = &(struct clk_init_data){
269 .name = "mmss_ahb_clk_src",
270 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
272 .ops = &clk_rcg2_ops,
276 static struct freq_tbl ftbl_mmss_axi_clk[] = {
277 F( 19200000, P_XO, 1, 0, 0),
278 F( 37500000, P_GPLL0, 16, 0, 0),
279 F( 50000000, P_GPLL0, 12, 0, 0),
280 F( 75000000, P_GPLL0, 8, 0, 0),
281 F(100000000, P_GPLL0, 6, 0, 0),
282 F(150000000, P_GPLL0, 4, 0, 0),
283 F(291750000, P_MMPLL1, 4, 0, 0),
284 F(400000000, P_MMPLL0, 2, 0, 0),
285 F(466800000, P_MMPLL1, 2.5, 0, 0),
289 static struct clk_rcg2 mmss_axi_clk_src = {
292 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
293 .freq_tbl = ftbl_mmss_axi_clk,
294 .clkr.hw.init = &(struct clk_init_data){
295 .name = "mmss_axi_clk_src",
296 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
298 .ops = &clk_rcg2_ops,
302 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
303 F( 19200000, P_XO, 1, 0, 0),
304 F( 37500000, P_GPLL0, 16, 0, 0),
305 F( 50000000, P_GPLL0, 12, 0, 0),
306 F( 75000000, P_GPLL0, 8, 0, 0),
307 F(100000000, P_GPLL0, 6, 0, 0),
308 F(150000000, P_GPLL0, 4, 0, 0),
309 F(291750000, P_MMPLL1, 4, 0, 0),
310 F(400000000, P_MMPLL0, 2, 0, 0),
314 static struct clk_rcg2 ocmemnoc_clk_src = {
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .freq_tbl = ftbl_ocmemnoc_clk,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "ocmemnoc_clk_src",
321 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
323 .ops = &clk_rcg2_ops,
327 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
328 F(100000000, P_GPLL0, 6, 0, 0),
329 F(200000000, P_MMPLL0, 4, 0, 0),
333 static struct clk_rcg2 csi0_clk_src = {
336 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
337 .freq_tbl = ftbl_camss_csi0_3_clk,
338 .clkr.hw.init = &(struct clk_init_data){
339 .name = "csi0_clk_src",
340 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
342 .ops = &clk_rcg2_ops,
346 static struct clk_rcg2 csi1_clk_src = {
349 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
350 .freq_tbl = ftbl_camss_csi0_3_clk,
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "csi1_clk_src",
353 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
355 .ops = &clk_rcg2_ops,
359 static struct clk_rcg2 csi2_clk_src = {
362 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
363 .freq_tbl = ftbl_camss_csi0_3_clk,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "csi2_clk_src",
366 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
368 .ops = &clk_rcg2_ops,
372 static struct clk_rcg2 csi3_clk_src = {
375 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
376 .freq_tbl = ftbl_camss_csi0_3_clk,
377 .clkr.hw.init = &(struct clk_init_data){
378 .name = "csi3_clk_src",
379 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
381 .ops = &clk_rcg2_ops,
385 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
386 F(37500000, P_GPLL0, 16, 0, 0),
387 F(50000000, P_GPLL0, 12, 0, 0),
388 F(60000000, P_GPLL0, 10, 0, 0),
389 F(80000000, P_GPLL0, 7.5, 0, 0),
390 F(100000000, P_GPLL0, 6, 0, 0),
391 F(109090000, P_GPLL0, 5.5, 0, 0),
392 F(133330000, P_GPLL0, 4.5, 0, 0),
393 F(200000000, P_GPLL0, 3, 0, 0),
394 F(228570000, P_MMPLL0, 3.5, 0, 0),
395 F(266670000, P_MMPLL0, 3, 0, 0),
396 F(320000000, P_MMPLL0, 2.5, 0, 0),
397 F(400000000, P_MMPLL0, 2, 0, 0),
398 F(465000000, P_MMPLL3, 2, 0, 0),
402 static struct clk_rcg2 vfe0_clk_src = {
405 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
406 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
407 .clkr.hw.init = &(struct clk_init_data){
408 .name = "vfe0_clk_src",
409 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
411 .ops = &clk_rcg2_ops,
415 static struct clk_rcg2 vfe1_clk_src = {
418 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
419 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "vfe1_clk_src",
422 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
424 .ops = &clk_rcg2_ops,
428 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
429 F(37500000, P_GPLL0, 16, 0, 0),
430 F(60000000, P_GPLL0, 10, 0, 0),
431 F(75000000, P_GPLL0, 8, 0, 0),
432 F(85710000, P_GPLL0, 7, 0, 0),
433 F(100000000, P_GPLL0, 6, 0, 0),
434 F(133330000, P_MMPLL0, 6, 0, 0),
435 F(160000000, P_MMPLL0, 5, 0, 0),
436 F(200000000, P_MMPLL0, 4, 0, 0),
437 F(228570000, P_MMPLL0, 3.5, 0, 0),
438 F(240000000, P_GPLL0, 2.5, 0, 0),
439 F(266670000, P_MMPLL0, 3, 0, 0),
440 F(320000000, P_MMPLL0, 2.5, 0, 0),
444 static struct clk_rcg2 mdp_clk_src = {
447 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
448 .freq_tbl = ftbl_mdss_mdp_clk,
449 .clkr.hw.init = &(struct clk_init_data){
450 .name = "mdp_clk_src",
451 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
453 .ops = &clk_rcg2_ops,
457 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
458 F(75000000, P_GPLL0, 8, 0, 0),
459 F(133330000, P_GPLL0, 4.5, 0, 0),
460 F(200000000, P_GPLL0, 3, 0, 0),
461 F(228570000, P_MMPLL0, 3.5, 0, 0),
462 F(266670000, P_MMPLL0, 3, 0, 0),
463 F(320000000, P_MMPLL0, 2.5, 0, 0),
467 static struct clk_rcg2 jpeg0_clk_src = {
470 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
471 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
472 .clkr.hw.init = &(struct clk_init_data){
473 .name = "jpeg0_clk_src",
474 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
476 .ops = &clk_rcg2_ops,
480 static struct clk_rcg2 jpeg1_clk_src = {
483 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
484 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "jpeg1_clk_src",
487 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
489 .ops = &clk_rcg2_ops,
493 static struct clk_rcg2 jpeg2_clk_src = {
496 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
497 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
498 .clkr.hw.init = &(struct clk_init_data){
499 .name = "jpeg2_clk_src",
500 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
502 .ops = &clk_rcg2_ops,
506 static struct clk_rcg2 pclk0_clk_src = {
510 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
511 .clkr.hw.init = &(struct clk_init_data){
512 .name = "pclk0_clk_src",
513 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
515 .ops = &clk_pixel_ops,
516 .flags = CLK_SET_RATE_PARENT,
520 static struct clk_rcg2 pclk1_clk_src = {
524 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "pclk1_clk_src",
527 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
529 .ops = &clk_pixel_ops,
530 .flags = CLK_SET_RATE_PARENT,
534 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
535 F(50000000, P_GPLL0, 12, 0, 0),
536 F(100000000, P_GPLL0, 6, 0, 0),
537 F(133330000, P_MMPLL0, 6, 0, 0),
538 F(200000000, P_MMPLL0, 4, 0, 0),
539 F(266670000, P_MMPLL0, 3, 0, 0),
540 F(465000000, P_MMPLL3, 2, 0, 0),
544 static struct clk_rcg2 vcodec0_clk_src = {
548 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
549 .freq_tbl = ftbl_venus0_vcodec0_clk,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "vcodec0_clk_src",
552 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
554 .ops = &clk_rcg2_ops,
558 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
559 F(19200000, P_XO, 1, 0, 0),
563 static struct clk_rcg2 cci_clk_src = {
566 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
567 .freq_tbl = ftbl_camss_cci_cci_clk,
568 .clkr.hw.init = &(struct clk_init_data){
569 .name = "cci_clk_src",
570 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
572 .ops = &clk_rcg2_ops,
576 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
577 F(10000, P_XO, 16, 1, 120),
578 F(24000, P_XO, 16, 1, 50),
579 F(6000000, P_GPLL0, 10, 1, 10),
580 F(12000000, P_GPLL0, 10, 1, 5),
581 F(13000000, P_GPLL0, 4, 13, 150),
582 F(24000000, P_GPLL0, 5, 1, 5),
586 static struct clk_rcg2 camss_gp0_clk_src = {
590 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
591 .freq_tbl = ftbl_camss_gp0_1_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "camss_gp0_clk_src",
594 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
596 .ops = &clk_rcg2_ops,
600 static struct clk_rcg2 camss_gp1_clk_src = {
604 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
605 .freq_tbl = ftbl_camss_gp0_1_clk,
606 .clkr.hw.init = &(struct clk_init_data){
607 .name = "camss_gp1_clk_src",
608 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
610 .ops = &clk_rcg2_ops,
614 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
615 F(4800000, P_XO, 4, 0, 0),
616 F(6000000, P_GPLL0, 10, 1, 10),
617 F(8000000, P_GPLL0, 15, 1, 5),
618 F(9600000, P_XO, 2, 0, 0),
619 F(16000000, P_GPLL0, 12.5, 1, 3),
620 F(19200000, P_XO, 1, 0, 0),
621 F(24000000, P_GPLL0, 5, 1, 5),
622 F(32000000, P_MMPLL0, 5, 1, 5),
623 F(48000000, P_GPLL0, 12.5, 0, 0),
624 F(64000000, P_MMPLL0, 12.5, 0, 0),
625 F(66670000, P_GPLL0, 9, 0, 0),
629 static struct clk_rcg2 mclk0_clk_src = {
632 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
633 .freq_tbl = ftbl_camss_mclk0_3_clk,
634 .clkr.hw.init = &(struct clk_init_data){
635 .name = "mclk0_clk_src",
636 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
638 .ops = &clk_rcg2_ops,
642 static struct clk_rcg2 mclk1_clk_src = {
645 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
646 .freq_tbl = ftbl_camss_mclk0_3_clk,
647 .clkr.hw.init = &(struct clk_init_data){
648 .name = "mclk1_clk_src",
649 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
651 .ops = &clk_rcg2_ops,
655 static struct clk_rcg2 mclk2_clk_src = {
658 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
659 .freq_tbl = ftbl_camss_mclk0_3_clk,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "mclk2_clk_src",
662 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
664 .ops = &clk_rcg2_ops,
668 static struct clk_rcg2 mclk3_clk_src = {
671 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
672 .freq_tbl = ftbl_camss_mclk0_3_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "mclk3_clk_src",
675 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
677 .ops = &clk_rcg2_ops,
681 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
682 F(100000000, P_GPLL0, 6, 0, 0),
683 F(200000000, P_MMPLL0, 4, 0, 0),
687 static struct clk_rcg2 csi0phytimer_clk_src = {
690 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
691 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "csi0phytimer_clk_src",
694 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
696 .ops = &clk_rcg2_ops,
700 static struct clk_rcg2 csi1phytimer_clk_src = {
703 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
704 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
705 .clkr.hw.init = &(struct clk_init_data){
706 .name = "csi1phytimer_clk_src",
707 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
709 .ops = &clk_rcg2_ops,
713 static struct clk_rcg2 csi2phytimer_clk_src = {
716 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
717 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
718 .clkr.hw.init = &(struct clk_init_data){
719 .name = "csi2phytimer_clk_src",
720 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
722 .ops = &clk_rcg2_ops,
726 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
727 F(133330000, P_GPLL0, 4.5, 0, 0),
728 F(266670000, P_MMPLL0, 3, 0, 0),
729 F(320000000, P_MMPLL0, 2.5, 0, 0),
730 F(400000000, P_MMPLL0, 2, 0, 0),
731 F(465000000, P_MMPLL3, 2, 0, 0),
735 static struct clk_rcg2 cpp_clk_src = {
738 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
739 .freq_tbl = ftbl_camss_vfe_cpp_clk,
740 .clkr.hw.init = &(struct clk_init_data){
741 .name = "cpp_clk_src",
742 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
744 .ops = &clk_rcg2_ops,
748 static struct freq_tbl byte_freq_tbl[] = {
749 { .src = P_DSI0PLL_BYTE },
753 static struct clk_rcg2 byte0_clk_src = {
756 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
757 .freq_tbl = byte_freq_tbl,
758 .clkr.hw.init = &(struct clk_init_data){
759 .name = "byte0_clk_src",
760 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
762 .ops = &clk_byte2_ops,
763 .flags = CLK_SET_RATE_PARENT,
767 static struct clk_rcg2 byte1_clk_src = {
770 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
771 .freq_tbl = byte_freq_tbl,
772 .clkr.hw.init = &(struct clk_init_data){
773 .name = "byte1_clk_src",
774 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
776 .ops = &clk_byte2_ops,
777 .flags = CLK_SET_RATE_PARENT,
781 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
782 F(19200000, P_XO, 1, 0, 0),
786 static struct clk_rcg2 edpaux_clk_src = {
789 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
790 .freq_tbl = ftbl_mdss_edpaux_clk,
791 .clkr.hw.init = &(struct clk_init_data){
792 .name = "edpaux_clk_src",
793 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
795 .ops = &clk_rcg2_ops,
799 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
800 F(135000000, P_EDPLINK, 2, 0, 0),
801 F(270000000, P_EDPLINK, 11, 0, 0),
805 static struct clk_rcg2 edplink_clk_src = {
808 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
809 .freq_tbl = ftbl_mdss_edplink_clk,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "edplink_clk_src",
812 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
814 .ops = &clk_rcg2_ops,
815 .flags = CLK_SET_RATE_PARENT,
819 static struct freq_tbl edp_pixel_freq_tbl[] = {
824 static struct clk_rcg2 edppixel_clk_src = {
828 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
829 .freq_tbl = edp_pixel_freq_tbl,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "edppixel_clk_src",
832 .parent_names = mmcc_xo_dsi_hdmi_edp,
834 .ops = &clk_edp_pixel_ops,
838 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
839 F(19200000, P_XO, 1, 0, 0),
843 static struct clk_rcg2 esc0_clk_src = {
846 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
847 .freq_tbl = ftbl_mdss_esc0_1_clk,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "esc0_clk_src",
850 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
852 .ops = &clk_rcg2_ops,
856 static struct clk_rcg2 esc1_clk_src = {
859 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
860 .freq_tbl = ftbl_mdss_esc0_1_clk,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "esc1_clk_src",
863 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
865 .ops = &clk_rcg2_ops,
869 static struct freq_tbl extpclk_freq_tbl[] = {
870 { .src = P_HDMIPLL },
874 static struct clk_rcg2 extpclk_clk_src = {
877 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
878 .freq_tbl = extpclk_freq_tbl,
879 .clkr.hw.init = &(struct clk_init_data){
880 .name = "extpclk_clk_src",
881 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
883 .ops = &clk_byte_ops,
884 .flags = CLK_SET_RATE_PARENT,
888 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
889 F(19200000, P_XO, 1, 0, 0),
893 static struct clk_rcg2 hdmi_clk_src = {
896 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
897 .freq_tbl = ftbl_mdss_hdmi_clk,
898 .clkr.hw.init = &(struct clk_init_data){
899 .name = "hdmi_clk_src",
900 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
902 .ops = &clk_rcg2_ops,
906 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
907 F(19200000, P_XO, 1, 0, 0),
911 static struct clk_rcg2 vsync_clk_src = {
914 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
915 .freq_tbl = ftbl_mdss_vsync_clk,
916 .clkr.hw.init = &(struct clk_init_data){
917 .name = "vsync_clk_src",
918 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
920 .ops = &clk_rcg2_ops,
924 static struct clk_branch camss_cci_cci_ahb_clk = {
927 .enable_reg = 0x3348,
928 .enable_mask = BIT(0),
929 .hw.init = &(struct clk_init_data){
930 .name = "camss_cci_cci_ahb_clk",
931 .parent_names = (const char *[]){
935 .ops = &clk_branch2_ops,
940 static struct clk_branch camss_cci_cci_clk = {
943 .enable_reg = 0x3344,
944 .enable_mask = BIT(0),
945 .hw.init = &(struct clk_init_data){
946 .name = "camss_cci_cci_clk",
947 .parent_names = (const char *[]){
951 .flags = CLK_SET_RATE_PARENT,
952 .ops = &clk_branch2_ops,
957 static struct clk_branch camss_csi0_ahb_clk = {
960 .enable_reg = 0x30bc,
961 .enable_mask = BIT(0),
962 .hw.init = &(struct clk_init_data){
963 .name = "camss_csi0_ahb_clk",
964 .parent_names = (const char *[]){
968 .ops = &clk_branch2_ops,
973 static struct clk_branch camss_csi0_clk = {
976 .enable_reg = 0x30b4,
977 .enable_mask = BIT(0),
978 .hw.init = &(struct clk_init_data){
979 .name = "camss_csi0_clk",
980 .parent_names = (const char *[]){
984 .flags = CLK_SET_RATE_PARENT,
985 .ops = &clk_branch2_ops,
990 static struct clk_branch camss_csi0phy_clk = {
993 .enable_reg = 0x30c4,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "camss_csi0phy_clk",
997 .parent_names = (const char *[]){
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1007 static struct clk_branch camss_csi0pix_clk = {
1010 .enable_reg = 0x30e4,
1011 .enable_mask = BIT(0),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "camss_csi0pix_clk",
1014 .parent_names = (const char *[]){
1018 .flags = CLK_SET_RATE_PARENT,
1019 .ops = &clk_branch2_ops,
1024 static struct clk_branch camss_csi0rdi_clk = {
1027 .enable_reg = 0x30d4,
1028 .enable_mask = BIT(0),
1029 .hw.init = &(struct clk_init_data){
1030 .name = "camss_csi0rdi_clk",
1031 .parent_names = (const char *[]){
1035 .flags = CLK_SET_RATE_PARENT,
1036 .ops = &clk_branch2_ops,
1041 static struct clk_branch camss_csi1_ahb_clk = {
1044 .enable_reg = 0x3128,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "camss_csi1_ahb_clk",
1048 .parent_names = (const char *[]){
1052 .ops = &clk_branch2_ops,
1057 static struct clk_branch camss_csi1_clk = {
1060 .enable_reg = 0x3124,
1061 .enable_mask = BIT(0),
1062 .hw.init = &(struct clk_init_data){
1063 .name = "camss_csi1_clk",
1064 .parent_names = (const char *[]){
1068 .flags = CLK_SET_RATE_PARENT,
1069 .ops = &clk_branch2_ops,
1074 static struct clk_branch camss_csi1phy_clk = {
1077 .enable_reg = 0x3134,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(struct clk_init_data){
1080 .name = "camss_csi1phy_clk",
1081 .parent_names = (const char *[]){
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_branch2_ops,
1091 static struct clk_branch camss_csi1pix_clk = {
1094 .enable_reg = 0x3154,
1095 .enable_mask = BIT(0),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "camss_csi1pix_clk",
1098 .parent_names = (const char *[]){
1102 .flags = CLK_SET_RATE_PARENT,
1103 .ops = &clk_branch2_ops,
1108 static struct clk_branch camss_csi1rdi_clk = {
1111 .enable_reg = 0x3144,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "camss_csi1rdi_clk",
1115 .parent_names = (const char *[]){
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1125 static struct clk_branch camss_csi2_ahb_clk = {
1128 .enable_reg = 0x3188,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "camss_csi2_ahb_clk",
1132 .parent_names = (const char *[]){
1136 .ops = &clk_branch2_ops,
1141 static struct clk_branch camss_csi2_clk = {
1144 .enable_reg = 0x3184,
1145 .enable_mask = BIT(0),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "camss_csi2_clk",
1148 .parent_names = (const char *[]){
1152 .flags = CLK_SET_RATE_PARENT,
1153 .ops = &clk_branch2_ops,
1158 static struct clk_branch camss_csi2phy_clk = {
1161 .enable_reg = 0x3194,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "camss_csi2phy_clk",
1165 .parent_names = (const char *[]){
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1175 static struct clk_branch camss_csi2pix_clk = {
1178 .enable_reg = 0x31b4,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "camss_csi2pix_clk",
1182 .parent_names = (const char *[]){
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1192 static struct clk_branch camss_csi2rdi_clk = {
1195 .enable_reg = 0x31a4,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "camss_csi2rdi_clk",
1199 .parent_names = (const char *[]){
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1209 static struct clk_branch camss_csi3_ahb_clk = {
1212 .enable_reg = 0x31e8,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_csi3_ahb_clk",
1216 .parent_names = (const char *[]){
1220 .ops = &clk_branch2_ops,
1225 static struct clk_branch camss_csi3_clk = {
1228 .enable_reg = 0x31e4,
1229 .enable_mask = BIT(0),
1230 .hw.init = &(struct clk_init_data){
1231 .name = "camss_csi3_clk",
1232 .parent_names = (const char *[]){
1236 .flags = CLK_SET_RATE_PARENT,
1237 .ops = &clk_branch2_ops,
1242 static struct clk_branch camss_csi3phy_clk = {
1245 .enable_reg = 0x31f4,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "camss_csi3phy_clk",
1249 .parent_names = (const char *[]){
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1259 static struct clk_branch camss_csi3pix_clk = {
1262 .enable_reg = 0x3214,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "camss_csi3pix_clk",
1266 .parent_names = (const char *[]){
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1276 static struct clk_branch camss_csi3rdi_clk = {
1279 .enable_reg = 0x3204,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "camss_csi3rdi_clk",
1283 .parent_names = (const char *[]){
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1293 static struct clk_branch camss_csi_vfe0_clk = {
1296 .enable_reg = 0x3704,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "camss_csi_vfe0_clk",
1300 .parent_names = (const char *[]){
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_branch2_ops,
1310 static struct clk_branch camss_csi_vfe1_clk = {
1313 .enable_reg = 0x3714,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi_vfe1_clk",
1317 .parent_names = (const char *[]){
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1327 static struct clk_branch camss_gp0_clk = {
1330 .enable_reg = 0x3444,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "camss_gp0_clk",
1334 .parent_names = (const char *[]){
1335 "camss_gp0_clk_src",
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1344 static struct clk_branch camss_gp1_clk = {
1347 .enable_reg = 0x3474,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "camss_gp1_clk",
1351 .parent_names = (const char *[]){
1352 "camss_gp1_clk_src",
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_branch2_ops,
1361 static struct clk_branch camss_ispif_ahb_clk = {
1364 .enable_reg = 0x3224,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_ispif_ahb_clk",
1368 .parent_names = (const char *[]){
1372 .ops = &clk_branch2_ops,
1377 static struct clk_branch camss_jpeg_jpeg0_clk = {
1380 .enable_reg = 0x35a8,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "camss_jpeg_jpeg0_clk",
1384 .parent_names = (const char *[]){
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1394 static struct clk_branch camss_jpeg_jpeg1_clk = {
1397 .enable_reg = 0x35ac,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "camss_jpeg_jpeg1_clk",
1401 .parent_names = (const char *[]){
1405 .flags = CLK_SET_RATE_PARENT,
1406 .ops = &clk_branch2_ops,
1411 static struct clk_branch camss_jpeg_jpeg2_clk = {
1414 .enable_reg = 0x35b0,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "camss_jpeg_jpeg2_clk",
1418 .parent_names = (const char *[]){
1422 .flags = CLK_SET_RATE_PARENT,
1423 .ops = &clk_branch2_ops,
1428 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1431 .enable_reg = 0x35b4,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data){
1434 .name = "camss_jpeg_jpeg_ahb_clk",
1435 .parent_names = (const char *[]){
1439 .ops = &clk_branch2_ops,
1444 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1447 .enable_reg = 0x35b8,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "camss_jpeg_jpeg_axi_clk",
1451 .parent_names = (const char *[]){
1455 .ops = &clk_branch2_ops,
1460 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1463 .enable_reg = 0x35bc,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(struct clk_init_data){
1466 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1467 .parent_names = (const char *[]){
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1477 static struct clk_branch camss_mclk0_clk = {
1480 .enable_reg = 0x3384,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "camss_mclk0_clk",
1484 .parent_names = (const char *[]){
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1494 static struct clk_branch camss_mclk1_clk = {
1497 .enable_reg = 0x33b4,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_mclk1_clk",
1501 .parent_names = (const char *[]){
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1511 static struct clk_branch camss_mclk2_clk = {
1514 .enable_reg = 0x33e4,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "camss_mclk2_clk",
1518 .parent_names = (const char *[]){
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1528 static struct clk_branch camss_mclk3_clk = {
1531 .enable_reg = 0x3414,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "camss_mclk3_clk",
1535 .parent_names = (const char *[]){
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1545 static struct clk_branch camss_micro_ahb_clk = {
1548 .enable_reg = 0x3494,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_micro_ahb_clk",
1552 .parent_names = (const char *[]){
1556 .ops = &clk_branch2_ops,
1561 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1564 .enable_reg = 0x3024,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "camss_phy0_csi0phytimer_clk",
1568 .parent_names = (const char *[]){
1569 "csi0phytimer_clk_src",
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1578 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1581 .enable_reg = 0x3054,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "camss_phy1_csi1phytimer_clk",
1585 .parent_names = (const char *[]){
1586 "csi1phytimer_clk_src",
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1598 .enable_reg = 0x3084,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camss_phy2_csi2phytimer_clk",
1602 .parent_names = (const char *[]){
1603 "csi2phytimer_clk_src",
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1612 static struct clk_branch camss_top_ahb_clk = {
1615 .enable_reg = 0x3484,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "camss_top_ahb_clk",
1619 .parent_names = (const char *[]){
1623 .ops = &clk_branch2_ops,
1628 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1631 .enable_reg = 0x36b4,
1632 .enable_mask = BIT(0),
1633 .hw.init = &(struct clk_init_data){
1634 .name = "camss_vfe_cpp_ahb_clk",
1635 .parent_names = (const char *[]){
1639 .ops = &clk_branch2_ops,
1644 static struct clk_branch camss_vfe_cpp_clk = {
1647 .enable_reg = 0x36b0,
1648 .enable_mask = BIT(0),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "camss_vfe_cpp_clk",
1651 .parent_names = (const char *[]){
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch camss_vfe_vfe0_clk = {
1664 .enable_reg = 0x36a8,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_vfe_vfe0_clk",
1668 .parent_names = (const char *[]){
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1678 static struct clk_branch camss_vfe_vfe1_clk = {
1681 .enable_reg = 0x36ac,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_vfe_vfe1_clk",
1685 .parent_names = (const char *[]){
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1695 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1698 .enable_reg = 0x36b8,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_vfe_vfe_ahb_clk",
1702 .parent_names = (const char *[]){
1706 .ops = &clk_branch2_ops,
1711 static struct clk_branch camss_vfe_vfe_axi_clk = {
1714 .enable_reg = 0x36bc,
1715 .enable_mask = BIT(0),
1716 .hw.init = &(struct clk_init_data){
1717 .name = "camss_vfe_vfe_axi_clk",
1718 .parent_names = (const char *[]){
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1730 .enable_reg = 0x36c0,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "camss_vfe_vfe_ocmemnoc_clk",
1734 .parent_names = (const char *[]){
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch mdss_ahb_clk = {
1747 .enable_reg = 0x2308,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "mdss_ahb_clk",
1751 .parent_names = (const char *[]){
1755 .ops = &clk_branch2_ops,
1760 static struct clk_branch mdss_axi_clk = {
1763 .enable_reg = 0x2310,
1764 .enable_mask = BIT(0),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "mdss_axi_clk",
1767 .parent_names = (const char *[]){
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch mdss_byte0_clk = {
1780 .enable_reg = 0x233c,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "mdss_byte0_clk",
1784 .parent_names = (const char *[]){
1788 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch mdss_byte1_clk = {
1797 .enable_reg = 0x2340,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "mdss_byte1_clk",
1801 .parent_names = (const char *[]){
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1811 static struct clk_branch mdss_edpaux_clk = {
1814 .enable_reg = 0x2334,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "mdss_edpaux_clk",
1818 .parent_names = (const char *[]){
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1828 static struct clk_branch mdss_edplink_clk = {
1831 .enable_reg = 0x2330,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "mdss_edplink_clk",
1835 .parent_names = (const char *[]){
1839 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops,
1845 static struct clk_branch mdss_edppixel_clk = {
1848 .enable_reg = 0x232c,
1849 .enable_mask = BIT(0),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "mdss_edppixel_clk",
1852 .parent_names = (const char *[]){
1856 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops,
1862 static struct clk_branch mdss_esc0_clk = {
1865 .enable_reg = 0x2344,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "mdss_esc0_clk",
1869 .parent_names = (const char *[]){
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1879 static struct clk_branch mdss_esc1_clk = {
1882 .enable_reg = 0x2348,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data){
1885 .name = "mdss_esc1_clk",
1886 .parent_names = (const char *[]){
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch mdss_extpclk_clk = {
1899 .enable_reg = 0x2324,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_extpclk_clk",
1903 .parent_names = (const char *[]){
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1913 static struct clk_branch mdss_hdmi_ahb_clk = {
1916 .enable_reg = 0x230c,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "mdss_hdmi_ahb_clk",
1920 .parent_names = (const char *[]){
1924 .ops = &clk_branch2_ops,
1929 static struct clk_branch mdss_hdmi_clk = {
1932 .enable_reg = 0x2338,
1933 .enable_mask = BIT(0),
1934 .hw.init = &(struct clk_init_data){
1935 .name = "mdss_hdmi_clk",
1936 .parent_names = (const char *[]){
1940 .flags = CLK_SET_RATE_PARENT,
1941 .ops = &clk_branch2_ops,
1946 static struct clk_branch mdss_mdp_clk = {
1949 .enable_reg = 0x231c,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "mdss_mdp_clk",
1953 .parent_names = (const char *[]){
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1963 static struct clk_branch mdss_mdp_lut_clk = {
1966 .enable_reg = 0x2320,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "mdss_mdp_lut_clk",
1970 .parent_names = (const char *[]){
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1980 static struct clk_branch mdss_pclk0_clk = {
1983 .enable_reg = 0x2314,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "mdss_pclk0_clk",
1987 .parent_names = (const char *[]){
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1997 static struct clk_branch mdss_pclk1_clk = {
2000 .enable_reg = 0x2318,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "mdss_pclk1_clk",
2004 .parent_names = (const char *[]){
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch mdss_vsync_clk = {
2017 .enable_reg = 0x2328,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "mdss_vsync_clk",
2021 .parent_names = (const char *[]){
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2031 static struct clk_branch mmss_misc_ahb_clk = {
2034 .enable_reg = 0x502c,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "mmss_misc_ahb_clk",
2038 .parent_names = (const char *[]){
2042 .ops = &clk_branch2_ops,
2047 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2050 .enable_reg = 0x5024,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "mmss_mmssnoc_ahb_clk",
2054 .parent_names = (const char *[]){
2058 .ops = &clk_branch2_ops,
2059 .flags = CLK_IGNORE_UNUSED,
2064 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2067 .enable_reg = 0x5028,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mmss_mmssnoc_bto_ahb_clk",
2071 .parent_names = (const char *[]){
2075 .ops = &clk_branch2_ops,
2076 .flags = CLK_IGNORE_UNUSED,
2081 static struct clk_branch mmss_mmssnoc_axi_clk = {
2084 .enable_reg = 0x506c,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mmss_mmssnoc_axi_clk",
2088 .parent_names = (const char *[]){
2092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch mmss_s0_axi_clk = {
2101 .enable_reg = 0x5064,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mmss_s0_axi_clk",
2105 .parent_names = (const char *[]){
2109 .ops = &clk_branch2_ops,
2110 .flags = CLK_IGNORE_UNUSED,
2115 static struct clk_branch ocmemcx_ahb_clk = {
2118 .enable_reg = 0x405c,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "ocmemcx_ahb_clk",
2122 .parent_names = (const char *[]){
2126 .ops = &clk_branch2_ops,
2131 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2134 .enable_reg = 0x4058,
2135 .enable_mask = BIT(0),
2136 .hw.init = &(struct clk_init_data){
2137 .name = "ocmemcx_ocmemnoc_clk",
2138 .parent_names = (const char *[]){
2142 .flags = CLK_SET_RATE_PARENT,
2143 .ops = &clk_branch2_ops,
2148 static struct clk_branch oxili_ocmemgx_clk = {
2151 .enable_reg = 0x402c,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "oxili_ocmemgx_clk",
2155 .parent_names = (const char *[]){
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2165 static struct clk_branch ocmemnoc_clk = {
2168 .enable_reg = 0x50b4,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "ocmemnoc_clk",
2172 .parent_names = (const char *[]){
2176 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops,
2182 static struct clk_branch oxili_gfx3d_clk = {
2185 .enable_reg = 0x4028,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "oxili_gfx3d_clk",
2189 .parent_names = (const char *[]){
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2199 static struct clk_branch oxilicx_ahb_clk = {
2202 .enable_reg = 0x403c,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "oxilicx_ahb_clk",
2206 .parent_names = (const char *[]){
2210 .ops = &clk_branch2_ops,
2215 static struct clk_branch oxilicx_axi_clk = {
2218 .enable_reg = 0x4038,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "oxilicx_axi_clk",
2222 .parent_names = (const char *[]){
2226 .ops = &clk_branch2_ops,
2231 static struct clk_branch venus0_ahb_clk = {
2234 .enable_reg = 0x1030,
2235 .enable_mask = BIT(0),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "venus0_ahb_clk",
2238 .parent_names = (const char *[]){
2242 .ops = &clk_branch2_ops,
2247 static struct clk_branch venus0_axi_clk = {
2250 .enable_reg = 0x1034,
2251 .enable_mask = BIT(0),
2252 .hw.init = &(struct clk_init_data){
2253 .name = "venus0_axi_clk",
2254 .parent_names = (const char *[]){
2258 .ops = &clk_branch2_ops,
2263 static struct clk_branch venus0_ocmemnoc_clk = {
2266 .enable_reg = 0x1038,
2267 .enable_mask = BIT(0),
2268 .hw.init = &(struct clk_init_data){
2269 .name = "venus0_ocmemnoc_clk",
2270 .parent_names = (const char *[]){
2274 .flags = CLK_SET_RATE_PARENT,
2275 .ops = &clk_branch2_ops,
2280 static struct clk_branch venus0_vcodec0_clk = {
2283 .enable_reg = 0x1028,
2284 .enable_mask = BIT(0),
2285 .hw.init = &(struct clk_init_data){
2286 .name = "venus0_vcodec0_clk",
2287 .parent_names = (const char *[]){
2291 .flags = CLK_SET_RATE_PARENT,
2292 .ops = &clk_branch2_ops,
2297 static const struct pll_config mmpll1_config = {
2302 .vco_mask = 0x3 << 20,
2304 .pre_div_mask = 0x7 << 12,
2305 .post_div_val = 0x0,
2306 .post_div_mask = 0x3 << 8,
2307 .mn_ena_mask = BIT(24),
2308 .main_output_mask = BIT(0),
2311 static struct pll_config mmpll3_config = {
2316 .vco_mask = 0x3 << 20,
2318 .pre_div_mask = 0x7 << 12,
2319 .post_div_val = 0x0,
2320 .post_div_mask = 0x3 << 8,
2321 .mn_ena_mask = BIT(24),
2322 .main_output_mask = BIT(0),
2323 .aux_output_mask = BIT(1),
2326 static struct gdsc venus0_gdsc = {
2328 .cxcs = (unsigned int []){ 0x1028 },
2330 .resets = (unsigned int []){ VENUS0_RESET },
2335 .pwrsts = PWRSTS_ON,
2338 static struct gdsc mdss_gdsc = {
2340 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2345 .pwrsts = PWRSTS_RET_ON,
2348 static struct gdsc camss_jpeg_gdsc = {
2350 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2353 .name = "camss_jpeg",
2355 .pwrsts = PWRSTS_OFF_ON,
2358 static struct gdsc camss_vfe_gdsc = {
2360 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2363 .name = "camss_vfe",
2365 .pwrsts = PWRSTS_OFF_ON,
2368 static struct gdsc oxili_gdsc = {
2370 .cxcs = (unsigned int []){ 0x4028 },
2375 .pwrsts = PWRSTS_OFF_ON,
2378 static struct gdsc oxilicx_gdsc = {
2383 .parent = &oxili_gdsc.pd,
2384 .pwrsts = PWRSTS_OFF_ON,
2387 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2388 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2389 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2390 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2391 [MMPLL0] = &mmpll0.clkr,
2392 [MMPLL0_VOTE] = &mmpll0_vote,
2393 [MMPLL1] = &mmpll1.clkr,
2394 [MMPLL1_VOTE] = &mmpll1_vote,
2395 [MMPLL2] = &mmpll2.clkr,
2396 [MMPLL3] = &mmpll3.clkr,
2397 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2398 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2399 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2400 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2401 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2402 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2403 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2404 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2405 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2406 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2407 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2408 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2409 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2410 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2411 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2412 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2413 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2414 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2415 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2416 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2417 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2418 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2419 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2420 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2421 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2422 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2423 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2424 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2425 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2426 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2427 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2428 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2429 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2430 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2431 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2432 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2433 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2434 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2435 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2436 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2437 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2438 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2439 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2440 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2441 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2442 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2443 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2444 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2445 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2446 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2447 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2448 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2449 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2450 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2451 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2452 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2453 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2454 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2455 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2456 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2457 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2458 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2459 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2460 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2461 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2462 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2463 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2464 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2465 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2466 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2467 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2468 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2469 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2470 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2471 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2472 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2473 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2474 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2475 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2476 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2477 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2478 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2479 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2480 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2481 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2482 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2483 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2484 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2485 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2486 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2487 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2488 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2489 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2490 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2491 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2492 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2493 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2494 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2495 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2496 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2497 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2498 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2499 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2500 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2501 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2502 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2503 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2504 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2505 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2506 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2507 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2508 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2509 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2510 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2511 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2512 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2515 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2516 [SPDM_RESET] = { 0x0200 },
2517 [SPDM_RM_RESET] = { 0x0300 },
2518 [VENUS0_RESET] = { 0x1020 },
2519 [MDSS_RESET] = { 0x2300 },
2520 [CAMSS_PHY0_RESET] = { 0x3020 },
2521 [CAMSS_PHY1_RESET] = { 0x3050 },
2522 [CAMSS_PHY2_RESET] = { 0x3080 },
2523 [CAMSS_CSI0_RESET] = { 0x30b0 },
2524 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2525 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2526 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2527 [CAMSS_CSI1_RESET] = { 0x3120 },
2528 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2529 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2530 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2531 [CAMSS_CSI2_RESET] = { 0x3180 },
2532 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2533 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2534 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2535 [CAMSS_CSI3_RESET] = { 0x31e0 },
2536 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2537 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2538 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2539 [CAMSS_ISPIF_RESET] = { 0x3220 },
2540 [CAMSS_CCI_RESET] = { 0x3340 },
2541 [CAMSS_MCLK0_RESET] = { 0x3380 },
2542 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2543 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2544 [CAMSS_MCLK3_RESET] = { 0x3410 },
2545 [CAMSS_GP0_RESET] = { 0x3440 },
2546 [CAMSS_GP1_RESET] = { 0x3470 },
2547 [CAMSS_TOP_RESET] = { 0x3480 },
2548 [CAMSS_MICRO_RESET] = { 0x3490 },
2549 [CAMSS_JPEG_RESET] = { 0x35a0 },
2550 [CAMSS_VFE_RESET] = { 0x36a0 },
2551 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2552 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2553 [OXILI_RESET] = { 0x4020 },
2554 [OXILICX_RESET] = { 0x4030 },
2555 [OCMEMCX_RESET] = { 0x4050 },
2556 [MMSS_RBCRP_RESET] = { 0x4080 },
2557 [MMSSNOCAHB_RESET] = { 0x5020 },
2558 [MMSSNOCAXI_RESET] = { 0x5060 },
2559 [OCMEMNOC_RESET] = { 0x50b0 },
2562 static struct gdsc *mmcc_msm8974_gdscs[] = {
2563 [VENUS0_GDSC] = &venus0_gdsc,
2564 [MDSS_GDSC] = &mdss_gdsc,
2565 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2566 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2567 [OXILI_GDSC] = &oxili_gdsc,
2568 [OXILICX_GDSC] = &oxilicx_gdsc,
2571 static const struct regmap_config mmcc_msm8974_regmap_config = {
2575 .max_register = 0x5104,
2579 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2580 .config = &mmcc_msm8974_regmap_config,
2581 .clks = mmcc_msm8974_clocks,
2582 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2583 .resets = mmcc_msm8974_resets,
2584 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2585 .gdscs = mmcc_msm8974_gdscs,
2586 .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2589 static const struct of_device_id mmcc_msm8974_match_table[] = {
2590 { .compatible = "qcom,mmcc-msm8974" },
2593 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2595 static int mmcc_msm8974_probe(struct platform_device *pdev)
2597 struct regmap *regmap;
2599 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2601 return PTR_ERR(regmap);
2603 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2604 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2606 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2609 static struct platform_driver mmcc_msm8974_driver = {
2610 .probe = mmcc_msm8974_probe,
2612 .name = "mmcc-msm8974",
2613 .of_match_table = mmcc_msm8974_match_table,
2616 module_platform_driver(mmcc_msm8974_driver);
2618 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2619 MODULE_LICENSE("GPL v2");
2620 MODULE_ALIAS("platform:mmcc-msm8974");