drivers/clk/qcom/mmcc-msm8974.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  18 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_MMPLL0,
  31         P_EDPLINK,
  32         P_MMPLL1,
  33         P_HDMIPLL,
  34         P_GPLL0,
  35         P_EDPVCO,
  36         P_GPLL1,
  37         P_DSI0PLL,
  38         P_DSI0PLL_BYTE,
  39         P_MMPLL2,
  40         P_MMPLL3,
  41         P_DSI1PLL,
  42         P_DSI1PLL_BYTE,
  43 };
  44
  45 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  46         { P_XO, 0 },
  47         { P_MMPLL0, 1 },
  48         { P_MMPLL1, 2 },
  49         { P_GPLL0, 5 }
  50 };
  51
  52 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  53         "xo",
  54         "mmpll0_vote",
  55         "mmpll1_vote",
  56         "mmss_gpll0_vote",
  57 };
  58
  59 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_MMPLL0, 1 },
  62         { P_HDMIPLL, 4 },
  63         { P_GPLL0, 5 },
  64         { P_DSI0PLL, 2 },
  65         { P_DSI1PLL, 3 }
  66 };
  67
  68 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  69         "xo",
  70         "mmpll0_vote",
  71         "hdmipll",
  72         "mmss_gpll0_vote",
  73         "dsi0pll",
  74         "dsi1pll",
  75 };
  76
  77 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
  78         { P_XO, 0 },
  79         { P_MMPLL0, 1 },
  80         { P_MMPLL1, 2 },
  81         { P_GPLL0, 5 },
  82         { P_MMPLL2, 3 }
  83 };
  84
  85 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
  86         "xo",
  87         "mmpll0_vote",
  88         "mmpll1_vote",
  89         "mmss_gpll0_vote",
  90         "mmpll2",
  91 };
  92
  93 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  94         { P_XO, 0 },
  95         { P_MMPLL0, 1 },
  96         { P_MMPLL1, 2 },
  97         { P_GPLL0, 5 },
  98         { P_MMPLL3, 3 }
  99 };
 100
 101 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
 102         "xo",
 103         "mmpll0_vote",
 104         "mmpll1_vote",
 105         "mmss_gpll0_vote",
 106         "mmpll3",
 107 };
 108
 109 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
 110         { P_XO, 0 },
 111         { P_MMPLL0, 1 },
 112         { P_MMPLL1, 2 },
 113         { P_GPLL0, 5 },
 114         { P_GPLL1, 4 }
 115 };
 116
 117 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
 118         "xo",
 119         "mmpll0_vote",
 120         "mmpll1_vote",
 121         "mmss_gpll0_vote",
 122         "gpll1_vote",
 123 };
 124
 125 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 126         { P_XO, 0 },
 127         { P_EDPLINK, 4 },
 128         { P_HDMIPLL, 3 },
 129         { P_EDPVCO, 5 },
 130         { P_DSI0PLL, 1 },
 131         { P_DSI1PLL, 2 }
 132 };
 133
 134 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
 135         "xo",
 136         "edp_link_clk",
 137         "hdmipll",
 138         "edp_vco_div",
 139         "dsi0pll",
 140         "dsi1pll",
 141 };
 142
 143 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 144         { P_XO, 0 },
 145         { P_EDPLINK, 4 },
 146         { P_HDMIPLL, 3 },
 147         { P_GPLL0, 5 },
 148         { P_DSI0PLL, 1 },
 149         { P_DSI1PLL, 2 }
 150 };
 151
 152 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 153         "xo",
 154         "edp_link_clk",
 155         "hdmipll",
 156         "gpll0_vote",
 157         "dsi0pll",
 158         "dsi1pll",
 159 };
 160
 161 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 162         { P_XO, 0 },
 163         { P_EDPLINK, 4 },
 164         { P_HDMIPLL, 3 },
 165         { P_GPLL0, 5 },
 166         { P_DSI0PLL_BYTE, 1 },
 167         { P_DSI1PLL_BYTE, 2 }
 168 };
 169
 170 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 171         "xo",
 172         "edp_link_clk",
 173         "hdmipll",
 174         "gpll0_vote",
 175         "dsi0pllbyte",
 176         "dsi1pllbyte",
 177 };
 178
 179 static struct clk_pll mmpll0 = {
 180         .l_reg = 0x0004,
 181         .m_reg = 0x0008,
 182         .n_reg = 0x000c,
 183         .config_reg = 0x0014,
 184         .mode_reg = 0x0000,
 185         .status_reg = 0x001c,
 186         .status_bit = 17,
 187         .clkr.hw.init = &(struct clk_init_data){
 188                 .name = "mmpll0",
 189                 .parent_names = (const char *[]){ "xo" },
 190                 .num_parents = 1,
 191                 .ops = &clk_pll_ops,
 192         },
 193 };
 194
 195 static struct clk_regmap mmpll0_vote = {
 196         .enable_reg = 0x0100,
 197         .enable_mask = BIT(0),
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "mmpll0_vote",
 200                 .parent_names = (const char *[]){ "mmpll0" },
 201                 .num_parents = 1,
 202                 .ops = &clk_pll_vote_ops,
 203         },
 204 };
 205
 206 static struct clk_pll mmpll1 = {
 207         .l_reg = 0x0044,
 208         .m_reg = 0x0048,
 209         .n_reg = 0x004c,
 210         .config_reg = 0x0050,
 211         .mode_reg = 0x0040,
 212         .status_reg = 0x005c,
 213         .status_bit = 17,
 214         .clkr.hw.init = &(struct clk_init_data){
 215                 .name = "mmpll1",
 216                 .parent_names = (const char *[]){ "xo" },
 217                 .num_parents = 1,
 218                 .ops = &clk_pll_ops,
 219         },
 220 };
 221
 222 static struct clk_regmap mmpll1_vote = {
 223         .enable_reg = 0x0100,
 224         .enable_mask = BIT(1),
 225         .hw.init = &(struct clk_init_data){
 226                 .name = "mmpll1_vote",
 227                 .parent_names = (const char *[]){ "mmpll1" },
 228                 .num_parents = 1,
 229                 .ops = &clk_pll_vote_ops,
 230         },
 231 };
 232
 233 static struct clk_pll mmpll2 = {
 234         .l_reg = 0x4104,
 235         .m_reg = 0x4108,
 236         .n_reg = 0x410c,
 237         .config_reg = 0x4110,
 238         .mode_reg = 0x4100,
 239         .status_reg = 0x411c,
 240         .clkr.hw.init = &(struct clk_init_data){
 241                 .name = "mmpll2",
 242                 .parent_names = (const char *[]){ "xo" },
 243                 .num_parents = 1,
 244                 .ops = &clk_pll_ops,
 245         },
 246 };
 247
 248 static struct clk_pll mmpll3 = {
 249         .l_reg = 0x0084,
 250         .m_reg = 0x0088,
 251         .n_reg = 0x008c,
 252         .config_reg = 0x0090,
 253         .mode_reg = 0x0080,
 254         .status_reg = 0x009c,
 255         .status_bit = 17,
 256         .clkr.hw.init = &(struct clk_init_data){
 257                 .name = "mmpll3",
 258                 .parent_names = (const char *[]){ "xo" },
 259                 .num_parents = 1,
 260                 .ops = &clk_pll_ops,
 261         },
 262 };
 263
 264 static struct clk_rcg2 mmss_ahb_clk_src = {
 265         .cmd_rcgr = 0x5000,
 266         .hid_width = 5,
 267         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 268         .clkr.hw.init = &(struct clk_init_data){
 269                 .name = "mmss_ahb_clk_src",
 270                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 271                 .num_parents = 4,
 272                 .ops = &clk_rcg2_ops,
 273         },
 274 };
 275
 276 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 277         F( 19200000, P_XO, 1, 0, 0),
 278         F( 37500000, P_GPLL0, 16, 0, 0),
 279         F( 50000000, P_GPLL0, 12, 0, 0),
 280         F( 75000000, P_GPLL0, 8, 0, 0),
 281         F(100000000, P_GPLL0, 6, 0, 0),
 282         F(150000000, P_GPLL0, 4, 0, 0),
 283         F(291750000, P_MMPLL1, 4, 0, 0),
 284         F(400000000, P_MMPLL0, 2, 0, 0),
 285         F(466800000, P_MMPLL1, 2.5, 0, 0),
 286         { }
 287 };
 288
 289 static struct clk_rcg2 mmss_axi_clk_src = {
 290         .cmd_rcgr = 0x5040,
 291         .hid_width = 5,
 292         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 293         .freq_tbl = ftbl_mmss_axi_clk,
 294         .clkr.hw.init = &(struct clk_init_data){
 295                 .name = "mmss_axi_clk_src",
 296                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 297                 .num_parents = 4,
 298                 .ops = &clk_rcg2_ops,
 299         },
 300 };
 301
 302 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 303         F( 19200000, P_XO, 1, 0, 0),
 304         F( 37500000, P_GPLL0, 16, 0, 0),
 305         F( 50000000, P_GPLL0, 12, 0, 0),
 306         F( 75000000, P_GPLL0, 8, 0, 0),
 307         F(100000000, P_GPLL0, 6, 0, 0),
 308         F(150000000, P_GPLL0, 4, 0, 0),
 309         F(291750000, P_MMPLL1, 4, 0, 0),
 310         F(400000000, P_MMPLL0, 2, 0, 0),
 311         { }
 312 };
 313
 314 static struct clk_rcg2 ocmemnoc_clk_src = {
 315         .cmd_rcgr = 0x5090,
 316         .hid_width = 5,
 317         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 318         .freq_tbl = ftbl_ocmemnoc_clk,
 319         .clkr.hw.init = &(struct clk_init_data){
 320                 .name = "ocmemnoc_clk_src",
 321                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 322                 .num_parents = 4,
 323                 .ops = &clk_rcg2_ops,
 324         },
 325 };
 326
 327 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 328         F(100000000, P_GPLL0, 6, 0, 0),
 329         F(200000000, P_MMPLL0, 4, 0, 0),
 330         { }
 331 };
 332
 333 static struct clk_rcg2 csi0_clk_src = {
 334         .cmd_rcgr = 0x3090,
 335         .hid_width = 5,
 336         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 337         .freq_tbl = ftbl_camss_csi0_3_clk,
 338         .clkr.hw.init = &(struct clk_init_data){
 339                 .name = "csi0_clk_src",
 340                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 341                 .num_parents = 4,
 342                 .ops = &clk_rcg2_ops,
 343         },
 344 };
 345
 346 static struct clk_rcg2 csi1_clk_src = {
 347         .cmd_rcgr = 0x3100,
 348         .hid_width = 5,
 349         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 350         .freq_tbl = ftbl_camss_csi0_3_clk,
 351         .clkr.hw.init = &(struct clk_init_data){
 352                 .name = "csi1_clk_src",
 353                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 354                 .num_parents = 4,
 355                 .ops = &clk_rcg2_ops,
 356         },
 357 };
 358
 359 static struct clk_rcg2 csi2_clk_src = {
 360         .cmd_rcgr = 0x3160,
 361         .hid_width = 5,
 362         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 363         .freq_tbl = ftbl_camss_csi0_3_clk,
 364         .clkr.hw.init = &(struct clk_init_data){
 365                 .name = "csi2_clk_src",
 366                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 367                 .num_parents = 4,
 368                 .ops = &clk_rcg2_ops,
 369         },
 370 };
 371
 372 static struct clk_rcg2 csi3_clk_src = {
 373         .cmd_rcgr = 0x31c0,
 374         .hid_width = 5,
 375         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 376         .freq_tbl = ftbl_camss_csi0_3_clk,
 377         .clkr.hw.init = &(struct clk_init_data){
 378                 .name = "csi3_clk_src",
 379                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 380                 .num_parents = 4,
 381                 .ops = &clk_rcg2_ops,
 382         },
 383 };
 384
 385 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 386         F(37500000, P_GPLL0, 16, 0, 0),
 387         F(50000000, P_GPLL0, 12, 0, 0),
 388         F(60000000, P_GPLL0, 10, 0, 0),
 389         F(80000000, P_GPLL0, 7.5, 0, 0),
 390         F(100000000, P_GPLL0, 6, 0, 0),
 391         F(109090000, P_GPLL0, 5.5, 0, 0),
 392         F(133330000, P_GPLL0, 4.5, 0, 0),
 393         F(200000000, P_GPLL0, 3, 0, 0),
 394         F(228570000, P_MMPLL0, 3.5, 0, 0),
 395         F(266670000, P_MMPLL0, 3, 0, 0),
 396         F(320000000, P_MMPLL0, 2.5, 0, 0),
 397         F(400000000, P_MMPLL0, 2, 0, 0),
 398         F(465000000, P_MMPLL3, 2, 0, 0),
 399         { }
 400 };
 401
 402 static struct clk_rcg2 vfe0_clk_src = {
 403         .cmd_rcgr = 0x3600,
 404         .hid_width = 5,
 405         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 406         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 407         .clkr.hw.init = &(struct clk_init_data){
 408                 .name = "vfe0_clk_src",
 409                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 410                 .num_parents = 4,
 411                 .ops = &clk_rcg2_ops,
 412         },
 413 };
 414
 415 static struct clk_rcg2 vfe1_clk_src = {
 416         .cmd_rcgr = 0x3620,
 417         .hid_width = 5,
 418         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 419         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "vfe1_clk_src",
 422                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 423                 .num_parents = 4,
 424                 .ops = &clk_rcg2_ops,
 425         },
 426 };
 427
 428 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 429         F(37500000, P_GPLL0, 16, 0, 0),
 430         F(60000000, P_GPLL0, 10, 0, 0),
 431         F(75000000, P_GPLL0, 8, 0, 0),
 432         F(85710000, P_GPLL0, 7, 0, 0),
 433         F(100000000, P_GPLL0, 6, 0, 0),
 434         F(133330000, P_MMPLL0, 6, 0, 0),
 435         F(160000000, P_MMPLL0, 5, 0, 0),
 436         F(200000000, P_MMPLL0, 4, 0, 0),
 437         F(228570000, P_MMPLL0, 3.5, 0, 0),
 438         F(240000000, P_GPLL0, 2.5, 0, 0),
 439         F(266670000, P_MMPLL0, 3, 0, 0),
 440         F(320000000, P_MMPLL0, 2.5, 0, 0),
 441         { }
 442 };
 443
 444 static struct clk_rcg2 mdp_clk_src = {
 445         .cmd_rcgr = 0x2040,
 446         .hid_width = 5,
 447         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 448         .freq_tbl = ftbl_mdss_mdp_clk,
 449         .clkr.hw.init = &(struct clk_init_data){
 450                 .name = "mdp_clk_src",
 451                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 452                 .num_parents = 6,
 453                 .ops = &clk_rcg2_ops,
 454         },
 455 };
 456
 457 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 458         F(75000000, P_GPLL0, 8, 0, 0),
 459         F(133330000, P_GPLL0, 4.5, 0, 0),
 460         F(200000000, P_GPLL0, 3, 0, 0),
 461         F(228570000, P_MMPLL0, 3.5, 0, 0),
 462         F(266670000, P_MMPLL0, 3, 0, 0),
 463         F(320000000, P_MMPLL0, 2.5, 0, 0),
 464         { }
 465 };
 466
 467 static struct clk_rcg2 jpeg0_clk_src = {
 468         .cmd_rcgr = 0x3500,
 469         .hid_width = 5,
 470         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 471         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 472         .clkr.hw.init = &(struct clk_init_data){
 473                 .name = "jpeg0_clk_src",
 474                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 475                 .num_parents = 4,
 476                 .ops = &clk_rcg2_ops,
 477         },
 478 };
 479
 480 static struct clk_rcg2 jpeg1_clk_src = {
 481         .cmd_rcgr = 0x3520,
 482         .hid_width = 5,
 483         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 484         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 485         .clkr.hw.init = &(struct clk_init_data){
 486                 .name = "jpeg1_clk_src",
 487                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 488                 .num_parents = 4,
 489                 .ops = &clk_rcg2_ops,
 490         },
 491 };
 492
 493 static struct clk_rcg2 jpeg2_clk_src = {
 494         .cmd_rcgr = 0x3540,
 495         .hid_width = 5,
 496         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 497         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 498         .clkr.hw.init = &(struct clk_init_data){
 499                 .name = "jpeg2_clk_src",
 500                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 501                 .num_parents = 4,
 502                 .ops = &clk_rcg2_ops,
 503         },
 504 };
 505
 506 static struct clk_rcg2 pclk0_clk_src = {
 507         .cmd_rcgr = 0x2000,
 508         .mnd_width = 8,
 509         .hid_width = 5,
 510         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 511         .clkr.hw.init = &(struct clk_init_data){
 512                 .name = "pclk0_clk_src",
 513                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 514                 .num_parents = 6,
 515                 .ops = &clk_pixel_ops,
 516                 .flags = CLK_SET_RATE_PARENT,
 517         },
 518 };
 519
 520 static struct clk_rcg2 pclk1_clk_src = {
 521         .cmd_rcgr = 0x2020,
 522         .mnd_width = 8,
 523         .hid_width = 5,
 524         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 525         .clkr.hw.init = &(struct clk_init_data){
 526                 .name = "pclk1_clk_src",
 527                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 528                 .num_parents = 6,
 529                 .ops = &clk_pixel_ops,
 530                 .flags = CLK_SET_RATE_PARENT,
 531         },
 532 };
 533
 534 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 535         F(50000000, P_GPLL0, 12, 0, 0),
 536         F(100000000, P_GPLL0, 6, 0, 0),
 537         F(133330000, P_MMPLL0, 6, 0, 0),
 538         F(200000000, P_MMPLL0, 4, 0, 0),
 539         F(266670000, P_MMPLL0, 3, 0, 0),
 540         F(465000000, P_MMPLL3, 2, 0, 0),
 541         { }
 542 };
 543
 544 static struct clk_rcg2 vcodec0_clk_src = {
 545         .cmd_rcgr = 0x1000,
 546         .mnd_width = 8,
 547         .hid_width = 5,
 548         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 549         .freq_tbl = ftbl_venus0_vcodec0_clk,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "vcodec0_clk_src",
 552                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 553                 .num_parents = 5,
 554                 .ops = &clk_rcg2_ops,
 555         },
 556 };
 557
 558 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 559         F(19200000, P_XO, 1, 0, 0),
 560         { }
 561 };
 562
 563 static struct clk_rcg2 cci_clk_src = {
 564         .cmd_rcgr = 0x3300,
 565         .hid_width = 5,
 566         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 567         .freq_tbl = ftbl_camss_cci_cci_clk,
 568         .clkr.hw.init = &(struct clk_init_data){
 569                 .name = "cci_clk_src",
 570                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 571                 .num_parents = 4,
 572                 .ops = &clk_rcg2_ops,
 573         },
 574 };
 575
 576 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 577         F(10000, P_XO, 16, 1, 120),
 578         F(24000, P_XO, 16, 1, 50),
 579         F(6000000, P_GPLL0, 10, 1, 10),
 580         F(12000000, P_GPLL0, 10, 1, 5),
 581         F(13000000, P_GPLL0, 4, 13, 150),
 582         F(24000000, P_GPLL0, 5, 1, 5),
 583         { }
 584 };
 585
 586 static struct clk_rcg2 camss_gp0_clk_src = {
 587         .cmd_rcgr = 0x3420,
 588         .mnd_width = 8,
 589         .hid_width = 5,
 590         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 591         .freq_tbl = ftbl_camss_gp0_1_clk,
 592         .clkr.hw.init = &(struct clk_init_data){
 593                 .name = "camss_gp0_clk_src",
 594                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 595                 .num_parents = 5,
 596                 .ops = &clk_rcg2_ops,
 597         },
 598 };
 599
 600 static struct clk_rcg2 camss_gp1_clk_src = {
 601         .cmd_rcgr = 0x3450,
 602         .mnd_width = 8,
 603         .hid_width = 5,
 604         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 605         .freq_tbl = ftbl_camss_gp0_1_clk,
 606         .clkr.hw.init = &(struct clk_init_data){
 607                 .name = "camss_gp1_clk_src",
 608                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 609                 .num_parents = 5,
 610                 .ops = &clk_rcg2_ops,
 611         },
 612 };
 613
 614 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 615         F(4800000, P_XO, 4, 0, 0),
 616         F(6000000, P_GPLL0, 10, 1, 10),
 617         F(8000000, P_GPLL0, 15, 1, 5),
 618         F(9600000, P_XO, 2, 0, 0),
 619         F(16000000, P_GPLL0, 12.5, 1, 3),
 620         F(19200000, P_XO, 1, 0, 0),
 621         F(24000000, P_GPLL0, 5, 1, 5),
 622         F(32000000, P_MMPLL0, 5, 1, 5),
 623         F(48000000, P_GPLL0, 12.5, 0, 0),
 624         F(64000000, P_MMPLL0, 12.5, 0, 0),
 625         F(66670000, P_GPLL0, 9, 0, 0),
 626         { }
 627 };
 628
 629 static struct clk_rcg2 mclk0_clk_src = {
 630         .cmd_rcgr = 0x3360,
 631         .hid_width = 5,
 632         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 633         .freq_tbl = ftbl_camss_mclk0_3_clk,
 634         .clkr.hw.init = &(struct clk_init_data){
 635                 .name = "mclk0_clk_src",
 636                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 637                 .num_parents = 4,
 638                 .ops = &clk_rcg2_ops,
 639         },
 640 };
 641
 642 static struct clk_rcg2 mclk1_clk_src = {
 643         .cmd_rcgr = 0x3390,
 644         .hid_width = 5,
 645         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 646         .freq_tbl = ftbl_camss_mclk0_3_clk,
 647         .clkr.hw.init = &(struct clk_init_data){
 648                 .name = "mclk1_clk_src",
 649                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 650                 .num_parents = 4,
 651                 .ops = &clk_rcg2_ops,
 652         },
 653 };
 654
 655 static struct clk_rcg2 mclk2_clk_src = {
 656         .cmd_rcgr = 0x33c0,
 657         .hid_width = 5,
 658         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 659         .freq_tbl = ftbl_camss_mclk0_3_clk,
 660         .clkr.hw.init = &(struct clk_init_data){
 661                 .name = "mclk2_clk_src",
 662                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 663                 .num_parents = 4,
 664                 .ops = &clk_rcg2_ops,
 665         },
 666 };
 667
 668 static struct clk_rcg2 mclk3_clk_src = {
 669         .cmd_rcgr = 0x33f0,
 670         .hid_width = 5,
 671         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 672         .freq_tbl = ftbl_camss_mclk0_3_clk,
 673         .clkr.hw.init = &(struct clk_init_data){
 674                 .name = "mclk3_clk_src",
 675                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 676                 .num_parents = 4,
 677                 .ops = &clk_rcg2_ops,
 678         },
 679 };
 680
 681 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 682         F(100000000, P_GPLL0, 6, 0, 0),
 683         F(200000000, P_MMPLL0, 4, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 csi0phytimer_clk_src = {
 688         .cmd_rcgr = 0x3000,
 689         .hid_width = 5,
 690         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 691         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "csi0phytimer_clk_src",
 694                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 695                 .num_parents = 4,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_rcg2 csi1phytimer_clk_src = {
 701         .cmd_rcgr = 0x3030,
 702         .hid_width = 5,
 703         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 704         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "csi1phytimer_clk_src",
 707                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 708                 .num_parents = 4,
 709                 .ops = &clk_rcg2_ops,
 710         },
 711 };
 712
 713 static struct clk_rcg2 csi2phytimer_clk_src = {
 714         .cmd_rcgr = 0x3060,
 715         .hid_width = 5,
 716         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 717         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 718         .clkr.hw.init = &(struct clk_init_data){
 719                 .name = "csi2phytimer_clk_src",
 720                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 721                 .num_parents = 4,
 722                 .ops = &clk_rcg2_ops,
 723         },
 724 };
 725
 726 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 727         F(133330000, P_GPLL0, 4.5, 0, 0),
 728         F(266670000, P_MMPLL0, 3, 0, 0),
 729         F(320000000, P_MMPLL0, 2.5, 0, 0),
 730         F(400000000, P_MMPLL0, 2, 0, 0),
 731         F(465000000, P_MMPLL3, 2, 0, 0),
 732         { }
 733 };
 734
 735 static struct clk_rcg2 cpp_clk_src = {
 736         .cmd_rcgr = 0x3640,
 737         .hid_width = 5,
 738         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 739         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 740         .clkr.hw.init = &(struct clk_init_data){
 741                 .name = "cpp_clk_src",
 742                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 743                 .num_parents = 4,
 744                 .ops = &clk_rcg2_ops,
 745         },
 746 };
 747
 748 static struct freq_tbl byte_freq_tbl[] = {
 749         { .src = P_DSI0PLL_BYTE },
 750         { }
 751 };
 752
 753 static struct clk_rcg2 byte0_clk_src = {
 754         .cmd_rcgr = 0x2120,
 755         .hid_width = 5,
 756         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 757         .freq_tbl = byte_freq_tbl,
 758         .clkr.hw.init = &(struct clk_init_data){
 759                 .name = "byte0_clk_src",
 760                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 761                 .num_parents = 6,
 762                 .ops = &clk_byte2_ops,
 763                 .flags = CLK_SET_RATE_PARENT,
 764         },
 765 };
 766
 767 static struct clk_rcg2 byte1_clk_src = {
 768         .cmd_rcgr = 0x2140,
 769         .hid_width = 5,
 770         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 771         .freq_tbl = byte_freq_tbl,
 772         .clkr.hw.init = &(struct clk_init_data){
 773                 .name = "byte1_clk_src",
 774                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 775                 .num_parents = 6,
 776                 .ops = &clk_byte2_ops,
 777                 .flags = CLK_SET_RATE_PARENT,
 778         },
 779 };
 780
 781 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 782         F(19200000, P_XO, 1, 0, 0),
 783         { }
 784 };
 785
 786 static struct clk_rcg2 edpaux_clk_src = {
 787         .cmd_rcgr = 0x20e0,
 788         .hid_width = 5,
 789         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 790         .freq_tbl = ftbl_mdss_edpaux_clk,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "edpaux_clk_src",
 793                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 794                 .num_parents = 4,
 795                 .ops = &clk_rcg2_ops,
 796         },
 797 };
 798
 799 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 800         F(135000000, P_EDPLINK, 2, 0, 0),
 801         F(270000000, P_EDPLINK, 11, 0, 0),
 802         { }
 803 };
 804
 805 static struct clk_rcg2 edplink_clk_src = {
 806         .cmd_rcgr = 0x20c0,
 807         .hid_width = 5,
 808         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 809         .freq_tbl = ftbl_mdss_edplink_clk,
 810         .clkr.hw.init = &(struct clk_init_data){
 811                 .name = "edplink_clk_src",
 812                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 813                 .num_parents = 6,
 814                 .ops = &clk_rcg2_ops,
 815                 .flags = CLK_SET_RATE_PARENT,
 816         },
 817 };
 818
 819 static struct freq_tbl edp_pixel_freq_tbl[] = {
 820         { .src = P_EDPVCO },
 821         { }
 822 };
 823
 824 static struct clk_rcg2 edppixel_clk_src = {
 825         .cmd_rcgr = 0x20a0,
 826         .mnd_width = 8,
 827         .hid_width = 5,
 828         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 829         .freq_tbl = edp_pixel_freq_tbl,
 830         .clkr.hw.init = &(struct clk_init_data){
 831                 .name = "edppixel_clk_src",
 832                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 833                 .num_parents = 6,
 834                 .ops = &clk_edp_pixel_ops,
 835         },
 836 };
 837
 838 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 839         F(19200000, P_XO, 1, 0, 0),
 840         { }
 841 };
 842
 843 static struct clk_rcg2 esc0_clk_src = {
 844         .cmd_rcgr = 0x2160,
 845         .hid_width = 5,
 846         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 847         .freq_tbl = ftbl_mdss_esc0_1_clk,
 848         .clkr.hw.init = &(struct clk_init_data){
 849                 .name = "esc0_clk_src",
 850                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 851                 .num_parents = 6,
 852                 .ops = &clk_rcg2_ops,
 853         },
 854 };
 855
 856 static struct clk_rcg2 esc1_clk_src = {
 857         .cmd_rcgr = 0x2180,
 858         .hid_width = 5,
 859         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 860         .freq_tbl = ftbl_mdss_esc0_1_clk,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "esc1_clk_src",
 863                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 864                 .num_parents = 6,
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static struct freq_tbl extpclk_freq_tbl[] = {
 870         { .src = P_HDMIPLL },
 871         { }
 872 };
 873
 874 static struct clk_rcg2 extpclk_clk_src = {
 875         .cmd_rcgr = 0x2060,
 876         .hid_width = 5,
 877         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 878         .freq_tbl = extpclk_freq_tbl,
 879         .clkr.hw.init = &(struct clk_init_data){
 880                 .name = "extpclk_clk_src",
 881                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 882                 .num_parents = 6,
 883                 .ops = &clk_byte_ops,
 884                 .flags = CLK_SET_RATE_PARENT,
 885         },
 886 };
 887
 888 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 889         F(19200000, P_XO, 1, 0, 0),
 890         { }
 891 };
 892
 893 static struct clk_rcg2 hdmi_clk_src = {
 894         .cmd_rcgr = 0x2100,
 895         .hid_width = 5,
 896         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 897         .freq_tbl = ftbl_mdss_hdmi_clk,
 898         .clkr.hw.init = &(struct clk_init_data){
 899                 .name = "hdmi_clk_src",
 900                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 901                 .num_parents = 4,
 902                 .ops = &clk_rcg2_ops,
 903         },
 904 };
 905
 906 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 907         F(19200000, P_XO, 1, 0, 0),
 908         { }
 909 };
 910
 911 static struct clk_rcg2 vsync_clk_src = {
 912         .cmd_rcgr = 0x2080,
 913         .hid_width = 5,
 914         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 915         .freq_tbl = ftbl_mdss_vsync_clk,
 916         .clkr.hw.init = &(struct clk_init_data){
 917                 .name = "vsync_clk_src",
 918                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 919                 .num_parents = 4,
 920                 .ops = &clk_rcg2_ops,
 921         },
 922 };
 923
 924 static struct clk_branch camss_cci_cci_ahb_clk = {
 925         .halt_reg = 0x3348,
 926         .clkr = {
 927                 .enable_reg = 0x3348,
 928                 .enable_mask = BIT(0),
 929                 .hw.init = &(struct clk_init_data){
 930                         .name = "camss_cci_cci_ahb_clk",
 931                         .parent_names = (const char *[]){
 932                                 "mmss_ahb_clk_src",
 933                         },
 934                         .num_parents = 1,
 935                         .ops = &clk_branch2_ops,
 936                 },
 937         },
 938 };
 939
 940 static struct clk_branch camss_cci_cci_clk = {
 941         .halt_reg = 0x3344,
 942         .clkr = {
 943                 .enable_reg = 0x3344,
 944                 .enable_mask = BIT(0),
 945                 .hw.init = &(struct clk_init_data){
 946                         .name = "camss_cci_cci_clk",
 947                         .parent_names = (const char *[]){
 948                                 "cci_clk_src",
 949                         },
 950                         .num_parents = 1,
 951                         .flags = CLK_SET_RATE_PARENT,
 952                         .ops = &clk_branch2_ops,
 953                 },
 954         },
 955 };
 956
 957 static struct clk_branch camss_csi0_ahb_clk = {
 958         .halt_reg = 0x30bc,
 959         .clkr = {
 960                 .enable_reg = 0x30bc,
 961                 .enable_mask = BIT(0),
 962                 .hw.init = &(struct clk_init_data){
 963                         .name = "camss_csi0_ahb_clk",
 964                         .parent_names = (const char *[]){
 965                                 "mmss_ahb_clk_src",
 966                         },
 967                         .num_parents = 1,
 968                         .ops = &clk_branch2_ops,
 969                 },
 970         },
 971 };
 972
 973 static struct clk_branch camss_csi0_clk = {
 974         .halt_reg = 0x30b4,
 975         .clkr = {
 976                 .enable_reg = 0x30b4,
 977                 .enable_mask = BIT(0),
 978                 .hw.init = &(struct clk_init_data){
 979                         .name = "camss_csi0_clk",
 980                         .parent_names = (const char *[]){
 981                                 "csi0_clk_src",
 982                         },
 983                         .num_parents = 1,
 984                         .flags = CLK_SET_RATE_PARENT,
 985                         .ops = &clk_branch2_ops,
 986                 },
 987         },
 988 };
 989
 990 static struct clk_branch camss_csi0phy_clk = {
 991         .halt_reg = 0x30c4,
 992         .clkr = {
 993                 .enable_reg = 0x30c4,
 994                 .enable_mask = BIT(0),
 995                 .hw.init = &(struct clk_init_data){
 996                         .name = "camss_csi0phy_clk",
 997                         .parent_names = (const char *[]){
 998                                 "csi0_clk_src",
 999                         },
1000                         .num_parents = 1,
1001                         .flags = CLK_SET_RATE_PARENT,
1002                         .ops = &clk_branch2_ops,
1003                 },
1004         },
1005 };
1006
1007 static struct clk_branch camss_csi0pix_clk = {
1008         .halt_reg = 0x30e4,
1009         .clkr = {
1010                 .enable_reg = 0x30e4,
1011                 .enable_mask = BIT(0),
1012                 .hw.init = &(struct clk_init_data){
1013                         .name = "camss_csi0pix_clk",
1014                         .parent_names = (const char *[]){
1015                                 "csi0_clk_src",
1016                         },
1017                         .num_parents = 1,
1018                         .flags = CLK_SET_RATE_PARENT,
1019                         .ops = &clk_branch2_ops,
1020                 },
1021         },
1022 };
1023
1024 static struct clk_branch camss_csi0rdi_clk = {
1025         .halt_reg = 0x30d4,
1026         .clkr = {
1027                 .enable_reg = 0x30d4,
1028                 .enable_mask = BIT(0),
1029                 .hw.init = &(struct clk_init_data){
1030                         .name = "camss_csi0rdi_clk",
1031                         .parent_names = (const char *[]){
1032                                 "csi0_clk_src",
1033                         },
1034                         .num_parents = 1,
1035                         .flags = CLK_SET_RATE_PARENT,
1036                         .ops = &clk_branch2_ops,
1037                 },
1038         },
1039 };
1040
1041 static struct clk_branch camss_csi1_ahb_clk = {
1042         .halt_reg = 0x3128,
1043         .clkr = {
1044                 .enable_reg = 0x3128,
1045                 .enable_mask = BIT(0),
1046                 .hw.init = &(struct clk_init_data){
1047                         .name = "camss_csi1_ahb_clk",
1048                         .parent_names = (const char *[]){
1049                                 "mmss_ahb_clk_src",
1050                         },
1051                         .num_parents = 1,
1052                         .ops = &clk_branch2_ops,
1053                 },
1054         },
1055 };
1056
1057 static struct clk_branch camss_csi1_clk = {
1058         .halt_reg = 0x3124,
1059         .clkr = {
1060                 .enable_reg = 0x3124,
1061                 .enable_mask = BIT(0),
1062                 .hw.init = &(struct clk_init_data){
1063                         .name = "camss_csi1_clk",
1064                         .parent_names = (const char *[]){
1065                                 "csi1_clk_src",
1066                         },
1067                         .num_parents = 1,
1068                         .flags = CLK_SET_RATE_PARENT,
1069                         .ops = &clk_branch2_ops,
1070                 },
1071         },
1072 };
1073
1074 static struct clk_branch camss_csi1phy_clk = {
1075         .halt_reg = 0x3134,
1076         .clkr = {
1077                 .enable_reg = 0x3134,
1078                 .enable_mask = BIT(0),
1079                 .hw.init = &(struct clk_init_data){
1080                         .name = "camss_csi1phy_clk",
1081                         .parent_names = (const char *[]){
1082                                 "csi1_clk_src",
1083                         },
1084                         .num_parents = 1,
1085                         .flags = CLK_SET_RATE_PARENT,
1086                         .ops = &clk_branch2_ops,
1087                 },
1088         },
1089 };
1090
1091 static struct clk_branch camss_csi1pix_clk = {
1092         .halt_reg = 0x3154,
1093         .clkr = {
1094                 .enable_reg = 0x3154,
1095                 .enable_mask = BIT(0),
1096                 .hw.init = &(struct clk_init_data){
1097                         .name = "camss_csi1pix_clk",
1098                         .parent_names = (const char *[]){
1099                                 "csi1_clk_src",
1100                         },
1101                         .num_parents = 1,
1102                         .flags = CLK_SET_RATE_PARENT,
1103                         .ops = &clk_branch2_ops,
1104                 },
1105         },
1106 };
1107
1108 static struct clk_branch camss_csi1rdi_clk = {
1109         .halt_reg = 0x3144,
1110         .clkr = {
1111                 .enable_reg = 0x3144,
1112                 .enable_mask = BIT(0),
1113                 .hw.init = &(struct clk_init_data){
1114                         .name = "camss_csi1rdi_clk",
1115                         .parent_names = (const char *[]){
1116                                 "csi1_clk_src",
1117                         },
1118                         .num_parents = 1,
1119                         .flags = CLK_SET_RATE_PARENT,
1120                         .ops = &clk_branch2_ops,
1121                 },
1122         },
1123 };
1124
1125 static struct clk_branch camss_csi2_ahb_clk = {
1126         .halt_reg = 0x3188,
1127         .clkr = {
1128                 .enable_reg = 0x3188,
1129                 .enable_mask = BIT(0),
1130                 .hw.init = &(struct clk_init_data){
1131                         .name = "camss_csi2_ahb_clk",
1132                         .parent_names = (const char *[]){
1133                                 "mmss_ahb_clk_src",
1134                         },
1135                         .num_parents = 1,
1136                         .ops = &clk_branch2_ops,
1137                 },
1138         },
1139 };
1140
1141 static struct clk_branch camss_csi2_clk = {
1142         .halt_reg = 0x3184,
1143         .clkr = {
1144                 .enable_reg = 0x3184,
1145                 .enable_mask = BIT(0),
1146                 .hw.init = &(struct clk_init_data){
1147                         .name = "camss_csi2_clk",
1148                         .parent_names = (const char *[]){
1149                                 "csi2_clk_src",
1150                         },
1151                         .num_parents = 1,
1152                         .flags = CLK_SET_RATE_PARENT,
1153                         .ops = &clk_branch2_ops,
1154                 },
1155         },
1156 };
1157
1158 static struct clk_branch camss_csi2phy_clk = {
1159         .halt_reg = 0x3194,
1160         .clkr = {
1161                 .enable_reg = 0x3194,
1162                 .enable_mask = BIT(0),
1163                 .hw.init = &(struct clk_init_data){
1164                         .name = "camss_csi2phy_clk",
1165                         .parent_names = (const char *[]){
1166                                 "csi2_clk_src",
1167                         },
1168                         .num_parents = 1,
1169                         .flags = CLK_SET_RATE_PARENT,
1170                         .ops = &clk_branch2_ops,
1171                 },
1172         },
1173 };
1174
1175 static struct clk_branch camss_csi2pix_clk = {
1176         .halt_reg = 0x31b4,
1177         .clkr = {
1178                 .enable_reg = 0x31b4,
1179                 .enable_mask = BIT(0),
1180                 .hw.init = &(struct clk_init_data){
1181                         .name = "camss_csi2pix_clk",
1182                         .parent_names = (const char *[]){
1183                                 "csi2_clk_src",
1184                         },
1185                         .num_parents = 1,
1186                         .flags = CLK_SET_RATE_PARENT,
1187                         .ops = &clk_branch2_ops,
1188                 },
1189         },
1190 };
1191
1192 static struct clk_branch camss_csi2rdi_clk = {
1193         .halt_reg = 0x31a4,
1194         .clkr = {
1195                 .enable_reg = 0x31a4,
1196                 .enable_mask = BIT(0),
1197                 .hw.init = &(struct clk_init_data){
1198                         .name = "camss_csi2rdi_clk",
1199                         .parent_names = (const char *[]){
1200                                 "csi2_clk_src",
1201                         },
1202                         .num_parents = 1,
1203                         .flags = CLK_SET_RATE_PARENT,
1204                         .ops = &clk_branch2_ops,
1205                 },
1206         },
1207 };
1208
1209 static struct clk_branch camss_csi3_ahb_clk = {
1210         .halt_reg = 0x31e8,
1211         .clkr = {
1212                 .enable_reg = 0x31e8,
1213                 .enable_mask = BIT(0),
1214                 .hw.init = &(struct clk_init_data){
1215                         .name = "camss_csi3_ahb_clk",
1216                         .parent_names = (const char *[]){
1217                                 "mmss_ahb_clk_src",
1218                         },
1219                         .num_parents = 1,
1220                         .ops = &clk_branch2_ops,
1221                 },
1222         },
1223 };
1224
1225 static struct clk_branch camss_csi3_clk = {
1226         .halt_reg = 0x31e4,
1227         .clkr = {
1228                 .enable_reg = 0x31e4,
1229                 .enable_mask = BIT(0),
1230                 .hw.init = &(struct clk_init_data){
1231                         .name = "camss_csi3_clk",
1232                         .parent_names = (const char *[]){
1233                                 "csi3_clk_src",
1234                         },
1235                         .num_parents = 1,
1236                         .flags = CLK_SET_RATE_PARENT,
1237                         .ops = &clk_branch2_ops,
1238                 },
1239         },
1240 };
1241
1242 static struct clk_branch camss_csi3phy_clk = {
1243         .halt_reg = 0x31f4,
1244         .clkr = {
1245                 .enable_reg = 0x31f4,
1246                 .enable_mask = BIT(0),
1247                 .hw.init = &(struct clk_init_data){
1248                         .name = "camss_csi3phy_clk",
1249                         .parent_names = (const char *[]){
1250                                 "csi3_clk_src",
1251                         },
1252                         .num_parents = 1,
1253                         .flags = CLK_SET_RATE_PARENT,
1254                         .ops = &clk_branch2_ops,
1255                 },
1256         },
1257 };
1258
1259 static struct clk_branch camss_csi3pix_clk = {
1260         .halt_reg = 0x3214,
1261         .clkr = {
1262                 .enable_reg = 0x3214,
1263                 .enable_mask = BIT(0),
1264                 .hw.init = &(struct clk_init_data){
1265                         .name = "camss_csi3pix_clk",
1266                         .parent_names = (const char *[]){
1267                                 "csi3_clk_src",
1268                         },
1269                         .num_parents = 1,
1270                         .flags = CLK_SET_RATE_PARENT,
1271                         .ops = &clk_branch2_ops,
1272                 },
1273         },
1274 };
1275
1276 static struct clk_branch camss_csi3rdi_clk = {
1277         .halt_reg = 0x3204,
1278         .clkr = {
1279                 .enable_reg = 0x3204,
1280                 .enable_mask = BIT(0),
1281                 .hw.init = &(struct clk_init_data){
1282                         .name = "camss_csi3rdi_clk",
1283                         .parent_names = (const char *[]){
1284                                 "csi3_clk_src",
1285                         },
1286                         .num_parents = 1,
1287                         .flags = CLK_SET_RATE_PARENT,
1288                         .ops = &clk_branch2_ops,
1289                 },
1290         },
1291 };
1292
1293 static struct clk_branch camss_csi_vfe0_clk = {
1294         .halt_reg = 0x3704,
1295         .clkr = {
1296                 .enable_reg = 0x3704,
1297                 .enable_mask = BIT(0),
1298                 .hw.init = &(struct clk_init_data){
1299                         .name = "camss_csi_vfe0_clk",
1300                         .parent_names = (const char *[]){
1301                                 "vfe0_clk_src",
1302                         },
1303                         .num_parents = 1,
1304                         .flags = CLK_SET_RATE_PARENT,
1305                         .ops = &clk_branch2_ops,
1306                 },
1307         },
1308 };
1309
1310 static struct clk_branch camss_csi_vfe1_clk = {
1311         .halt_reg = 0x3714,
1312         .clkr = {
1313                 .enable_reg = 0x3714,
1314                 .enable_mask = BIT(0),
1315                 .hw.init = &(struct clk_init_data){
1316                         .name = "camss_csi_vfe1_clk",
1317                         .parent_names = (const char *[]){
1318                                 "vfe1_clk_src",
1319                         },
1320                         .num_parents = 1,
1321                         .flags = CLK_SET_RATE_PARENT,
1322                         .ops = &clk_branch2_ops,
1323                 },
1324         },
1325 };
1326
1327 static struct clk_branch camss_gp0_clk = {
1328         .halt_reg = 0x3444,
1329         .clkr = {
1330                 .enable_reg = 0x3444,
1331                 .enable_mask = BIT(0),
1332                 .hw.init = &(struct clk_init_data){
1333                         .name = "camss_gp0_clk",
1334                         .parent_names = (const char *[]){
1335                                 "camss_gp0_clk_src",
1336                         },
1337                         .num_parents = 1,
1338                         .flags = CLK_SET_RATE_PARENT,
1339                         .ops = &clk_branch2_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch camss_gp1_clk = {
1345         .halt_reg = 0x3474,
1346         .clkr = {
1347                 .enable_reg = 0x3474,
1348                 .enable_mask = BIT(0),
1349                 .hw.init = &(struct clk_init_data){
1350                         .name = "camss_gp1_clk",
1351                         .parent_names = (const char *[]){
1352                                 "camss_gp1_clk_src",
1353                         },
1354                         .num_parents = 1,
1355                         .flags = CLK_SET_RATE_PARENT,
1356                         .ops = &clk_branch2_ops,
1357                 },
1358         },
1359 };
1360
1361 static struct clk_branch camss_ispif_ahb_clk = {
1362         .halt_reg = 0x3224,
1363         .clkr = {
1364                 .enable_reg = 0x3224,
1365                 .enable_mask = BIT(0),
1366                 .hw.init = &(struct clk_init_data){
1367                         .name = "camss_ispif_ahb_clk",
1368                         .parent_names = (const char *[]){
1369                                 "mmss_ahb_clk_src",
1370                         },
1371                         .num_parents = 1,
1372                         .ops = &clk_branch2_ops,
1373                 },
1374         },
1375 };
1376
1377 static struct clk_branch camss_jpeg_jpeg0_clk = {
1378         .halt_reg = 0x35a8,
1379         .clkr = {
1380                 .enable_reg = 0x35a8,
1381                 .enable_mask = BIT(0),
1382                 .hw.init = &(struct clk_init_data){
1383                         .name = "camss_jpeg_jpeg0_clk",
1384                         .parent_names = (const char *[]){
1385                                 "jpeg0_clk_src",
1386                         },
1387                         .num_parents = 1,
1388                         .flags = CLK_SET_RATE_PARENT,
1389                         .ops = &clk_branch2_ops,
1390                 },
1391         },
1392 };
1393
1394 static struct clk_branch camss_jpeg_jpeg1_clk = {
1395         .halt_reg = 0x35ac,
1396         .clkr = {
1397                 .enable_reg = 0x35ac,
1398                 .enable_mask = BIT(0),
1399                 .hw.init = &(struct clk_init_data){
1400                         .name = "camss_jpeg_jpeg1_clk",
1401                         .parent_names = (const char *[]){
1402                                 "jpeg1_clk_src",
1403                         },
1404                         .num_parents = 1,
1405                         .flags = CLK_SET_RATE_PARENT,
1406                         .ops = &clk_branch2_ops,
1407                 },
1408         },
1409 };
1410
1411 static struct clk_branch camss_jpeg_jpeg2_clk = {
1412         .halt_reg = 0x35b0,
1413         .clkr = {
1414                 .enable_reg = 0x35b0,
1415                 .enable_mask = BIT(0),
1416                 .hw.init = &(struct clk_init_data){
1417                         .name = "camss_jpeg_jpeg2_clk",
1418                         .parent_names = (const char *[]){
1419                                 "jpeg2_clk_src",
1420                         },
1421                         .num_parents = 1,
1422                         .flags = CLK_SET_RATE_PARENT,
1423                         .ops = &clk_branch2_ops,
1424                 },
1425         },
1426 };
1427
1428 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1429         .halt_reg = 0x35b4,
1430         .clkr = {
1431                 .enable_reg = 0x35b4,
1432                 .enable_mask = BIT(0),
1433                 .hw.init = &(struct clk_init_data){
1434                         .name = "camss_jpeg_jpeg_ahb_clk",
1435                         .parent_names = (const char *[]){
1436                                 "mmss_ahb_clk_src",
1437                         },
1438                         .num_parents = 1,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1445         .halt_reg = 0x35b8,
1446         .clkr = {
1447                 .enable_reg = 0x35b8,
1448                 .enable_mask = BIT(0),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "camss_jpeg_jpeg_axi_clk",
1451                         .parent_names = (const char *[]){
1452                                 "mmss_axi_clk_src",
1453                         },
1454                         .num_parents = 1,
1455                         .ops = &clk_branch2_ops,
1456                 },
1457         },
1458 };
1459
1460 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1461         .halt_reg = 0x35bc,
1462         .clkr = {
1463                 .enable_reg = 0x35bc,
1464                 .enable_mask = BIT(0),
1465                 .hw.init = &(struct clk_init_data){
1466                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1467                         .parent_names = (const char *[]){
1468                                 "ocmemnoc_clk_src",
1469                         },
1470                         .num_parents = 1,
1471                         .flags = CLK_SET_RATE_PARENT,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_branch camss_mclk0_clk = {
1478         .halt_reg = 0x3384,
1479         .clkr = {
1480                 .enable_reg = 0x3384,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "camss_mclk0_clk",
1484                         .parent_names = (const char *[]){
1485                                 "mclk0_clk_src",
1486                         },
1487                         .num_parents = 1,
1488                         .flags = CLK_SET_RATE_PARENT,
1489                         .ops = &clk_branch2_ops,
1490                 },
1491         },
1492 };
1493
1494 static struct clk_branch camss_mclk1_clk = {
1495         .halt_reg = 0x33b4,
1496         .clkr = {
1497                 .enable_reg = 0x33b4,
1498                 .enable_mask = BIT(0),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "camss_mclk1_clk",
1501                         .parent_names = (const char *[]){
1502                                 "mclk1_clk_src",
1503                         },
1504                         .num_parents = 1,
1505                         .flags = CLK_SET_RATE_PARENT,
1506                         .ops = &clk_branch2_ops,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_branch camss_mclk2_clk = {
1512         .halt_reg = 0x33e4,
1513         .clkr = {
1514                 .enable_reg = 0x33e4,
1515                 .enable_mask = BIT(0),
1516                 .hw.init = &(struct clk_init_data){
1517                         .name = "camss_mclk2_clk",
1518                         .parent_names = (const char *[]){
1519                                 "mclk2_clk_src",
1520                         },
1521                         .num_parents = 1,
1522                         .flags = CLK_SET_RATE_PARENT,
1523                         .ops = &clk_branch2_ops,
1524                 },
1525         },
1526 };
1527
1528 static struct clk_branch camss_mclk3_clk = {
1529         .halt_reg = 0x3414,
1530         .clkr = {
1531                 .enable_reg = 0x3414,
1532                 .enable_mask = BIT(0),
1533                 .hw.init = &(struct clk_init_data){
1534                         .name = "camss_mclk3_clk",
1535                         .parent_names = (const char *[]){
1536                                 "mclk3_clk_src",
1537                         },
1538                         .num_parents = 1,
1539                         .flags = CLK_SET_RATE_PARENT,
1540                         .ops = &clk_branch2_ops,
1541                 },
1542         },
1543 };
1544
1545 static struct clk_branch camss_micro_ahb_clk = {
1546         .halt_reg = 0x3494,
1547         .clkr = {
1548                 .enable_reg = 0x3494,
1549                 .enable_mask = BIT(0),
1550                 .hw.init = &(struct clk_init_data){
1551                         .name = "camss_micro_ahb_clk",
1552                         .parent_names = (const char *[]){
1553                                 "mmss_ahb_clk_src",
1554                         },
1555                         .num_parents = 1,
1556                         .ops = &clk_branch2_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1562         .halt_reg = 0x3024,
1563         .clkr = {
1564                 .enable_reg = 0x3024,
1565                 .enable_mask = BIT(0),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "camss_phy0_csi0phytimer_clk",
1568                         .parent_names = (const char *[]){
1569                                 "csi0phytimer_clk_src",
1570                         },
1571                         .num_parents = 1,
1572                         .flags = CLK_SET_RATE_PARENT,
1573                         .ops = &clk_branch2_ops,
1574                 },
1575         },
1576 };
1577
1578 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1579         .halt_reg = 0x3054,
1580         .clkr = {
1581                 .enable_reg = 0x3054,
1582                 .enable_mask = BIT(0),
1583                 .hw.init = &(struct clk_init_data){
1584                         .name = "camss_phy1_csi1phytimer_clk",
1585                         .parent_names = (const char *[]){
1586                                 "csi1phytimer_clk_src",
1587                         },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1596         .halt_reg = 0x3084,
1597         .clkr = {
1598                 .enable_reg = 0x3084,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "camss_phy2_csi2phytimer_clk",
1602                         .parent_names = (const char *[]){
1603                                 "csi2phytimer_clk_src",
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch camss_top_ahb_clk = {
1613         .halt_reg = 0x3484,
1614         .clkr = {
1615                 .enable_reg = 0x3484,
1616                 .enable_mask = BIT(0),
1617                 .hw.init = &(struct clk_init_data){
1618                         .name = "camss_top_ahb_clk",
1619                         .parent_names = (const char *[]){
1620                                 "mmss_ahb_clk_src",
1621                         },
1622                         .num_parents = 1,
1623                         .ops = &clk_branch2_ops,
1624                 },
1625         },
1626 };
1627
1628 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1629         .halt_reg = 0x36b4,
1630         .clkr = {
1631                 .enable_reg = 0x36b4,
1632                 .enable_mask = BIT(0),
1633                 .hw.init = &(struct clk_init_data){
1634                         .name = "camss_vfe_cpp_ahb_clk",
1635                         .parent_names = (const char *[]){
1636                                 "mmss_ahb_clk_src",
1637                         },
1638                         .num_parents = 1,
1639                         .ops = &clk_branch2_ops,
1640                 },
1641         },
1642 };
1643
1644 static struct clk_branch camss_vfe_cpp_clk = {
1645         .halt_reg = 0x36b0,
1646         .clkr = {
1647                 .enable_reg = 0x36b0,
1648                 .enable_mask = BIT(0),
1649                 .hw.init = &(struct clk_init_data){
1650                         .name = "camss_vfe_cpp_clk",
1651                         .parent_names = (const char *[]){
1652                                 "cpp_clk_src",
1653                         },
1654                         .num_parents = 1,
1655                         .flags = CLK_SET_RATE_PARENT,
1656                         .ops = &clk_branch2_ops,
1657                 },
1658         },
1659 };
1660
1661 static struct clk_branch camss_vfe_vfe0_clk = {
1662         .halt_reg = 0x36a8,
1663         .clkr = {
1664                 .enable_reg = 0x36a8,
1665                 .enable_mask = BIT(0),
1666                 .hw.init = &(struct clk_init_data){
1667                         .name = "camss_vfe_vfe0_clk",
1668                         .parent_names = (const char *[]){
1669                                 "vfe0_clk_src",
1670                         },
1671                         .num_parents = 1,
1672                         .flags = CLK_SET_RATE_PARENT,
1673                         .ops = &clk_branch2_ops,
1674                 },
1675         },
1676 };
1677
1678 static struct clk_branch camss_vfe_vfe1_clk = {
1679         .halt_reg = 0x36ac,
1680         .clkr = {
1681                 .enable_reg = 0x36ac,
1682                 .enable_mask = BIT(0),
1683                 .hw.init = &(struct clk_init_data){
1684                         .name = "camss_vfe_vfe1_clk",
1685                         .parent_names = (const char *[]){
1686                                 "vfe1_clk_src",
1687                         },
1688                         .num_parents = 1,
1689                         .flags = CLK_SET_RATE_PARENT,
1690                         .ops = &clk_branch2_ops,
1691                 },
1692         },
1693 };
1694
1695 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1696         .halt_reg = 0x36b8,
1697         .clkr = {
1698                 .enable_reg = 0x36b8,
1699                 .enable_mask = BIT(0),
1700                 .hw.init = &(struct clk_init_data){
1701                         .name = "camss_vfe_vfe_ahb_clk",
1702                         .parent_names = (const char *[]){
1703                                 "mmss_ahb_clk_src",
1704                         },
1705                         .num_parents = 1,
1706                         .ops = &clk_branch2_ops,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch camss_vfe_vfe_axi_clk = {
1712         .halt_reg = 0x36bc,
1713         .clkr = {
1714                 .enable_reg = 0x36bc,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "camss_vfe_vfe_axi_clk",
1718                         .parent_names = (const char *[]){
1719                                 "mmss_axi_clk_src",
1720                         },
1721                         .num_parents = 1,
1722                         .ops = &clk_branch2_ops,
1723                 },
1724         },
1725 };
1726
1727 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1728         .halt_reg = 0x36c0,
1729         .clkr = {
1730                 .enable_reg = 0x36c0,
1731                 .enable_mask = BIT(0),
1732                 .hw.init = &(struct clk_init_data){
1733                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1734                         .parent_names = (const char *[]){
1735                                 "ocmemnoc_clk_src",
1736                         },
1737                         .num_parents = 1,
1738                         .flags = CLK_SET_RATE_PARENT,
1739                         .ops = &clk_branch2_ops,
1740                 },
1741         },
1742 };
1743
1744 static struct clk_branch mdss_ahb_clk = {
1745         .halt_reg = 0x2308,
1746         .clkr = {
1747                 .enable_reg = 0x2308,
1748                 .enable_mask = BIT(0),
1749                 .hw.init = &(struct clk_init_data){
1750                         .name = "mdss_ahb_clk",
1751                         .parent_names = (const char *[]){
1752                                 "mmss_ahb_clk_src",
1753                         },
1754                         .num_parents = 1,
1755                         .ops = &clk_branch2_ops,
1756                 },
1757         },
1758 };
1759
1760 static struct clk_branch mdss_axi_clk = {
1761         .halt_reg = 0x2310,
1762         .clkr = {
1763                 .enable_reg = 0x2310,
1764                 .enable_mask = BIT(0),
1765                 .hw.init = &(struct clk_init_data){
1766                         .name = "mdss_axi_clk",
1767                         .parent_names = (const char *[]){
1768                                 "mmss_axi_clk_src",
1769                         },
1770                         .num_parents = 1,
1771                         .flags = CLK_SET_RATE_PARENT,
1772                         .ops = &clk_branch2_ops,
1773                 },
1774         },
1775 };
1776
1777 static struct clk_branch mdss_byte0_clk = {
1778         .halt_reg = 0x233c,
1779         .clkr = {
1780                 .enable_reg = 0x233c,
1781                 .enable_mask = BIT(0),
1782                 .hw.init = &(struct clk_init_data){
1783                         .name = "mdss_byte0_clk",
1784                         .parent_names = (const char *[]){
1785                                 "byte0_clk_src",
1786                         },
1787                         .num_parents = 1,
1788                         .flags = CLK_SET_RATE_PARENT,
1789                         .ops = &clk_branch2_ops,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch mdss_byte1_clk = {
1795         .halt_reg = 0x2340,
1796         .clkr = {
1797                 .enable_reg = 0x2340,
1798                 .enable_mask = BIT(0),
1799                 .hw.init = &(struct clk_init_data){
1800                         .name = "mdss_byte1_clk",
1801                         .parent_names = (const char *[]){
1802                                 "byte1_clk_src",
1803                         },
1804                         .num_parents = 1,
1805                         .flags = CLK_SET_RATE_PARENT,
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 static struct clk_branch mdss_edpaux_clk = {
1812         .halt_reg = 0x2334,
1813         .clkr = {
1814                 .enable_reg = 0x2334,
1815                 .enable_mask = BIT(0),
1816                 .hw.init = &(struct clk_init_data){
1817                         .name = "mdss_edpaux_clk",
1818                         .parent_names = (const char *[]){
1819                                 "edpaux_clk_src",
1820                         },
1821                         .num_parents = 1,
1822                         .flags = CLK_SET_RATE_PARENT,
1823                         .ops = &clk_branch2_ops,
1824                 },
1825         },
1826 };
1827
1828 static struct clk_branch mdss_edplink_clk = {
1829         .halt_reg = 0x2330,
1830         .clkr = {
1831                 .enable_reg = 0x2330,
1832                 .enable_mask = BIT(0),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "mdss_edplink_clk",
1835                         .parent_names = (const char *[]){
1836                                 "edplink_clk_src",
1837                         },
1838                         .num_parents = 1,
1839                         .flags = CLK_SET_RATE_PARENT,
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static struct clk_branch mdss_edppixel_clk = {
1846         .halt_reg = 0x232c,
1847         .clkr = {
1848                 .enable_reg = 0x232c,
1849                 .enable_mask = BIT(0),
1850                 .hw.init = &(struct clk_init_data){
1851                         .name = "mdss_edppixel_clk",
1852                         .parent_names = (const char *[]){
1853                                 "edppixel_clk_src",
1854                         },
1855                         .num_parents = 1,
1856                         .flags = CLK_SET_RATE_PARENT,
1857                         .ops = &clk_branch2_ops,
1858                 },
1859         },
1860 };
1861
1862 static struct clk_branch mdss_esc0_clk = {
1863         .halt_reg = 0x2344,
1864         .clkr = {
1865                 .enable_reg = 0x2344,
1866                 .enable_mask = BIT(0),
1867                 .hw.init = &(struct clk_init_data){
1868                         .name = "mdss_esc0_clk",
1869                         .parent_names = (const char *[]){
1870                                 "esc0_clk_src",
1871                         },
1872                         .num_parents = 1,
1873                         .flags = CLK_SET_RATE_PARENT,
1874                         .ops = &clk_branch2_ops,
1875                 },
1876         },
1877 };
1878
1879 static struct clk_branch mdss_esc1_clk = {
1880         .halt_reg = 0x2348,
1881         .clkr = {
1882                 .enable_reg = 0x2348,
1883                 .enable_mask = BIT(0),
1884                 .hw.init = &(struct clk_init_data){
1885                         .name = "mdss_esc1_clk",
1886                         .parent_names = (const char *[]){
1887                                 "esc1_clk_src",
1888                         },
1889                         .num_parents = 1,
1890                         .flags = CLK_SET_RATE_PARENT,
1891                         .ops = &clk_branch2_ops,
1892                 },
1893         },
1894 };
1895
1896 static struct clk_branch mdss_extpclk_clk = {
1897         .halt_reg = 0x2324,
1898         .clkr = {
1899                 .enable_reg = 0x2324,
1900                 .enable_mask = BIT(0),
1901                 .hw.init = &(struct clk_init_data){
1902                         .name = "mdss_extpclk_clk",
1903                         .parent_names = (const char *[]){
1904                                 "extpclk_clk_src",
1905                         },
1906                         .num_parents = 1,
1907                         .flags = CLK_SET_RATE_PARENT,
1908                         .ops = &clk_branch2_ops,
1909                 },
1910         },
1911 };
1912
1913 static struct clk_branch mdss_hdmi_ahb_clk = {
1914         .halt_reg = 0x230c,
1915         .clkr = {
1916                 .enable_reg = 0x230c,
1917                 .enable_mask = BIT(0),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "mdss_hdmi_ahb_clk",
1920                         .parent_names = (const char *[]){
1921                                 "mmss_ahb_clk_src",
1922                         },
1923                         .num_parents = 1,
1924                         .ops = &clk_branch2_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch mdss_hdmi_clk = {
1930         .halt_reg = 0x2338,
1931         .clkr = {
1932                 .enable_reg = 0x2338,
1933                 .enable_mask = BIT(0),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "mdss_hdmi_clk",
1936                         .parent_names = (const char *[]){
1937                                 "hdmi_clk_src",
1938                         },
1939                         .num_parents = 1,
1940                         .flags = CLK_SET_RATE_PARENT,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch mdss_mdp_clk = {
1947         .halt_reg = 0x231c,
1948         .clkr = {
1949                 .enable_reg = 0x231c,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "mdss_mdp_clk",
1953                         .parent_names = (const char *[]){
1954                                 "mdp_clk_src",
1955                         },
1956                         .num_parents = 1,
1957                         .flags = CLK_SET_RATE_PARENT,
1958                         .ops = &clk_branch2_ops,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch mdss_mdp_lut_clk = {
1964         .halt_reg = 0x2320,
1965         .clkr = {
1966                 .enable_reg = 0x2320,
1967                 .enable_mask = BIT(0),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "mdss_mdp_lut_clk",
1970                         .parent_names = (const char *[]){
1971                                 "mdp_clk_src",
1972                         },
1973                         .num_parents = 1,
1974                         .flags = CLK_SET_RATE_PARENT,
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch mdss_pclk0_clk = {
1981         .halt_reg = 0x2314,
1982         .clkr = {
1983                 .enable_reg = 0x2314,
1984                 .enable_mask = BIT(0),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "mdss_pclk0_clk",
1987                         .parent_names = (const char *[]){
1988                                 "pclk0_clk_src",
1989                         },
1990                         .num_parents = 1,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch mdss_pclk1_clk = {
1998         .halt_reg = 0x2318,
1999         .clkr = {
2000                 .enable_reg = 0x2318,
2001                 .enable_mask = BIT(0),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "mdss_pclk1_clk",
2004                         .parent_names = (const char *[]){
2005                                 "pclk1_clk_src",
2006                         },
2007                         .num_parents = 1,
2008                         .flags = CLK_SET_RATE_PARENT,
2009                         .ops = &clk_branch2_ops,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch mdss_vsync_clk = {
2015         .halt_reg = 0x2328,
2016         .clkr = {
2017                 .enable_reg = 0x2328,
2018                 .enable_mask = BIT(0),
2019                 .hw.init = &(struct clk_init_data){
2020                         .name = "mdss_vsync_clk",
2021                         .parent_names = (const char *[]){
2022                                 "vsync_clk_src",
2023                         },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch mmss_misc_ahb_clk = {
2032         .halt_reg = 0x502c,
2033         .clkr = {
2034                 .enable_reg = 0x502c,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "mmss_misc_ahb_clk",
2038                         .parent_names = (const char *[]){
2039                                 "mmss_ahb_clk_src",
2040                         },
2041                         .num_parents = 1,
2042                         .ops = &clk_branch2_ops,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2048         .halt_reg = 0x5024,
2049         .clkr = {
2050                 .enable_reg = 0x5024,
2051                 .enable_mask = BIT(0),
2052                 .hw.init = &(struct clk_init_data){
2053                         .name = "mmss_mmssnoc_ahb_clk",
2054                         .parent_names = (const char *[]){
2055                                 "mmss_ahb_clk_src",
2056                         },
2057                         .num_parents = 1,
2058                         .ops = &clk_branch2_ops,
2059                         .flags = CLK_IGNORE_UNUSED,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2065         .halt_reg = 0x5028,
2066         .clkr = {
2067                 .enable_reg = 0x5028,
2068                 .enable_mask = BIT(0),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "mmss_mmssnoc_bto_ahb_clk",
2071                         .parent_names = (const char *[]){
2072                                 "mmss_ahb_clk_src",
2073                         },
2074                         .num_parents = 1,
2075                         .ops = &clk_branch2_ops,
2076                         .flags = CLK_IGNORE_UNUSED,
2077                 },
2078         },
2079 };
2080
2081 static struct clk_branch mmss_mmssnoc_axi_clk = {
2082         .halt_reg = 0x506c,
2083         .clkr = {
2084                 .enable_reg = 0x506c,
2085                 .enable_mask = BIT(0),
2086                 .hw.init = &(struct clk_init_data){
2087                         .name = "mmss_mmssnoc_axi_clk",
2088                         .parent_names = (const char *[]){
2089                                 "mmss_axi_clk_src",
2090                         },
2091                         .num_parents = 1,
2092                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2093                         .ops = &clk_branch2_ops,
2094                 },
2095         },
2096 };
2097
2098 static struct clk_branch mmss_s0_axi_clk = {
2099         .halt_reg = 0x5064,
2100         .clkr = {
2101                 .enable_reg = 0x5064,
2102                 .enable_mask = BIT(0),
2103                 .hw.init = &(struct clk_init_data){
2104                         .name = "mmss_s0_axi_clk",
2105                         .parent_names = (const char *[]){
2106                                 "mmss_axi_clk_src",
2107                         },
2108                         .num_parents = 1,
2109                         .ops = &clk_branch2_ops,
2110                         .flags = CLK_IGNORE_UNUSED,
2111                 },
2112         },
2113 };
2114
2115 static struct clk_branch ocmemcx_ahb_clk = {
2116         .halt_reg = 0x405c,
2117         .clkr = {
2118                 .enable_reg = 0x405c,
2119                 .enable_mask = BIT(0),
2120                 .hw.init = &(struct clk_init_data){
2121                         .name = "ocmemcx_ahb_clk",
2122                         .parent_names = (const char *[]){
2123                                 "mmss_ahb_clk_src",
2124                         },
2125                         .num_parents = 1,
2126                         .ops = &clk_branch2_ops,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2132         .halt_reg = 0x4058,
2133         .clkr = {
2134                 .enable_reg = 0x4058,
2135                 .enable_mask = BIT(0),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "ocmemcx_ocmemnoc_clk",
2138                         .parent_names = (const char *[]){
2139                                 "ocmemnoc_clk_src",
2140                         },
2141                         .num_parents = 1,
2142                         .flags = CLK_SET_RATE_PARENT,
2143                         .ops = &clk_branch2_ops,
2144                 },
2145         },
2146 };
2147
2148 static struct clk_branch oxili_ocmemgx_clk = {
2149         .halt_reg = 0x402c,
2150         .clkr = {
2151                 .enable_reg = 0x402c,
2152                 .enable_mask = BIT(0),
2153                 .hw.init = &(struct clk_init_data){
2154                         .name = "oxili_ocmemgx_clk",
2155                         .parent_names = (const char *[]){
2156                                 "gfx3d_clk_src",
2157                         },
2158                         .num_parents = 1,
2159                         .flags = CLK_SET_RATE_PARENT,
2160                         .ops = &clk_branch2_ops,
2161                 },
2162         },
2163 };
2164
2165 static struct clk_branch ocmemnoc_clk = {
2166         .halt_reg = 0x50b4,
2167         .clkr = {
2168                 .enable_reg = 0x50b4,
2169                 .enable_mask = BIT(0),
2170                 .hw.init = &(struct clk_init_data){
2171                         .name = "ocmemnoc_clk",
2172                         .parent_names = (const char *[]){
2173                                 "ocmemnoc_clk_src",
2174                         },
2175                         .num_parents = 1,
2176                         .flags = CLK_SET_RATE_PARENT,
2177                         .ops = &clk_branch2_ops,
2178                 },
2179         },
2180 };
2181
2182 static struct clk_branch oxili_gfx3d_clk = {
2183         .halt_reg = 0x4028,
2184         .clkr = {
2185                 .enable_reg = 0x4028,
2186                 .enable_mask = BIT(0),
2187                 .hw.init = &(struct clk_init_data){
2188                         .name = "oxili_gfx3d_clk",
2189                         .parent_names = (const char *[]){
2190                                 "gfx3d_clk_src",
2191                         },
2192                         .num_parents = 1,
2193                         .flags = CLK_SET_RATE_PARENT,
2194                         .ops = &clk_branch2_ops,
2195                 },
2196         },
2197 };
2198
2199 static struct clk_branch oxilicx_ahb_clk = {
2200         .halt_reg = 0x403c,
2201         .clkr = {
2202                 .enable_reg = 0x403c,
2203                 .enable_mask = BIT(0),
2204                 .hw.init = &(struct clk_init_data){
2205                         .name = "oxilicx_ahb_clk",
2206                         .parent_names = (const char *[]){
2207                                 "mmss_ahb_clk_src",
2208                         },
2209                         .num_parents = 1,
2210                         .ops = &clk_branch2_ops,
2211                 },
2212         },
2213 };
2214
2215 static struct clk_branch oxilicx_axi_clk = {
2216         .halt_reg = 0x4038,
2217         .clkr = {
2218                 .enable_reg = 0x4038,
2219                 .enable_mask = BIT(0),
2220                 .hw.init = &(struct clk_init_data){
2221                         .name = "oxilicx_axi_clk",
2222                         .parent_names = (const char *[]){
2223                                 "mmss_axi_clk_src",
2224                         },
2225                         .num_parents = 1,
2226                         .ops = &clk_branch2_ops,
2227                 },
2228         },
2229 };
2230
2231 static struct clk_branch venus0_ahb_clk = {
2232         .halt_reg = 0x1030,
2233         .clkr = {
2234                 .enable_reg = 0x1030,
2235                 .enable_mask = BIT(0),
2236                 .hw.init = &(struct clk_init_data){
2237                         .name = "venus0_ahb_clk",
2238                         .parent_names = (const char *[]){
2239                                 "mmss_ahb_clk_src",
2240                         },
2241                         .num_parents = 1,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch venus0_axi_clk = {
2248         .halt_reg = 0x1034,
2249         .clkr = {
2250                 .enable_reg = 0x1034,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "venus0_axi_clk",
2254                         .parent_names = (const char *[]){
2255                                 "mmss_axi_clk_src",
2256                         },
2257                         .num_parents = 1,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch venus0_ocmemnoc_clk = {
2264         .halt_reg = 0x1038,
2265         .clkr = {
2266                 .enable_reg = 0x1038,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "venus0_ocmemnoc_clk",
2270                         .parent_names = (const char *[]){
2271                                 "ocmemnoc_clk_src",
2272                         },
2273                         .num_parents = 1,
2274                         .flags = CLK_SET_RATE_PARENT,
2275                         .ops = &clk_branch2_ops,
2276                 },
2277         },
2278 };
2279
2280 static struct clk_branch venus0_vcodec0_clk = {
2281         .halt_reg = 0x1028,
2282         .clkr = {
2283                 .enable_reg = 0x1028,
2284                 .enable_mask = BIT(0),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "venus0_vcodec0_clk",
2287                         .parent_names = (const char *[]){
2288                                 "vcodec0_clk_src",
2289                         },
2290                         .num_parents = 1,
2291                         .flags = CLK_SET_RATE_PARENT,
2292                         .ops = &clk_branch2_ops,
2293                 },
2294         },
2295 };
2296
2297 static const struct pll_config mmpll1_config = {
2298         .l = 60,
2299         .m = 25,
2300         .n = 32,
2301         .vco_val = 0x0,
2302         .vco_mask = 0x3 << 20,
2303         .pre_div_val = 0x0,
2304         .pre_div_mask = 0x7 << 12,
2305         .post_div_val = 0x0,
2306         .post_div_mask = 0x3 << 8,
2307         .mn_ena_mask = BIT(24),
2308         .main_output_mask = BIT(0),
2309 };
2310
2311 static struct pll_config mmpll3_config = {
2312         .l = 48,
2313         .m = 7,
2314         .n = 16,
2315         .vco_val = 0x0,
2316         .vco_mask = 0x3 << 20,
2317         .pre_div_val = 0x0,
2318         .pre_div_mask = 0x7 << 12,
2319         .post_div_val = 0x0,
2320         .post_div_mask = 0x3 << 8,
2321         .mn_ena_mask = BIT(24),
2322         .main_output_mask = BIT(0),
2323         .aux_output_mask = BIT(1),
2324 };
2325
2326 static struct gdsc venus0_gdsc = {
2327         .gdscr = 0x1024,
2328         .cxcs = (unsigned int []){ 0x1028 },
2329         .cxc_count = 1,
2330         .resets = (unsigned int []){ VENUS0_RESET },
2331         .reset_count = 1,
2332         .pd = {
2333                 .name = "venus0",
2334         },
2335         .pwrsts = PWRSTS_ON,
2336 };
2337
2338 static struct gdsc mdss_gdsc = {
2339         .gdscr = 0x2304,
2340         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2341         .cxc_count = 2,
2342         .pd = {
2343                 .name = "mdss",
2344         },
2345         .pwrsts = PWRSTS_RET_ON,
2346 };
2347
2348 static struct gdsc camss_jpeg_gdsc = {
2349         .gdscr = 0x35a4,
2350         .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2351         .cxc_count = 3,
2352         .pd = {
2353                 .name = "camss_jpeg",
2354         },
2355         .pwrsts = PWRSTS_OFF_ON,
2356 };
2357
2358 static struct gdsc camss_vfe_gdsc = {
2359         .gdscr = 0x36a4,
2360         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2361         .cxc_count = 5,
2362         .pd = {
2363                 .name = "camss_vfe",
2364         },
2365         .pwrsts = PWRSTS_OFF_ON,
2366 };
2367
2368 static struct gdsc oxili_gdsc = {
2369         .gdscr = 0x4024,
2370         .cxcs = (unsigned int []){ 0x4028 },
2371         .cxc_count = 1,
2372         .pd = {
2373                 .name = "oxili",
2374         },
2375         .pwrsts = PWRSTS_OFF_ON,
2376 };
2377
2378 static struct gdsc oxilicx_gdsc = {
2379         .gdscr = 0x4034,
2380         .pd = {
2381                 .name = "oxilicx",
2382         },
2383         .parent = &oxili_gdsc.pd,
2384         .pwrsts = PWRSTS_OFF_ON,
2385 };
2386
2387 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2388         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2389         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2390         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2391         [MMPLL0] = &mmpll0.clkr,
2392         [MMPLL0_VOTE] = &mmpll0_vote,
2393         [MMPLL1] = &mmpll1.clkr,
2394         [MMPLL1_VOTE] = &mmpll1_vote,
2395         [MMPLL2] = &mmpll2.clkr,
2396         [MMPLL3] = &mmpll3.clkr,
2397         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2398         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2399         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2400         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2401         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2402         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2403         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2404         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2405         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2406         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2407         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2408         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2409         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2410         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2411         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2412         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2413         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2414         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2415         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2416         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2417         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2418         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2419         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2420         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2421         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2422         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2423         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2424         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2425         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2426         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2427         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2428         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2429         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2430         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2431         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2432         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2433         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2434         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2435         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2436         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2437         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2438         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2439         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2440         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2441         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2442         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2443         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2444         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2445         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2446         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2447         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2448         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2449         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2450         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2451         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2452         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2453         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2454         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2455         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2456         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2457         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2458         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2459         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2460         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2461         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2462         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2463         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2464         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2465         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2466         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2467         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2468         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2469         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2470         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2471         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2472         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2473         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2474         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2475         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2476         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2477         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2478         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2479         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2480         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2481         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2482         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2483         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2484         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2485         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2486         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2487         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2488         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2489         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2490         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2491         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2492         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2493         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2494         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2495         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2496         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2497         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2498         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2499         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2500         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2501         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2502         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2503         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2504         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2505         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2506         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2507         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2508         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2509         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2510         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2511         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2512         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2513 };
2514
2515 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2516         [SPDM_RESET] = { 0x0200 },
2517         [SPDM_RM_RESET] = { 0x0300 },
2518         [VENUS0_RESET] = { 0x1020 },
2519         [MDSS_RESET] = { 0x2300 },
2520         [CAMSS_PHY0_RESET] = { 0x3020 },
2521         [CAMSS_PHY1_RESET] = { 0x3050 },
2522         [CAMSS_PHY2_RESET] = { 0x3080 },
2523         [CAMSS_CSI0_RESET] = { 0x30b0 },
2524         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2525         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2526         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2527         [CAMSS_CSI1_RESET] = { 0x3120 },
2528         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2529         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2530         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2531         [CAMSS_CSI2_RESET] = { 0x3180 },
2532         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2533         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2534         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2535         [CAMSS_CSI3_RESET] = { 0x31e0 },
2536         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2537         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2538         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2539         [CAMSS_ISPIF_RESET] = { 0x3220 },
2540         [CAMSS_CCI_RESET] = { 0x3340 },
2541         [CAMSS_MCLK0_RESET] = { 0x3380 },
2542         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2543         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2544         [CAMSS_MCLK3_RESET] = { 0x3410 },
2545         [CAMSS_GP0_RESET] = { 0x3440 },
2546         [CAMSS_GP1_RESET] = { 0x3470 },
2547         [CAMSS_TOP_RESET] = { 0x3480 },
2548         [CAMSS_MICRO_RESET] = { 0x3490 },
2549         [CAMSS_JPEG_RESET] = { 0x35a0 },
2550         [CAMSS_VFE_RESET] = { 0x36a0 },
2551         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2552         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2553         [OXILI_RESET] = { 0x4020 },
2554         [OXILICX_RESET] = { 0x4030 },
2555         [OCMEMCX_RESET] = { 0x4050 },
2556         [MMSS_RBCRP_RESET] = { 0x4080 },
2557         [MMSSNOCAHB_RESET] = { 0x5020 },
2558         [MMSSNOCAXI_RESET] = { 0x5060 },
2559         [OCMEMNOC_RESET] = { 0x50b0 },
2560 };
2561
2562 static struct gdsc *mmcc_msm8974_gdscs[] = {
2563         [VENUS0_GDSC] = &venus0_gdsc,
2564         [MDSS_GDSC] = &mdss_gdsc,
2565         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2566         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2567         [OXILI_GDSC] = &oxili_gdsc,
2568         [OXILICX_GDSC] = &oxilicx_gdsc,
2569 };
2570
2571 static const struct regmap_config mmcc_msm8974_regmap_config = {
2572         .reg_bits       = 32,
2573         .reg_stride     = 4,
2574         .val_bits       = 32,
2575         .max_register   = 0x5104,
2576         .fast_io        = true,
2577 };
2578
2579 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2580         .config = &mmcc_msm8974_regmap_config,
2581         .clks = mmcc_msm8974_clocks,
2582         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2583         .resets = mmcc_msm8974_resets,
2584         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2585         .gdscs = mmcc_msm8974_gdscs,
2586         .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2587 };
2588
2589 static const struct of_device_id mmcc_msm8974_match_table[] = {
2590         { .compatible = "qcom,mmcc-msm8974" },
2591         { }
2592 };
2593 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2594
2595 static int mmcc_msm8974_probe(struct platform_device *pdev)
2596 {
2597         struct regmap *regmap;
2598
2599         regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2600         if (IS_ERR(regmap))
2601                 return PTR_ERR(regmap);
2602
2603         clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2604         clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2605
2606         return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2607 }
2608
2609 static struct platform_driver mmcc_msm8974_driver = {
2610         .probe          = mmcc_msm8974_probe,
2611         .driver         = {
2612                 .name   = "mmcc-msm8974",
2613                 .of_match_table = mmcc_msm8974_match_table,
2614         },
2615 };
2616 module_platform_driver(mmcc_msm8974_driver);
2617
2618 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2619 MODULE_LICENSE("GPL v2");
2620 MODULE_ALIAS("platform:mmcc-msm8974");