1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
12 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
13 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
16 #include "clk-regmap.h"
19 #include "clk-branch.h"
42 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
49 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
56 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
65 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
74 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
82 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
90 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
98 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
106 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
115 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
124 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
133 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
142 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
147 { P_DSI0PLL_BYTE, 1 },
148 { P_DSI1PLL_BYTE, 2 }
151 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
160 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
168 static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
176 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
185 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
194 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
204 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
214 static struct clk_pll mmpll0 = {
218 .config_reg = 0x0014,
220 .status_reg = 0x001c,
222 .clkr.hw.init = &(struct clk_init_data){
224 .parent_names = (const char *[]){ "xo" },
230 static struct clk_regmap mmpll0_vote = {
231 .enable_reg = 0x0100,
232 .enable_mask = BIT(0),
233 .hw.init = &(struct clk_init_data){
234 .name = "mmpll0_vote",
235 .parent_names = (const char *[]){ "mmpll0" },
237 .ops = &clk_pll_vote_ops,
241 static struct clk_pll mmpll1 = {
245 .config_reg = 0x0050,
247 .status_reg = 0x005c,
249 .clkr.hw.init = &(struct clk_init_data){
251 .parent_names = (const char *[]){ "xo" },
257 static struct clk_regmap mmpll1_vote = {
258 .enable_reg = 0x0100,
259 .enable_mask = BIT(1),
260 .hw.init = &(struct clk_init_data){
261 .name = "mmpll1_vote",
262 .parent_names = (const char *[]){ "mmpll1" },
264 .ops = &clk_pll_vote_ops,
268 static struct clk_pll mmpll2 = {
272 .config_reg = 0x4110,
274 .status_reg = 0x411c,
275 .clkr.hw.init = &(struct clk_init_data){
277 .parent_names = (const char *[]){ "xo" },
283 static struct clk_pll mmpll3 = {
287 .config_reg = 0x0090,
289 .status_reg = 0x009c,
291 .clkr.hw.init = &(struct clk_init_data){
293 .parent_names = (const char *[]){ "xo" },
299 static struct clk_pll mmpll4 = {
303 .config_reg = 0x00b0,
305 .status_reg = 0x00bc,
306 .clkr.hw.init = &(struct clk_init_data){
308 .parent_names = (const char *[]){ "xo" },
314 static struct clk_rcg2 mmss_ahb_clk_src = {
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .clkr.hw.init = &(struct clk_init_data){
319 .name = "mmss_ahb_clk_src",
320 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
322 .ops = &clk_rcg2_ops,
326 static struct freq_tbl ftbl_mmss_axi_clk[] = {
327 F(19200000, P_XO, 1, 0, 0),
328 F(37500000, P_GPLL0, 16, 0, 0),
329 F(50000000, P_GPLL0, 12, 0, 0),
330 F(75000000, P_GPLL0, 8, 0, 0),
331 F(100000000, P_GPLL0, 6, 0, 0),
332 F(150000000, P_GPLL0, 4, 0, 0),
333 F(333430000, P_MMPLL1, 3.5, 0, 0),
334 F(400000000, P_MMPLL0, 2, 0, 0),
335 F(466800000, P_MMPLL1, 2.5, 0, 0),
338 static struct clk_rcg2 mmss_axi_clk_src = {
341 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
342 .freq_tbl = ftbl_mmss_axi_clk,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "mmss_axi_clk_src",
345 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
347 .ops = &clk_rcg2_ops,
351 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
352 F(19200000, P_XO, 1, 0, 0),
353 F(37500000, P_GPLL0, 16, 0, 0),
354 F(50000000, P_GPLL0, 12, 0, 0),
355 F(75000000, P_GPLL0, 8, 0, 0),
356 F(109090000, P_GPLL0, 5.5, 0, 0),
357 F(150000000, P_GPLL0, 4, 0, 0),
358 F(228570000, P_MMPLL0, 3.5, 0, 0),
359 F(320000000, P_MMPLL0, 2.5, 0, 0),
362 static struct clk_rcg2 ocmemnoc_clk_src = {
365 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
366 .freq_tbl = ftbl_ocmemnoc_clk,
367 .clkr.hw.init = &(struct clk_init_data){
368 .name = "ocmemnoc_clk_src",
369 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
371 .ops = &clk_rcg2_ops,
375 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
376 F(100000000, P_GPLL0, 6, 0, 0),
377 F(200000000, P_MMPLL0, 4, 0, 0),
381 static struct clk_rcg2 csi0_clk_src = {
384 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
385 .freq_tbl = ftbl_camss_csi0_3_clk,
386 .clkr.hw.init = &(struct clk_init_data){
387 .name = "csi0_clk_src",
388 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
390 .ops = &clk_rcg2_ops,
394 static struct clk_rcg2 csi1_clk_src = {
397 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
398 .freq_tbl = ftbl_camss_csi0_3_clk,
399 .clkr.hw.init = &(struct clk_init_data){
400 .name = "csi1_clk_src",
401 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
403 .ops = &clk_rcg2_ops,
407 static struct clk_rcg2 csi2_clk_src = {
410 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
411 .freq_tbl = ftbl_camss_csi0_3_clk,
412 .clkr.hw.init = &(struct clk_init_data){
413 .name = "csi2_clk_src",
414 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
416 .ops = &clk_rcg2_ops,
420 static struct clk_rcg2 csi3_clk_src = {
423 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
424 .freq_tbl = ftbl_camss_csi0_3_clk,
425 .clkr.hw.init = &(struct clk_init_data){
426 .name = "csi3_clk_src",
427 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
429 .ops = &clk_rcg2_ops,
433 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
434 F(37500000, P_GPLL0, 16, 0, 0),
435 F(50000000, P_GPLL0, 12, 0, 0),
436 F(60000000, P_GPLL0, 10, 0, 0),
437 F(80000000, P_GPLL0, 7.5, 0, 0),
438 F(100000000, P_GPLL0, 6, 0, 0),
439 F(109090000, P_GPLL0, 5.5, 0, 0),
440 F(133330000, P_GPLL0, 4.5, 0, 0),
441 F(200000000, P_GPLL0, 3, 0, 0),
442 F(228570000, P_MMPLL0, 3.5, 0, 0),
443 F(266670000, P_MMPLL0, 3, 0, 0),
444 F(320000000, P_MMPLL0, 2.5, 0, 0),
445 F(465000000, P_MMPLL4, 2, 0, 0),
446 F(600000000, P_GPLL0, 1, 0, 0),
450 static struct clk_rcg2 vfe0_clk_src = {
453 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
454 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
455 .clkr.hw.init = &(struct clk_init_data){
456 .name = "vfe0_clk_src",
457 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
459 .ops = &clk_rcg2_ops,
463 static struct clk_rcg2 vfe1_clk_src = {
466 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
467 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "vfe1_clk_src",
470 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
472 .ops = &clk_rcg2_ops,
476 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
477 F(37500000, P_GPLL0, 16, 0, 0),
478 F(60000000, P_GPLL0, 10, 0, 0),
479 F(75000000, P_GPLL0, 8, 0, 0),
480 F(85710000, P_GPLL0, 7, 0, 0),
481 F(100000000, P_GPLL0, 6, 0, 0),
482 F(150000000, P_GPLL0, 4, 0, 0),
483 F(160000000, P_MMPLL0, 5, 0, 0),
484 F(200000000, P_MMPLL0, 4, 0, 0),
485 F(228570000, P_MMPLL0, 3.5, 0, 0),
486 F(300000000, P_GPLL0, 2, 0, 0),
487 F(320000000, P_MMPLL0, 2.5, 0, 0),
491 static struct clk_rcg2 mdp_clk_src = {
494 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
495 .freq_tbl = ftbl_mdss_mdp_clk,
496 .clkr.hw.init = &(struct clk_init_data){
497 .name = "mdp_clk_src",
498 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
500 .ops = &clk_rcg2_ops,
504 static struct clk_rcg2 gfx3d_clk_src = {
507 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
508 .clkr.hw.init = &(struct clk_init_data){
509 .name = "gfx3d_clk_src",
510 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
512 .ops = &clk_rcg2_ops,
516 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
517 F(75000000, P_GPLL0, 8, 0, 0),
518 F(133330000, P_GPLL0, 4.5, 0, 0),
519 F(200000000, P_GPLL0, 3, 0, 0),
520 F(228570000, P_MMPLL0, 3.5, 0, 0),
521 F(266670000, P_MMPLL0, 3, 0, 0),
522 F(320000000, P_MMPLL0, 2.5, 0, 0),
526 static struct clk_rcg2 jpeg0_clk_src = {
529 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
530 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "jpeg0_clk_src",
533 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
535 .ops = &clk_rcg2_ops,
539 static struct clk_rcg2 jpeg1_clk_src = {
542 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
543 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
544 .clkr.hw.init = &(struct clk_init_data){
545 .name = "jpeg1_clk_src",
546 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
548 .ops = &clk_rcg2_ops,
552 static struct clk_rcg2 jpeg2_clk_src = {
555 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
556 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
557 .clkr.hw.init = &(struct clk_init_data){
558 .name = "jpeg2_clk_src",
559 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
561 .ops = &clk_rcg2_ops,
565 static struct clk_rcg2 pclk0_clk_src = {
569 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
570 .clkr.hw.init = &(struct clk_init_data){
571 .name = "pclk0_clk_src",
572 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
574 .ops = &clk_pixel_ops,
575 .flags = CLK_SET_RATE_PARENT,
579 static struct clk_rcg2 pclk1_clk_src = {
583 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
584 .clkr.hw.init = &(struct clk_init_data){
585 .name = "pclk1_clk_src",
586 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
588 .ops = &clk_pixel_ops,
589 .flags = CLK_SET_RATE_PARENT,
593 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
594 F(50000000, P_GPLL0, 12, 0, 0),
595 F(100000000, P_GPLL0, 6, 0, 0),
596 F(133330000, P_GPLL0, 4.5, 0, 0),
597 F(200000000, P_MMPLL0, 4, 0, 0),
598 F(266670000, P_MMPLL0, 3, 0, 0),
599 F(465000000, P_MMPLL3, 2, 0, 0),
603 static struct clk_rcg2 vcodec0_clk_src = {
607 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
608 .freq_tbl = ftbl_venus0_vcodec0_clk,
609 .clkr.hw.init = &(struct clk_init_data){
610 .name = "vcodec0_clk_src",
611 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
613 .ops = &clk_rcg2_ops,
617 static struct freq_tbl ftbl_avsync_vp_clk[] = {
618 F(150000000, P_GPLL0, 4, 0, 0),
619 F(320000000, P_MMPLL0, 2.5, 0, 0),
623 static struct clk_rcg2 vp_clk_src = {
626 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
627 .freq_tbl = ftbl_avsync_vp_clk,
628 .clkr.hw.init = &(struct clk_init_data){
629 .name = "vp_clk_src",
630 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
632 .ops = &clk_rcg2_ops,
636 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
637 F(19200000, P_XO, 1, 0, 0),
641 static struct clk_rcg2 cci_clk_src = {
645 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
646 .freq_tbl = ftbl_camss_cci_cci_clk,
647 .clkr.hw.init = &(struct clk_init_data){
648 .name = "cci_clk_src",
649 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
651 .ops = &clk_rcg2_ops,
655 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
656 F(10000, P_XO, 16, 1, 120),
657 F(24000, P_XO, 16, 1, 50),
658 F(6000000, P_GPLL0, 10, 1, 10),
659 F(12000000, P_GPLL0, 10, 1, 5),
660 F(13000000, P_GPLL0, 4, 13, 150),
661 F(24000000, P_GPLL0, 5, 1, 5),
665 static struct clk_rcg2 camss_gp0_clk_src = {
669 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
670 .freq_tbl = ftbl_camss_gp0_1_clk,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "camss_gp0_clk_src",
673 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
675 .ops = &clk_rcg2_ops,
679 static struct clk_rcg2 camss_gp1_clk_src = {
683 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
684 .freq_tbl = ftbl_camss_gp0_1_clk,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "camss_gp1_clk_src",
687 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
689 .ops = &clk_rcg2_ops,
693 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
694 F(4800000, P_XO, 4, 0, 0),
695 F(6000000, P_GPLL0, 10, 1, 10),
696 F(8000000, P_GPLL0, 15, 1, 5),
697 F(9600000, P_XO, 2, 0, 0),
698 F(16000000, P_MMPLL0, 10, 1, 5),
699 F(19200000, P_XO, 1, 0, 0),
700 F(24000000, P_GPLL0, 5, 1, 5),
701 F(32000000, P_MMPLL0, 5, 1, 5),
702 F(48000000, P_GPLL0, 12.5, 0, 0),
703 F(64000000, P_MMPLL0, 12.5, 0, 0),
707 static struct clk_rcg2 mclk0_clk_src = {
711 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
712 .freq_tbl = ftbl_camss_mclk0_3_clk,
713 .clkr.hw.init = &(struct clk_init_data){
714 .name = "mclk0_clk_src",
715 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
717 .ops = &clk_rcg2_ops,
721 static struct clk_rcg2 mclk1_clk_src = {
725 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
726 .freq_tbl = ftbl_camss_mclk0_3_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "mclk1_clk_src",
729 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
731 .ops = &clk_rcg2_ops,
735 static struct clk_rcg2 mclk2_clk_src = {
739 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
740 .freq_tbl = ftbl_camss_mclk0_3_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "mclk2_clk_src",
743 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
745 .ops = &clk_rcg2_ops,
749 static struct clk_rcg2 mclk3_clk_src = {
753 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
754 .freq_tbl = ftbl_camss_mclk0_3_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "mclk3_clk_src",
757 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
759 .ops = &clk_rcg2_ops,
763 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
764 F(100000000, P_GPLL0, 6, 0, 0),
765 F(200000000, P_MMPLL0, 4, 0, 0),
769 static struct clk_rcg2 csi0phytimer_clk_src = {
772 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
773 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "csi0phytimer_clk_src",
776 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
778 .ops = &clk_rcg2_ops,
782 static struct clk_rcg2 csi1phytimer_clk_src = {
785 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
786 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
787 .clkr.hw.init = &(struct clk_init_data){
788 .name = "csi1phytimer_clk_src",
789 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
791 .ops = &clk_rcg2_ops,
795 static struct clk_rcg2 csi2phytimer_clk_src = {
798 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
799 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "csi2phytimer_clk_src",
802 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
804 .ops = &clk_rcg2_ops,
808 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
809 F(133330000, P_GPLL0, 4.5, 0, 0),
810 F(266670000, P_MMPLL0, 3, 0, 0),
811 F(320000000, P_MMPLL0, 2.5, 0, 0),
812 F(372000000, P_MMPLL4, 2.5, 0, 0),
813 F(465000000, P_MMPLL4, 2, 0, 0),
814 F(600000000, P_GPLL0, 1, 0, 0),
818 static struct clk_rcg2 cpp_clk_src = {
821 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
822 .freq_tbl = ftbl_camss_vfe_cpp_clk,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "cpp_clk_src",
825 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
827 .ops = &clk_rcg2_ops,
831 static struct clk_rcg2 byte0_clk_src = {
834 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
835 .clkr.hw.init = &(struct clk_init_data){
836 .name = "byte0_clk_src",
837 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
839 .ops = &clk_byte2_ops,
840 .flags = CLK_SET_RATE_PARENT,
844 static struct clk_rcg2 byte1_clk_src = {
847 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "byte1_clk_src",
850 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
852 .ops = &clk_byte2_ops,
853 .flags = CLK_SET_RATE_PARENT,
857 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
858 F(19200000, P_XO, 1, 0, 0),
862 static struct clk_rcg2 edpaux_clk_src = {
865 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
866 .freq_tbl = ftbl_mdss_edpaux_clk,
867 .clkr.hw.init = &(struct clk_init_data){
868 .name = "edpaux_clk_src",
869 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
871 .ops = &clk_rcg2_ops,
875 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
876 F(135000000, P_EDPLINK, 2, 0, 0),
877 F(270000000, P_EDPLINK, 11, 0, 0),
881 static struct clk_rcg2 edplink_clk_src = {
884 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
885 .freq_tbl = ftbl_mdss_edplink_clk,
886 .clkr.hw.init = &(struct clk_init_data){
887 .name = "edplink_clk_src",
888 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
890 .ops = &clk_rcg2_ops,
891 .flags = CLK_SET_RATE_PARENT,
895 static struct freq_tbl edp_pixel_freq_tbl[] = {
900 static struct clk_rcg2 edppixel_clk_src = {
904 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
905 .freq_tbl = edp_pixel_freq_tbl,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "edppixel_clk_src",
908 .parent_names = mmcc_xo_dsi_hdmi_edp,
910 .ops = &clk_edp_pixel_ops,
914 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
915 F(19200000, P_XO, 1, 0, 0),
919 static struct clk_rcg2 esc0_clk_src = {
922 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
923 .freq_tbl = ftbl_mdss_esc0_1_clk,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "esc0_clk_src",
926 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
928 .ops = &clk_rcg2_ops,
932 static struct clk_rcg2 esc1_clk_src = {
935 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
936 .freq_tbl = ftbl_mdss_esc0_1_clk,
937 .clkr.hw.init = &(struct clk_init_data){
938 .name = "esc1_clk_src",
939 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
941 .ops = &clk_rcg2_ops,
945 static struct freq_tbl extpclk_freq_tbl[] = {
946 { .src = P_HDMIPLL },
950 static struct clk_rcg2 extpclk_clk_src = {
953 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
954 .freq_tbl = extpclk_freq_tbl,
955 .clkr.hw.init = &(struct clk_init_data){
956 .name = "extpclk_clk_src",
957 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
959 .ops = &clk_byte_ops,
960 .flags = CLK_SET_RATE_PARENT,
964 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
965 F(19200000, P_XO, 1, 0, 0),
969 static struct clk_rcg2 hdmi_clk_src = {
972 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
973 .freq_tbl = ftbl_mdss_hdmi_clk,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "hdmi_clk_src",
976 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
978 .ops = &clk_rcg2_ops,
982 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
983 F(19200000, P_XO, 1, 0, 0),
987 static struct clk_rcg2 vsync_clk_src = {
990 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
991 .freq_tbl = ftbl_mdss_vsync_clk,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "vsync_clk_src",
994 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
996 .ops = &clk_rcg2_ops,
1000 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1001 F(50000000, P_GPLL0, 12, 0, 0),
1005 static struct clk_rcg2 rbcpr_clk_src = {
1008 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1009 .freq_tbl = ftbl_mmss_rbcpr_clk,
1010 .clkr.hw.init = &(struct clk_init_data){
1011 .name = "rbcpr_clk_src",
1012 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1014 .ops = &clk_rcg2_ops,
1018 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1019 F(19200000, P_XO, 1, 0, 0),
1023 static struct clk_rcg2 rbbmtimer_clk_src = {
1026 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1027 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "rbbmtimer_clk_src",
1030 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1032 .ops = &clk_rcg2_ops,
1036 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1037 F(50000000, P_GPLL0, 12, 0, 0),
1038 F(100000000, P_GPLL0, 6, 0, 0),
1039 F(133330000, P_GPLL0, 4.5, 0, 0),
1040 F(200000000, P_MMPLL0, 4, 0, 0),
1041 F(266670000, P_MMPLL0, 3, 0, 0),
1042 F(465000000, P_MMPLL3, 2, 0, 0),
1046 static struct clk_rcg2 maple_clk_src = {
1049 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1050 .freq_tbl = ftbl_vpu_maple_clk,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "maple_clk_src",
1053 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1055 .ops = &clk_rcg2_ops,
1059 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1060 F(50000000, P_GPLL0, 12, 0, 0),
1061 F(100000000, P_GPLL0, 6, 0, 0),
1062 F(200000000, P_MMPLL0, 4, 0, 0),
1063 F(320000000, P_MMPLL0, 2.5, 0, 0),
1064 F(400000000, P_MMPLL0, 2, 0, 0),
1068 static struct clk_rcg2 vdp_clk_src = {
1071 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1072 .freq_tbl = ftbl_vpu_vdp_clk,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "vdp_clk_src",
1075 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1077 .ops = &clk_rcg2_ops,
1081 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1082 F(40000000, P_GPLL0, 15, 0, 0),
1083 F(80000000, P_MMPLL0, 10, 0, 0),
1087 static struct clk_rcg2 vpu_bus_clk_src = {
1090 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1091 .freq_tbl = ftbl_vpu_bus_clk,
1092 .clkr.hw.init = &(struct clk_init_data){
1093 .name = "vpu_bus_clk_src",
1094 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1096 .ops = &clk_rcg2_ops,
1100 static struct clk_branch mmss_cxo_clk = {
1103 .enable_reg = 0x5104,
1104 .enable_mask = BIT(0),
1105 .hw.init = &(struct clk_init_data){
1106 .name = "mmss_cxo_clk",
1107 .parent_names = (const char *[]){ "xo" },
1109 .flags = CLK_SET_RATE_PARENT,
1110 .ops = &clk_branch2_ops,
1115 static struct clk_branch mmss_sleepclk_clk = {
1118 .enable_reg = 0x5100,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "mmss_sleepclk_clk",
1122 .parent_names = (const char *[]){
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_branch2_ops,
1132 static struct clk_branch avsync_ahb_clk = {
1135 .enable_reg = 0x2414,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "avsync_ahb_clk",
1139 .parent_names = (const char *[]){
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1149 static struct clk_branch avsync_edppixel_clk = {
1152 .enable_reg = 0x2418,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(struct clk_init_data){
1155 .name = "avsync_edppixel_clk",
1156 .parent_names = (const char *[]){
1160 .flags = CLK_SET_RATE_PARENT,
1161 .ops = &clk_branch2_ops,
1166 static struct clk_branch avsync_extpclk_clk = {
1169 .enable_reg = 0x2410,
1170 .enable_mask = BIT(0),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "avsync_extpclk_clk",
1173 .parent_names = (const char *[]){
1177 .flags = CLK_SET_RATE_PARENT,
1178 .ops = &clk_branch2_ops,
1183 static struct clk_branch avsync_pclk0_clk = {
1186 .enable_reg = 0x241c,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "avsync_pclk0_clk",
1190 .parent_names = (const char *[]){
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_branch2_ops,
1200 static struct clk_branch avsync_pclk1_clk = {
1203 .enable_reg = 0x2420,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "avsync_pclk1_clk",
1207 .parent_names = (const char *[]){
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1217 static struct clk_branch avsync_vp_clk = {
1220 .enable_reg = 0x2404,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "avsync_vp_clk",
1224 .parent_names = (const char *[]){
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1234 static struct clk_branch camss_ahb_clk = {
1237 .enable_reg = 0x348c,
1238 .enable_mask = BIT(0),
1239 .hw.init = &(struct clk_init_data){
1240 .name = "camss_ahb_clk",
1241 .parent_names = (const char *[]){
1245 .flags = CLK_SET_RATE_PARENT,
1246 .ops = &clk_branch2_ops,
1251 static struct clk_branch camss_cci_cci_ahb_clk = {
1254 .enable_reg = 0x3348,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(struct clk_init_data){
1257 .name = "camss_cci_cci_ahb_clk",
1258 .parent_names = (const char *[]){
1262 .ops = &clk_branch2_ops,
1267 static struct clk_branch camss_cci_cci_clk = {
1270 .enable_reg = 0x3344,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "camss_cci_cci_clk",
1274 .parent_names = (const char *[]){
1278 .flags = CLK_SET_RATE_PARENT,
1279 .ops = &clk_branch2_ops,
1284 static struct clk_branch camss_csi0_ahb_clk = {
1287 .enable_reg = 0x30bc,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "camss_csi0_ahb_clk",
1291 .parent_names = (const char *[]){
1295 .ops = &clk_branch2_ops,
1300 static struct clk_branch camss_csi0_clk = {
1303 .enable_reg = 0x30b4,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "camss_csi0_clk",
1307 .parent_names = (const char *[]){
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch camss_csi0phy_clk = {
1320 .enable_reg = 0x30c4,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data){
1323 .name = "camss_csi0phy_clk",
1324 .parent_names = (const char *[]){
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1334 static struct clk_branch camss_csi0pix_clk = {
1337 .enable_reg = 0x30e4,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "camss_csi0pix_clk",
1341 .parent_names = (const char *[]){
1345 .flags = CLK_SET_RATE_PARENT,
1346 .ops = &clk_branch2_ops,
1351 static struct clk_branch camss_csi0rdi_clk = {
1354 .enable_reg = 0x30d4,
1355 .enable_mask = BIT(0),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "camss_csi0rdi_clk",
1358 .parent_names = (const char *[]){
1362 .flags = CLK_SET_RATE_PARENT,
1363 .ops = &clk_branch2_ops,
1368 static struct clk_branch camss_csi1_ahb_clk = {
1371 .enable_reg = 0x3128,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "camss_csi1_ahb_clk",
1375 .parent_names = (const char *[]){
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch camss_csi1_clk = {
1388 .enable_reg = 0x3124,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "camss_csi1_clk",
1392 .parent_names = (const char *[]){
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch camss_csi1phy_clk = {
1405 .enable_reg = 0x3134,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "camss_csi1phy_clk",
1409 .parent_names = (const char *[]){
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1419 static struct clk_branch camss_csi1pix_clk = {
1422 .enable_reg = 0x3154,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "camss_csi1pix_clk",
1426 .parent_names = (const char *[]){
1430 .flags = CLK_SET_RATE_PARENT,
1431 .ops = &clk_branch2_ops,
1436 static struct clk_branch camss_csi1rdi_clk = {
1439 .enable_reg = 0x3144,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "camss_csi1rdi_clk",
1443 .parent_names = (const char *[]){
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1453 static struct clk_branch camss_csi2_ahb_clk = {
1456 .enable_reg = 0x3188,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "camss_csi2_ahb_clk",
1460 .parent_names = (const char *[]){
1464 .ops = &clk_branch2_ops,
1469 static struct clk_branch camss_csi2_clk = {
1472 .enable_reg = 0x3184,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "camss_csi2_clk",
1476 .parent_names = (const char *[]){
1480 .flags = CLK_SET_RATE_PARENT,
1481 .ops = &clk_branch2_ops,
1486 static struct clk_branch camss_csi2phy_clk = {
1489 .enable_reg = 0x3194,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "camss_csi2phy_clk",
1493 .parent_names = (const char *[]){
1497 .flags = CLK_SET_RATE_PARENT,
1498 .ops = &clk_branch2_ops,
1503 static struct clk_branch camss_csi2pix_clk = {
1506 .enable_reg = 0x31b4,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "camss_csi2pix_clk",
1510 .parent_names = (const char *[]){
1514 .flags = CLK_SET_RATE_PARENT,
1515 .ops = &clk_branch2_ops,
1520 static struct clk_branch camss_csi2rdi_clk = {
1523 .enable_reg = 0x31a4,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "camss_csi2rdi_clk",
1527 .parent_names = (const char *[]){
1531 .flags = CLK_SET_RATE_PARENT,
1532 .ops = &clk_branch2_ops,
1537 static struct clk_branch camss_csi3_ahb_clk = {
1540 .enable_reg = 0x31e8,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(struct clk_init_data){
1543 .name = "camss_csi3_ahb_clk",
1544 .parent_names = (const char *[]){
1548 .ops = &clk_branch2_ops,
1553 static struct clk_branch camss_csi3_clk = {
1556 .enable_reg = 0x31e4,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "camss_csi3_clk",
1560 .parent_names = (const char *[]){
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1570 static struct clk_branch camss_csi3phy_clk = {
1573 .enable_reg = 0x31f4,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "camss_csi3phy_clk",
1577 .parent_names = (const char *[]){
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch camss_csi3pix_clk = {
1590 .enable_reg = 0x3214,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "camss_csi3pix_clk",
1594 .parent_names = (const char *[]){
1598 .flags = CLK_SET_RATE_PARENT,
1599 .ops = &clk_branch2_ops,
1604 static struct clk_branch camss_csi3rdi_clk = {
1607 .enable_reg = 0x3204,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "camss_csi3rdi_clk",
1611 .parent_names = (const char *[]){
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch camss_csi_vfe0_clk = {
1624 .enable_reg = 0x3704,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "camss_csi_vfe0_clk",
1628 .parent_names = (const char *[]){
1632 .flags = CLK_SET_RATE_PARENT,
1633 .ops = &clk_branch2_ops,
1638 static struct clk_branch camss_csi_vfe1_clk = {
1641 .enable_reg = 0x3714,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "camss_csi_vfe1_clk",
1645 .parent_names = (const char *[]){
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1655 static struct clk_branch camss_gp0_clk = {
1658 .enable_reg = 0x3444,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "camss_gp0_clk",
1662 .parent_names = (const char *[]){
1663 "camss_gp0_clk_src",
1666 .flags = CLK_SET_RATE_PARENT,
1667 .ops = &clk_branch2_ops,
1672 static struct clk_branch camss_gp1_clk = {
1675 .enable_reg = 0x3474,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "camss_gp1_clk",
1679 .parent_names = (const char *[]){
1680 "camss_gp1_clk_src",
1683 .flags = CLK_SET_RATE_PARENT,
1684 .ops = &clk_branch2_ops,
1689 static struct clk_branch camss_ispif_ahb_clk = {
1692 .enable_reg = 0x3224,
1693 .enable_mask = BIT(0),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "camss_ispif_ahb_clk",
1696 .parent_names = (const char *[]){
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch camss_jpeg_jpeg0_clk = {
1709 .enable_reg = 0x35a8,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "camss_jpeg_jpeg0_clk",
1713 .parent_names = (const char *[]){
1717 .flags = CLK_SET_RATE_PARENT,
1718 .ops = &clk_branch2_ops,
1723 static struct clk_branch camss_jpeg_jpeg1_clk = {
1726 .enable_reg = 0x35ac,
1727 .enable_mask = BIT(0),
1728 .hw.init = &(struct clk_init_data){
1729 .name = "camss_jpeg_jpeg1_clk",
1730 .parent_names = (const char *[]){
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch camss_jpeg_jpeg2_clk = {
1743 .enable_reg = 0x35b0,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "camss_jpeg_jpeg2_clk",
1747 .parent_names = (const char *[]){
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1760 .enable_reg = 0x35b4,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(struct clk_init_data){
1763 .name = "camss_jpeg_jpeg_ahb_clk",
1764 .parent_names = (const char *[]){
1768 .ops = &clk_branch2_ops,
1773 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1776 .enable_reg = 0x35b8,
1777 .enable_mask = BIT(0),
1778 .hw.init = &(struct clk_init_data){
1779 .name = "camss_jpeg_jpeg_axi_clk",
1780 .parent_names = (const char *[]){
1784 .ops = &clk_branch2_ops,
1789 static struct clk_branch camss_mclk0_clk = {
1792 .enable_reg = 0x3384,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "camss_mclk0_clk",
1796 .parent_names = (const char *[]){
1800 .flags = CLK_SET_RATE_PARENT,
1801 .ops = &clk_branch2_ops,
1806 static struct clk_branch camss_mclk1_clk = {
1809 .enable_reg = 0x33b4,
1810 .enable_mask = BIT(0),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "camss_mclk1_clk",
1813 .parent_names = (const char *[]){
1817 .flags = CLK_SET_RATE_PARENT,
1818 .ops = &clk_branch2_ops,
1823 static struct clk_branch camss_mclk2_clk = {
1826 .enable_reg = 0x33e4,
1827 .enable_mask = BIT(0),
1828 .hw.init = &(struct clk_init_data){
1829 .name = "camss_mclk2_clk",
1830 .parent_names = (const char *[]){
1834 .flags = CLK_SET_RATE_PARENT,
1835 .ops = &clk_branch2_ops,
1840 static struct clk_branch camss_mclk3_clk = {
1843 .enable_reg = 0x3414,
1844 .enable_mask = BIT(0),
1845 .hw.init = &(struct clk_init_data){
1846 .name = "camss_mclk3_clk",
1847 .parent_names = (const char *[]){
1851 .flags = CLK_SET_RATE_PARENT,
1852 .ops = &clk_branch2_ops,
1857 static struct clk_branch camss_micro_ahb_clk = {
1860 .enable_reg = 0x3494,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "camss_micro_ahb_clk",
1864 .parent_names = (const char *[]){
1868 .ops = &clk_branch2_ops,
1873 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1876 .enable_reg = 0x3024,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data){
1879 .name = "camss_phy0_csi0phytimer_clk",
1880 .parent_names = (const char *[]){
1881 "csi0phytimer_clk_src",
1884 .flags = CLK_SET_RATE_PARENT,
1885 .ops = &clk_branch2_ops,
1890 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1893 .enable_reg = 0x3054,
1894 .enable_mask = BIT(0),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "camss_phy1_csi1phytimer_clk",
1897 .parent_names = (const char *[]){
1898 "csi1phytimer_clk_src",
1901 .flags = CLK_SET_RATE_PARENT,
1902 .ops = &clk_branch2_ops,
1907 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1910 .enable_reg = 0x3084,
1911 .enable_mask = BIT(0),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "camss_phy2_csi2phytimer_clk",
1914 .parent_names = (const char *[]){
1915 "csi2phytimer_clk_src",
1918 .flags = CLK_SET_RATE_PARENT,
1919 .ops = &clk_branch2_ops,
1924 static struct clk_branch camss_top_ahb_clk = {
1927 .enable_reg = 0x3484,
1928 .enable_mask = BIT(0),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "camss_top_ahb_clk",
1931 .parent_names = (const char *[]){
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1941 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1944 .enable_reg = 0x36b4,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "camss_vfe_cpp_ahb_clk",
1948 .parent_names = (const char *[]){
1952 .flags = CLK_SET_RATE_PARENT,
1953 .ops = &clk_branch2_ops,
1958 static struct clk_branch camss_vfe_cpp_clk = {
1961 .enable_reg = 0x36b0,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "camss_vfe_cpp_clk",
1965 .parent_names = (const char *[]){
1969 .flags = CLK_SET_RATE_PARENT,
1970 .ops = &clk_branch2_ops,
1975 static struct clk_branch camss_vfe_vfe0_clk = {
1978 .enable_reg = 0x36a8,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "camss_vfe_vfe0_clk",
1982 .parent_names = (const char *[]){
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1992 static struct clk_branch camss_vfe_vfe1_clk = {
1995 .enable_reg = 0x36ac,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "camss_vfe_vfe1_clk",
1999 .parent_names = (const char *[]){
2003 .flags = CLK_SET_RATE_PARENT,
2004 .ops = &clk_branch2_ops,
2009 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2012 .enable_reg = 0x36b8,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "camss_vfe_vfe_ahb_clk",
2016 .parent_names = (const char *[]){
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2026 static struct clk_branch camss_vfe_vfe_axi_clk = {
2029 .enable_reg = 0x36bc,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "camss_vfe_vfe_axi_clk",
2033 .parent_names = (const char *[]){
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2043 static struct clk_branch mdss_ahb_clk = {
2046 .enable_reg = 0x2308,
2047 .enable_mask = BIT(0),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "mdss_ahb_clk",
2050 .parent_names = (const char *[]){
2054 .flags = CLK_SET_RATE_PARENT,
2055 .ops = &clk_branch2_ops,
2060 static struct clk_branch mdss_axi_clk = {
2063 .enable_reg = 0x2310,
2064 .enable_mask = BIT(0),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "mdss_axi_clk",
2067 .parent_names = (const char *[]){
2071 .flags = CLK_SET_RATE_PARENT,
2072 .ops = &clk_branch2_ops,
2077 static struct clk_branch mdss_byte0_clk = {
2080 .enable_reg = 0x233c,
2081 .enable_mask = BIT(0),
2082 .hw.init = &(struct clk_init_data){
2083 .name = "mdss_byte0_clk",
2084 .parent_names = (const char *[]){
2088 .flags = CLK_SET_RATE_PARENT,
2089 .ops = &clk_branch2_ops,
2094 static struct clk_branch mdss_byte1_clk = {
2097 .enable_reg = 0x2340,
2098 .enable_mask = BIT(0),
2099 .hw.init = &(struct clk_init_data){
2100 .name = "mdss_byte1_clk",
2101 .parent_names = (const char *[]){
2105 .flags = CLK_SET_RATE_PARENT,
2106 .ops = &clk_branch2_ops,
2111 static struct clk_branch mdss_edpaux_clk = {
2114 .enable_reg = 0x2334,
2115 .enable_mask = BIT(0),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "mdss_edpaux_clk",
2118 .parent_names = (const char *[]){
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2128 static struct clk_branch mdss_edplink_clk = {
2131 .enable_reg = 0x2330,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "mdss_edplink_clk",
2135 .parent_names = (const char *[]){
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch mdss_edppixel_clk = {
2148 .enable_reg = 0x232c,
2149 .enable_mask = BIT(0),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "mdss_edppixel_clk",
2152 .parent_names = (const char *[]){
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2162 static struct clk_branch mdss_esc0_clk = {
2165 .enable_reg = 0x2344,
2166 .enable_mask = BIT(0),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "mdss_esc0_clk",
2169 .parent_names = (const char *[]){
2173 .flags = CLK_SET_RATE_PARENT,
2174 .ops = &clk_branch2_ops,
2179 static struct clk_branch mdss_esc1_clk = {
2182 .enable_reg = 0x2348,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "mdss_esc1_clk",
2186 .parent_names = (const char *[]){
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2196 static struct clk_branch mdss_extpclk_clk = {
2199 .enable_reg = 0x2324,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "mdss_extpclk_clk",
2203 .parent_names = (const char *[]){
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2213 static struct clk_branch mdss_hdmi_ahb_clk = {
2216 .enable_reg = 0x230c,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "mdss_hdmi_ahb_clk",
2220 .parent_names = (const char *[]){
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2230 static struct clk_branch mdss_hdmi_clk = {
2233 .enable_reg = 0x2338,
2234 .enable_mask = BIT(0),
2235 .hw.init = &(struct clk_init_data){
2236 .name = "mdss_hdmi_clk",
2237 .parent_names = (const char *[]){
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2247 static struct clk_branch mdss_mdp_clk = {
2250 .enable_reg = 0x231c,
2251 .enable_mask = BIT(0),
2252 .hw.init = &(struct clk_init_data){
2253 .name = "mdss_mdp_clk",
2254 .parent_names = (const char *[]){
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2264 static struct clk_branch mdss_mdp_lut_clk = {
2267 .enable_reg = 0x2320,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "mdss_mdp_lut_clk",
2271 .parent_names = (const char *[]){
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2281 static struct clk_branch mdss_pclk0_clk = {
2284 .enable_reg = 0x2314,
2285 .enable_mask = BIT(0),
2286 .hw.init = &(struct clk_init_data){
2287 .name = "mdss_pclk0_clk",
2288 .parent_names = (const char *[]){
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2298 static struct clk_branch mdss_pclk1_clk = {
2301 .enable_reg = 0x2318,
2302 .enable_mask = BIT(0),
2303 .hw.init = &(struct clk_init_data){
2304 .name = "mdss_pclk1_clk",
2305 .parent_names = (const char *[]){
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2315 static struct clk_branch mdss_vsync_clk = {
2318 .enable_reg = 0x2328,
2319 .enable_mask = BIT(0),
2320 .hw.init = &(struct clk_init_data){
2321 .name = "mdss_vsync_clk",
2322 .parent_names = (const char *[]){
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2332 static struct clk_branch mmss_rbcpr_ahb_clk = {
2335 .enable_reg = 0x4088,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "mmss_rbcpr_ahb_clk",
2339 .parent_names = (const char *[]){
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2349 static struct clk_branch mmss_rbcpr_clk = {
2352 .enable_reg = 0x4084,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "mmss_rbcpr_clk",
2356 .parent_names = (const char *[]){
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2366 static struct clk_branch mmss_spdm_ahb_clk = {
2369 .enable_reg = 0x0230,
2370 .enable_mask = BIT(0),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "mmss_spdm_ahb_clk",
2373 .parent_names = (const char *[]){
2374 "mmss_spdm_ahb_div_clk",
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2383 static struct clk_branch mmss_spdm_axi_clk = {
2386 .enable_reg = 0x0210,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "mmss_spdm_axi_clk",
2390 .parent_names = (const char *[]){
2391 "mmss_spdm_axi_div_clk",
2394 .flags = CLK_SET_RATE_PARENT,
2395 .ops = &clk_branch2_ops,
2400 static struct clk_branch mmss_spdm_csi0_clk = {
2403 .enable_reg = 0x023c,
2404 .enable_mask = BIT(0),
2405 .hw.init = &(struct clk_init_data){
2406 .name = "mmss_spdm_csi0_clk",
2407 .parent_names = (const char *[]){
2408 "mmss_spdm_csi0_div_clk",
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2417 static struct clk_branch mmss_spdm_gfx3d_clk = {
2420 .enable_reg = 0x022c,
2421 .enable_mask = BIT(0),
2422 .hw.init = &(struct clk_init_data){
2423 .name = "mmss_spdm_gfx3d_clk",
2424 .parent_names = (const char *[]){
2425 "mmss_spdm_gfx3d_div_clk",
2428 .flags = CLK_SET_RATE_PARENT,
2429 .ops = &clk_branch2_ops,
2434 static struct clk_branch mmss_spdm_jpeg0_clk = {
2437 .enable_reg = 0x0204,
2438 .enable_mask = BIT(0),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "mmss_spdm_jpeg0_clk",
2441 .parent_names = (const char *[]){
2442 "mmss_spdm_jpeg0_div_clk",
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2451 static struct clk_branch mmss_spdm_jpeg1_clk = {
2454 .enable_reg = 0x0208,
2455 .enable_mask = BIT(0),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "mmss_spdm_jpeg1_clk",
2458 .parent_names = (const char *[]){
2459 "mmss_spdm_jpeg1_div_clk",
2462 .flags = CLK_SET_RATE_PARENT,
2463 .ops = &clk_branch2_ops,
2468 static struct clk_branch mmss_spdm_jpeg2_clk = {
2471 .enable_reg = 0x0224,
2472 .enable_mask = BIT(0),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "mmss_spdm_jpeg2_clk",
2475 .parent_names = (const char *[]){
2476 "mmss_spdm_jpeg2_div_clk",
2479 .flags = CLK_SET_RATE_PARENT,
2480 .ops = &clk_branch2_ops,
2485 static struct clk_branch mmss_spdm_mdp_clk = {
2488 .enable_reg = 0x020c,
2489 .enable_mask = BIT(0),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "mmss_spdm_mdp_clk",
2492 .parent_names = (const char *[]){
2493 "mmss_spdm_mdp_div_clk",
2496 .flags = CLK_SET_RATE_PARENT,
2497 .ops = &clk_branch2_ops,
2502 static struct clk_branch mmss_spdm_pclk0_clk = {
2505 .enable_reg = 0x0234,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "mmss_spdm_pclk0_clk",
2509 .parent_names = (const char *[]){
2510 "mmss_spdm_pclk0_div_clk",
2513 .flags = CLK_SET_RATE_PARENT,
2514 .ops = &clk_branch2_ops,
2519 static struct clk_branch mmss_spdm_pclk1_clk = {
2522 .enable_reg = 0x0228,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "mmss_spdm_pclk1_clk",
2526 .parent_names = (const char *[]){
2527 "mmss_spdm_pclk1_div_clk",
2530 .flags = CLK_SET_RATE_PARENT,
2531 .ops = &clk_branch2_ops,
2536 static struct clk_branch mmss_spdm_vcodec0_clk = {
2539 .enable_reg = 0x0214,
2540 .enable_mask = BIT(0),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "mmss_spdm_vcodec0_clk",
2543 .parent_names = (const char *[]){
2544 "mmss_spdm_vcodec0_div_clk",
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2553 static struct clk_branch mmss_spdm_vfe0_clk = {
2556 .enable_reg = 0x0218,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "mmss_spdm_vfe0_clk",
2560 .parent_names = (const char *[]){
2561 "mmss_spdm_vfe0_div_clk",
2564 .flags = CLK_SET_RATE_PARENT,
2565 .ops = &clk_branch2_ops,
2570 static struct clk_branch mmss_spdm_vfe1_clk = {
2573 .enable_reg = 0x021c,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "mmss_spdm_vfe1_clk",
2577 .parent_names = (const char *[]){
2578 "mmss_spdm_vfe1_div_clk",
2581 .flags = CLK_SET_RATE_PARENT,
2582 .ops = &clk_branch2_ops,
2587 static struct clk_branch mmss_spdm_rm_axi_clk = {
2590 .enable_reg = 0x0304,
2591 .enable_mask = BIT(0),
2592 .hw.init = &(struct clk_init_data){
2593 .name = "mmss_spdm_rm_axi_clk",
2594 .parent_names = (const char *[]){
2598 .flags = CLK_SET_RATE_PARENT,
2599 .ops = &clk_branch2_ops,
2604 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2607 .enable_reg = 0x0308,
2608 .enable_mask = BIT(0),
2609 .hw.init = &(struct clk_init_data){
2610 .name = "mmss_spdm_rm_ocmemnoc_clk",
2611 .parent_names = (const char *[]){
2615 .flags = CLK_SET_RATE_PARENT,
2616 .ops = &clk_branch2_ops,
2622 static struct clk_branch mmss_misc_ahb_clk = {
2625 .enable_reg = 0x502c,
2626 .enable_mask = BIT(0),
2627 .hw.init = &(struct clk_init_data){
2628 .name = "mmss_misc_ahb_clk",
2629 .parent_names = (const char *[]){
2633 .flags = CLK_SET_RATE_PARENT,
2634 .ops = &clk_branch2_ops,
2639 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2642 .enable_reg = 0x5024,
2643 .enable_mask = BIT(0),
2644 .hw.init = &(struct clk_init_data){
2645 .name = "mmss_mmssnoc_ahb_clk",
2646 .parent_names = (const char *[]){
2650 .ops = &clk_branch2_ops,
2651 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2656 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2659 .enable_reg = 0x5028,
2660 .enable_mask = BIT(0),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "mmss_mmssnoc_bto_ahb_clk",
2663 .parent_names = (const char *[]){
2667 .ops = &clk_branch2_ops,
2668 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2673 static struct clk_branch mmss_mmssnoc_axi_clk = {
2676 .enable_reg = 0x506c,
2677 .enable_mask = BIT(0),
2678 .hw.init = &(struct clk_init_data){
2679 .name = "mmss_mmssnoc_axi_clk",
2680 .parent_names = (const char *[]){
2684 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2685 .ops = &clk_branch2_ops,
2690 static struct clk_branch mmss_s0_axi_clk = {
2693 .enable_reg = 0x5064,
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "mmss_s0_axi_clk",
2697 .parent_names = (const char *[]){
2701 .ops = &clk_branch2_ops,
2702 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2707 static struct clk_branch ocmemcx_ahb_clk = {
2710 .enable_reg = 0x405c,
2711 .enable_mask = BIT(0),
2712 .hw.init = &(struct clk_init_data){
2713 .name = "ocmemcx_ahb_clk",
2714 .parent_names = (const char *[]){
2718 .flags = CLK_SET_RATE_PARENT,
2719 .ops = &clk_branch2_ops,
2724 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2727 .enable_reg = 0x4058,
2728 .enable_mask = BIT(0),
2729 .hw.init = &(struct clk_init_data){
2730 .name = "ocmemcx_ocmemnoc_clk",
2731 .parent_names = (const char *[]){
2735 .flags = CLK_SET_RATE_PARENT,
2736 .ops = &clk_branch2_ops,
2741 static struct clk_branch oxili_ocmemgx_clk = {
2744 .enable_reg = 0x402c,
2745 .enable_mask = BIT(0),
2746 .hw.init = &(struct clk_init_data){
2747 .name = "oxili_ocmemgx_clk",
2748 .parent_names = (const char *[]){
2752 .flags = CLK_SET_RATE_PARENT,
2753 .ops = &clk_branch2_ops,
2758 static struct clk_branch oxili_gfx3d_clk = {
2761 .enable_reg = 0x4028,
2762 .enable_mask = BIT(0),
2763 .hw.init = &(struct clk_init_data){
2764 .name = "oxili_gfx3d_clk",
2765 .parent_names = (const char *[]){
2769 .flags = CLK_SET_RATE_PARENT,
2770 .ops = &clk_branch2_ops,
2775 static struct clk_branch oxili_rbbmtimer_clk = {
2778 .enable_reg = 0x40b0,
2779 .enable_mask = BIT(0),
2780 .hw.init = &(struct clk_init_data){
2781 .name = "oxili_rbbmtimer_clk",
2782 .parent_names = (const char *[]){
2783 "rbbmtimer_clk_src",
2786 .flags = CLK_SET_RATE_PARENT,
2787 .ops = &clk_branch2_ops,
2792 static struct clk_branch oxilicx_ahb_clk = {
2795 .enable_reg = 0x403c,
2796 .enable_mask = BIT(0),
2797 .hw.init = &(struct clk_init_data){
2798 .name = "oxilicx_ahb_clk",
2799 .parent_names = (const char *[]){
2803 .flags = CLK_SET_RATE_PARENT,
2804 .ops = &clk_branch2_ops,
2809 static struct clk_branch venus0_ahb_clk = {
2812 .enable_reg = 0x1030,
2813 .enable_mask = BIT(0),
2814 .hw.init = &(struct clk_init_data){
2815 .name = "venus0_ahb_clk",
2816 .parent_names = (const char *[]){
2820 .flags = CLK_SET_RATE_PARENT,
2821 .ops = &clk_branch2_ops,
2826 static struct clk_branch venus0_axi_clk = {
2829 .enable_reg = 0x1034,
2830 .enable_mask = BIT(0),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "venus0_axi_clk",
2833 .parent_names = (const char *[]){
2837 .flags = CLK_SET_RATE_PARENT,
2838 .ops = &clk_branch2_ops,
2843 static struct clk_branch venus0_core0_vcodec_clk = {
2846 .enable_reg = 0x1048,
2847 .enable_mask = BIT(0),
2848 .hw.init = &(struct clk_init_data){
2849 .name = "venus0_core0_vcodec_clk",
2850 .parent_names = (const char *[]){
2854 .flags = CLK_SET_RATE_PARENT,
2855 .ops = &clk_branch2_ops,
2860 static struct clk_branch venus0_core1_vcodec_clk = {
2863 .enable_reg = 0x104c,
2864 .enable_mask = BIT(0),
2865 .hw.init = &(struct clk_init_data){
2866 .name = "venus0_core1_vcodec_clk",
2867 .parent_names = (const char *[]){
2871 .flags = CLK_SET_RATE_PARENT,
2872 .ops = &clk_branch2_ops,
2877 static struct clk_branch venus0_ocmemnoc_clk = {
2880 .enable_reg = 0x1038,
2881 .enable_mask = BIT(0),
2882 .hw.init = &(struct clk_init_data){
2883 .name = "venus0_ocmemnoc_clk",
2884 .parent_names = (const char *[]){
2888 .flags = CLK_SET_RATE_PARENT,
2889 .ops = &clk_branch2_ops,
2894 static struct clk_branch venus0_vcodec0_clk = {
2897 .enable_reg = 0x1028,
2898 .enable_mask = BIT(0),
2899 .hw.init = &(struct clk_init_data){
2900 .name = "venus0_vcodec0_clk",
2901 .parent_names = (const char *[]){
2905 .flags = CLK_SET_RATE_PARENT,
2906 .ops = &clk_branch2_ops,
2911 static struct clk_branch vpu_ahb_clk = {
2914 .enable_reg = 0x1430,
2915 .enable_mask = BIT(0),
2916 .hw.init = &(struct clk_init_data){
2917 .name = "vpu_ahb_clk",
2918 .parent_names = (const char *[]){
2922 .flags = CLK_SET_RATE_PARENT,
2923 .ops = &clk_branch2_ops,
2928 static struct clk_branch vpu_axi_clk = {
2931 .enable_reg = 0x143c,
2932 .enable_mask = BIT(0),
2933 .hw.init = &(struct clk_init_data){
2934 .name = "vpu_axi_clk",
2935 .parent_names = (const char *[]){
2939 .flags = CLK_SET_RATE_PARENT,
2940 .ops = &clk_branch2_ops,
2945 static struct clk_branch vpu_bus_clk = {
2948 .enable_reg = 0x1440,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data){
2951 .name = "vpu_bus_clk",
2952 .parent_names = (const char *[]){
2956 .flags = CLK_SET_RATE_PARENT,
2957 .ops = &clk_branch2_ops,
2962 static struct clk_branch vpu_cxo_clk = {
2965 .enable_reg = 0x1434,
2966 .enable_mask = BIT(0),
2967 .hw.init = &(struct clk_init_data){
2968 .name = "vpu_cxo_clk",
2969 .parent_names = (const char *[]){ "xo" },
2971 .flags = CLK_SET_RATE_PARENT,
2972 .ops = &clk_branch2_ops,
2977 static struct clk_branch vpu_maple_clk = {
2980 .enable_reg = 0x142c,
2981 .enable_mask = BIT(0),
2982 .hw.init = &(struct clk_init_data){
2983 .name = "vpu_maple_clk",
2984 .parent_names = (const char *[]){
2988 .flags = CLK_SET_RATE_PARENT,
2989 .ops = &clk_branch2_ops,
2994 static struct clk_branch vpu_sleep_clk = {
2997 .enable_reg = 0x1438,
2998 .enable_mask = BIT(0),
2999 .hw.init = &(struct clk_init_data){
3000 .name = "vpu_sleep_clk",
3001 .parent_names = (const char *[]){
3005 .flags = CLK_SET_RATE_PARENT,
3006 .ops = &clk_branch2_ops,
3011 static struct clk_branch vpu_vdp_clk = {
3014 .enable_reg = 0x1428,
3015 .enable_mask = BIT(0),
3016 .hw.init = &(struct clk_init_data){
3017 .name = "vpu_vdp_clk",
3018 .parent_names = (const char *[]){
3022 .flags = CLK_SET_RATE_PARENT,
3023 .ops = &clk_branch2_ops,
3028 static const struct pll_config mmpll1_config = {
3033 .vco_mask = 0x3 << 20,
3035 .pre_div_mask = 0x7 << 12,
3036 .post_div_val = 0x0,
3037 .post_div_mask = 0x3 << 8,
3038 .mn_ena_mask = BIT(24),
3039 .main_output_mask = BIT(0),
3042 static const struct pll_config mmpll3_config = {
3047 .vco_mask = 0x3 << 20,
3049 .pre_div_mask = 0x7 << 12,
3050 .post_div_val = 0x0,
3051 .post_div_mask = 0x3 << 8,
3052 .mn_ena_mask = BIT(24),
3053 .main_output_mask = BIT(0),
3054 .aux_output_mask = BIT(1),
3057 static struct gdsc venus0_gdsc = {
3062 .pwrsts = PWRSTS_OFF_ON,
3065 static struct gdsc venus0_core0_gdsc = {
3068 .name = "venus0_core0",
3070 .pwrsts = PWRSTS_OFF_ON,
3073 static struct gdsc venus0_core1_gdsc = {
3076 .name = "venus0_core1",
3078 .pwrsts = PWRSTS_OFF_ON,
3081 static struct gdsc mdss_gdsc = {
3083 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3088 .pwrsts = PWRSTS_OFF_ON,
3091 static struct gdsc camss_jpeg_gdsc = {
3094 .name = "camss_jpeg",
3096 .pwrsts = PWRSTS_OFF_ON,
3099 static struct gdsc camss_vfe_gdsc = {
3101 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3104 .name = "camss_vfe",
3106 .pwrsts = PWRSTS_OFF_ON,
3109 static struct gdsc oxili_gdsc = {
3111 .cxcs = (unsigned int []){ 0x4028 },
3116 .pwrsts = PWRSTS_OFF_ON,
3119 static struct gdsc oxilicx_gdsc = {
3124 .pwrsts = PWRSTS_OFF_ON,
3127 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3128 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3129 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3130 [MMPLL0] = &mmpll0.clkr,
3131 [MMPLL0_VOTE] = &mmpll0_vote,
3132 [MMPLL1] = &mmpll1.clkr,
3133 [MMPLL1_VOTE] = &mmpll1_vote,
3134 [MMPLL2] = &mmpll2.clkr,
3135 [MMPLL3] = &mmpll3.clkr,
3136 [MMPLL4] = &mmpll4.clkr,
3137 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3138 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3139 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3140 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3141 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3142 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3143 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3144 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3145 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3146 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3147 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3148 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3149 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3150 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3151 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3152 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3153 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3154 [VP_CLK_SRC] = &vp_clk_src.clkr,
3155 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3156 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3157 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3158 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3159 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3160 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3161 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3162 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3163 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3164 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3165 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3166 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3167 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3168 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3169 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3170 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3171 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3172 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3173 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3174 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3175 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3176 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3177 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3178 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3179 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3180 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3181 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3182 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3183 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3184 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3185 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3186 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3187 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3188 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3189 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3190 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3191 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3192 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3193 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3194 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3195 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3196 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3197 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3198 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3199 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3200 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3201 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3202 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3203 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3204 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3205 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3206 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3207 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3208 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3209 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3210 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3211 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3212 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3213 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3214 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3215 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3216 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3217 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3218 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3219 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3220 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3221 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3222 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3223 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3224 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3225 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3226 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3227 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3228 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3229 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3230 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3231 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3232 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3233 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3234 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3235 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3236 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3237 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3238 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3239 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3240 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3241 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3242 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3243 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3244 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3245 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3246 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3247 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3248 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3249 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3250 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3251 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3252 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3253 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3254 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3255 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3256 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3257 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3258 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3259 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3260 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3261 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3262 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3263 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3264 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3265 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3266 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3267 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3268 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3269 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3270 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3271 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3272 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3273 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3274 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3275 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3276 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3277 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3278 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3279 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3280 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3281 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3282 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3283 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3284 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3285 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3286 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3287 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3288 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3289 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3290 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3291 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3292 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3295 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3296 [MMSS_SPDM_RESET] = { 0x0200 },
3297 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3298 [VENUS0_RESET] = { 0x1020 },
3299 [VPU_RESET] = { 0x1400 },
3300 [MDSS_RESET] = { 0x2300 },
3301 [AVSYNC_RESET] = { 0x2400 },
3302 [CAMSS_PHY0_RESET] = { 0x3020 },
3303 [CAMSS_PHY1_RESET] = { 0x3050 },
3304 [CAMSS_PHY2_RESET] = { 0x3080 },
3305 [CAMSS_CSI0_RESET] = { 0x30b0 },
3306 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3307 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3308 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3309 [CAMSS_CSI1_RESET] = { 0x3120 },
3310 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3311 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3312 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3313 [CAMSS_CSI2_RESET] = { 0x3180 },
3314 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3315 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3316 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3317 [CAMSS_CSI3_RESET] = { 0x31e0 },
3318 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3319 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3320 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3321 [CAMSS_ISPIF_RESET] = { 0x3220 },
3322 [CAMSS_CCI_RESET] = { 0x3340 },
3323 [CAMSS_MCLK0_RESET] = { 0x3380 },
3324 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3325 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3326 [CAMSS_MCLK3_RESET] = { 0x3410 },
3327 [CAMSS_GP0_RESET] = { 0x3440 },
3328 [CAMSS_GP1_RESET] = { 0x3470 },
3329 [CAMSS_TOP_RESET] = { 0x3480 },
3330 [CAMSS_AHB_RESET] = { 0x3488 },
3331 [CAMSS_MICRO_RESET] = { 0x3490 },
3332 [CAMSS_JPEG_RESET] = { 0x35a0 },
3333 [CAMSS_VFE_RESET] = { 0x36a0 },
3334 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3335 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3336 [OXILI_RESET] = { 0x4020 },
3337 [OXILICX_RESET] = { 0x4030 },
3338 [OCMEMCX_RESET] = { 0x4050 },
3339 [MMSS_RBCRP_RESET] = { 0x4080 },
3340 [MMSSNOCAHB_RESET] = { 0x5020 },
3341 [MMSSNOCAXI_RESET] = { 0x5060 },
3344 static struct gdsc *mmcc_apq8084_gdscs[] = {
3345 [VENUS0_GDSC] = &venus0_gdsc,
3346 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3347 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3348 [MDSS_GDSC] = &mdss_gdsc,
3349 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3350 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3351 [OXILI_GDSC] = &oxili_gdsc,
3352 [OXILICX_GDSC] = &oxilicx_gdsc,
3355 static const struct regmap_config mmcc_apq8084_regmap_config = {
3359 .max_register = 0x5104,
3363 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3364 .config = &mmcc_apq8084_regmap_config,
3365 .clks = mmcc_apq8084_clocks,
3366 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3367 .resets = mmcc_apq8084_resets,
3368 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3369 .gdscs = mmcc_apq8084_gdscs,
3370 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
3373 static const struct of_device_id mmcc_apq8084_match_table[] = {
3374 { .compatible = "qcom,mmcc-apq8084" },
3377 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3379 static int mmcc_apq8084_probe(struct platform_device *pdev)
3382 struct regmap *regmap;
3384 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3388 regmap = dev_get_regmap(&pdev->dev, NULL);
3389 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3390 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3395 static struct platform_driver mmcc_apq8084_driver = {
3396 .probe = mmcc_apq8084_probe,
3398 .name = "mmcc-apq8084",
3399 .of_match_table = mmcc_apq8084_match_table,
3402 module_platform_driver(mmcc_apq8084_driver);
3404 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3405 MODULE_LICENSE("GPL v2");
3406 MODULE_ALIAS("platform:mmcc-apq8084");