1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/kernel.h>
8 #include <linux/platform_device.h>
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11 #include <linux/reset-controller.h>
13 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
14 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
17 #include "clk-regmap.h"
20 #include "clk-branch.h"
43 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
50 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
57 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
66 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
75 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
83 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
91 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
99 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
107 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
116 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
125 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
134 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
143 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 { P_DSI0PLL_BYTE, 1 },
149 { P_DSI1PLL_BYTE, 2 }
152 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
161 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
169 static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
177 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
186 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
195 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
205 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
215 static struct clk_pll mmpll0 = {
219 .config_reg = 0x0014,
221 .status_reg = 0x001c,
223 .clkr.hw.init = &(struct clk_init_data){
225 .parent_names = (const char *[]){ "xo" },
231 static struct clk_regmap mmpll0_vote = {
232 .enable_reg = 0x0100,
233 .enable_mask = BIT(0),
234 .hw.init = &(struct clk_init_data){
235 .name = "mmpll0_vote",
236 .parent_names = (const char *[]){ "mmpll0" },
238 .ops = &clk_pll_vote_ops,
242 static struct clk_pll mmpll1 = {
246 .config_reg = 0x0050,
248 .status_reg = 0x005c,
250 .clkr.hw.init = &(struct clk_init_data){
252 .parent_names = (const char *[]){ "xo" },
258 static struct clk_regmap mmpll1_vote = {
259 .enable_reg = 0x0100,
260 .enable_mask = BIT(1),
261 .hw.init = &(struct clk_init_data){
262 .name = "mmpll1_vote",
263 .parent_names = (const char *[]){ "mmpll1" },
265 .ops = &clk_pll_vote_ops,
269 static struct clk_pll mmpll2 = {
273 .config_reg = 0x4110,
275 .status_reg = 0x411c,
276 .clkr.hw.init = &(struct clk_init_data){
278 .parent_names = (const char *[]){ "xo" },
284 static struct clk_pll mmpll3 = {
288 .config_reg = 0x0090,
290 .status_reg = 0x009c,
292 .clkr.hw.init = &(struct clk_init_data){
294 .parent_names = (const char *[]){ "xo" },
300 static struct clk_pll mmpll4 = {
304 .config_reg = 0x00b0,
306 .status_reg = 0x00bc,
307 .clkr.hw.init = &(struct clk_init_data){
309 .parent_names = (const char *[]){ "xo" },
315 static struct clk_rcg2 mmss_ahb_clk_src = {
318 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "mmss_ahb_clk_src",
321 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
323 .ops = &clk_rcg2_ops,
327 static struct freq_tbl ftbl_mmss_axi_clk[] = {
328 F(19200000, P_XO, 1, 0, 0),
329 F(37500000, P_GPLL0, 16, 0, 0),
330 F(50000000, P_GPLL0, 12, 0, 0),
331 F(75000000, P_GPLL0, 8, 0, 0),
332 F(100000000, P_GPLL0, 6, 0, 0),
333 F(150000000, P_GPLL0, 4, 0, 0),
334 F(333430000, P_MMPLL1, 3.5, 0, 0),
335 F(400000000, P_MMPLL0, 2, 0, 0),
336 F(466800000, P_MMPLL1, 2.5, 0, 0),
339 static struct clk_rcg2 mmss_axi_clk_src = {
342 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
343 .freq_tbl = ftbl_mmss_axi_clk,
344 .clkr.hw.init = &(struct clk_init_data){
345 .name = "mmss_axi_clk_src",
346 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
348 .ops = &clk_rcg2_ops,
352 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
353 F(19200000, P_XO, 1, 0, 0),
354 F(37500000, P_GPLL0, 16, 0, 0),
355 F(50000000, P_GPLL0, 12, 0, 0),
356 F(75000000, P_GPLL0, 8, 0, 0),
357 F(109090000, P_GPLL0, 5.5, 0, 0),
358 F(150000000, P_GPLL0, 4, 0, 0),
359 F(228570000, P_MMPLL0, 3.5, 0, 0),
360 F(320000000, P_MMPLL0, 2.5, 0, 0),
363 static struct clk_rcg2 ocmemnoc_clk_src = {
366 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
367 .freq_tbl = ftbl_ocmemnoc_clk,
368 .clkr.hw.init = &(struct clk_init_data){
369 .name = "ocmemnoc_clk_src",
370 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
372 .ops = &clk_rcg2_ops,
376 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
377 F(100000000, P_GPLL0, 6, 0, 0),
378 F(200000000, P_MMPLL0, 4, 0, 0),
382 static struct clk_rcg2 csi0_clk_src = {
385 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
386 .freq_tbl = ftbl_camss_csi0_3_clk,
387 .clkr.hw.init = &(struct clk_init_data){
388 .name = "csi0_clk_src",
389 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
391 .ops = &clk_rcg2_ops,
395 static struct clk_rcg2 csi1_clk_src = {
398 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
399 .freq_tbl = ftbl_camss_csi0_3_clk,
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "csi1_clk_src",
402 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
404 .ops = &clk_rcg2_ops,
408 static struct clk_rcg2 csi2_clk_src = {
411 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
412 .freq_tbl = ftbl_camss_csi0_3_clk,
413 .clkr.hw.init = &(struct clk_init_data){
414 .name = "csi2_clk_src",
415 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
417 .ops = &clk_rcg2_ops,
421 static struct clk_rcg2 csi3_clk_src = {
424 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
425 .freq_tbl = ftbl_camss_csi0_3_clk,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "csi3_clk_src",
428 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
430 .ops = &clk_rcg2_ops,
434 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
435 F(37500000, P_GPLL0, 16, 0, 0),
436 F(50000000, P_GPLL0, 12, 0, 0),
437 F(60000000, P_GPLL0, 10, 0, 0),
438 F(80000000, P_GPLL0, 7.5, 0, 0),
439 F(100000000, P_GPLL0, 6, 0, 0),
440 F(109090000, P_GPLL0, 5.5, 0, 0),
441 F(133330000, P_GPLL0, 4.5, 0, 0),
442 F(200000000, P_GPLL0, 3, 0, 0),
443 F(228570000, P_MMPLL0, 3.5, 0, 0),
444 F(266670000, P_MMPLL0, 3, 0, 0),
445 F(320000000, P_MMPLL0, 2.5, 0, 0),
446 F(465000000, P_MMPLL4, 2, 0, 0),
447 F(600000000, P_GPLL0, 1, 0, 0),
451 static struct clk_rcg2 vfe0_clk_src = {
454 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
455 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "vfe0_clk_src",
458 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
460 .ops = &clk_rcg2_ops,
464 static struct clk_rcg2 vfe1_clk_src = {
467 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
468 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
469 .clkr.hw.init = &(struct clk_init_data){
470 .name = "vfe1_clk_src",
471 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
473 .ops = &clk_rcg2_ops,
477 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
478 F(37500000, P_GPLL0, 16, 0, 0),
479 F(60000000, P_GPLL0, 10, 0, 0),
480 F(75000000, P_GPLL0, 8, 0, 0),
481 F(85710000, P_GPLL0, 7, 0, 0),
482 F(100000000, P_GPLL0, 6, 0, 0),
483 F(150000000, P_GPLL0, 4, 0, 0),
484 F(160000000, P_MMPLL0, 5, 0, 0),
485 F(200000000, P_MMPLL0, 4, 0, 0),
486 F(228570000, P_MMPLL0, 3.5, 0, 0),
487 F(300000000, P_GPLL0, 2, 0, 0),
488 F(320000000, P_MMPLL0, 2.5, 0, 0),
492 static struct clk_rcg2 mdp_clk_src = {
495 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
496 .freq_tbl = ftbl_mdss_mdp_clk,
497 .clkr.hw.init = &(struct clk_init_data){
498 .name = "mdp_clk_src",
499 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
501 .ops = &clk_rcg2_ops,
505 static struct clk_rcg2 gfx3d_clk_src = {
508 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "gfx3d_clk_src",
511 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
513 .ops = &clk_rcg2_ops,
517 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
518 F(75000000, P_GPLL0, 8, 0, 0),
519 F(133330000, P_GPLL0, 4.5, 0, 0),
520 F(200000000, P_GPLL0, 3, 0, 0),
521 F(228570000, P_MMPLL0, 3.5, 0, 0),
522 F(266670000, P_MMPLL0, 3, 0, 0),
523 F(320000000, P_MMPLL0, 2.5, 0, 0),
527 static struct clk_rcg2 jpeg0_clk_src = {
530 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
531 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
532 .clkr.hw.init = &(struct clk_init_data){
533 .name = "jpeg0_clk_src",
534 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
536 .ops = &clk_rcg2_ops,
540 static struct clk_rcg2 jpeg1_clk_src = {
543 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
544 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
545 .clkr.hw.init = &(struct clk_init_data){
546 .name = "jpeg1_clk_src",
547 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
549 .ops = &clk_rcg2_ops,
553 static struct clk_rcg2 jpeg2_clk_src = {
556 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
557 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "jpeg2_clk_src",
560 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
562 .ops = &clk_rcg2_ops,
566 static struct clk_rcg2 pclk0_clk_src = {
570 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
571 .clkr.hw.init = &(struct clk_init_data){
572 .name = "pclk0_clk_src",
573 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
575 .ops = &clk_pixel_ops,
576 .flags = CLK_SET_RATE_PARENT,
580 static struct clk_rcg2 pclk1_clk_src = {
584 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "pclk1_clk_src",
587 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
589 .ops = &clk_pixel_ops,
590 .flags = CLK_SET_RATE_PARENT,
594 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
595 F(50000000, P_GPLL0, 12, 0, 0),
596 F(100000000, P_GPLL0, 6, 0, 0),
597 F(133330000, P_GPLL0, 4.5, 0, 0),
598 F(200000000, P_MMPLL0, 4, 0, 0),
599 F(266670000, P_MMPLL0, 3, 0, 0),
600 F(465000000, P_MMPLL3, 2, 0, 0),
604 static struct clk_rcg2 vcodec0_clk_src = {
608 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
609 .freq_tbl = ftbl_venus0_vcodec0_clk,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "vcodec0_clk_src",
612 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
614 .ops = &clk_rcg2_ops,
618 static struct freq_tbl ftbl_avsync_vp_clk[] = {
619 F(150000000, P_GPLL0, 4, 0, 0),
620 F(320000000, P_MMPLL0, 2.5, 0, 0),
624 static struct clk_rcg2 vp_clk_src = {
627 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
628 .freq_tbl = ftbl_avsync_vp_clk,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "vp_clk_src",
631 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
633 .ops = &clk_rcg2_ops,
637 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
638 F(19200000, P_XO, 1, 0, 0),
642 static struct clk_rcg2 cci_clk_src = {
646 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
647 .freq_tbl = ftbl_camss_cci_cci_clk,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "cci_clk_src",
650 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
652 .ops = &clk_rcg2_ops,
656 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
657 F(10000, P_XO, 16, 1, 120),
658 F(24000, P_XO, 16, 1, 50),
659 F(6000000, P_GPLL0, 10, 1, 10),
660 F(12000000, P_GPLL0, 10, 1, 5),
661 F(13000000, P_GPLL0, 4, 13, 150),
662 F(24000000, P_GPLL0, 5, 1, 5),
666 static struct clk_rcg2 camss_gp0_clk_src = {
670 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
671 .freq_tbl = ftbl_camss_gp0_1_clk,
672 .clkr.hw.init = &(struct clk_init_data){
673 .name = "camss_gp0_clk_src",
674 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
676 .ops = &clk_rcg2_ops,
680 static struct clk_rcg2 camss_gp1_clk_src = {
684 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
685 .freq_tbl = ftbl_camss_gp0_1_clk,
686 .clkr.hw.init = &(struct clk_init_data){
687 .name = "camss_gp1_clk_src",
688 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
690 .ops = &clk_rcg2_ops,
694 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
695 F(4800000, P_XO, 4, 0, 0),
696 F(6000000, P_GPLL0, 10, 1, 10),
697 F(8000000, P_GPLL0, 15, 1, 5),
698 F(9600000, P_XO, 2, 0, 0),
699 F(16000000, P_MMPLL0, 10, 1, 5),
700 F(19200000, P_XO, 1, 0, 0),
701 F(24000000, P_GPLL0, 5, 1, 5),
702 F(32000000, P_MMPLL0, 5, 1, 5),
703 F(48000000, P_GPLL0, 12.5, 0, 0),
704 F(64000000, P_MMPLL0, 12.5, 0, 0),
708 static struct clk_rcg2 mclk0_clk_src = {
712 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
713 .freq_tbl = ftbl_camss_mclk0_3_clk,
714 .clkr.hw.init = &(struct clk_init_data){
715 .name = "mclk0_clk_src",
716 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
718 .ops = &clk_rcg2_ops,
722 static struct clk_rcg2 mclk1_clk_src = {
726 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
727 .freq_tbl = ftbl_camss_mclk0_3_clk,
728 .clkr.hw.init = &(struct clk_init_data){
729 .name = "mclk1_clk_src",
730 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
732 .ops = &clk_rcg2_ops,
736 static struct clk_rcg2 mclk2_clk_src = {
740 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
741 .freq_tbl = ftbl_camss_mclk0_3_clk,
742 .clkr.hw.init = &(struct clk_init_data){
743 .name = "mclk2_clk_src",
744 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
746 .ops = &clk_rcg2_ops,
750 static struct clk_rcg2 mclk3_clk_src = {
754 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
755 .freq_tbl = ftbl_camss_mclk0_3_clk,
756 .clkr.hw.init = &(struct clk_init_data){
757 .name = "mclk3_clk_src",
758 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
760 .ops = &clk_rcg2_ops,
764 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
765 F(100000000, P_GPLL0, 6, 0, 0),
766 F(200000000, P_MMPLL0, 4, 0, 0),
770 static struct clk_rcg2 csi0phytimer_clk_src = {
773 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
774 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "csi0phytimer_clk_src",
777 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
779 .ops = &clk_rcg2_ops,
783 static struct clk_rcg2 csi1phytimer_clk_src = {
786 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
787 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "csi1phytimer_clk_src",
790 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
792 .ops = &clk_rcg2_ops,
796 static struct clk_rcg2 csi2phytimer_clk_src = {
799 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
800 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi2phytimer_clk_src",
803 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
805 .ops = &clk_rcg2_ops,
809 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
810 F(133330000, P_GPLL0, 4.5, 0, 0),
811 F(266670000, P_MMPLL0, 3, 0, 0),
812 F(320000000, P_MMPLL0, 2.5, 0, 0),
813 F(372000000, P_MMPLL4, 2.5, 0, 0),
814 F(465000000, P_MMPLL4, 2, 0, 0),
815 F(600000000, P_GPLL0, 1, 0, 0),
819 static struct clk_rcg2 cpp_clk_src = {
822 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
823 .freq_tbl = ftbl_camss_vfe_cpp_clk,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "cpp_clk_src",
826 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
828 .ops = &clk_rcg2_ops,
832 static struct clk_rcg2 byte0_clk_src = {
835 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
836 .clkr.hw.init = &(struct clk_init_data){
837 .name = "byte0_clk_src",
838 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
840 .ops = &clk_byte2_ops,
841 .flags = CLK_SET_RATE_PARENT,
845 static struct clk_rcg2 byte1_clk_src = {
848 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
849 .clkr.hw.init = &(struct clk_init_data){
850 .name = "byte1_clk_src",
851 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
853 .ops = &clk_byte2_ops,
854 .flags = CLK_SET_RATE_PARENT,
858 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
859 F(19200000, P_XO, 1, 0, 0),
863 static struct clk_rcg2 edpaux_clk_src = {
866 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
867 .freq_tbl = ftbl_mdss_edpaux_clk,
868 .clkr.hw.init = &(struct clk_init_data){
869 .name = "edpaux_clk_src",
870 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
872 .ops = &clk_rcg2_ops,
876 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
877 F(135000000, P_EDPLINK, 2, 0, 0),
878 F(270000000, P_EDPLINK, 11, 0, 0),
882 static struct clk_rcg2 edplink_clk_src = {
885 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
886 .freq_tbl = ftbl_mdss_edplink_clk,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "edplink_clk_src",
889 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
891 .ops = &clk_rcg2_ops,
892 .flags = CLK_SET_RATE_PARENT,
896 static struct freq_tbl edp_pixel_freq_tbl[] = {
901 static struct clk_rcg2 edppixel_clk_src = {
905 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
906 .freq_tbl = edp_pixel_freq_tbl,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "edppixel_clk_src",
909 .parent_names = mmcc_xo_dsi_hdmi_edp,
911 .ops = &clk_edp_pixel_ops,
915 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
916 F(19200000, P_XO, 1, 0, 0),
920 static struct clk_rcg2 esc0_clk_src = {
923 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
924 .freq_tbl = ftbl_mdss_esc0_1_clk,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "esc0_clk_src",
927 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
929 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 esc1_clk_src = {
936 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
937 .freq_tbl = ftbl_mdss_esc0_1_clk,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "esc1_clk_src",
940 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
942 .ops = &clk_rcg2_ops,
946 static struct freq_tbl extpclk_freq_tbl[] = {
947 { .src = P_HDMIPLL },
951 static struct clk_rcg2 extpclk_clk_src = {
954 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
955 .freq_tbl = extpclk_freq_tbl,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "extpclk_clk_src",
958 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
960 .ops = &clk_byte_ops,
961 .flags = CLK_SET_RATE_PARENT,
965 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
966 F(19200000, P_XO, 1, 0, 0),
970 static struct clk_rcg2 hdmi_clk_src = {
973 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
974 .freq_tbl = ftbl_mdss_hdmi_clk,
975 .clkr.hw.init = &(struct clk_init_data){
976 .name = "hdmi_clk_src",
977 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
979 .ops = &clk_rcg2_ops,
983 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
984 F(19200000, P_XO, 1, 0, 0),
988 static struct clk_rcg2 vsync_clk_src = {
991 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
992 .freq_tbl = ftbl_mdss_vsync_clk,
993 .clkr.hw.init = &(struct clk_init_data){
994 .name = "vsync_clk_src",
995 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
997 .ops = &clk_rcg2_ops,
1001 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1002 F(50000000, P_GPLL0, 12, 0, 0),
1006 static struct clk_rcg2 rbcpr_clk_src = {
1009 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1010 .freq_tbl = ftbl_mmss_rbcpr_clk,
1011 .clkr.hw.init = &(struct clk_init_data){
1012 .name = "rbcpr_clk_src",
1013 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1015 .ops = &clk_rcg2_ops,
1019 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1020 F(19200000, P_XO, 1, 0, 0),
1024 static struct clk_rcg2 rbbmtimer_clk_src = {
1027 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1028 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1029 .clkr.hw.init = &(struct clk_init_data){
1030 .name = "rbbmtimer_clk_src",
1031 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1033 .ops = &clk_rcg2_ops,
1037 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1038 F(50000000, P_GPLL0, 12, 0, 0),
1039 F(100000000, P_GPLL0, 6, 0, 0),
1040 F(133330000, P_GPLL0, 4.5, 0, 0),
1041 F(200000000, P_MMPLL0, 4, 0, 0),
1042 F(266670000, P_MMPLL0, 3, 0, 0),
1043 F(465000000, P_MMPLL3, 2, 0, 0),
1047 static struct clk_rcg2 maple_clk_src = {
1050 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1051 .freq_tbl = ftbl_vpu_maple_clk,
1052 .clkr.hw.init = &(struct clk_init_data){
1053 .name = "maple_clk_src",
1054 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1056 .ops = &clk_rcg2_ops,
1060 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1061 F(50000000, P_GPLL0, 12, 0, 0),
1062 F(100000000, P_GPLL0, 6, 0, 0),
1063 F(200000000, P_MMPLL0, 4, 0, 0),
1064 F(320000000, P_MMPLL0, 2.5, 0, 0),
1065 F(400000000, P_MMPLL0, 2, 0, 0),
1069 static struct clk_rcg2 vdp_clk_src = {
1072 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1073 .freq_tbl = ftbl_vpu_vdp_clk,
1074 .clkr.hw.init = &(struct clk_init_data){
1075 .name = "vdp_clk_src",
1076 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1078 .ops = &clk_rcg2_ops,
1082 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1083 F(40000000, P_GPLL0, 15, 0, 0),
1084 F(80000000, P_MMPLL0, 10, 0, 0),
1088 static struct clk_rcg2 vpu_bus_clk_src = {
1091 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1092 .freq_tbl = ftbl_vpu_bus_clk,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "vpu_bus_clk_src",
1095 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1097 .ops = &clk_rcg2_ops,
1101 static struct clk_branch mmss_cxo_clk = {
1104 .enable_reg = 0x5104,
1105 .enable_mask = BIT(0),
1106 .hw.init = &(struct clk_init_data){
1107 .name = "mmss_cxo_clk",
1108 .parent_names = (const char *[]){ "xo" },
1110 .flags = CLK_SET_RATE_PARENT,
1111 .ops = &clk_branch2_ops,
1116 static struct clk_branch mmss_sleepclk_clk = {
1119 .enable_reg = 0x5100,
1120 .enable_mask = BIT(0),
1121 .hw.init = &(struct clk_init_data){
1122 .name = "mmss_sleepclk_clk",
1123 .parent_names = (const char *[]){
1127 .flags = CLK_SET_RATE_PARENT,
1128 .ops = &clk_branch2_ops,
1133 static struct clk_branch avsync_ahb_clk = {
1136 .enable_reg = 0x2414,
1137 .enable_mask = BIT(0),
1138 .hw.init = &(struct clk_init_data){
1139 .name = "avsync_ahb_clk",
1140 .parent_names = (const char *[]){
1144 .flags = CLK_SET_RATE_PARENT,
1145 .ops = &clk_branch2_ops,
1150 static struct clk_branch avsync_edppixel_clk = {
1153 .enable_reg = 0x2418,
1154 .enable_mask = BIT(0),
1155 .hw.init = &(struct clk_init_data){
1156 .name = "avsync_edppixel_clk",
1157 .parent_names = (const char *[]){
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1167 static struct clk_branch avsync_extpclk_clk = {
1170 .enable_reg = 0x2410,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "avsync_extpclk_clk",
1174 .parent_names = (const char *[]){
1178 .flags = CLK_SET_RATE_PARENT,
1179 .ops = &clk_branch2_ops,
1184 static struct clk_branch avsync_pclk0_clk = {
1187 .enable_reg = 0x241c,
1188 .enable_mask = BIT(0),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "avsync_pclk0_clk",
1191 .parent_names = (const char *[]){
1195 .flags = CLK_SET_RATE_PARENT,
1196 .ops = &clk_branch2_ops,
1201 static struct clk_branch avsync_pclk1_clk = {
1204 .enable_reg = 0x2420,
1205 .enable_mask = BIT(0),
1206 .hw.init = &(struct clk_init_data){
1207 .name = "avsync_pclk1_clk",
1208 .parent_names = (const char *[]){
1212 .flags = CLK_SET_RATE_PARENT,
1213 .ops = &clk_branch2_ops,
1218 static struct clk_branch avsync_vp_clk = {
1221 .enable_reg = 0x2404,
1222 .enable_mask = BIT(0),
1223 .hw.init = &(struct clk_init_data){
1224 .name = "avsync_vp_clk",
1225 .parent_names = (const char *[]){
1229 .flags = CLK_SET_RATE_PARENT,
1230 .ops = &clk_branch2_ops,
1235 static struct clk_branch camss_ahb_clk = {
1238 .enable_reg = 0x348c,
1239 .enable_mask = BIT(0),
1240 .hw.init = &(struct clk_init_data){
1241 .name = "camss_ahb_clk",
1242 .parent_names = (const char *[]){
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1252 static struct clk_branch camss_cci_cci_ahb_clk = {
1255 .enable_reg = 0x3348,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "camss_cci_cci_ahb_clk",
1259 .parent_names = (const char *[]){
1263 .ops = &clk_branch2_ops,
1268 static struct clk_branch camss_cci_cci_clk = {
1271 .enable_reg = 0x3344,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "camss_cci_cci_clk",
1275 .parent_names = (const char *[]){
1279 .flags = CLK_SET_RATE_PARENT,
1280 .ops = &clk_branch2_ops,
1285 static struct clk_branch camss_csi0_ahb_clk = {
1288 .enable_reg = 0x30bc,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "camss_csi0_ahb_clk",
1292 .parent_names = (const char *[]){
1296 .ops = &clk_branch2_ops,
1301 static struct clk_branch camss_csi0_clk = {
1304 .enable_reg = 0x30b4,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "camss_csi0_clk",
1308 .parent_names = (const char *[]){
1312 .flags = CLK_SET_RATE_PARENT,
1313 .ops = &clk_branch2_ops,
1318 static struct clk_branch camss_csi0phy_clk = {
1321 .enable_reg = 0x30c4,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "camss_csi0phy_clk",
1325 .parent_names = (const char *[]){
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch camss_csi0pix_clk = {
1338 .enable_reg = 0x30e4,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "camss_csi0pix_clk",
1342 .parent_names = (const char *[]){
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1352 static struct clk_branch camss_csi0rdi_clk = {
1355 .enable_reg = 0x30d4,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "camss_csi0rdi_clk",
1359 .parent_names = (const char *[]){
1363 .flags = CLK_SET_RATE_PARENT,
1364 .ops = &clk_branch2_ops,
1369 static struct clk_branch camss_csi1_ahb_clk = {
1372 .enable_reg = 0x3128,
1373 .enable_mask = BIT(0),
1374 .hw.init = &(struct clk_init_data){
1375 .name = "camss_csi1_ahb_clk",
1376 .parent_names = (const char *[]){
1380 .flags = CLK_SET_RATE_PARENT,
1381 .ops = &clk_branch2_ops,
1386 static struct clk_branch camss_csi1_clk = {
1389 .enable_reg = 0x3124,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "camss_csi1_clk",
1393 .parent_names = (const char *[]){
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1403 static struct clk_branch camss_csi1phy_clk = {
1406 .enable_reg = 0x3134,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "camss_csi1phy_clk",
1410 .parent_names = (const char *[]){
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch camss_csi1pix_clk = {
1423 .enable_reg = 0x3154,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "camss_csi1pix_clk",
1427 .parent_names = (const char *[]){
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1437 static struct clk_branch camss_csi1rdi_clk = {
1440 .enable_reg = 0x3144,
1441 .enable_mask = BIT(0),
1442 .hw.init = &(struct clk_init_data){
1443 .name = "camss_csi1rdi_clk",
1444 .parent_names = (const char *[]){
1448 .flags = CLK_SET_RATE_PARENT,
1449 .ops = &clk_branch2_ops,
1454 static struct clk_branch camss_csi2_ahb_clk = {
1457 .enable_reg = 0x3188,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "camss_csi2_ahb_clk",
1461 .parent_names = (const char *[]){
1465 .ops = &clk_branch2_ops,
1470 static struct clk_branch camss_csi2_clk = {
1473 .enable_reg = 0x3184,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "camss_csi2_clk",
1477 .parent_names = (const char *[]){
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1487 static struct clk_branch camss_csi2phy_clk = {
1490 .enable_reg = 0x3194,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data){
1493 .name = "camss_csi2phy_clk",
1494 .parent_names = (const char *[]){
1498 .flags = CLK_SET_RATE_PARENT,
1499 .ops = &clk_branch2_ops,
1504 static struct clk_branch camss_csi2pix_clk = {
1507 .enable_reg = 0x31b4,
1508 .enable_mask = BIT(0),
1509 .hw.init = &(struct clk_init_data){
1510 .name = "camss_csi2pix_clk",
1511 .parent_names = (const char *[]){
1515 .flags = CLK_SET_RATE_PARENT,
1516 .ops = &clk_branch2_ops,
1521 static struct clk_branch camss_csi2rdi_clk = {
1524 .enable_reg = 0x31a4,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "camss_csi2rdi_clk",
1528 .parent_names = (const char *[]){
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1538 static struct clk_branch camss_csi3_ahb_clk = {
1541 .enable_reg = 0x31e8,
1542 .enable_mask = BIT(0),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "camss_csi3_ahb_clk",
1545 .parent_names = (const char *[]){
1549 .ops = &clk_branch2_ops,
1554 static struct clk_branch camss_csi3_clk = {
1557 .enable_reg = 0x31e4,
1558 .enable_mask = BIT(0),
1559 .hw.init = &(struct clk_init_data){
1560 .name = "camss_csi3_clk",
1561 .parent_names = (const char *[]){
1565 .flags = CLK_SET_RATE_PARENT,
1566 .ops = &clk_branch2_ops,
1571 static struct clk_branch camss_csi3phy_clk = {
1574 .enable_reg = 0x31f4,
1575 .enable_mask = BIT(0),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "camss_csi3phy_clk",
1578 .parent_names = (const char *[]){
1582 .flags = CLK_SET_RATE_PARENT,
1583 .ops = &clk_branch2_ops,
1588 static struct clk_branch camss_csi3pix_clk = {
1591 .enable_reg = 0x3214,
1592 .enable_mask = BIT(0),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "camss_csi3pix_clk",
1595 .parent_names = (const char *[]){
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch camss_csi3rdi_clk = {
1608 .enable_reg = 0x3204,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "camss_csi3rdi_clk",
1612 .parent_names = (const char *[]){
1616 .flags = CLK_SET_RATE_PARENT,
1617 .ops = &clk_branch2_ops,
1622 static struct clk_branch camss_csi_vfe0_clk = {
1625 .enable_reg = 0x3704,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "camss_csi_vfe0_clk",
1629 .parent_names = (const char *[]){
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1639 static struct clk_branch camss_csi_vfe1_clk = {
1642 .enable_reg = 0x3714,
1643 .enable_mask = BIT(0),
1644 .hw.init = &(struct clk_init_data){
1645 .name = "camss_csi_vfe1_clk",
1646 .parent_names = (const char *[]){
1650 .flags = CLK_SET_RATE_PARENT,
1651 .ops = &clk_branch2_ops,
1656 static struct clk_branch camss_gp0_clk = {
1659 .enable_reg = 0x3444,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "camss_gp0_clk",
1663 .parent_names = (const char *[]){
1664 "camss_gp0_clk_src",
1667 .flags = CLK_SET_RATE_PARENT,
1668 .ops = &clk_branch2_ops,
1673 static struct clk_branch camss_gp1_clk = {
1676 .enable_reg = 0x3474,
1677 .enable_mask = BIT(0),
1678 .hw.init = &(struct clk_init_data){
1679 .name = "camss_gp1_clk",
1680 .parent_names = (const char *[]){
1681 "camss_gp1_clk_src",
1684 .flags = CLK_SET_RATE_PARENT,
1685 .ops = &clk_branch2_ops,
1690 static struct clk_branch camss_ispif_ahb_clk = {
1693 .enable_reg = 0x3224,
1694 .enable_mask = BIT(0),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "camss_ispif_ahb_clk",
1697 .parent_names = (const char *[]){
1701 .flags = CLK_SET_RATE_PARENT,
1702 .ops = &clk_branch2_ops,
1707 static struct clk_branch camss_jpeg_jpeg0_clk = {
1710 .enable_reg = 0x35a8,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "camss_jpeg_jpeg0_clk",
1714 .parent_names = (const char *[]){
1718 .flags = CLK_SET_RATE_PARENT,
1719 .ops = &clk_branch2_ops,
1724 static struct clk_branch camss_jpeg_jpeg1_clk = {
1727 .enable_reg = 0x35ac,
1728 .enable_mask = BIT(0),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "camss_jpeg_jpeg1_clk",
1731 .parent_names = (const char *[]){
1735 .flags = CLK_SET_RATE_PARENT,
1736 .ops = &clk_branch2_ops,
1741 static struct clk_branch camss_jpeg_jpeg2_clk = {
1744 .enable_reg = 0x35b0,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "camss_jpeg_jpeg2_clk",
1748 .parent_names = (const char *[]){
1752 .flags = CLK_SET_RATE_PARENT,
1753 .ops = &clk_branch2_ops,
1758 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1761 .enable_reg = 0x35b4,
1762 .enable_mask = BIT(0),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "camss_jpeg_jpeg_ahb_clk",
1765 .parent_names = (const char *[]){
1769 .ops = &clk_branch2_ops,
1774 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1777 .enable_reg = 0x35b8,
1778 .enable_mask = BIT(0),
1779 .hw.init = &(struct clk_init_data){
1780 .name = "camss_jpeg_jpeg_axi_clk",
1781 .parent_names = (const char *[]){
1785 .ops = &clk_branch2_ops,
1790 static struct clk_branch camss_mclk0_clk = {
1793 .enable_reg = 0x3384,
1794 .enable_mask = BIT(0),
1795 .hw.init = &(struct clk_init_data){
1796 .name = "camss_mclk0_clk",
1797 .parent_names = (const char *[]){
1801 .flags = CLK_SET_RATE_PARENT,
1802 .ops = &clk_branch2_ops,
1807 static struct clk_branch camss_mclk1_clk = {
1810 .enable_reg = 0x33b4,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "camss_mclk1_clk",
1814 .parent_names = (const char *[]){
1818 .flags = CLK_SET_RATE_PARENT,
1819 .ops = &clk_branch2_ops,
1824 static struct clk_branch camss_mclk2_clk = {
1827 .enable_reg = 0x33e4,
1828 .enable_mask = BIT(0),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "camss_mclk2_clk",
1831 .parent_names = (const char *[]){
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1841 static struct clk_branch camss_mclk3_clk = {
1844 .enable_reg = 0x3414,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "camss_mclk3_clk",
1848 .parent_names = (const char *[]){
1852 .flags = CLK_SET_RATE_PARENT,
1853 .ops = &clk_branch2_ops,
1858 static struct clk_branch camss_micro_ahb_clk = {
1861 .enable_reg = 0x3494,
1862 .enable_mask = BIT(0),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "camss_micro_ahb_clk",
1865 .parent_names = (const char *[]){
1869 .ops = &clk_branch2_ops,
1874 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1877 .enable_reg = 0x3024,
1878 .enable_mask = BIT(0),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "camss_phy0_csi0phytimer_clk",
1881 .parent_names = (const char *[]){
1882 "csi0phytimer_clk_src",
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1891 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1894 .enable_reg = 0x3054,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "camss_phy1_csi1phytimer_clk",
1898 .parent_names = (const char *[]){
1899 "csi1phytimer_clk_src",
1902 .flags = CLK_SET_RATE_PARENT,
1903 .ops = &clk_branch2_ops,
1908 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1911 .enable_reg = 0x3084,
1912 .enable_mask = BIT(0),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "camss_phy2_csi2phytimer_clk",
1915 .parent_names = (const char *[]){
1916 "csi2phytimer_clk_src",
1919 .flags = CLK_SET_RATE_PARENT,
1920 .ops = &clk_branch2_ops,
1925 static struct clk_branch camss_top_ahb_clk = {
1928 .enable_reg = 0x3484,
1929 .enable_mask = BIT(0),
1930 .hw.init = &(struct clk_init_data){
1931 .name = "camss_top_ahb_clk",
1932 .parent_names = (const char *[]){
1936 .flags = CLK_SET_RATE_PARENT,
1937 .ops = &clk_branch2_ops,
1942 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1945 .enable_reg = 0x36b4,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "camss_vfe_cpp_ahb_clk",
1949 .parent_names = (const char *[]){
1953 .flags = CLK_SET_RATE_PARENT,
1954 .ops = &clk_branch2_ops,
1959 static struct clk_branch camss_vfe_cpp_clk = {
1962 .enable_reg = 0x36b0,
1963 .enable_mask = BIT(0),
1964 .hw.init = &(struct clk_init_data){
1965 .name = "camss_vfe_cpp_clk",
1966 .parent_names = (const char *[]){
1970 .flags = CLK_SET_RATE_PARENT,
1971 .ops = &clk_branch2_ops,
1976 static struct clk_branch camss_vfe_vfe0_clk = {
1979 .enable_reg = 0x36a8,
1980 .enable_mask = BIT(0),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "camss_vfe_vfe0_clk",
1983 .parent_names = (const char *[]){
1987 .flags = CLK_SET_RATE_PARENT,
1988 .ops = &clk_branch2_ops,
1993 static struct clk_branch camss_vfe_vfe1_clk = {
1996 .enable_reg = 0x36ac,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "camss_vfe_vfe1_clk",
2000 .parent_names = (const char *[]){
2004 .flags = CLK_SET_RATE_PARENT,
2005 .ops = &clk_branch2_ops,
2010 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2013 .enable_reg = 0x36b8,
2014 .enable_mask = BIT(0),
2015 .hw.init = &(struct clk_init_data){
2016 .name = "camss_vfe_vfe_ahb_clk",
2017 .parent_names = (const char *[]){
2021 .flags = CLK_SET_RATE_PARENT,
2022 .ops = &clk_branch2_ops,
2027 static struct clk_branch camss_vfe_vfe_axi_clk = {
2030 .enable_reg = 0x36bc,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "camss_vfe_vfe_axi_clk",
2034 .parent_names = (const char *[]){
2038 .flags = CLK_SET_RATE_PARENT,
2039 .ops = &clk_branch2_ops,
2044 static struct clk_branch mdss_ahb_clk = {
2047 .enable_reg = 0x2308,
2048 .enable_mask = BIT(0),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "mdss_ahb_clk",
2051 .parent_names = (const char *[]){
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2061 static struct clk_branch mdss_axi_clk = {
2064 .enable_reg = 0x2310,
2065 .enable_mask = BIT(0),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "mdss_axi_clk",
2068 .parent_names = (const char *[]){
2072 .flags = CLK_SET_RATE_PARENT,
2073 .ops = &clk_branch2_ops,
2078 static struct clk_branch mdss_byte0_clk = {
2081 .enable_reg = 0x233c,
2082 .enable_mask = BIT(0),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "mdss_byte0_clk",
2085 .parent_names = (const char *[]){
2089 .flags = CLK_SET_RATE_PARENT,
2090 .ops = &clk_branch2_ops,
2095 static struct clk_branch mdss_byte1_clk = {
2098 .enable_reg = 0x2340,
2099 .enable_mask = BIT(0),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "mdss_byte1_clk",
2102 .parent_names = (const char *[]){
2106 .flags = CLK_SET_RATE_PARENT,
2107 .ops = &clk_branch2_ops,
2112 static struct clk_branch mdss_edpaux_clk = {
2115 .enable_reg = 0x2334,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "mdss_edpaux_clk",
2119 .parent_names = (const char *[]){
2123 .flags = CLK_SET_RATE_PARENT,
2124 .ops = &clk_branch2_ops,
2129 static struct clk_branch mdss_edplink_clk = {
2132 .enable_reg = 0x2330,
2133 .enable_mask = BIT(0),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "mdss_edplink_clk",
2136 .parent_names = (const char *[]){
2140 .flags = CLK_SET_RATE_PARENT,
2141 .ops = &clk_branch2_ops,
2146 static struct clk_branch mdss_edppixel_clk = {
2149 .enable_reg = 0x232c,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "mdss_edppixel_clk",
2153 .parent_names = (const char *[]){
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2163 static struct clk_branch mdss_esc0_clk = {
2166 .enable_reg = 0x2344,
2167 .enable_mask = BIT(0),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "mdss_esc0_clk",
2170 .parent_names = (const char *[]){
2174 .flags = CLK_SET_RATE_PARENT,
2175 .ops = &clk_branch2_ops,
2180 static struct clk_branch mdss_esc1_clk = {
2183 .enable_reg = 0x2348,
2184 .enable_mask = BIT(0),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "mdss_esc1_clk",
2187 .parent_names = (const char *[]){
2191 .flags = CLK_SET_RATE_PARENT,
2192 .ops = &clk_branch2_ops,
2197 static struct clk_branch mdss_extpclk_clk = {
2200 .enable_reg = 0x2324,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "mdss_extpclk_clk",
2204 .parent_names = (const char *[]){
2208 .flags = CLK_SET_RATE_PARENT,
2209 .ops = &clk_branch2_ops,
2214 static struct clk_branch mdss_hdmi_ahb_clk = {
2217 .enable_reg = 0x230c,
2218 .enable_mask = BIT(0),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "mdss_hdmi_ahb_clk",
2221 .parent_names = (const char *[]){
2225 .flags = CLK_SET_RATE_PARENT,
2226 .ops = &clk_branch2_ops,
2231 static struct clk_branch mdss_hdmi_clk = {
2234 .enable_reg = 0x2338,
2235 .enable_mask = BIT(0),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "mdss_hdmi_clk",
2238 .parent_names = (const char *[]){
2242 .flags = CLK_SET_RATE_PARENT,
2243 .ops = &clk_branch2_ops,
2248 static struct clk_branch mdss_mdp_clk = {
2251 .enable_reg = 0x231c,
2252 .enable_mask = BIT(0),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "mdss_mdp_clk",
2255 .parent_names = (const char *[]){
2259 .flags = CLK_SET_RATE_PARENT,
2260 .ops = &clk_branch2_ops,
2265 static struct clk_branch mdss_mdp_lut_clk = {
2268 .enable_reg = 0x2320,
2269 .enable_mask = BIT(0),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "mdss_mdp_lut_clk",
2272 .parent_names = (const char *[]){
2276 .flags = CLK_SET_RATE_PARENT,
2277 .ops = &clk_branch2_ops,
2282 static struct clk_branch mdss_pclk0_clk = {
2285 .enable_reg = 0x2314,
2286 .enable_mask = BIT(0),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "mdss_pclk0_clk",
2289 .parent_names = (const char *[]){
2293 .flags = CLK_SET_RATE_PARENT,
2294 .ops = &clk_branch2_ops,
2299 static struct clk_branch mdss_pclk1_clk = {
2302 .enable_reg = 0x2318,
2303 .enable_mask = BIT(0),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "mdss_pclk1_clk",
2306 .parent_names = (const char *[]){
2310 .flags = CLK_SET_RATE_PARENT,
2311 .ops = &clk_branch2_ops,
2316 static struct clk_branch mdss_vsync_clk = {
2319 .enable_reg = 0x2328,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "mdss_vsync_clk",
2323 .parent_names = (const char *[]){
2327 .flags = CLK_SET_RATE_PARENT,
2328 .ops = &clk_branch2_ops,
2333 static struct clk_branch mmss_rbcpr_ahb_clk = {
2336 .enable_reg = 0x4088,
2337 .enable_mask = BIT(0),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "mmss_rbcpr_ahb_clk",
2340 .parent_names = (const char *[]){
2344 .flags = CLK_SET_RATE_PARENT,
2345 .ops = &clk_branch2_ops,
2350 static struct clk_branch mmss_rbcpr_clk = {
2353 .enable_reg = 0x4084,
2354 .enable_mask = BIT(0),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "mmss_rbcpr_clk",
2357 .parent_names = (const char *[]){
2361 .flags = CLK_SET_RATE_PARENT,
2362 .ops = &clk_branch2_ops,
2367 static struct clk_branch mmss_spdm_ahb_clk = {
2370 .enable_reg = 0x0230,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "mmss_spdm_ahb_clk",
2374 .parent_names = (const char *[]){
2375 "mmss_spdm_ahb_div_clk",
2378 .flags = CLK_SET_RATE_PARENT,
2379 .ops = &clk_branch2_ops,
2384 static struct clk_branch mmss_spdm_axi_clk = {
2387 .enable_reg = 0x0210,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "mmss_spdm_axi_clk",
2391 .parent_names = (const char *[]){
2392 "mmss_spdm_axi_div_clk",
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2401 static struct clk_branch mmss_spdm_csi0_clk = {
2404 .enable_reg = 0x023c,
2405 .enable_mask = BIT(0),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "mmss_spdm_csi0_clk",
2408 .parent_names = (const char *[]){
2409 "mmss_spdm_csi0_div_clk",
2412 .flags = CLK_SET_RATE_PARENT,
2413 .ops = &clk_branch2_ops,
2418 static struct clk_branch mmss_spdm_gfx3d_clk = {
2421 .enable_reg = 0x022c,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "mmss_spdm_gfx3d_clk",
2425 .parent_names = (const char *[]){
2426 "mmss_spdm_gfx3d_div_clk",
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2435 static struct clk_branch mmss_spdm_jpeg0_clk = {
2438 .enable_reg = 0x0204,
2439 .enable_mask = BIT(0),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "mmss_spdm_jpeg0_clk",
2442 .parent_names = (const char *[]){
2443 "mmss_spdm_jpeg0_div_clk",
2446 .flags = CLK_SET_RATE_PARENT,
2447 .ops = &clk_branch2_ops,
2452 static struct clk_branch mmss_spdm_jpeg1_clk = {
2455 .enable_reg = 0x0208,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "mmss_spdm_jpeg1_clk",
2459 .parent_names = (const char *[]){
2460 "mmss_spdm_jpeg1_div_clk",
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2469 static struct clk_branch mmss_spdm_jpeg2_clk = {
2472 .enable_reg = 0x0224,
2473 .enable_mask = BIT(0),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "mmss_spdm_jpeg2_clk",
2476 .parent_names = (const char *[]){
2477 "mmss_spdm_jpeg2_div_clk",
2480 .flags = CLK_SET_RATE_PARENT,
2481 .ops = &clk_branch2_ops,
2486 static struct clk_branch mmss_spdm_mdp_clk = {
2489 .enable_reg = 0x020c,
2490 .enable_mask = BIT(0),
2491 .hw.init = &(struct clk_init_data){
2492 .name = "mmss_spdm_mdp_clk",
2493 .parent_names = (const char *[]){
2494 "mmss_spdm_mdp_div_clk",
2497 .flags = CLK_SET_RATE_PARENT,
2498 .ops = &clk_branch2_ops,
2503 static struct clk_branch mmss_spdm_pclk0_clk = {
2506 .enable_reg = 0x0234,
2507 .enable_mask = BIT(0),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "mmss_spdm_pclk0_clk",
2510 .parent_names = (const char *[]){
2511 "mmss_spdm_pclk0_div_clk",
2514 .flags = CLK_SET_RATE_PARENT,
2515 .ops = &clk_branch2_ops,
2520 static struct clk_branch mmss_spdm_pclk1_clk = {
2523 .enable_reg = 0x0228,
2524 .enable_mask = BIT(0),
2525 .hw.init = &(struct clk_init_data){
2526 .name = "mmss_spdm_pclk1_clk",
2527 .parent_names = (const char *[]){
2528 "mmss_spdm_pclk1_div_clk",
2531 .flags = CLK_SET_RATE_PARENT,
2532 .ops = &clk_branch2_ops,
2537 static struct clk_branch mmss_spdm_vcodec0_clk = {
2540 .enable_reg = 0x0214,
2541 .enable_mask = BIT(0),
2542 .hw.init = &(struct clk_init_data){
2543 .name = "mmss_spdm_vcodec0_clk",
2544 .parent_names = (const char *[]){
2545 "mmss_spdm_vcodec0_div_clk",
2548 .flags = CLK_SET_RATE_PARENT,
2549 .ops = &clk_branch2_ops,
2554 static struct clk_branch mmss_spdm_vfe0_clk = {
2557 .enable_reg = 0x0218,
2558 .enable_mask = BIT(0),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "mmss_spdm_vfe0_clk",
2561 .parent_names = (const char *[]){
2562 "mmss_spdm_vfe0_div_clk",
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_branch2_ops,
2571 static struct clk_branch mmss_spdm_vfe1_clk = {
2574 .enable_reg = 0x021c,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "mmss_spdm_vfe1_clk",
2578 .parent_names = (const char *[]){
2579 "mmss_spdm_vfe1_div_clk",
2582 .flags = CLK_SET_RATE_PARENT,
2583 .ops = &clk_branch2_ops,
2588 static struct clk_branch mmss_spdm_rm_axi_clk = {
2591 .enable_reg = 0x0304,
2592 .enable_mask = BIT(0),
2593 .hw.init = &(struct clk_init_data){
2594 .name = "mmss_spdm_rm_axi_clk",
2595 .parent_names = (const char *[]){
2599 .flags = CLK_SET_RATE_PARENT,
2600 .ops = &clk_branch2_ops,
2605 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2608 .enable_reg = 0x0308,
2609 .enable_mask = BIT(0),
2610 .hw.init = &(struct clk_init_data){
2611 .name = "mmss_spdm_rm_ocmemnoc_clk",
2612 .parent_names = (const char *[]){
2616 .flags = CLK_SET_RATE_PARENT,
2617 .ops = &clk_branch2_ops,
2623 static struct clk_branch mmss_misc_ahb_clk = {
2626 .enable_reg = 0x502c,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data){
2629 .name = "mmss_misc_ahb_clk",
2630 .parent_names = (const char *[]){
2634 .flags = CLK_SET_RATE_PARENT,
2635 .ops = &clk_branch2_ops,
2640 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2643 .enable_reg = 0x5024,
2644 .enable_mask = BIT(0),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "mmss_mmssnoc_ahb_clk",
2647 .parent_names = (const char *[]){
2651 .ops = &clk_branch2_ops,
2652 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2657 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2660 .enable_reg = 0x5028,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "mmss_mmssnoc_bto_ahb_clk",
2664 .parent_names = (const char *[]){
2668 .ops = &clk_branch2_ops,
2669 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2674 static struct clk_branch mmss_mmssnoc_axi_clk = {
2677 .enable_reg = 0x506c,
2678 .enable_mask = BIT(0),
2679 .hw.init = &(struct clk_init_data){
2680 .name = "mmss_mmssnoc_axi_clk",
2681 .parent_names = (const char *[]){
2685 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2686 .ops = &clk_branch2_ops,
2691 static struct clk_branch mmss_s0_axi_clk = {
2694 .enable_reg = 0x5064,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "mmss_s0_axi_clk",
2698 .parent_names = (const char *[]){
2702 .ops = &clk_branch2_ops,
2703 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2708 static struct clk_branch ocmemcx_ahb_clk = {
2711 .enable_reg = 0x405c,
2712 .enable_mask = BIT(0),
2713 .hw.init = &(struct clk_init_data){
2714 .name = "ocmemcx_ahb_clk",
2715 .parent_names = (const char *[]){
2719 .flags = CLK_SET_RATE_PARENT,
2720 .ops = &clk_branch2_ops,
2725 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2728 .enable_reg = 0x4058,
2729 .enable_mask = BIT(0),
2730 .hw.init = &(struct clk_init_data){
2731 .name = "ocmemcx_ocmemnoc_clk",
2732 .parent_names = (const char *[]){
2736 .flags = CLK_SET_RATE_PARENT,
2737 .ops = &clk_branch2_ops,
2742 static struct clk_branch oxili_ocmemgx_clk = {
2745 .enable_reg = 0x402c,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(struct clk_init_data){
2748 .name = "oxili_ocmemgx_clk",
2749 .parent_names = (const char *[]){
2753 .flags = CLK_SET_RATE_PARENT,
2754 .ops = &clk_branch2_ops,
2759 static struct clk_branch oxili_gfx3d_clk = {
2762 .enable_reg = 0x4028,
2763 .enable_mask = BIT(0),
2764 .hw.init = &(struct clk_init_data){
2765 .name = "oxili_gfx3d_clk",
2766 .parent_names = (const char *[]){
2770 .flags = CLK_SET_RATE_PARENT,
2771 .ops = &clk_branch2_ops,
2776 static struct clk_branch oxili_rbbmtimer_clk = {
2779 .enable_reg = 0x40b0,
2780 .enable_mask = BIT(0),
2781 .hw.init = &(struct clk_init_data){
2782 .name = "oxili_rbbmtimer_clk",
2783 .parent_names = (const char *[]){
2784 "rbbmtimer_clk_src",
2787 .flags = CLK_SET_RATE_PARENT,
2788 .ops = &clk_branch2_ops,
2793 static struct clk_branch oxilicx_ahb_clk = {
2796 .enable_reg = 0x403c,
2797 .enable_mask = BIT(0),
2798 .hw.init = &(struct clk_init_data){
2799 .name = "oxilicx_ahb_clk",
2800 .parent_names = (const char *[]){
2804 .flags = CLK_SET_RATE_PARENT,
2805 .ops = &clk_branch2_ops,
2810 static struct clk_branch venus0_ahb_clk = {
2813 .enable_reg = 0x1030,
2814 .enable_mask = BIT(0),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "venus0_ahb_clk",
2817 .parent_names = (const char *[]){
2821 .flags = CLK_SET_RATE_PARENT,
2822 .ops = &clk_branch2_ops,
2827 static struct clk_branch venus0_axi_clk = {
2830 .enable_reg = 0x1034,
2831 .enable_mask = BIT(0),
2832 .hw.init = &(struct clk_init_data){
2833 .name = "venus0_axi_clk",
2834 .parent_names = (const char *[]){
2838 .flags = CLK_SET_RATE_PARENT,
2839 .ops = &clk_branch2_ops,
2844 static struct clk_branch venus0_core0_vcodec_clk = {
2847 .enable_reg = 0x1048,
2848 .enable_mask = BIT(0),
2849 .hw.init = &(struct clk_init_data){
2850 .name = "venus0_core0_vcodec_clk",
2851 .parent_names = (const char *[]){
2855 .flags = CLK_SET_RATE_PARENT,
2856 .ops = &clk_branch2_ops,
2861 static struct clk_branch venus0_core1_vcodec_clk = {
2864 .enable_reg = 0x104c,
2865 .enable_mask = BIT(0),
2866 .hw.init = &(struct clk_init_data){
2867 .name = "venus0_core1_vcodec_clk",
2868 .parent_names = (const char *[]){
2872 .flags = CLK_SET_RATE_PARENT,
2873 .ops = &clk_branch2_ops,
2878 static struct clk_branch venus0_ocmemnoc_clk = {
2881 .enable_reg = 0x1038,
2882 .enable_mask = BIT(0),
2883 .hw.init = &(struct clk_init_data){
2884 .name = "venus0_ocmemnoc_clk",
2885 .parent_names = (const char *[]){
2889 .flags = CLK_SET_RATE_PARENT,
2890 .ops = &clk_branch2_ops,
2895 static struct clk_branch venus0_vcodec0_clk = {
2898 .enable_reg = 0x1028,
2899 .enable_mask = BIT(0),
2900 .hw.init = &(struct clk_init_data){
2901 .name = "venus0_vcodec0_clk",
2902 .parent_names = (const char *[]){
2906 .flags = CLK_SET_RATE_PARENT,
2907 .ops = &clk_branch2_ops,
2912 static struct clk_branch vpu_ahb_clk = {
2915 .enable_reg = 0x1430,
2916 .enable_mask = BIT(0),
2917 .hw.init = &(struct clk_init_data){
2918 .name = "vpu_ahb_clk",
2919 .parent_names = (const char *[]){
2923 .flags = CLK_SET_RATE_PARENT,
2924 .ops = &clk_branch2_ops,
2929 static struct clk_branch vpu_axi_clk = {
2932 .enable_reg = 0x143c,
2933 .enable_mask = BIT(0),
2934 .hw.init = &(struct clk_init_data){
2935 .name = "vpu_axi_clk",
2936 .parent_names = (const char *[]){
2940 .flags = CLK_SET_RATE_PARENT,
2941 .ops = &clk_branch2_ops,
2946 static struct clk_branch vpu_bus_clk = {
2949 .enable_reg = 0x1440,
2950 .enable_mask = BIT(0),
2951 .hw.init = &(struct clk_init_data){
2952 .name = "vpu_bus_clk",
2953 .parent_names = (const char *[]){
2957 .flags = CLK_SET_RATE_PARENT,
2958 .ops = &clk_branch2_ops,
2963 static struct clk_branch vpu_cxo_clk = {
2966 .enable_reg = 0x1434,
2967 .enable_mask = BIT(0),
2968 .hw.init = &(struct clk_init_data){
2969 .name = "vpu_cxo_clk",
2970 .parent_names = (const char *[]){ "xo" },
2972 .flags = CLK_SET_RATE_PARENT,
2973 .ops = &clk_branch2_ops,
2978 static struct clk_branch vpu_maple_clk = {
2981 .enable_reg = 0x142c,
2982 .enable_mask = BIT(0),
2983 .hw.init = &(struct clk_init_data){
2984 .name = "vpu_maple_clk",
2985 .parent_names = (const char *[]){
2989 .flags = CLK_SET_RATE_PARENT,
2990 .ops = &clk_branch2_ops,
2995 static struct clk_branch vpu_sleep_clk = {
2998 .enable_reg = 0x1438,
2999 .enable_mask = BIT(0),
3000 .hw.init = &(struct clk_init_data){
3001 .name = "vpu_sleep_clk",
3002 .parent_names = (const char *[]){
3006 .flags = CLK_SET_RATE_PARENT,
3007 .ops = &clk_branch2_ops,
3012 static struct clk_branch vpu_vdp_clk = {
3015 .enable_reg = 0x1428,
3016 .enable_mask = BIT(0),
3017 .hw.init = &(struct clk_init_data){
3018 .name = "vpu_vdp_clk",
3019 .parent_names = (const char *[]){
3023 .flags = CLK_SET_RATE_PARENT,
3024 .ops = &clk_branch2_ops,
3029 static const struct pll_config mmpll1_config = {
3034 .vco_mask = 0x3 << 20,
3036 .pre_div_mask = 0x7 << 12,
3037 .post_div_val = 0x0,
3038 .post_div_mask = 0x3 << 8,
3039 .mn_ena_mask = BIT(24),
3040 .main_output_mask = BIT(0),
3043 static const struct pll_config mmpll3_config = {
3048 .vco_mask = 0x3 << 20,
3050 .pre_div_mask = 0x7 << 12,
3051 .post_div_val = 0x0,
3052 .post_div_mask = 0x3 << 8,
3053 .mn_ena_mask = BIT(24),
3054 .main_output_mask = BIT(0),
3055 .aux_output_mask = BIT(1),
3058 static struct gdsc venus0_gdsc = {
3063 .pwrsts = PWRSTS_OFF_ON,
3066 static struct gdsc venus0_core0_gdsc = {
3069 .name = "venus0_core0",
3071 .pwrsts = PWRSTS_OFF_ON,
3074 static struct gdsc venus0_core1_gdsc = {
3077 .name = "venus0_core1",
3079 .pwrsts = PWRSTS_OFF_ON,
3082 static struct gdsc mdss_gdsc = {
3084 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3089 .pwrsts = PWRSTS_OFF_ON,
3092 static struct gdsc camss_jpeg_gdsc = {
3095 .name = "camss_jpeg",
3097 .pwrsts = PWRSTS_OFF_ON,
3100 static struct gdsc camss_vfe_gdsc = {
3102 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3105 .name = "camss_vfe",
3107 .pwrsts = PWRSTS_OFF_ON,
3110 static struct gdsc oxili_gdsc = {
3112 .cxcs = (unsigned int []){ 0x4028 },
3117 .pwrsts = PWRSTS_OFF_ON,
3120 static struct gdsc oxilicx_gdsc = {
3125 .pwrsts = PWRSTS_OFF_ON,
3128 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3129 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3130 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3131 [MMPLL0] = &mmpll0.clkr,
3132 [MMPLL0_VOTE] = &mmpll0_vote,
3133 [MMPLL1] = &mmpll1.clkr,
3134 [MMPLL1_VOTE] = &mmpll1_vote,
3135 [MMPLL2] = &mmpll2.clkr,
3136 [MMPLL3] = &mmpll3.clkr,
3137 [MMPLL4] = &mmpll4.clkr,
3138 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3139 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3140 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3141 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3142 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3143 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3144 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3145 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3146 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3147 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3148 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3149 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3150 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3151 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3152 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3153 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3154 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3155 [VP_CLK_SRC] = &vp_clk_src.clkr,
3156 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3157 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3158 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3159 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3160 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3161 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3162 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3163 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3164 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3165 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3166 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3167 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3168 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3169 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3170 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3171 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3172 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3173 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3174 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3175 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3176 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3177 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3178 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3179 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3180 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3181 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3182 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3183 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3184 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3185 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3186 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3187 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3188 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3189 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3190 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3191 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3192 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3193 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3194 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3195 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3196 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3197 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3198 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3199 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3200 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3201 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3202 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3203 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3204 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3205 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3206 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3207 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3208 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3209 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3210 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3211 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3212 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3213 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3214 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3215 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3216 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3217 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3218 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3219 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3220 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3221 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3222 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3223 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3224 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3225 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3226 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3227 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3228 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3229 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3230 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3231 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3232 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3233 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3234 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3235 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3236 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3237 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3238 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3239 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3240 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3241 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3242 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3243 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3244 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3245 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3246 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3247 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3248 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3249 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3250 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3251 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3252 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3253 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3254 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3255 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3256 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3257 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3258 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3259 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3260 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3261 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3262 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3263 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3264 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3265 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3266 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3267 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3268 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3269 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3270 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3271 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3272 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3273 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3274 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3275 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3276 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3277 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3278 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3279 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3280 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3281 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3282 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3283 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3284 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3285 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3286 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3287 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3288 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3289 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3290 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3291 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3292 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3293 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3296 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3297 [MMSS_SPDM_RESET] = { 0x0200 },
3298 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3299 [VENUS0_RESET] = { 0x1020 },
3300 [VPU_RESET] = { 0x1400 },
3301 [MDSS_RESET] = { 0x2300 },
3302 [AVSYNC_RESET] = { 0x2400 },
3303 [CAMSS_PHY0_RESET] = { 0x3020 },
3304 [CAMSS_PHY1_RESET] = { 0x3050 },
3305 [CAMSS_PHY2_RESET] = { 0x3080 },
3306 [CAMSS_CSI0_RESET] = { 0x30b0 },
3307 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3308 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3309 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3310 [CAMSS_CSI1_RESET] = { 0x3120 },
3311 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3312 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3313 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3314 [CAMSS_CSI2_RESET] = { 0x3180 },
3315 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3316 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3317 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3318 [CAMSS_CSI3_RESET] = { 0x31e0 },
3319 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3320 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3321 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3322 [CAMSS_ISPIF_RESET] = { 0x3220 },
3323 [CAMSS_CCI_RESET] = { 0x3340 },
3324 [CAMSS_MCLK0_RESET] = { 0x3380 },
3325 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3326 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3327 [CAMSS_MCLK3_RESET] = { 0x3410 },
3328 [CAMSS_GP0_RESET] = { 0x3440 },
3329 [CAMSS_GP1_RESET] = { 0x3470 },
3330 [CAMSS_TOP_RESET] = { 0x3480 },
3331 [CAMSS_AHB_RESET] = { 0x3488 },
3332 [CAMSS_MICRO_RESET] = { 0x3490 },
3333 [CAMSS_JPEG_RESET] = { 0x35a0 },
3334 [CAMSS_VFE_RESET] = { 0x36a0 },
3335 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3336 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3337 [OXILI_RESET] = { 0x4020 },
3338 [OXILICX_RESET] = { 0x4030 },
3339 [OCMEMCX_RESET] = { 0x4050 },
3340 [MMSS_RBCRP_RESET] = { 0x4080 },
3341 [MMSSNOCAHB_RESET] = { 0x5020 },
3342 [MMSSNOCAXI_RESET] = { 0x5060 },
3345 static struct gdsc *mmcc_apq8084_gdscs[] = {
3346 [VENUS0_GDSC] = &venus0_gdsc,
3347 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3348 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3349 [MDSS_GDSC] = &mdss_gdsc,
3350 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3351 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3352 [OXILI_GDSC] = &oxili_gdsc,
3353 [OXILICX_GDSC] = &oxilicx_gdsc,
3356 static const struct regmap_config mmcc_apq8084_regmap_config = {
3360 .max_register = 0x5104,
3364 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3365 .config = &mmcc_apq8084_regmap_config,
3366 .clks = mmcc_apq8084_clocks,
3367 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3368 .resets = mmcc_apq8084_resets,
3369 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3370 .gdscs = mmcc_apq8084_gdscs,
3371 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
3374 static const struct of_device_id mmcc_apq8084_match_table[] = {
3375 { .compatible = "qcom,mmcc-apq8084" },
3378 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3380 static int mmcc_apq8084_probe(struct platform_device *pdev)
3383 struct regmap *regmap;
3385 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3389 regmap = dev_get_regmap(&pdev->dev, NULL);
3390 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3391 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3396 static struct platform_driver mmcc_apq8084_driver = {
3397 .probe = mmcc_apq8084_probe,
3399 .name = "mmcc-apq8084",
3400 .of_match_table = mmcc_apq8084_match_table,
3403 module_platform_driver(mmcc_apq8084_driver);
3405 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3406 MODULE_LICENSE("GPL v2");
3407 MODULE_ALIAS("platform:mmcc-apq8084");