1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
12 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
13 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
16 #include "clk-regmap.h"
19 #include "clk-branch.h"
42 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
49 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
56 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
65 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
74 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
82 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
90 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
98 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
106 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
115 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
124 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
133 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
142 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
147 { P_DSI0PLL_BYTE, 1 },
148 { P_DSI1PLL_BYTE, 2 }
151 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
160 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
168 static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
176 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
185 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
194 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
204 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
214 static struct clk_pll mmpll0 = {
218 .config_reg = 0x0014,
220 .status_reg = 0x001c,
222 .clkr.hw.init = &(struct clk_init_data){
224 .parent_names = (const char *[]){ "xo" },
230 static struct clk_regmap mmpll0_vote = {
231 .enable_reg = 0x0100,
232 .enable_mask = BIT(0),
233 .hw.init = &(struct clk_init_data){
234 .name = "mmpll0_vote",
235 .parent_names = (const char *[]){ "mmpll0" },
237 .ops = &clk_pll_vote_ops,
241 static struct clk_pll mmpll1 = {
245 .config_reg = 0x0050,
247 .status_reg = 0x005c,
249 .clkr.hw.init = &(struct clk_init_data){
251 .parent_names = (const char *[]){ "xo" },
257 static struct clk_regmap mmpll1_vote = {
258 .enable_reg = 0x0100,
259 .enable_mask = BIT(1),
260 .hw.init = &(struct clk_init_data){
261 .name = "mmpll1_vote",
262 .parent_names = (const char *[]){ "mmpll1" },
264 .ops = &clk_pll_vote_ops,
268 static struct clk_pll mmpll2 = {
272 .config_reg = 0x4110,
274 .status_reg = 0x411c,
275 .clkr.hw.init = &(struct clk_init_data){
277 .parent_names = (const char *[]){ "xo" },
283 static struct clk_pll mmpll3 = {
287 .config_reg = 0x0090,
289 .status_reg = 0x009c,
291 .clkr.hw.init = &(struct clk_init_data){
293 .parent_names = (const char *[]){ "xo" },
299 static struct clk_pll mmpll4 = {
303 .config_reg = 0x00b0,
305 .status_reg = 0x00bc,
306 .clkr.hw.init = &(struct clk_init_data){
308 .parent_names = (const char *[]){ "xo" },
314 static struct clk_rcg2 mmss_ahb_clk_src = {
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .clkr.hw.init = &(struct clk_init_data){
319 .name = "mmss_ahb_clk_src",
320 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
322 .ops = &clk_rcg2_ops,
326 static struct freq_tbl ftbl_mmss_axi_clk[] = {
327 F(19200000, P_XO, 1, 0, 0),
328 F(37500000, P_GPLL0, 16, 0, 0),
329 F(50000000, P_GPLL0, 12, 0, 0),
330 F(75000000, P_GPLL0, 8, 0, 0),
331 F(100000000, P_GPLL0, 6, 0, 0),
332 F(150000000, P_GPLL0, 4, 0, 0),
333 F(333430000, P_MMPLL1, 3.5, 0, 0),
334 F(400000000, P_MMPLL0, 2, 0, 0),
335 F(466800000, P_MMPLL1, 2.5, 0, 0),
339 static struct clk_rcg2 mmss_axi_clk_src = {
342 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
343 .freq_tbl = ftbl_mmss_axi_clk,
344 .clkr.hw.init = &(struct clk_init_data){
345 .name = "mmss_axi_clk_src",
346 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
348 .ops = &clk_rcg2_ops,
352 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
353 F(19200000, P_XO, 1, 0, 0),
354 F(37500000, P_GPLL0, 16, 0, 0),
355 F(50000000, P_GPLL0, 12, 0, 0),
356 F(75000000, P_GPLL0, 8, 0, 0),
357 F(109090000, P_GPLL0, 5.5, 0, 0),
358 F(150000000, P_GPLL0, 4, 0, 0),
359 F(228570000, P_MMPLL0, 3.5, 0, 0),
360 F(320000000, P_MMPLL0, 2.5, 0, 0),
364 static struct clk_rcg2 ocmemnoc_clk_src = {
367 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
368 .freq_tbl = ftbl_ocmemnoc_clk,
369 .clkr.hw.init = &(struct clk_init_data){
370 .name = "ocmemnoc_clk_src",
371 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
373 .ops = &clk_rcg2_ops,
377 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
378 F(100000000, P_GPLL0, 6, 0, 0),
379 F(200000000, P_MMPLL0, 4, 0, 0),
383 static struct clk_rcg2 csi0_clk_src = {
386 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
387 .freq_tbl = ftbl_camss_csi0_3_clk,
388 .clkr.hw.init = &(struct clk_init_data){
389 .name = "csi0_clk_src",
390 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
392 .ops = &clk_rcg2_ops,
396 static struct clk_rcg2 csi1_clk_src = {
399 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
400 .freq_tbl = ftbl_camss_csi0_3_clk,
401 .clkr.hw.init = &(struct clk_init_data){
402 .name = "csi1_clk_src",
403 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
405 .ops = &clk_rcg2_ops,
409 static struct clk_rcg2 csi2_clk_src = {
412 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
413 .freq_tbl = ftbl_camss_csi0_3_clk,
414 .clkr.hw.init = &(struct clk_init_data){
415 .name = "csi2_clk_src",
416 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
418 .ops = &clk_rcg2_ops,
422 static struct clk_rcg2 csi3_clk_src = {
425 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
426 .freq_tbl = ftbl_camss_csi0_3_clk,
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "csi3_clk_src",
429 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
431 .ops = &clk_rcg2_ops,
435 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
436 F(37500000, P_GPLL0, 16, 0, 0),
437 F(50000000, P_GPLL0, 12, 0, 0),
438 F(60000000, P_GPLL0, 10, 0, 0),
439 F(80000000, P_GPLL0, 7.5, 0, 0),
440 F(100000000, P_GPLL0, 6, 0, 0),
441 F(109090000, P_GPLL0, 5.5, 0, 0),
442 F(133330000, P_GPLL0, 4.5, 0, 0),
443 F(200000000, P_GPLL0, 3, 0, 0),
444 F(228570000, P_MMPLL0, 3.5, 0, 0),
445 F(266670000, P_MMPLL0, 3, 0, 0),
446 F(320000000, P_MMPLL0, 2.5, 0, 0),
447 F(465000000, P_MMPLL4, 2, 0, 0),
448 F(600000000, P_GPLL0, 1, 0, 0),
452 static struct clk_rcg2 vfe0_clk_src = {
455 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
456 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
457 .clkr.hw.init = &(struct clk_init_data){
458 .name = "vfe0_clk_src",
459 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
461 .ops = &clk_rcg2_ops,
465 static struct clk_rcg2 vfe1_clk_src = {
468 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
469 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "vfe1_clk_src",
472 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
474 .ops = &clk_rcg2_ops,
478 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
479 F(37500000, P_GPLL0, 16, 0, 0),
480 F(60000000, P_GPLL0, 10, 0, 0),
481 F(75000000, P_GPLL0, 8, 0, 0),
482 F(85710000, P_GPLL0, 7, 0, 0),
483 F(100000000, P_GPLL0, 6, 0, 0),
484 F(150000000, P_GPLL0, 4, 0, 0),
485 F(160000000, P_MMPLL0, 5, 0, 0),
486 F(200000000, P_MMPLL0, 4, 0, 0),
487 F(228570000, P_MMPLL0, 3.5, 0, 0),
488 F(300000000, P_GPLL0, 2, 0, 0),
489 F(320000000, P_MMPLL0, 2.5, 0, 0),
493 static struct clk_rcg2 mdp_clk_src = {
496 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
497 .freq_tbl = ftbl_mdss_mdp_clk,
498 .clkr.hw.init = &(struct clk_init_data){
499 .name = "mdp_clk_src",
500 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
502 .ops = &clk_rcg2_ops,
506 static struct clk_rcg2 gfx3d_clk_src = {
509 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "gfx3d_clk_src",
512 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
514 .ops = &clk_rcg2_ops,
518 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
519 F(75000000, P_GPLL0, 8, 0, 0),
520 F(133330000, P_GPLL0, 4.5, 0, 0),
521 F(200000000, P_GPLL0, 3, 0, 0),
522 F(228570000, P_MMPLL0, 3.5, 0, 0),
523 F(266670000, P_MMPLL0, 3, 0, 0),
524 F(320000000, P_MMPLL0, 2.5, 0, 0),
528 static struct clk_rcg2 jpeg0_clk_src = {
531 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
532 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "jpeg0_clk_src",
535 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
537 .ops = &clk_rcg2_ops,
541 static struct clk_rcg2 jpeg1_clk_src = {
544 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
545 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
546 .clkr.hw.init = &(struct clk_init_data){
547 .name = "jpeg1_clk_src",
548 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
550 .ops = &clk_rcg2_ops,
554 static struct clk_rcg2 jpeg2_clk_src = {
557 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
558 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "jpeg2_clk_src",
561 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
563 .ops = &clk_rcg2_ops,
567 static struct clk_rcg2 pclk0_clk_src = {
571 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
572 .clkr.hw.init = &(struct clk_init_data){
573 .name = "pclk0_clk_src",
574 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
576 .ops = &clk_pixel_ops,
577 .flags = CLK_SET_RATE_PARENT,
581 static struct clk_rcg2 pclk1_clk_src = {
585 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
586 .clkr.hw.init = &(struct clk_init_data){
587 .name = "pclk1_clk_src",
588 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
590 .ops = &clk_pixel_ops,
591 .flags = CLK_SET_RATE_PARENT,
595 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
596 F(50000000, P_GPLL0, 12, 0, 0),
597 F(100000000, P_GPLL0, 6, 0, 0),
598 F(133330000, P_GPLL0, 4.5, 0, 0),
599 F(200000000, P_MMPLL0, 4, 0, 0),
600 F(266670000, P_MMPLL0, 3, 0, 0),
601 F(465000000, P_MMPLL3, 2, 0, 0),
605 static struct clk_rcg2 vcodec0_clk_src = {
609 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
610 .freq_tbl = ftbl_venus0_vcodec0_clk,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "vcodec0_clk_src",
613 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
615 .ops = &clk_rcg2_ops,
619 static struct freq_tbl ftbl_avsync_vp_clk[] = {
620 F(150000000, P_GPLL0, 4, 0, 0),
621 F(320000000, P_MMPLL0, 2.5, 0, 0),
625 static struct clk_rcg2 vp_clk_src = {
628 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
629 .freq_tbl = ftbl_avsync_vp_clk,
630 .clkr.hw.init = &(struct clk_init_data){
631 .name = "vp_clk_src",
632 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
634 .ops = &clk_rcg2_ops,
638 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
639 F(19200000, P_XO, 1, 0, 0),
643 static struct clk_rcg2 cci_clk_src = {
647 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
648 .freq_tbl = ftbl_camss_cci_cci_clk,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "cci_clk_src",
651 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
653 .ops = &clk_rcg2_ops,
657 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
658 F(10000, P_XO, 16, 1, 120),
659 F(24000, P_XO, 16, 1, 50),
660 F(6000000, P_GPLL0, 10, 1, 10),
661 F(12000000, P_GPLL0, 10, 1, 5),
662 F(13000000, P_GPLL0, 4, 13, 150),
663 F(24000000, P_GPLL0, 5, 1, 5),
667 static struct clk_rcg2 camss_gp0_clk_src = {
671 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
672 .freq_tbl = ftbl_camss_gp0_1_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "camss_gp0_clk_src",
675 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
677 .ops = &clk_rcg2_ops,
681 static struct clk_rcg2 camss_gp1_clk_src = {
685 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
686 .freq_tbl = ftbl_camss_gp0_1_clk,
687 .clkr.hw.init = &(struct clk_init_data){
688 .name = "camss_gp1_clk_src",
689 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
691 .ops = &clk_rcg2_ops,
695 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
696 F(4800000, P_XO, 4, 0, 0),
697 F(6000000, P_GPLL0, 10, 1, 10),
698 F(8000000, P_GPLL0, 15, 1, 5),
699 F(9600000, P_XO, 2, 0, 0),
700 F(16000000, P_MMPLL0, 10, 1, 5),
701 F(19200000, P_XO, 1, 0, 0),
702 F(24000000, P_GPLL0, 5, 1, 5),
703 F(32000000, P_MMPLL0, 5, 1, 5),
704 F(48000000, P_GPLL0, 12.5, 0, 0),
705 F(64000000, P_MMPLL0, 12.5, 0, 0),
709 static struct clk_rcg2 mclk0_clk_src = {
713 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
714 .freq_tbl = ftbl_camss_mclk0_3_clk,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "mclk0_clk_src",
717 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
719 .ops = &clk_rcg2_ops,
723 static struct clk_rcg2 mclk1_clk_src = {
727 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
728 .freq_tbl = ftbl_camss_mclk0_3_clk,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "mclk1_clk_src",
731 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
733 .ops = &clk_rcg2_ops,
737 static struct clk_rcg2 mclk2_clk_src = {
741 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
742 .freq_tbl = ftbl_camss_mclk0_3_clk,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "mclk2_clk_src",
745 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
747 .ops = &clk_rcg2_ops,
751 static struct clk_rcg2 mclk3_clk_src = {
755 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
756 .freq_tbl = ftbl_camss_mclk0_3_clk,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "mclk3_clk_src",
759 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
761 .ops = &clk_rcg2_ops,
765 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
766 F(100000000, P_GPLL0, 6, 0, 0),
767 F(200000000, P_MMPLL0, 4, 0, 0),
771 static struct clk_rcg2 csi0phytimer_clk_src = {
774 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
775 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
776 .clkr.hw.init = &(struct clk_init_data){
777 .name = "csi0phytimer_clk_src",
778 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
780 .ops = &clk_rcg2_ops,
784 static struct clk_rcg2 csi1phytimer_clk_src = {
787 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
788 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
789 .clkr.hw.init = &(struct clk_init_data){
790 .name = "csi1phytimer_clk_src",
791 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
793 .ops = &clk_rcg2_ops,
797 static struct clk_rcg2 csi2phytimer_clk_src = {
800 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
801 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
802 .clkr.hw.init = &(struct clk_init_data){
803 .name = "csi2phytimer_clk_src",
804 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
806 .ops = &clk_rcg2_ops,
810 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
811 F(133330000, P_GPLL0, 4.5, 0, 0),
812 F(266670000, P_MMPLL0, 3, 0, 0),
813 F(320000000, P_MMPLL0, 2.5, 0, 0),
814 F(372000000, P_MMPLL4, 2.5, 0, 0),
815 F(465000000, P_MMPLL4, 2, 0, 0),
816 F(600000000, P_GPLL0, 1, 0, 0),
820 static struct clk_rcg2 cpp_clk_src = {
823 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
824 .freq_tbl = ftbl_camss_vfe_cpp_clk,
825 .clkr.hw.init = &(struct clk_init_data){
826 .name = "cpp_clk_src",
827 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
829 .ops = &clk_rcg2_ops,
833 static struct clk_rcg2 byte0_clk_src = {
836 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "byte0_clk_src",
839 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
841 .ops = &clk_byte2_ops,
842 .flags = CLK_SET_RATE_PARENT,
846 static struct clk_rcg2 byte1_clk_src = {
849 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
850 .clkr.hw.init = &(struct clk_init_data){
851 .name = "byte1_clk_src",
852 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
854 .ops = &clk_byte2_ops,
855 .flags = CLK_SET_RATE_PARENT,
859 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
860 F(19200000, P_XO, 1, 0, 0),
864 static struct clk_rcg2 edpaux_clk_src = {
867 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
868 .freq_tbl = ftbl_mdss_edpaux_clk,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "edpaux_clk_src",
871 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
873 .ops = &clk_rcg2_ops,
877 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
878 F(135000000, P_EDPLINK, 2, 0, 0),
879 F(270000000, P_EDPLINK, 11, 0, 0),
883 static struct clk_rcg2 edplink_clk_src = {
886 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
887 .freq_tbl = ftbl_mdss_edplink_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edplink_clk_src",
890 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
892 .ops = &clk_rcg2_ops,
893 .flags = CLK_SET_RATE_PARENT,
897 static struct freq_tbl edp_pixel_freq_tbl[] = {
902 static struct clk_rcg2 edppixel_clk_src = {
906 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
907 .freq_tbl = edp_pixel_freq_tbl,
908 .clkr.hw.init = &(struct clk_init_data){
909 .name = "edppixel_clk_src",
910 .parent_names = mmcc_xo_dsi_hdmi_edp,
912 .ops = &clk_edp_pixel_ops,
916 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
917 F(19200000, P_XO, 1, 0, 0),
921 static struct clk_rcg2 esc0_clk_src = {
924 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
925 .freq_tbl = ftbl_mdss_esc0_1_clk,
926 .clkr.hw.init = &(struct clk_init_data){
927 .name = "esc0_clk_src",
928 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
930 .ops = &clk_rcg2_ops,
934 static struct clk_rcg2 esc1_clk_src = {
937 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
938 .freq_tbl = ftbl_mdss_esc0_1_clk,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "esc1_clk_src",
941 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
943 .ops = &clk_rcg2_ops,
947 static struct freq_tbl extpclk_freq_tbl[] = {
948 { .src = P_HDMIPLL },
952 static struct clk_rcg2 extpclk_clk_src = {
955 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
956 .freq_tbl = extpclk_freq_tbl,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "extpclk_clk_src",
959 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
961 .ops = &clk_byte_ops,
962 .flags = CLK_SET_RATE_PARENT,
966 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
967 F(19200000, P_XO, 1, 0, 0),
971 static struct clk_rcg2 hdmi_clk_src = {
974 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
975 .freq_tbl = ftbl_mdss_hdmi_clk,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "hdmi_clk_src",
978 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
980 .ops = &clk_rcg2_ops,
984 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
985 F(19200000, P_XO, 1, 0, 0),
989 static struct clk_rcg2 vsync_clk_src = {
992 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
993 .freq_tbl = ftbl_mdss_vsync_clk,
994 .clkr.hw.init = &(struct clk_init_data){
995 .name = "vsync_clk_src",
996 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
998 .ops = &clk_rcg2_ops,
1002 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1003 F(50000000, P_GPLL0, 12, 0, 0),
1007 static struct clk_rcg2 rbcpr_clk_src = {
1010 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1011 .freq_tbl = ftbl_mmss_rbcpr_clk,
1012 .clkr.hw.init = &(struct clk_init_data){
1013 .name = "rbcpr_clk_src",
1014 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1016 .ops = &clk_rcg2_ops,
1020 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1021 F(19200000, P_XO, 1, 0, 0),
1025 static struct clk_rcg2 rbbmtimer_clk_src = {
1028 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1029 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1030 .clkr.hw.init = &(struct clk_init_data){
1031 .name = "rbbmtimer_clk_src",
1032 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1034 .ops = &clk_rcg2_ops,
1038 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1039 F(50000000, P_GPLL0, 12, 0, 0),
1040 F(100000000, P_GPLL0, 6, 0, 0),
1041 F(133330000, P_GPLL0, 4.5, 0, 0),
1042 F(200000000, P_MMPLL0, 4, 0, 0),
1043 F(266670000, P_MMPLL0, 3, 0, 0),
1044 F(465000000, P_MMPLL3, 2, 0, 0),
1048 static struct clk_rcg2 maple_clk_src = {
1051 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1052 .freq_tbl = ftbl_vpu_maple_clk,
1053 .clkr.hw.init = &(struct clk_init_data){
1054 .name = "maple_clk_src",
1055 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1057 .ops = &clk_rcg2_ops,
1061 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1062 F(50000000, P_GPLL0, 12, 0, 0),
1063 F(100000000, P_GPLL0, 6, 0, 0),
1064 F(200000000, P_MMPLL0, 4, 0, 0),
1065 F(320000000, P_MMPLL0, 2.5, 0, 0),
1066 F(400000000, P_MMPLL0, 2, 0, 0),
1070 static struct clk_rcg2 vdp_clk_src = {
1073 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1074 .freq_tbl = ftbl_vpu_vdp_clk,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "vdp_clk_src",
1077 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1079 .ops = &clk_rcg2_ops,
1083 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1084 F(40000000, P_GPLL0, 15, 0, 0),
1085 F(80000000, P_MMPLL0, 10, 0, 0),
1089 static struct clk_rcg2 vpu_bus_clk_src = {
1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1093 .freq_tbl = ftbl_vpu_bus_clk,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "vpu_bus_clk_src",
1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1098 .ops = &clk_rcg2_ops,
1102 static struct clk_branch mmss_cxo_clk = {
1105 .enable_reg = 0x5104,
1106 .enable_mask = BIT(0),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "mmss_cxo_clk",
1109 .parent_names = (const char *[]){ "xo" },
1111 .flags = CLK_SET_RATE_PARENT,
1112 .ops = &clk_branch2_ops,
1117 static struct clk_branch mmss_sleepclk_clk = {
1120 .enable_reg = 0x5100,
1121 .enable_mask = BIT(0),
1122 .hw.init = &(struct clk_init_data){
1123 .name = "mmss_sleepclk_clk",
1124 .parent_names = (const char *[]){
1128 .flags = CLK_SET_RATE_PARENT,
1129 .ops = &clk_branch2_ops,
1134 static struct clk_branch avsync_ahb_clk = {
1137 .enable_reg = 0x2414,
1138 .enable_mask = BIT(0),
1139 .hw.init = &(struct clk_init_data){
1140 .name = "avsync_ahb_clk",
1141 .parent_names = (const char *[]){
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1151 static struct clk_branch avsync_edppixel_clk = {
1154 .enable_reg = 0x2418,
1155 .enable_mask = BIT(0),
1156 .hw.init = &(struct clk_init_data){
1157 .name = "avsync_edppixel_clk",
1158 .parent_names = (const char *[]){
1162 .flags = CLK_SET_RATE_PARENT,
1163 .ops = &clk_branch2_ops,
1168 static struct clk_branch avsync_extpclk_clk = {
1171 .enable_reg = 0x2410,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "avsync_extpclk_clk",
1175 .parent_names = (const char *[]){
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1185 static struct clk_branch avsync_pclk0_clk = {
1188 .enable_reg = 0x241c,
1189 .enable_mask = BIT(0),
1190 .hw.init = &(struct clk_init_data){
1191 .name = "avsync_pclk0_clk",
1192 .parent_names = (const char *[]){
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1202 static struct clk_branch avsync_pclk1_clk = {
1205 .enable_reg = 0x2420,
1206 .enable_mask = BIT(0),
1207 .hw.init = &(struct clk_init_data){
1208 .name = "avsync_pclk1_clk",
1209 .parent_names = (const char *[]){
1213 .flags = CLK_SET_RATE_PARENT,
1214 .ops = &clk_branch2_ops,
1219 static struct clk_branch avsync_vp_clk = {
1222 .enable_reg = 0x2404,
1223 .enable_mask = BIT(0),
1224 .hw.init = &(struct clk_init_data){
1225 .name = "avsync_vp_clk",
1226 .parent_names = (const char *[]){
1230 .flags = CLK_SET_RATE_PARENT,
1231 .ops = &clk_branch2_ops,
1236 static struct clk_branch camss_ahb_clk = {
1239 .enable_reg = 0x348c,
1240 .enable_mask = BIT(0),
1241 .hw.init = &(struct clk_init_data){
1242 .name = "camss_ahb_clk",
1243 .parent_names = (const char *[]){
1247 .flags = CLK_SET_RATE_PARENT,
1248 .ops = &clk_branch2_ops,
1253 static struct clk_branch camss_cci_cci_ahb_clk = {
1256 .enable_reg = 0x3348,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "camss_cci_cci_ahb_clk",
1260 .parent_names = (const char *[]){
1264 .ops = &clk_branch2_ops,
1269 static struct clk_branch camss_cci_cci_clk = {
1272 .enable_reg = 0x3344,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "camss_cci_cci_clk",
1276 .parent_names = (const char *[]){
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1286 static struct clk_branch camss_csi0_ahb_clk = {
1289 .enable_reg = 0x30bc,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "camss_csi0_ahb_clk",
1293 .parent_names = (const char *[]){
1297 .ops = &clk_branch2_ops,
1302 static struct clk_branch camss_csi0_clk = {
1305 .enable_reg = 0x30b4,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "camss_csi0_clk",
1309 .parent_names = (const char *[]){
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1319 static struct clk_branch camss_csi0phy_clk = {
1322 .enable_reg = 0x30c4,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "camss_csi0phy_clk",
1326 .parent_names = (const char *[]){
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_branch2_ops,
1336 static struct clk_branch camss_csi0pix_clk = {
1339 .enable_reg = 0x30e4,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "camss_csi0pix_clk",
1343 .parent_names = (const char *[]){
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1353 static struct clk_branch camss_csi0rdi_clk = {
1356 .enable_reg = 0x30d4,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "camss_csi0rdi_clk",
1360 .parent_names = (const char *[]){
1364 .flags = CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1370 static struct clk_branch camss_csi1_ahb_clk = {
1373 .enable_reg = 0x3128,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "camss_csi1_ahb_clk",
1377 .parent_names = (const char *[]){
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_branch2_ops,
1387 static struct clk_branch camss_csi1_clk = {
1390 .enable_reg = 0x3124,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "camss_csi1_clk",
1394 .parent_names = (const char *[]){
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1404 static struct clk_branch camss_csi1phy_clk = {
1407 .enable_reg = 0x3134,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "camss_csi1phy_clk",
1411 .parent_names = (const char *[]){
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch camss_csi1pix_clk = {
1424 .enable_reg = 0x3154,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "camss_csi1pix_clk",
1428 .parent_names = (const char *[]){
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch camss_csi1rdi_clk = {
1441 .enable_reg = 0x3144,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camss_csi1rdi_clk",
1445 .parent_names = (const char *[]){
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1455 static struct clk_branch camss_csi2_ahb_clk = {
1458 .enable_reg = 0x3188,
1459 .enable_mask = BIT(0),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "camss_csi2_ahb_clk",
1462 .parent_names = (const char *[]){
1466 .ops = &clk_branch2_ops,
1471 static struct clk_branch camss_csi2_clk = {
1474 .enable_reg = 0x3184,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "camss_csi2_clk",
1478 .parent_names = (const char *[]){
1482 .flags = CLK_SET_RATE_PARENT,
1483 .ops = &clk_branch2_ops,
1488 static struct clk_branch camss_csi2phy_clk = {
1491 .enable_reg = 0x3194,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "camss_csi2phy_clk",
1495 .parent_names = (const char *[]){
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1505 static struct clk_branch camss_csi2pix_clk = {
1508 .enable_reg = 0x31b4,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "camss_csi2pix_clk",
1512 .parent_names = (const char *[]){
1516 .flags = CLK_SET_RATE_PARENT,
1517 .ops = &clk_branch2_ops,
1522 static struct clk_branch camss_csi2rdi_clk = {
1525 .enable_reg = 0x31a4,
1526 .enable_mask = BIT(0),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "camss_csi2rdi_clk",
1529 .parent_names = (const char *[]){
1533 .flags = CLK_SET_RATE_PARENT,
1534 .ops = &clk_branch2_ops,
1539 static struct clk_branch camss_csi3_ahb_clk = {
1542 .enable_reg = 0x31e8,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "camss_csi3_ahb_clk",
1546 .parent_names = (const char *[]){
1550 .ops = &clk_branch2_ops,
1555 static struct clk_branch camss_csi3_clk = {
1558 .enable_reg = 0x31e4,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "camss_csi3_clk",
1562 .parent_names = (const char *[]){
1566 .flags = CLK_SET_RATE_PARENT,
1567 .ops = &clk_branch2_ops,
1572 static struct clk_branch camss_csi3phy_clk = {
1575 .enable_reg = 0x31f4,
1576 .enable_mask = BIT(0),
1577 .hw.init = &(struct clk_init_data){
1578 .name = "camss_csi3phy_clk",
1579 .parent_names = (const char *[]){
1583 .flags = CLK_SET_RATE_PARENT,
1584 .ops = &clk_branch2_ops,
1589 static struct clk_branch camss_csi3pix_clk = {
1592 .enable_reg = 0x3214,
1593 .enable_mask = BIT(0),
1594 .hw.init = &(struct clk_init_data){
1595 .name = "camss_csi3pix_clk",
1596 .parent_names = (const char *[]){
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1606 static struct clk_branch camss_csi3rdi_clk = {
1609 .enable_reg = 0x3204,
1610 .enable_mask = BIT(0),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "camss_csi3rdi_clk",
1613 .parent_names = (const char *[]){
1617 .flags = CLK_SET_RATE_PARENT,
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch camss_csi_vfe0_clk = {
1626 .enable_reg = 0x3704,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "camss_csi_vfe0_clk",
1630 .parent_names = (const char *[]){
1634 .flags = CLK_SET_RATE_PARENT,
1635 .ops = &clk_branch2_ops,
1640 static struct clk_branch camss_csi_vfe1_clk = {
1643 .enable_reg = 0x3714,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "camss_csi_vfe1_clk",
1647 .parent_names = (const char *[]){
1651 .flags = CLK_SET_RATE_PARENT,
1652 .ops = &clk_branch2_ops,
1657 static struct clk_branch camss_gp0_clk = {
1660 .enable_reg = 0x3444,
1661 .enable_mask = BIT(0),
1662 .hw.init = &(struct clk_init_data){
1663 .name = "camss_gp0_clk",
1664 .parent_names = (const char *[]){
1665 "camss_gp0_clk_src",
1668 .flags = CLK_SET_RATE_PARENT,
1669 .ops = &clk_branch2_ops,
1674 static struct clk_branch camss_gp1_clk = {
1677 .enable_reg = 0x3474,
1678 .enable_mask = BIT(0),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "camss_gp1_clk",
1681 .parent_names = (const char *[]){
1682 "camss_gp1_clk_src",
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch camss_ispif_ahb_clk = {
1694 .enable_reg = 0x3224,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "camss_ispif_ahb_clk",
1698 .parent_names = (const char *[]){
1702 .flags = CLK_SET_RATE_PARENT,
1703 .ops = &clk_branch2_ops,
1708 static struct clk_branch camss_jpeg_jpeg0_clk = {
1711 .enable_reg = 0x35a8,
1712 .enable_mask = BIT(0),
1713 .hw.init = &(struct clk_init_data){
1714 .name = "camss_jpeg_jpeg0_clk",
1715 .parent_names = (const char *[]){
1719 .flags = CLK_SET_RATE_PARENT,
1720 .ops = &clk_branch2_ops,
1725 static struct clk_branch camss_jpeg_jpeg1_clk = {
1728 .enable_reg = 0x35ac,
1729 .enable_mask = BIT(0),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "camss_jpeg_jpeg1_clk",
1732 .parent_names = (const char *[]){
1736 .flags = CLK_SET_RATE_PARENT,
1737 .ops = &clk_branch2_ops,
1742 static struct clk_branch camss_jpeg_jpeg2_clk = {
1745 .enable_reg = 0x35b0,
1746 .enable_mask = BIT(0),
1747 .hw.init = &(struct clk_init_data){
1748 .name = "camss_jpeg_jpeg2_clk",
1749 .parent_names = (const char *[]){
1753 .flags = CLK_SET_RATE_PARENT,
1754 .ops = &clk_branch2_ops,
1759 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1762 .enable_reg = 0x35b4,
1763 .enable_mask = BIT(0),
1764 .hw.init = &(struct clk_init_data){
1765 .name = "camss_jpeg_jpeg_ahb_clk",
1766 .parent_names = (const char *[]){
1770 .ops = &clk_branch2_ops,
1775 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1778 .enable_reg = 0x35b8,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "camss_jpeg_jpeg_axi_clk",
1782 .parent_names = (const char *[]){
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch camss_mclk0_clk = {
1794 .enable_reg = 0x3384,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "camss_mclk0_clk",
1798 .parent_names = (const char *[]){
1802 .flags = CLK_SET_RATE_PARENT,
1803 .ops = &clk_branch2_ops,
1808 static struct clk_branch camss_mclk1_clk = {
1811 .enable_reg = 0x33b4,
1812 .enable_mask = BIT(0),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "camss_mclk1_clk",
1815 .parent_names = (const char *[]){
1819 .flags = CLK_SET_RATE_PARENT,
1820 .ops = &clk_branch2_ops,
1825 static struct clk_branch camss_mclk2_clk = {
1828 .enable_reg = 0x33e4,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "camss_mclk2_clk",
1832 .parent_names = (const char *[]){
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1842 static struct clk_branch camss_mclk3_clk = {
1845 .enable_reg = 0x3414,
1846 .enable_mask = BIT(0),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "camss_mclk3_clk",
1849 .parent_names = (const char *[]){
1853 .flags = CLK_SET_RATE_PARENT,
1854 .ops = &clk_branch2_ops,
1859 static struct clk_branch camss_micro_ahb_clk = {
1862 .enable_reg = 0x3494,
1863 .enable_mask = BIT(0),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "camss_micro_ahb_clk",
1866 .parent_names = (const char *[]){
1870 .ops = &clk_branch2_ops,
1875 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1878 .enable_reg = 0x3024,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "camss_phy0_csi0phytimer_clk",
1882 .parent_names = (const char *[]){
1883 "csi0phytimer_clk_src",
1886 .flags = CLK_SET_RATE_PARENT,
1887 .ops = &clk_branch2_ops,
1892 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1895 .enable_reg = 0x3054,
1896 .enable_mask = BIT(0),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "camss_phy1_csi1phytimer_clk",
1899 .parent_names = (const char *[]){
1900 "csi1phytimer_clk_src",
1903 .flags = CLK_SET_RATE_PARENT,
1904 .ops = &clk_branch2_ops,
1909 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1912 .enable_reg = 0x3084,
1913 .enable_mask = BIT(0),
1914 .hw.init = &(struct clk_init_data){
1915 .name = "camss_phy2_csi2phytimer_clk",
1916 .parent_names = (const char *[]){
1917 "csi2phytimer_clk_src",
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1926 static struct clk_branch camss_top_ahb_clk = {
1929 .enable_reg = 0x3484,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "camss_top_ahb_clk",
1933 .parent_names = (const char *[]){
1937 .flags = CLK_SET_RATE_PARENT,
1938 .ops = &clk_branch2_ops,
1943 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1946 .enable_reg = 0x36b4,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "camss_vfe_cpp_ahb_clk",
1950 .parent_names = (const char *[]){
1954 .flags = CLK_SET_RATE_PARENT,
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch camss_vfe_cpp_clk = {
1963 .enable_reg = 0x36b0,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "camss_vfe_cpp_clk",
1967 .parent_names = (const char *[]){
1971 .flags = CLK_SET_RATE_PARENT,
1972 .ops = &clk_branch2_ops,
1977 static struct clk_branch camss_vfe_vfe0_clk = {
1980 .enable_reg = 0x36a8,
1981 .enable_mask = BIT(0),
1982 .hw.init = &(struct clk_init_data){
1983 .name = "camss_vfe_vfe0_clk",
1984 .parent_names = (const char *[]){
1988 .flags = CLK_SET_RATE_PARENT,
1989 .ops = &clk_branch2_ops,
1994 static struct clk_branch camss_vfe_vfe1_clk = {
1997 .enable_reg = 0x36ac,
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "camss_vfe_vfe1_clk",
2001 .parent_names = (const char *[]){
2005 .flags = CLK_SET_RATE_PARENT,
2006 .ops = &clk_branch2_ops,
2011 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2014 .enable_reg = 0x36b8,
2015 .enable_mask = BIT(0),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "camss_vfe_vfe_ahb_clk",
2018 .parent_names = (const char *[]){
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2028 static struct clk_branch camss_vfe_vfe_axi_clk = {
2031 .enable_reg = 0x36bc,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "camss_vfe_vfe_axi_clk",
2035 .parent_names = (const char *[]){
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch mdss_ahb_clk = {
2048 .enable_reg = 0x2308,
2049 .enable_mask = BIT(0),
2050 .hw.init = &(struct clk_init_data){
2051 .name = "mdss_ahb_clk",
2052 .parent_names = (const char *[]){
2056 .flags = CLK_SET_RATE_PARENT,
2057 .ops = &clk_branch2_ops,
2062 static struct clk_branch mdss_axi_clk = {
2065 .enable_reg = 0x2310,
2066 .enable_mask = BIT(0),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "mdss_axi_clk",
2069 .parent_names = (const char *[]){
2073 .flags = CLK_SET_RATE_PARENT,
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch mdss_byte0_clk = {
2082 .enable_reg = 0x233c,
2083 .enable_mask = BIT(0),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "mdss_byte0_clk",
2086 .parent_names = (const char *[]){
2090 .flags = CLK_SET_RATE_PARENT,
2091 .ops = &clk_branch2_ops,
2096 static struct clk_branch mdss_byte1_clk = {
2099 .enable_reg = 0x2340,
2100 .enable_mask = BIT(0),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "mdss_byte1_clk",
2103 .parent_names = (const char *[]){
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2113 static struct clk_branch mdss_edpaux_clk = {
2116 .enable_reg = 0x2334,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "mdss_edpaux_clk",
2120 .parent_names = (const char *[]){
2124 .flags = CLK_SET_RATE_PARENT,
2125 .ops = &clk_branch2_ops,
2130 static struct clk_branch mdss_edplink_clk = {
2133 .enable_reg = 0x2330,
2134 .enable_mask = BIT(0),
2135 .hw.init = &(struct clk_init_data){
2136 .name = "mdss_edplink_clk",
2137 .parent_names = (const char *[]){
2141 .flags = CLK_SET_RATE_PARENT,
2142 .ops = &clk_branch2_ops,
2147 static struct clk_branch mdss_edppixel_clk = {
2150 .enable_reg = 0x232c,
2151 .enable_mask = BIT(0),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "mdss_edppixel_clk",
2154 .parent_names = (const char *[]){
2158 .flags = CLK_SET_RATE_PARENT,
2159 .ops = &clk_branch2_ops,
2164 static struct clk_branch mdss_esc0_clk = {
2167 .enable_reg = 0x2344,
2168 .enable_mask = BIT(0),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "mdss_esc0_clk",
2171 .parent_names = (const char *[]){
2175 .flags = CLK_SET_RATE_PARENT,
2176 .ops = &clk_branch2_ops,
2181 static struct clk_branch mdss_esc1_clk = {
2184 .enable_reg = 0x2348,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "mdss_esc1_clk",
2188 .parent_names = (const char *[]){
2192 .flags = CLK_SET_RATE_PARENT,
2193 .ops = &clk_branch2_ops,
2198 static struct clk_branch mdss_extpclk_clk = {
2201 .enable_reg = 0x2324,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "mdss_extpclk_clk",
2205 .parent_names = (const char *[]){
2209 .flags = CLK_SET_RATE_PARENT,
2210 .ops = &clk_branch2_ops,
2215 static struct clk_branch mdss_hdmi_ahb_clk = {
2218 .enable_reg = 0x230c,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "mdss_hdmi_ahb_clk",
2222 .parent_names = (const char *[]){
2226 .flags = CLK_SET_RATE_PARENT,
2227 .ops = &clk_branch2_ops,
2232 static struct clk_branch mdss_hdmi_clk = {
2235 .enable_reg = 0x2338,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "mdss_hdmi_clk",
2239 .parent_names = (const char *[]){
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2249 static struct clk_branch mdss_mdp_clk = {
2252 .enable_reg = 0x231c,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "mdss_mdp_clk",
2256 .parent_names = (const char *[]){
2260 .flags = CLK_SET_RATE_PARENT,
2261 .ops = &clk_branch2_ops,
2266 static struct clk_branch mdss_mdp_lut_clk = {
2269 .enable_reg = 0x2320,
2270 .enable_mask = BIT(0),
2271 .hw.init = &(struct clk_init_data){
2272 .name = "mdss_mdp_lut_clk",
2273 .parent_names = (const char *[]){
2277 .flags = CLK_SET_RATE_PARENT,
2278 .ops = &clk_branch2_ops,
2283 static struct clk_branch mdss_pclk0_clk = {
2286 .enable_reg = 0x2314,
2287 .enable_mask = BIT(0),
2288 .hw.init = &(struct clk_init_data){
2289 .name = "mdss_pclk0_clk",
2290 .parent_names = (const char *[]){
2294 .flags = CLK_SET_RATE_PARENT,
2295 .ops = &clk_branch2_ops,
2300 static struct clk_branch mdss_pclk1_clk = {
2303 .enable_reg = 0x2318,
2304 .enable_mask = BIT(0),
2305 .hw.init = &(struct clk_init_data){
2306 .name = "mdss_pclk1_clk",
2307 .parent_names = (const char *[]){
2311 .flags = CLK_SET_RATE_PARENT,
2312 .ops = &clk_branch2_ops,
2317 static struct clk_branch mdss_vsync_clk = {
2320 .enable_reg = 0x2328,
2321 .enable_mask = BIT(0),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "mdss_vsync_clk",
2324 .parent_names = (const char *[]){
2328 .flags = CLK_SET_RATE_PARENT,
2329 .ops = &clk_branch2_ops,
2334 static struct clk_branch mmss_rbcpr_ahb_clk = {
2337 .enable_reg = 0x4088,
2338 .enable_mask = BIT(0),
2339 .hw.init = &(struct clk_init_data){
2340 .name = "mmss_rbcpr_ahb_clk",
2341 .parent_names = (const char *[]){
2345 .flags = CLK_SET_RATE_PARENT,
2346 .ops = &clk_branch2_ops,
2351 static struct clk_branch mmss_rbcpr_clk = {
2354 .enable_reg = 0x4084,
2355 .enable_mask = BIT(0),
2356 .hw.init = &(struct clk_init_data){
2357 .name = "mmss_rbcpr_clk",
2358 .parent_names = (const char *[]){
2362 .flags = CLK_SET_RATE_PARENT,
2363 .ops = &clk_branch2_ops,
2368 static struct clk_branch mmss_spdm_ahb_clk = {
2371 .enable_reg = 0x0230,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "mmss_spdm_ahb_clk",
2375 .parent_names = (const char *[]){
2376 "mmss_spdm_ahb_div_clk",
2379 .flags = CLK_SET_RATE_PARENT,
2380 .ops = &clk_branch2_ops,
2385 static struct clk_branch mmss_spdm_axi_clk = {
2388 .enable_reg = 0x0210,
2389 .enable_mask = BIT(0),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "mmss_spdm_axi_clk",
2392 .parent_names = (const char *[]){
2393 "mmss_spdm_axi_div_clk",
2396 .flags = CLK_SET_RATE_PARENT,
2397 .ops = &clk_branch2_ops,
2402 static struct clk_branch mmss_spdm_csi0_clk = {
2405 .enable_reg = 0x023c,
2406 .enable_mask = BIT(0),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "mmss_spdm_csi0_clk",
2409 .parent_names = (const char *[]){
2410 "mmss_spdm_csi0_div_clk",
2413 .flags = CLK_SET_RATE_PARENT,
2414 .ops = &clk_branch2_ops,
2419 static struct clk_branch mmss_spdm_gfx3d_clk = {
2422 .enable_reg = 0x022c,
2423 .enable_mask = BIT(0),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "mmss_spdm_gfx3d_clk",
2426 .parent_names = (const char *[]){
2427 "mmss_spdm_gfx3d_div_clk",
2430 .flags = CLK_SET_RATE_PARENT,
2431 .ops = &clk_branch2_ops,
2436 static struct clk_branch mmss_spdm_jpeg0_clk = {
2439 .enable_reg = 0x0204,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "mmss_spdm_jpeg0_clk",
2443 .parent_names = (const char *[]){
2444 "mmss_spdm_jpeg0_div_clk",
2447 .flags = CLK_SET_RATE_PARENT,
2448 .ops = &clk_branch2_ops,
2453 static struct clk_branch mmss_spdm_jpeg1_clk = {
2456 .enable_reg = 0x0208,
2457 .enable_mask = BIT(0),
2458 .hw.init = &(struct clk_init_data){
2459 .name = "mmss_spdm_jpeg1_clk",
2460 .parent_names = (const char *[]){
2461 "mmss_spdm_jpeg1_div_clk",
2464 .flags = CLK_SET_RATE_PARENT,
2465 .ops = &clk_branch2_ops,
2470 static struct clk_branch mmss_spdm_jpeg2_clk = {
2473 .enable_reg = 0x0224,
2474 .enable_mask = BIT(0),
2475 .hw.init = &(struct clk_init_data){
2476 .name = "mmss_spdm_jpeg2_clk",
2477 .parent_names = (const char *[]){
2478 "mmss_spdm_jpeg2_div_clk",
2481 .flags = CLK_SET_RATE_PARENT,
2482 .ops = &clk_branch2_ops,
2487 static struct clk_branch mmss_spdm_mdp_clk = {
2490 .enable_reg = 0x020c,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "mmss_spdm_mdp_clk",
2494 .parent_names = (const char *[]){
2495 "mmss_spdm_mdp_div_clk",
2498 .flags = CLK_SET_RATE_PARENT,
2499 .ops = &clk_branch2_ops,
2504 static struct clk_branch mmss_spdm_pclk0_clk = {
2507 .enable_reg = 0x0234,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "mmss_spdm_pclk0_clk",
2511 .parent_names = (const char *[]){
2512 "mmss_spdm_pclk0_div_clk",
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2521 static struct clk_branch mmss_spdm_pclk1_clk = {
2524 .enable_reg = 0x0228,
2525 .enable_mask = BIT(0),
2526 .hw.init = &(struct clk_init_data){
2527 .name = "mmss_spdm_pclk1_clk",
2528 .parent_names = (const char *[]){
2529 "mmss_spdm_pclk1_div_clk",
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2538 static struct clk_branch mmss_spdm_vcodec0_clk = {
2541 .enable_reg = 0x0214,
2542 .enable_mask = BIT(0),
2543 .hw.init = &(struct clk_init_data){
2544 .name = "mmss_spdm_vcodec0_clk",
2545 .parent_names = (const char *[]){
2546 "mmss_spdm_vcodec0_div_clk",
2549 .flags = CLK_SET_RATE_PARENT,
2550 .ops = &clk_branch2_ops,
2555 static struct clk_branch mmss_spdm_vfe0_clk = {
2558 .enable_reg = 0x0218,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(struct clk_init_data){
2561 .name = "mmss_spdm_vfe0_clk",
2562 .parent_names = (const char *[]){
2563 "mmss_spdm_vfe0_div_clk",
2566 .flags = CLK_SET_RATE_PARENT,
2567 .ops = &clk_branch2_ops,
2572 static struct clk_branch mmss_spdm_vfe1_clk = {
2575 .enable_reg = 0x021c,
2576 .enable_mask = BIT(0),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "mmss_spdm_vfe1_clk",
2579 .parent_names = (const char *[]){
2580 "mmss_spdm_vfe1_div_clk",
2583 .flags = CLK_SET_RATE_PARENT,
2584 .ops = &clk_branch2_ops,
2589 static struct clk_branch mmss_spdm_rm_axi_clk = {
2592 .enable_reg = 0x0304,
2593 .enable_mask = BIT(0),
2594 .hw.init = &(struct clk_init_data){
2595 .name = "mmss_spdm_rm_axi_clk",
2596 .parent_names = (const char *[]){
2600 .flags = CLK_SET_RATE_PARENT,
2601 .ops = &clk_branch2_ops,
2606 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2609 .enable_reg = 0x0308,
2610 .enable_mask = BIT(0),
2611 .hw.init = &(struct clk_init_data){
2612 .name = "mmss_spdm_rm_ocmemnoc_clk",
2613 .parent_names = (const char *[]){
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2624 static struct clk_branch mmss_misc_ahb_clk = {
2627 .enable_reg = 0x502c,
2628 .enable_mask = BIT(0),
2629 .hw.init = &(struct clk_init_data){
2630 .name = "mmss_misc_ahb_clk",
2631 .parent_names = (const char *[]){
2635 .flags = CLK_SET_RATE_PARENT,
2636 .ops = &clk_branch2_ops,
2641 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2644 .enable_reg = 0x5024,
2645 .enable_mask = BIT(0),
2646 .hw.init = &(struct clk_init_data){
2647 .name = "mmss_mmssnoc_ahb_clk",
2648 .parent_names = (const char *[]){
2652 .ops = &clk_branch2_ops,
2653 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2658 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2661 .enable_reg = 0x5028,
2662 .enable_mask = BIT(0),
2663 .hw.init = &(struct clk_init_data){
2664 .name = "mmss_mmssnoc_bto_ahb_clk",
2665 .parent_names = (const char *[]){
2669 .ops = &clk_branch2_ops,
2670 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2675 static struct clk_branch mmss_mmssnoc_axi_clk = {
2678 .enable_reg = 0x506c,
2679 .enable_mask = BIT(0),
2680 .hw.init = &(struct clk_init_data){
2681 .name = "mmss_mmssnoc_axi_clk",
2682 .parent_names = (const char *[]){
2686 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2687 .ops = &clk_branch2_ops,
2692 static struct clk_branch mmss_s0_axi_clk = {
2695 .enable_reg = 0x5064,
2696 .enable_mask = BIT(0),
2697 .hw.init = &(struct clk_init_data){
2698 .name = "mmss_s0_axi_clk",
2699 .parent_names = (const char *[]){
2703 .ops = &clk_branch2_ops,
2704 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2709 static struct clk_branch ocmemcx_ahb_clk = {
2712 .enable_reg = 0x405c,
2713 .enable_mask = BIT(0),
2714 .hw.init = &(struct clk_init_data){
2715 .name = "ocmemcx_ahb_clk",
2716 .parent_names = (const char *[]){
2720 .flags = CLK_SET_RATE_PARENT,
2721 .ops = &clk_branch2_ops,
2726 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2729 .enable_reg = 0x4058,
2730 .enable_mask = BIT(0),
2731 .hw.init = &(struct clk_init_data){
2732 .name = "ocmemcx_ocmemnoc_clk",
2733 .parent_names = (const char *[]){
2737 .flags = CLK_SET_RATE_PARENT,
2738 .ops = &clk_branch2_ops,
2743 static struct clk_branch oxili_ocmemgx_clk = {
2746 .enable_reg = 0x402c,
2747 .enable_mask = BIT(0),
2748 .hw.init = &(struct clk_init_data){
2749 .name = "oxili_ocmemgx_clk",
2750 .parent_names = (const char *[]){
2754 .flags = CLK_SET_RATE_PARENT,
2755 .ops = &clk_branch2_ops,
2760 static struct clk_branch oxili_gfx3d_clk = {
2763 .enable_reg = 0x4028,
2764 .enable_mask = BIT(0),
2765 .hw.init = &(struct clk_init_data){
2766 .name = "oxili_gfx3d_clk",
2767 .parent_names = (const char *[]){
2771 .flags = CLK_SET_RATE_PARENT,
2772 .ops = &clk_branch2_ops,
2777 static struct clk_branch oxili_rbbmtimer_clk = {
2780 .enable_reg = 0x40b0,
2781 .enable_mask = BIT(0),
2782 .hw.init = &(struct clk_init_data){
2783 .name = "oxili_rbbmtimer_clk",
2784 .parent_names = (const char *[]){
2785 "rbbmtimer_clk_src",
2788 .flags = CLK_SET_RATE_PARENT,
2789 .ops = &clk_branch2_ops,
2794 static struct clk_branch oxilicx_ahb_clk = {
2797 .enable_reg = 0x403c,
2798 .enable_mask = BIT(0),
2799 .hw.init = &(struct clk_init_data){
2800 .name = "oxilicx_ahb_clk",
2801 .parent_names = (const char *[]){
2805 .flags = CLK_SET_RATE_PARENT,
2806 .ops = &clk_branch2_ops,
2811 static struct clk_branch venus0_ahb_clk = {
2814 .enable_reg = 0x1030,
2815 .enable_mask = BIT(0),
2816 .hw.init = &(struct clk_init_data){
2817 .name = "venus0_ahb_clk",
2818 .parent_names = (const char *[]){
2822 .flags = CLK_SET_RATE_PARENT,
2823 .ops = &clk_branch2_ops,
2828 static struct clk_branch venus0_axi_clk = {
2831 .enable_reg = 0x1034,
2832 .enable_mask = BIT(0),
2833 .hw.init = &(struct clk_init_data){
2834 .name = "venus0_axi_clk",
2835 .parent_names = (const char *[]){
2839 .flags = CLK_SET_RATE_PARENT,
2840 .ops = &clk_branch2_ops,
2845 static struct clk_branch venus0_core0_vcodec_clk = {
2848 .enable_reg = 0x1048,
2849 .enable_mask = BIT(0),
2850 .hw.init = &(struct clk_init_data){
2851 .name = "venus0_core0_vcodec_clk",
2852 .parent_names = (const char *[]){
2856 .flags = CLK_SET_RATE_PARENT,
2857 .ops = &clk_branch2_ops,
2862 static struct clk_branch venus0_core1_vcodec_clk = {
2865 .enable_reg = 0x104c,
2866 .enable_mask = BIT(0),
2867 .hw.init = &(struct clk_init_data){
2868 .name = "venus0_core1_vcodec_clk",
2869 .parent_names = (const char *[]){
2873 .flags = CLK_SET_RATE_PARENT,
2874 .ops = &clk_branch2_ops,
2879 static struct clk_branch venus0_ocmemnoc_clk = {
2882 .enable_reg = 0x1038,
2883 .enable_mask = BIT(0),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "venus0_ocmemnoc_clk",
2886 .parent_names = (const char *[]){
2890 .flags = CLK_SET_RATE_PARENT,
2891 .ops = &clk_branch2_ops,
2896 static struct clk_branch venus0_vcodec0_clk = {
2899 .enable_reg = 0x1028,
2900 .enable_mask = BIT(0),
2901 .hw.init = &(struct clk_init_data){
2902 .name = "venus0_vcodec0_clk",
2903 .parent_names = (const char *[]){
2907 .flags = CLK_SET_RATE_PARENT,
2908 .ops = &clk_branch2_ops,
2913 static struct clk_branch vpu_ahb_clk = {
2916 .enable_reg = 0x1430,
2917 .enable_mask = BIT(0),
2918 .hw.init = &(struct clk_init_data){
2919 .name = "vpu_ahb_clk",
2920 .parent_names = (const char *[]){
2924 .flags = CLK_SET_RATE_PARENT,
2925 .ops = &clk_branch2_ops,
2930 static struct clk_branch vpu_axi_clk = {
2933 .enable_reg = 0x143c,
2934 .enable_mask = BIT(0),
2935 .hw.init = &(struct clk_init_data){
2936 .name = "vpu_axi_clk",
2937 .parent_names = (const char *[]){
2941 .flags = CLK_SET_RATE_PARENT,
2942 .ops = &clk_branch2_ops,
2947 static struct clk_branch vpu_bus_clk = {
2950 .enable_reg = 0x1440,
2951 .enable_mask = BIT(0),
2952 .hw.init = &(struct clk_init_data){
2953 .name = "vpu_bus_clk",
2954 .parent_names = (const char *[]){
2958 .flags = CLK_SET_RATE_PARENT,
2959 .ops = &clk_branch2_ops,
2964 static struct clk_branch vpu_cxo_clk = {
2967 .enable_reg = 0x1434,
2968 .enable_mask = BIT(0),
2969 .hw.init = &(struct clk_init_data){
2970 .name = "vpu_cxo_clk",
2971 .parent_names = (const char *[]){ "xo" },
2973 .flags = CLK_SET_RATE_PARENT,
2974 .ops = &clk_branch2_ops,
2979 static struct clk_branch vpu_maple_clk = {
2982 .enable_reg = 0x142c,
2983 .enable_mask = BIT(0),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "vpu_maple_clk",
2986 .parent_names = (const char *[]){
2990 .flags = CLK_SET_RATE_PARENT,
2991 .ops = &clk_branch2_ops,
2996 static struct clk_branch vpu_sleep_clk = {
2999 .enable_reg = 0x1438,
3000 .enable_mask = BIT(0),
3001 .hw.init = &(struct clk_init_data){
3002 .name = "vpu_sleep_clk",
3003 .parent_names = (const char *[]){
3007 .flags = CLK_SET_RATE_PARENT,
3008 .ops = &clk_branch2_ops,
3013 static struct clk_branch vpu_vdp_clk = {
3016 .enable_reg = 0x1428,
3017 .enable_mask = BIT(0),
3018 .hw.init = &(struct clk_init_data){
3019 .name = "vpu_vdp_clk",
3020 .parent_names = (const char *[]){
3024 .flags = CLK_SET_RATE_PARENT,
3025 .ops = &clk_branch2_ops,
3030 static const struct pll_config mmpll1_config = {
3035 .vco_mask = 0x3 << 20,
3037 .pre_div_mask = 0x7 << 12,
3038 .post_div_val = 0x0,
3039 .post_div_mask = 0x3 << 8,
3040 .mn_ena_mask = BIT(24),
3041 .main_output_mask = BIT(0),
3044 static const struct pll_config mmpll3_config = {
3049 .vco_mask = 0x3 << 20,
3051 .pre_div_mask = 0x7 << 12,
3052 .post_div_val = 0x0,
3053 .post_div_mask = 0x3 << 8,
3054 .mn_ena_mask = BIT(24),
3055 .main_output_mask = BIT(0),
3056 .aux_output_mask = BIT(1),
3059 static struct gdsc venus0_gdsc = {
3064 .pwrsts = PWRSTS_OFF_ON,
3067 static struct gdsc venus0_core0_gdsc = {
3070 .name = "venus0_core0",
3072 .pwrsts = PWRSTS_OFF_ON,
3075 static struct gdsc venus0_core1_gdsc = {
3078 .name = "venus0_core1",
3080 .pwrsts = PWRSTS_OFF_ON,
3083 static struct gdsc mdss_gdsc = {
3085 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3090 .pwrsts = PWRSTS_OFF_ON,
3093 static struct gdsc camss_jpeg_gdsc = {
3096 .name = "camss_jpeg",
3098 .pwrsts = PWRSTS_OFF_ON,
3101 static struct gdsc camss_vfe_gdsc = {
3103 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3106 .name = "camss_vfe",
3108 .pwrsts = PWRSTS_OFF_ON,
3111 static struct gdsc oxili_gdsc = {
3113 .cxcs = (unsigned int []){ 0x4028 },
3118 .pwrsts = PWRSTS_OFF_ON,
3121 static struct gdsc oxilicx_gdsc = {
3126 .pwrsts = PWRSTS_OFF_ON,
3129 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3130 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3131 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3132 [MMPLL0] = &mmpll0.clkr,
3133 [MMPLL0_VOTE] = &mmpll0_vote,
3134 [MMPLL1] = &mmpll1.clkr,
3135 [MMPLL1_VOTE] = &mmpll1_vote,
3136 [MMPLL2] = &mmpll2.clkr,
3137 [MMPLL3] = &mmpll3.clkr,
3138 [MMPLL4] = &mmpll4.clkr,
3139 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3140 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3141 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3142 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3143 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3144 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3145 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3146 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3147 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3148 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3149 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3150 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3151 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3152 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3153 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3154 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3155 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3156 [VP_CLK_SRC] = &vp_clk_src.clkr,
3157 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3158 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3159 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3160 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3161 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3162 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3163 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3164 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3165 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3166 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3167 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3168 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3169 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3170 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3171 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3172 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3173 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3174 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3175 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3176 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3177 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3178 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3179 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3180 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3181 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3182 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3183 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3184 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3185 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3186 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3187 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3188 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3189 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3190 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3191 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3192 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3193 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3194 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3195 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3196 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3197 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3198 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3199 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3200 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3201 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3202 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3203 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3204 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3205 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3206 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3207 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3208 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3209 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3210 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3211 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3212 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3213 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3214 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3215 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3216 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3217 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3218 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3219 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3220 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3221 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3222 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3223 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3224 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3225 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3226 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3227 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3228 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3229 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3230 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3231 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3232 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3233 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3234 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3235 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3236 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3237 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3238 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3239 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3240 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3241 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3242 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3243 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3244 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3245 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3246 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3247 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3248 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3249 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3250 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3251 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3252 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3253 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3254 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3255 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3256 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3257 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3258 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3259 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3260 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3261 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3262 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3263 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3264 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3265 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3266 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3267 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3268 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3269 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3270 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3271 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3272 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3273 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3274 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3275 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3276 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3277 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3278 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3279 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3280 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3281 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3282 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3283 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3284 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3285 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3286 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3287 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3288 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3289 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3290 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3291 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3292 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3293 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3294 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3297 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3298 [MMSS_SPDM_RESET] = { 0x0200 },
3299 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3300 [VENUS0_RESET] = { 0x1020 },
3301 [VPU_RESET] = { 0x1400 },
3302 [MDSS_RESET] = { 0x2300 },
3303 [AVSYNC_RESET] = { 0x2400 },
3304 [CAMSS_PHY0_RESET] = { 0x3020 },
3305 [CAMSS_PHY1_RESET] = { 0x3050 },
3306 [CAMSS_PHY2_RESET] = { 0x3080 },
3307 [CAMSS_CSI0_RESET] = { 0x30b0 },
3308 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3309 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3310 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3311 [CAMSS_CSI1_RESET] = { 0x3120 },
3312 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3313 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3314 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3315 [CAMSS_CSI2_RESET] = { 0x3180 },
3316 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3317 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3318 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3319 [CAMSS_CSI3_RESET] = { 0x31e0 },
3320 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3321 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3322 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3323 [CAMSS_ISPIF_RESET] = { 0x3220 },
3324 [CAMSS_CCI_RESET] = { 0x3340 },
3325 [CAMSS_MCLK0_RESET] = { 0x3380 },
3326 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3327 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3328 [CAMSS_MCLK3_RESET] = { 0x3410 },
3329 [CAMSS_GP0_RESET] = { 0x3440 },
3330 [CAMSS_GP1_RESET] = { 0x3470 },
3331 [CAMSS_TOP_RESET] = { 0x3480 },
3332 [CAMSS_AHB_RESET] = { 0x3488 },
3333 [CAMSS_MICRO_RESET] = { 0x3490 },
3334 [CAMSS_JPEG_RESET] = { 0x35a0 },
3335 [CAMSS_VFE_RESET] = { 0x36a0 },
3336 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3337 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3338 [OXILI_RESET] = { 0x4020 },
3339 [OXILICX_RESET] = { 0x4030 },
3340 [OCMEMCX_RESET] = { 0x4050 },
3341 [MMSS_RBCRP_RESET] = { 0x4080 },
3342 [MMSSNOCAHB_RESET] = { 0x5020 },
3343 [MMSSNOCAXI_RESET] = { 0x5060 },
3346 static struct gdsc *mmcc_apq8084_gdscs[] = {
3347 [VENUS0_GDSC] = &venus0_gdsc,
3348 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3349 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3350 [MDSS_GDSC] = &mdss_gdsc,
3351 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3352 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3353 [OXILI_GDSC] = &oxili_gdsc,
3354 [OXILICX_GDSC] = &oxilicx_gdsc,
3357 static const struct regmap_config mmcc_apq8084_regmap_config = {
3361 .max_register = 0x5104,
3365 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3366 .config = &mmcc_apq8084_regmap_config,
3367 .clks = mmcc_apq8084_clocks,
3368 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3369 .resets = mmcc_apq8084_resets,
3370 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3371 .gdscs = mmcc_apq8084_gdscs,
3372 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
3375 static const struct of_device_id mmcc_apq8084_match_table[] = {
3376 { .compatible = "qcom,mmcc-apq8084" },
3379 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3381 static int mmcc_apq8084_probe(struct platform_device *pdev)
3384 struct regmap *regmap;
3386 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3390 regmap = dev_get_regmap(&pdev->dev, NULL);
3391 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3392 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3397 static struct platform_driver mmcc_apq8084_driver = {
3398 .probe = mmcc_apq8084_probe,
3400 .name = "mmcc-apq8084",
3401 .of_match_table = mmcc_apq8084_match_table,
3404 module_platform_driver(mmcc_apq8084_driver);
3406 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3407 MODULE_LICENSE("GPL v2");
3408 MODULE_ALIAS("platform:mmcc-apq8084");