1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
15 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
18 #include "clk-regmap.h"
21 #include "clk-branch.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-regmap-mux.h"
26 static struct clk_pll pll4 = {
34 .clkr.hw.init = &(struct clk_init_data){
36 .parent_data = &(const struct clk_parent_data) {
37 .fw_name = "pxo", .name = "pxo_board",
44 static const struct pll_config pll4_config = {
49 .vco_mask = BIT(17) | BIT(16),
51 .pre_div_mask = BIT(19),
53 .post_div_mask = BIT(21) | BIT(20),
54 .mn_ena_mask = BIT(22),
55 .main_output_mask = BIT(23),
63 static const struct parent_map lcc_pxo_pll4_map[] = {
68 static const struct clk_parent_data lcc_pxo_pll4[] = {
69 { .fw_name = "pxo", .name = "pxo_board" },
70 { .fw_name = "pll4_vote", .name = "pll4_vote" },
73 static struct freq_tbl clk_tbl_aif_mi2s[] = {
74 { 1024000, P_PLL4, 4, 1, 96 },
75 { 1411200, P_PLL4, 4, 2, 139 },
76 { 1536000, P_PLL4, 4, 1, 64 },
77 { 2048000, P_PLL4, 4, 1, 48 },
78 { 2116800, P_PLL4, 4, 2, 93 },
79 { 2304000, P_PLL4, 4, 2, 85 },
80 { 2822400, P_PLL4, 4, 6, 209 },
81 { 3072000, P_PLL4, 4, 1, 32 },
82 { 3175200, P_PLL4, 4, 1, 31 },
83 { 4096000, P_PLL4, 4, 1, 24 },
84 { 4233600, P_PLL4, 4, 9, 209 },
85 { 4608000, P_PLL4, 4, 3, 64 },
86 { 5644800, P_PLL4, 4, 12, 209 },
87 { 6144000, P_PLL4, 4, 1, 16 },
88 { 6350400, P_PLL4, 4, 2, 31 },
89 { 8192000, P_PLL4, 4, 1, 12 },
90 { 8467200, P_PLL4, 4, 18, 209 },
91 { 9216000, P_PLL4, 4, 3, 32 },
92 { 11289600, P_PLL4, 4, 24, 209 },
93 { 12288000, P_PLL4, 4, 1, 8 },
94 { 12700800, P_PLL4, 4, 27, 209 },
95 { 13824000, P_PLL4, 4, 9, 64 },
96 { 16384000, P_PLL4, 4, 1, 6 },
97 { 16934400, P_PLL4, 4, 41, 238 },
98 { 18432000, P_PLL4, 4, 3, 16 },
99 { 22579200, P_PLL4, 2, 24, 209 },
100 { 24576000, P_PLL4, 4, 1, 4 },
101 { 27648000, P_PLL4, 4, 9, 32 },
102 { 33868800, P_PLL4, 4, 41, 119 },
103 { 36864000, P_PLL4, 4, 3, 8 },
104 { 45158400, P_PLL4, 1, 24, 209 },
105 { 49152000, P_PLL4, 4, 1, 2 },
106 { 50803200, P_PLL4, 1, 27, 209 },
110 static struct clk_rcg mi2s_osr_src = {
115 .mnctr_reset_bit = 7,
116 .mnctr_mode_shift = 5,
127 .parent_map = lcc_pxo_pll4_map,
129 .freq_tbl = clk_tbl_aif_mi2s,
132 .enable_mask = BIT(9),
133 .hw.init = &(struct clk_init_data){
134 .name = "mi2s_osr_src",
135 .parent_data = lcc_pxo_pll4,
136 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
138 .flags = CLK_SET_RATE_GATE,
143 static struct clk_branch mi2s_osr_clk = {
146 .halt_check = BRANCH_HALT_ENABLE,
149 .enable_mask = BIT(17),
150 .hw.init = &(struct clk_init_data){
151 .name = "mi2s_osr_clk",
152 .parent_hws = (const struct clk_hw*[]) {
153 &mi2s_osr_src.clkr.hw,
156 .ops = &clk_branch_ops,
157 .flags = CLK_SET_RATE_PARENT,
162 static struct clk_regmap_div mi2s_div_clk = {
167 .hw.init = &(struct clk_init_data){
168 .name = "mi2s_div_clk",
169 .parent_hws = (const struct clk_hw*[]) {
170 &mi2s_osr_src.clkr.hw,
173 .ops = &clk_regmap_div_ops,
178 static struct clk_branch mi2s_bit_div_clk = {
181 .halt_check = BRANCH_HALT_ENABLE,
184 .enable_mask = BIT(15),
185 .hw.init = &(struct clk_init_data){
186 .name = "mi2s_bit_div_clk",
187 .parent_hws = (const struct clk_hw*[]) {
188 &mi2s_div_clk.clkr.hw,
191 .ops = &clk_branch_ops,
192 .flags = CLK_SET_RATE_PARENT,
197 static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
198 { .hw = &mi2s_bit_div_clk.clkr.hw, },
199 { .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
202 static struct clk_regmap_mux mi2s_bit_clk = {
207 .hw.init = &(struct clk_init_data){
208 .name = "mi2s_bit_clk",
209 .parent_data = lcc_mi2s_bit_div_codec_clk,
210 .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
211 .ops = &clk_regmap_mux_closest_ops,
212 .flags = CLK_SET_RATE_PARENT,
217 static struct freq_tbl clk_tbl_pcm[] = {
218 { 64000, P_PLL4, 4, 1, 1536 },
219 { 128000, P_PLL4, 4, 1, 768 },
220 { 256000, P_PLL4, 4, 1, 384 },
221 { 512000, P_PLL4, 4, 1, 192 },
222 { 1024000, P_PLL4, 4, 1, 96 },
223 { 2048000, P_PLL4, 4, 1, 48 },
227 static struct clk_rcg pcm_src = {
232 .mnctr_reset_bit = 7,
233 .mnctr_mode_shift = 5,
244 .parent_map = lcc_pxo_pll4_map,
246 .freq_tbl = clk_tbl_pcm,
249 .enable_mask = BIT(9),
250 .hw.init = &(struct clk_init_data){
252 .parent_data = lcc_pxo_pll4,
253 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
255 .flags = CLK_SET_RATE_GATE,
260 static struct clk_branch pcm_clk_out = {
263 .halt_check = BRANCH_HALT_ENABLE,
266 .enable_mask = BIT(11),
267 .hw.init = &(struct clk_init_data){
268 .name = "pcm_clk_out",
269 .parent_hws = (const struct clk_hw*[]) {
273 .ops = &clk_branch_ops,
274 .flags = CLK_SET_RATE_PARENT,
279 static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
280 { .hw = &pcm_clk_out.clkr.hw, },
281 { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
284 static struct clk_regmap_mux pcm_clk = {
289 .hw.init = &(struct clk_init_data){
291 .parent_data = lcc_pcm_clk_out_codec_clk,
292 .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
293 .ops = &clk_regmap_mux_closest_ops,
294 .flags = CLK_SET_RATE_PARENT,
299 static struct freq_tbl clk_tbl_aif_osr[] = {
300 { 2822400, P_PLL4, 1, 147, 20480 },
301 { 4096000, P_PLL4, 1, 1, 96 },
302 { 5644800, P_PLL4, 1, 147, 10240 },
303 { 6144000, P_PLL4, 1, 1, 64 },
304 { 11289600, P_PLL4, 1, 147, 5120 },
305 { 12288000, P_PLL4, 1, 1, 32 },
306 { 22579200, P_PLL4, 1, 147, 2560 },
307 { 24576000, P_PLL4, 1, 1, 16 },
311 static struct clk_rcg spdif_src = {
316 .mnctr_reset_bit = 7,
317 .mnctr_mode_shift = 5,
328 .parent_map = lcc_pxo_pll4_map,
330 .freq_tbl = clk_tbl_aif_osr,
333 .enable_mask = BIT(9),
334 .hw.init = &(struct clk_init_data){
336 .parent_data = lcc_pxo_pll4,
337 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
339 .flags = CLK_SET_RATE_GATE,
344 static struct clk_branch spdif_clk = {
347 .halt_check = BRANCH_HALT_ENABLE,
350 .enable_mask = BIT(12),
351 .hw.init = &(struct clk_init_data){
353 .parent_hws = (const struct clk_hw*[]) {
357 .ops = &clk_branch_ops,
358 .flags = CLK_SET_RATE_PARENT,
363 static struct freq_tbl clk_tbl_ahbix[] = {
364 { 131072000, P_PLL4, 1, 1, 3 },
368 static struct clk_rcg ahbix_clk = {
373 .mnctr_reset_bit = 7,
374 .mnctr_mode_shift = 5,
385 .parent_map = lcc_pxo_pll4_map,
387 .freq_tbl = clk_tbl_ahbix,
390 .enable_mask = BIT(11),
391 .hw.init = &(struct clk_init_data){
393 .parent_data = lcc_pxo_pll4,
394 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
395 .ops = &clk_rcg_lcc_ops,
400 static struct clk_regmap *lcc_ipq806x_clks[] = {
402 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
403 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
404 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
405 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
406 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
407 [PCM_SRC] = &pcm_src.clkr,
408 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
409 [PCM_CLK] = &pcm_clk.clkr,
410 [SPDIF_SRC] = &spdif_src.clkr,
411 [SPDIF_CLK] = &spdif_clk.clkr,
412 [AHBIX_CLK] = &ahbix_clk.clkr,
415 static const struct qcom_reset_map lcc_ipq806x_resets[] = {
416 [LCC_PCM_RESET] = { 0x54, 13 },
419 static const struct regmap_config lcc_ipq806x_regmap_config = {
423 .max_register = 0xfc,
427 static const struct qcom_cc_desc lcc_ipq806x_desc = {
428 .config = &lcc_ipq806x_regmap_config,
429 .clks = lcc_ipq806x_clks,
430 .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
431 .resets = lcc_ipq806x_resets,
432 .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
435 static const struct of_device_id lcc_ipq806x_match_table[] = {
436 { .compatible = "qcom,lcc-ipq8064" },
439 MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
441 static int lcc_ipq806x_probe(struct platform_device *pdev)
444 struct regmap *regmap;
446 regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
448 return PTR_ERR(regmap);
450 /* Configure the rate of PLL4 if the bootloader hasn't already */
451 regmap_read(regmap, 0x0, &val);
453 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
454 /* Enable PLL4 source on the LPASS Primary PLL Mux */
455 regmap_write(regmap, 0xc4, 0x1);
457 return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
460 static struct platform_driver lcc_ipq806x_driver = {
461 .probe = lcc_ipq806x_probe,
463 .name = "lcc-ipq806x",
464 .of_match_table = lcc_ipq806x_match_table,
467 module_platform_driver(lcc_ipq806x_driver);
469 MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
470 MODULE_LICENSE("GPL v2");
471 MODULE_ALIAS("platform:lcc-ipq806x");