1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/jiffies.h>
11 #include <linux/kernel.h>
12 #include <linux/ktime.h>
13 #include <linux/pm_domain.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset-controller.h>
17 #include <linux/slab.h>
20 #define PWR_ON_MASK BIT(31)
21 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
22 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
23 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
24 #define SW_OVERRIDE_MASK BIT(2)
25 #define HW_CONTROL_MASK BIT(1)
26 #define SW_COLLAPSE_MASK BIT(0)
27 #define GMEM_CLAMP_IO_MASK BIT(0)
28 #define GMEM_RESET_MASK BIT(4)
31 #define GDSC_POWER_UP_COMPLETE BIT(16)
32 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
33 #define GDSC_RETAIN_FF_ENABLE BIT(11)
34 #define CFG_GDSCR_OFFSET 0x4
36 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
37 #define EN_REST_WAIT_VAL 0x2
38 #define EN_FEW_WAIT_VAL 0x8
39 #define CLK_DIS_WAIT_VAL 0x2
41 /* Transition delay shifts */
42 #define EN_REST_WAIT_SHIFT 20
43 #define EN_FEW_WAIT_SHIFT 16
44 #define CLK_DIS_WAIT_SHIFT 12
46 #define RETAIN_MEM BIT(14)
47 #define RETAIN_PERIPH BIT(13)
49 #define TIMEOUT_US 500
51 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
58 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
59 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
65 if (sc->flags & POLL_CFG_GDSCR)
66 reg = sc->gdscr + CFG_GDSCR_OFFSET;
67 else if (sc->gds_hw_ctrl)
68 reg = sc->gds_hw_ctrl;
72 ret = regmap_read(sc->regmap, reg, &val);
76 if (sc->flags & POLL_CFG_GDSCR) {
79 return !!(val & GDSC_POWER_UP_COMPLETE);
81 return !!(val & GDSC_POWER_DOWN_COMPLETE);
87 return !!(val & PWR_ON_MASK);
89 return !(val & PWR_ON_MASK);
95 static int gdsc_hwctrl(struct gdsc *sc, bool en)
97 u32 val = en ? HW_CONTROL_MASK : 0;
99 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
102 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
108 if (gdsc_check_status(sc, status))
110 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
112 if (gdsc_check_status(sc, status))
118 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
121 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
123 if (status == GDSC_ON && sc->rsupply) {
124 ret = regulator_enable(sc->rsupply);
129 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
133 /* If disabling votable gdscs, don't poll on status */
134 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
136 * Add a short delay here to ensure that an enable
137 * right after it was disabled does not put it in an
144 if (sc->gds_hw_ctrl) {
146 * The gds hw controller asserts/de-asserts the status bit soon
147 * after it receives a power on/off request from a master.
148 * The controller then takes around 8 xo cycles to start its
149 * internal state machine and update the status bit. During
150 * this time, the status bit does not reflect the true status
152 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
153 * and polling the status bit.
158 ret = gdsc_poll_status(sc, status);
159 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
161 if (!ret && status == GDSC_OFF && sc->rsupply) {
162 ret = regulator_disable(sc->rsupply);
170 static inline int gdsc_deassert_reset(struct gdsc *sc)
174 for (i = 0; i < sc->reset_count; i++)
175 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
179 static inline int gdsc_assert_reset(struct gdsc *sc)
183 for (i = 0; i < sc->reset_count; i++)
184 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
188 static inline void gdsc_force_mem_on(struct gdsc *sc)
191 u32 mask = RETAIN_MEM;
193 if (!(sc->flags & NO_RET_PERIPH))
194 mask |= RETAIN_PERIPH;
196 for (i = 0; i < sc->cxc_count; i++)
197 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
200 static inline void gdsc_clear_mem_on(struct gdsc *sc)
203 u32 mask = RETAIN_MEM;
205 if (!(sc->flags & NO_RET_PERIPH))
206 mask |= RETAIN_PERIPH;
208 for (i = 0; i < sc->cxc_count; i++)
209 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
212 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
214 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
215 GMEM_CLAMP_IO_MASK, 0);
218 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
220 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
221 GMEM_CLAMP_IO_MASK, 1);
224 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
226 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
229 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
233 static void gdsc_retain_ff_on(struct gdsc *sc)
235 u32 mask = GDSC_RETAIN_FF_ENABLE;
237 regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
240 static int gdsc_enable(struct generic_pm_domain *domain)
242 struct gdsc *sc = domain_to_gdsc(domain);
245 if (sc->pwrsts == PWRSTS_ON)
246 return gdsc_deassert_reset(sc);
248 if (sc->flags & SW_RESET) {
249 gdsc_assert_reset(sc);
251 gdsc_deassert_reset(sc);
254 if (sc->flags & CLAMP_IO) {
255 if (sc->flags & AON_RESET)
256 gdsc_assert_reset_aon(sc);
257 gdsc_deassert_clamp_io(sc);
260 ret = gdsc_toggle_logic(sc, GDSC_ON);
264 if (sc->pwrsts & PWRSTS_OFF)
265 gdsc_force_mem_on(sc);
268 * If clocks to this power domain were already on, they will take an
269 * additional 4 clock cycles to re-enable after the power domain is
270 * enabled. Delay to account for this. A delay is also needed to ensure
271 * clocks are not enabled within 400ns of enabling power to the
276 /* Turn on HW trigger mode if supported */
277 if (sc->flags & HW_CTRL) {
278 ret = gdsc_hwctrl(sc, true);
282 * Wait for the GDSC to go through a power down and
283 * up cycle. In case a firmware ends up polling status
284 * bits for the gdsc, it might read an 'on' status before
285 * the GDSC can finish the power cycle.
286 * We wait 1us before returning to ensure the firmware
287 * can't immediately poll the status bits.
292 if (sc->flags & RETAIN_FF_ENABLE)
293 gdsc_retain_ff_on(sc);
298 static int gdsc_disable(struct generic_pm_domain *domain)
300 struct gdsc *sc = domain_to_gdsc(domain);
303 if (sc->pwrsts == PWRSTS_ON)
304 return gdsc_assert_reset(sc);
306 /* Turn off HW trigger mode if supported */
307 if (sc->flags & HW_CTRL) {
308 ret = gdsc_hwctrl(sc, false);
312 * Wait for the GDSC to go through a power down and
313 * up cycle. In case we end up polling status
314 * bits for the gdsc before the power cycle is completed
315 * it might read an 'on' status wrongly.
319 ret = gdsc_poll_status(sc, GDSC_ON);
324 if (sc->pwrsts & PWRSTS_OFF)
325 gdsc_clear_mem_on(sc);
327 ret = gdsc_toggle_logic(sc, GDSC_OFF);
331 if (sc->flags & CLAMP_IO)
332 gdsc_assert_clamp_io(sc);
337 static int gdsc_init(struct gdsc *sc)
343 * Disable HW trigger: collapse/restore occur based on registers writes.
344 * Disable SW override: Use hardware state-machine for sequencing.
345 * Configure wait time between states.
347 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
348 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
350 if (!sc->en_rest_wait_val)
351 sc->en_rest_wait_val = EN_REST_WAIT_VAL;
352 if (!sc->en_few_wait_val)
353 sc->en_few_wait_val = EN_FEW_WAIT_VAL;
354 if (!sc->clk_dis_wait_val)
355 sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
357 val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
358 sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
359 sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
361 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
365 /* Force gdsc ON if only ON state is supported */
366 if (sc->pwrsts == PWRSTS_ON) {
367 ret = gdsc_toggle_logic(sc, GDSC_ON);
372 on = gdsc_check_status(sc, GDSC_ON);
377 /* The regulator must be on, sync the kernel state */
379 ret = regulator_enable(sc->rsupply);
385 * Votable GDSCs can be ON due to Vote from other masters.
386 * If a Votable GDSC is ON, make sure we have a Vote.
388 if (sc->flags & VOTABLE) {
389 ret = regmap_update_bits(sc->regmap, sc->gdscr,
390 SW_COLLAPSE_MASK, val);
395 /* Turn on HW trigger mode if supported */
396 if (sc->flags & HW_CTRL) {
397 ret = gdsc_hwctrl(sc, true);
403 * Make sure the retain bit is set if the GDSC is already on,
404 * otherwise we end up turning off the GDSC and destroying all
405 * the register contents that we thought we were saving.
407 if (sc->flags & RETAIN_FF_ENABLE)
408 gdsc_retain_ff_on(sc);
409 } else if (sc->flags & ALWAYS_ON) {
410 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
411 gdsc_enable(&sc->pd);
415 if (on || (sc->pwrsts & PWRSTS_RET))
416 gdsc_force_mem_on(sc);
418 gdsc_clear_mem_on(sc);
420 if (sc->flags & ALWAYS_ON)
421 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
422 if (!sc->pd.power_off)
423 sc->pd.power_off = gdsc_disable;
424 if (!sc->pd.power_on)
425 sc->pd.power_on = gdsc_enable;
426 pm_genpd_init(&sc->pd, NULL, !on);
431 int gdsc_register(struct gdsc_desc *desc,
432 struct reset_controller_dev *rcdev, struct regmap *regmap)
435 struct genpd_onecell_data *data;
436 struct device *dev = desc->dev;
437 struct gdsc **scs = desc->scs;
438 size_t num = desc->num;
440 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
444 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
449 for (i = 0; i < num; i++) {
450 if (!scs[i] || !scs[i]->supply)
453 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
454 if (IS_ERR(scs[i]->rsupply))
455 return PTR_ERR(scs[i]->rsupply);
458 data->num_domains = num;
459 for (i = 0; i < num; i++) {
462 scs[i]->regmap = regmap;
463 scs[i]->rcdev = rcdev;
464 ret = gdsc_init(scs[i]);
467 data->domains[i] = &scs[i]->pd;
471 for (i = 0; i < num; i++) {
475 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
478 return of_genpd_add_provider_onecell(dev->of_node, data);
481 void gdsc_unregister(struct gdsc_desc *desc)
484 struct device *dev = desc->dev;
485 struct gdsc **scs = desc->scs;
486 size_t num = desc->num;
488 /* Remove subdomains */
489 for (i = 0; i < num; i++) {
493 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
495 of_genpd_del_provider(dev->of_node);
499 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
500 * running in the CX domain so the CPU doesn't need to know anything about the
501 * GX domain EXCEPT....
503 * Hardware constraints dictate that the GX be powered down before the CX. If
504 * the GMU crashes it could leave the GX on. In order to successfully bring back
505 * the device the CPU needs to disable the GX headswitch. There being no sane
506 * way to reach in and touch that register from deep inside the GPU driver we
507 * need to set up the infrastructure to be able to ensure that the GPU can
508 * ensure that the GX is off during this super special case. We do this by
509 * defining a GX gdsc with a dummy enable function and a "default" disable
512 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
513 * driver. During power up, nothing will happen from the CPU (and the GMU will
514 * power up normally but during power down this will ensure that the GX domain
515 * is *really* off - this gives us a semi standard way of doing what we need.
517 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
519 /* Do nothing but give genpd the impression that we were successful */
522 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);