drivers/clk/qcom/gcc-sm7150.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com>
   5  * Copyright (c) 2023, David Wronek <davidwronek@gmail.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/err.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <dt-bindings/clock/qcom,sm7150-gcc.h>
  17
  18 #include "clk-alpha-pll.h"
  19 #include "clk-branch.h"
  20 #include "clk-rcg.h"
  21 #include "clk-regmap.h"
  22 #include "common.h"
  23 #include "gdsc.h"
  24 #include "reset.h"
  25
  26 enum {
  27         DT_BI_TCXO,
  28         DT_BI_TCXO_AO,
  29         DT_SLEEP_CLK
  30 };
  31
  32 enum {
  33         P_BI_TCXO,
  34         P_GPLL0_OUT_EVEN,
  35         P_GPLL0_OUT_MAIN,
  36         P_GPLL6_OUT_MAIN,
  37         P_GPLL7_OUT_MAIN,
  38         P_SLEEP_CLK,
  39 };
  40
  41 static struct clk_alpha_pll gpll0 = {
  42         .offset = 0x0,
  43         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  44         .clkr = {
  45                 .enable_reg = 0x52000,
  46                 .enable_mask = BIT(0),
  47                 .hw.init = &(struct clk_init_data){
  48                         .name = "gpll0",
  49                         .parent_data = &(const struct clk_parent_data){
  50                                 .index = DT_BI_TCXO,
  51                         },
  52                         .num_parents = 1,
  53                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  54                 },
  55         },
  56 };
  57
  58 static const struct clk_div_table post_div_table_fabia_even[] = {
  59         { 0x0, 1 },
  60         { 0x1, 2 },
  61         { 0x3, 4 },
  62         { 0x7, 8 },
  63         { }
  64 };
  65
  66 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  67         .offset = 0x0,
  68         .post_div_shift = 8,
  69         .post_div_table = post_div_table_fabia_even,
  70         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
  71         .width = 4,
  72         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  73         .clkr.hw.init = &(struct clk_init_data){
  74                 .name = "gpll0_out_even",
  75                 .parent_hws = (const struct clk_hw*[]){
  76                         &gpll0.clkr.hw,
  77                 },
  78                 .num_parents = 1,
  79                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  80         },
  81 };
  82
  83 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
  84         .mult = 1,
  85         .div = 2,
  86         .hw.init = &(struct clk_init_data){
  87                 .name = "gcc_pll0_main_div_cdiv",
  88                 .parent_hws = (const struct clk_hw*[]){
  89                         &gpll0.clkr.hw,
  90                 },
  91                 .num_parents = 1,
  92                 .ops = &clk_fixed_factor_ops,
  93         },
  94 };
  95
  96 static struct clk_alpha_pll gpll6 = {
  97         .offset = 0x13000,
  98         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  99         .clkr = {
 100                 .enable_reg = 0x52000,
 101                 .enable_mask = BIT(6),
 102                 .hw.init = &(struct clk_init_data){
 103                         .name = "gpll6",
 104                         .parent_data = &(const struct clk_parent_data){
 105                                 .index = DT_BI_TCXO,
 106                         },
 107                         .num_parents = 1,
 108                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 109                 },
 110         },
 111 };
 112
 113 static struct clk_alpha_pll gpll7 = {
 114         .offset = 0x27000,
 115         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 116         .clkr = {
 117                 .enable_reg = 0x52000,
 118                 .enable_mask = BIT(7),
 119                 .hw.init = &(struct clk_init_data){
 120                         .name = "gpll7",
 121                         .parent_data = &(const struct clk_parent_data){
 122                                 .index = DT_BI_TCXO,
 123                         },
 124                         .num_parents = 1,
 125                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 126                 },
 127         },
 128 };
 129
 130 static const struct parent_map gcc_parent_map_0[] = {
 131         { P_BI_TCXO, 0 },
 132         { P_GPLL0_OUT_MAIN, 1 },
 133         { P_GPLL0_OUT_EVEN, 6 },
 134 };
 135
 136 static const struct clk_parent_data gcc_parent_data_0[] = {
 137         { .index = DT_BI_TCXO },
 138         { .hw = &gpll0.clkr.hw },
 139         { .hw = &gpll0_out_even.clkr.hw },
 140 };
 141 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
 142         { .index = DT_BI_TCXO_AO },
 143         { .hw = &gpll0.clkr.hw },
 144         { .hw = &gpll0_out_even.clkr.hw },
 145 };
 146
 147 static const struct parent_map gcc_parent_map_1[] = {
 148         { P_BI_TCXO, 0 },
 149         { P_GPLL0_OUT_MAIN, 1 },
 150         { P_SLEEP_CLK, 5 },
 151         { P_GPLL0_OUT_EVEN, 6 },
 152 };
 153
 154 static const struct clk_parent_data gcc_parent_data_1[] = {
 155         { .index = DT_BI_TCXO },
 156         { .hw = &gpll0.clkr.hw },
 157         { .index = DT_SLEEP_CLK },
 158         { .hw = &gpll0_out_even.clkr.hw },
 159 };
 160
 161 static const struct parent_map gcc_parent_map_2[] = {
 162         { P_BI_TCXO, 0 },
 163         { P_GPLL0_OUT_MAIN, 1 },
 164 };
 165
 166 static const struct clk_parent_data gcc_parent_data_2[] = {
 167         { .index = DT_BI_TCXO },
 168         { .hw = &gpll0.clkr.hw },
 169 };
 170
 171 static const struct clk_parent_data gcc_parent_data_2_ao[] = {
 172         { .index = DT_BI_TCXO_AO },
 173         { .hw = &gpll0.clkr.hw },
 174 };
 175
 176 static const struct parent_map gcc_parent_map_3[] = {
 177         { P_BI_TCXO, 0 },
 178         { P_SLEEP_CLK, 5 },
 179 };
 180
 181 static const struct clk_parent_data gcc_parent_data_3[] = {
 182         { .index = DT_BI_TCXO },
 183         { .index = DT_SLEEP_CLK },
 184 };
 185
 186 static const struct parent_map gcc_parent_map_4[] = {
 187         { P_BI_TCXO, 0 },
 188 };
 189
 190 static const struct clk_parent_data gcc_parent_data_4[] = {
 191         { .index = DT_BI_TCXO },
 192 };
 193
 194 static const struct parent_map gcc_parent_map_5[] = {
 195         { P_BI_TCXO, 0 },
 196         { P_GPLL0_OUT_MAIN, 1 },
 197         { P_GPLL6_OUT_MAIN, 2 },
 198         { P_GPLL0_OUT_EVEN, 6 },
 199 };
 200
 201 static const struct clk_parent_data gcc_parent_data_5[] = {
 202         { .index = DT_BI_TCXO },
 203         { .hw = &gpll0.clkr.hw },
 204         { .hw = &gpll6.clkr.hw },
 205         { .hw = &gpll0_out_even.clkr.hw },
 206 };
 207
 208 static const struct parent_map gcc_parent_map_6[] = {
 209         { P_BI_TCXO, 0 },
 210         { P_GPLL0_OUT_MAIN, 1 },
 211         { P_GPLL7_OUT_MAIN, 3 },
 212         { P_GPLL0_OUT_EVEN, 6 },
 213 };
 214
 215 static const struct clk_parent_data gcc_parent_data_6[] = {
 216         { .index = DT_BI_TCXO },
 217         { .hw = &gpll0.clkr.hw },
 218         { .hw = &gpll7.clkr.hw },
 219         { .hw = &gpll0_out_even.clkr.hw },
 220 };
 221
 222 static const struct parent_map gcc_parent_map_7[] = {
 223         { P_BI_TCXO, 0 },
 224         { P_GPLL0_OUT_MAIN, 1 },
 225         { P_GPLL0_OUT_EVEN, 6 },
 226 };
 227
 228 static const struct clk_parent_data gcc_parent_data_7[] = {
 229         { .index = DT_BI_TCXO },
 230         { .hw = &gpll0.clkr.hw },
 231         { .hw = &gpll0_out_even.clkr.hw },
 232 };
 233
 234 static const struct parent_map gcc_parent_map_8[] = {
 235         { P_BI_TCXO, 0 },
 236         { P_GPLL0_OUT_MAIN, 1 },
 237 };
 238
 239 static const struct clk_parent_data gcc_parent_data_8[] = {
 240         { .index = DT_BI_TCXO },
 241         { .hw = &gpll0.clkr.hw },
 242 };
 243
 244 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 245         F(19200000, P_BI_TCXO, 1, 0, 0),
 246         { }
 247 };
 248
 249 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 250         .cmd_rcgr = 0x48014,
 251         .mnd_width = 0,
 252         .hid_width = 5,
 253         .parent_map = gcc_parent_map_0,
 254         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 255         .clkr.hw.init = &(struct clk_init_data){
 256                 .name = "gcc_cpuss_ahb_clk_src",
 257                 .parent_data = gcc_parent_data_0_ao,
 258                 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
 259                 .flags = CLK_SET_RATE_PARENT,
 260                 .ops = &clk_rcg2_ops,
 261         },
 262 };
 263
 264 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
 265         F(19200000, P_BI_TCXO, 1, 0, 0),
 266         { }
 267 };
 268
 269 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
 270         .cmd_rcgr = 0x4815c,
 271         .mnd_width = 0,
 272         .hid_width = 5,
 273         .parent_map = gcc_parent_map_2,
 274         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 275         .clkr.hw.init = &(struct clk_init_data){
 276                 .name = "gcc_cpuss_rbcpr_clk_src",
 277                 .parent_data = gcc_parent_data_2_ao,
 278                 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
 279                 .ops = &clk_rcg2_ops,
 280         },
 281 };
 282
 283 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 284         F(19200000, P_BI_TCXO, 1, 0, 0),
 285         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 286         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 287         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 288         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 289         { }
 290 };
 291
 292 static struct clk_rcg2 gcc_gp1_clk_src = {
 293         .cmd_rcgr = 0x64004,
 294         .mnd_width = 8,
 295         .hid_width = 5,
 296         .parent_map = gcc_parent_map_1,
 297         .freq_tbl = ftbl_gcc_gp1_clk_src,
 298         .clkr.hw.init = &(struct clk_init_data){
 299                 .name = "gcc_gp1_clk_src",
 300                 .parent_data = gcc_parent_data_1,
 301                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 302                 .ops = &clk_rcg2_ops,
 303         },
 304 };
 305
 306 static struct clk_rcg2 gcc_gp2_clk_src = {
 307         .cmd_rcgr = 0x65004,
 308         .mnd_width = 8,
 309         .hid_width = 5,
 310         .parent_map = gcc_parent_map_1,
 311         .freq_tbl = ftbl_gcc_gp1_clk_src,
 312         .clkr.hw.init = &(struct clk_init_data){
 313                 .name = "gcc_gp2_clk_src",
 314                 .parent_data = gcc_parent_data_1,
 315                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 316                 .ops = &clk_rcg2_ops,
 317         },
 318 };
 319
 320 static struct clk_rcg2 gcc_gp3_clk_src = {
 321         .cmd_rcgr = 0x66004,
 322         .mnd_width = 8,
 323         .hid_width = 5,
 324         .parent_map = gcc_parent_map_1,
 325         .freq_tbl = ftbl_gcc_gp1_clk_src,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "gcc_gp3_clk_src",
 328                 .parent_data = gcc_parent_data_1,
 329                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 335         F(9600000, P_BI_TCXO, 2, 0, 0),
 336         F(19200000, P_BI_TCXO, 1, 0, 0),
 337         { }
 338 };
 339
 340 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 341         .cmd_rcgr = 0x6b028,
 342         .mnd_width = 16,
 343         .hid_width = 5,
 344         .parent_map = gcc_parent_map_3,
 345         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "gcc_pcie_0_aux_clk_src",
 348                 .parent_data = gcc_parent_data_3,
 349                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 355         F(19200000, P_BI_TCXO, 1, 0, 0),
 356         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 357         { }
 358 };
 359
 360 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 361         .cmd_rcgr = 0x6f014,
 362         .mnd_width = 0,
 363         .hid_width = 5,
 364         .parent_map = gcc_parent_map_0,
 365         .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 366         .clkr.hw.init = &(struct clk_init_data){
 367                 .name = "gcc_pcie_phy_refgen_clk_src",
 368                 .parent_data = gcc_parent_data_0,
 369                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 370                 .ops = &clk_rcg2_ops,
 371         },
 372 };
 373
 374 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 375         F(19200000, P_BI_TCXO, 1, 0, 0),
 376         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 377         { }
 378 };
 379
 380 static struct clk_rcg2 gcc_pdm2_clk_src = {
 381         .cmd_rcgr = 0x33010,
 382         .mnd_width = 0,
 383         .hid_width = 5,
 384         .parent_map = gcc_parent_map_0,
 385         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 386         .clkr.hw.init = &(struct clk_init_data){
 387                 .name = "gcc_pdm2_clk_src",
 388                 .parent_data = gcc_parent_data_0,
 389                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 390                 .ops = &clk_rcg2_ops,
 391         },
 392 };
 393
 394 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 395         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 396         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 397         F(19200000, P_BI_TCXO, 1, 0, 0),
 398         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 399         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 400         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 401         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 402         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 403         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 404         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 405         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 406         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 407         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 408         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 409         F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 410         { }
 411 };
 412
 413 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 414         .name = "gcc_qupv3_wrap0_s0_clk_src",
 415         .parent_data = gcc_parent_data_0,
 416         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 417         .ops = &clk_rcg2_ops,
 418 };
 419
 420 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 421         .cmd_rcgr = 0x17034,
 422         .mnd_width = 16,
 423         .hid_width = 5,
 424         .parent_map = gcc_parent_map_0,
 425         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 426         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 427 };
 428
 429 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 430         .name = "gcc_qupv3_wrap0_s1_clk_src",
 431         .parent_data = gcc_parent_data_0,
 432         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 433         .ops = &clk_rcg2_ops,
 434 };
 435
 436 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 437         .cmd_rcgr = 0x17164,
 438         .mnd_width = 16,
 439         .hid_width = 5,
 440         .parent_map = gcc_parent_map_0,
 441         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 442         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 443 };
 444
 445 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 446         .name = "gcc_qupv3_wrap0_s2_clk_src",
 447         .parent_data = gcc_parent_data_0,
 448         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 449         .ops = &clk_rcg2_ops,
 450 };
 451
 452 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 453         .cmd_rcgr = 0x17294,
 454         .mnd_width = 16,
 455         .hid_width = 5,
 456         .parent_map = gcc_parent_map_0,
 457         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 458         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 459 };
 460
 461 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 462         .name = "gcc_qupv3_wrap0_s3_clk_src",
 463         .parent_data = gcc_parent_data_0,
 464         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 465         .ops = &clk_rcg2_ops,
 466 };
 467
 468 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 469         .cmd_rcgr = 0x173c4,
 470         .mnd_width = 16,
 471         .hid_width = 5,
 472         .parent_map = gcc_parent_map_0,
 473         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 474         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 475 };
 476
 477 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 478         .name = "gcc_qupv3_wrap0_s4_clk_src",
 479         .parent_data = gcc_parent_data_0,
 480         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 481         .ops = &clk_rcg2_ops,
 482 };
 483
 484 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 485         .cmd_rcgr = 0x174f4,
 486         .mnd_width = 16,
 487         .hid_width = 5,
 488         .parent_map = gcc_parent_map_0,
 489         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 490         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 491 };
 492
 493 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 494         .name = "gcc_qupv3_wrap0_s5_clk_src",
 495         .parent_data = gcc_parent_data_0,
 496         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 497         .ops = &clk_rcg2_ops,
 498 };
 499
 500 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 501         .cmd_rcgr = 0x17624,
 502         .mnd_width = 16,
 503         .hid_width = 5,
 504         .parent_map = gcc_parent_map_0,
 505         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 506         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 507 };
 508
 509 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 510         .name = "gcc_qupv3_wrap0_s6_clk_src",
 511         .parent_data = gcc_parent_data_0,
 512         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 513         .flags = CLK_SET_RATE_PARENT,
 514         .ops = &clk_rcg2_ops,
 515 };
 516
 517 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 518         .cmd_rcgr = 0x17754,
 519         .mnd_width = 16,
 520         .hid_width = 5,
 521         .parent_map = gcc_parent_map_0,
 522         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 523         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 524 };
 525
 526 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 527         .name = "gcc_qupv3_wrap0_s7_clk_src",
 528         .parent_data = gcc_parent_data_0,
 529         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 530         .flags = CLK_SET_RATE_PARENT,
 531         .ops = &clk_rcg2_ops,
 532 };
 533
 534 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 535         .cmd_rcgr = 0x17884,
 536         .mnd_width = 16,
 537         .hid_width = 5,
 538         .parent_map = gcc_parent_map_0,
 539         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 540         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 541 };
 542
 543 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 544         .name = "gcc_qupv3_wrap1_s0_clk_src",
 545         .parent_data = gcc_parent_data_0,
 546         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 547         .ops = &clk_rcg2_ops,
 548 };
 549
 550 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 551         .cmd_rcgr = 0x18018,
 552         .mnd_width = 16,
 553         .hid_width = 5,
 554         .parent_map = gcc_parent_map_0,
 555         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 556         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 557 };
 558
 559 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 560         .name = "gcc_qupv3_wrap1_s1_clk_src",
 561         .parent_data = gcc_parent_data_0,
 562         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 563         .ops = &clk_rcg2_ops,
 564 };
 565
 566 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 567         .cmd_rcgr = 0x18148,
 568         .mnd_width = 16,
 569         .hid_width = 5,
 570         .parent_map = gcc_parent_map_0,
 571         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 572         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 573 };
 574
 575 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 576         .name = "gcc_qupv3_wrap1_s2_clk_src",
 577         .parent_data = gcc_parent_data_0,
 578         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 579         .ops = &clk_rcg2_ops,
 580 };
 581
 582 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 583         .cmd_rcgr = 0x18278,
 584         .mnd_width = 16,
 585         .hid_width = 5,
 586         .parent_map = gcc_parent_map_0,
 587         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 588         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 589 };
 590
 591 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 592         .name = "gcc_qupv3_wrap1_s3_clk_src",
 593         .parent_data = gcc_parent_data_0,
 594         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 595         .ops = &clk_rcg2_ops,
 596 };
 597
 598 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 599         .cmd_rcgr = 0x183a8,
 600         .mnd_width = 16,
 601         .hid_width = 5,
 602         .parent_map = gcc_parent_map_0,
 603         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 604         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 605 };
 606
 607 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 608         .name = "gcc_qupv3_wrap1_s4_clk_src",
 609         .parent_data = gcc_parent_data_0,
 610         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 611         .ops = &clk_rcg2_ops,
 612 };
 613
 614 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 615         .cmd_rcgr = 0x184d8,
 616         .mnd_width = 16,
 617         .hid_width = 5,
 618         .parent_map = gcc_parent_map_0,
 619         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 620         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 621 };
 622
 623 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 624         .name = "gcc_qupv3_wrap1_s5_clk_src",
 625         .parent_data = gcc_parent_data_0,
 626         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 627         .ops = &clk_rcg2_ops,
 628 };
 629
 630 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 631         .cmd_rcgr = 0x18608,
 632         .mnd_width = 16,
 633         .hid_width = 5,
 634         .parent_map = gcc_parent_map_0,
 635         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 636         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 637 };
 638
 639 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 640         .name = "gcc_qupv3_wrap1_s6_clk_src",
 641         .parent_data = gcc_parent_data_0,
 642         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 643         .ops = &clk_rcg2_ops,
 644 };
 645
 646 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 647         .cmd_rcgr = 0x18738,
 648         .mnd_width = 16,
 649         .hid_width = 5,
 650         .parent_map = gcc_parent_map_0,
 651         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 652         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 653 };
 654
 655 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 656         .name = "gcc_qupv3_wrap1_s7_clk_src",
 657         .parent_data = gcc_parent_data_0,
 658         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 659         .ops = &clk_rcg2_ops,
 660 };
 661
 662 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 663         .cmd_rcgr = 0x18868,
 664         .mnd_width = 16,
 665         .hid_width = 5,
 666         .parent_map = gcc_parent_map_0,
 667         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 668         .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 669 };
 670
 671 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 672         F(144000, P_BI_TCXO, 16, 3, 25),
 673         F(400000, P_BI_TCXO, 12, 1, 4),
 674         F(19200000, P_BI_TCXO, 1, 0, 0),
 675         F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
 676         F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
 677         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 678         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 679         F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
 680         F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
 681         { }
 682 };
 683
 684 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 685         .cmd_rcgr = 0x12028,
 686         .mnd_width = 8,
 687         .hid_width = 5,
 688         .parent_map = gcc_parent_map_5,
 689         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 690         .clkr.hw.init = &(struct clk_init_data){
 691                 .name = "gcc_sdcc1_apps_clk_src",
 692                 .parent_data = gcc_parent_data_5,
 693                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 694                 .ops = &clk_rcg2_floor_ops,
 695         },
 696 };
 697
 698 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 699         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 700         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 701         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 702         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 707         .cmd_rcgr = 0x12010,
 708         .mnd_width = 0,
 709         .hid_width = 5,
 710         .parent_map = gcc_parent_map_0,
 711         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "gcc_sdcc1_ice_core_clk_src",
 714                 .parent_data = gcc_parent_data_0,
 715                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 721         F(400000, P_BI_TCXO, 12, 1, 4),
 722         F(9600000, P_BI_TCXO, 2, 0, 0),
 723         F(19200000, P_BI_TCXO, 1, 0, 0),
 724         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 725         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 726         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 727         F(208000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 728         { }
 729 };
 730
 731 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 732         .cmd_rcgr = 0x1400c,
 733         .mnd_width = 8,
 734         .hid_width = 5,
 735         .parent_map = gcc_parent_map_6,
 736         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 737         .clkr.hw.init = &(struct clk_init_data){
 738                 .name = "gcc_sdcc2_apps_clk_src",
 739                 .parent_data = gcc_parent_data_6,
 740                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 741                 .ops = &clk_rcg2_floor_ops,
 742                 .flags = CLK_OPS_PARENT_ENABLE,
 743         },
 744 };
 745
 746 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 747         F(400000, P_BI_TCXO, 12, 1, 4),
 748         F(9600000, P_BI_TCXO, 2, 0, 0),
 749         F(19200000, P_BI_TCXO, 1, 0, 0),
 750         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 751         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
 752         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 753         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 754         { }
 755 };
 756
 757 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 758         .cmd_rcgr = 0x1600c,
 759         .mnd_width = 8,
 760         .hid_width = 5,
 761         .parent_map = gcc_parent_map_0,
 762         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "gcc_sdcc4_apps_clk_src",
 765                 .parent_data = gcc_parent_data_0,
 766                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 767                 .ops = &clk_rcg2_floor_ops,
 768         },
 769 };
 770
 771 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 772         F(105495, P_BI_TCXO, 2, 1, 91),
 773         { }
 774 };
 775
 776 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 777         .cmd_rcgr = 0x36010,
 778         .mnd_width = 8,
 779         .hid_width = 5,
 780         .parent_map = gcc_parent_map_7,
 781         .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "gcc_tsif_ref_clk_src",
 784                 .parent_data = gcc_parent_data_7,
 785                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 791         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 792         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 793         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 794         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 795         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 796         { }
 797 };
 798
 799 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 800         .cmd_rcgr = 0x77020,
 801         .mnd_width = 8,
 802         .hid_width = 5,
 803         .parent_map = gcc_parent_map_0,
 804         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "gcc_ufs_phy_axi_clk_src",
 807                 .parent_data = gcc_parent_data_0,
 808                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 809                 .ops = &clk_rcg2_ops,
 810         },
 811 };
 812
 813 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 814         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 815         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 816         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 817         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 818         { }
 819 };
 820
 821 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 822         .cmd_rcgr = 0x77048,
 823         .mnd_width = 0,
 824         .hid_width = 5,
 825         .parent_map = gcc_parent_map_0,
 826         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
 827         .clkr.hw.init = &(struct clk_init_data){
 828                 .name = "gcc_ufs_phy_ice_core_clk_src",
 829                 .parent_data = gcc_parent_data_0,
 830                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 831                 .ops = &clk_rcg2_ops,
 832         },
 833 };
 834
 835 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 836         .cmd_rcgr = 0x77098,
 837         .mnd_width = 0,
 838         .hid_width = 5,
 839         .parent_map = gcc_parent_map_4,
 840         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 841         .clkr.hw.init = &(struct clk_init_data){
 842                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 843                 .parent_data = gcc_parent_data_4,
 844                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 845                 .ops = &clk_rcg2_ops,
 846         },
 847 };
 848
 849 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
 850         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 851         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 852         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 853         { }
 854 };
 855
 856 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 857         .cmd_rcgr = 0x77060,
 858         .mnd_width = 0,
 859         .hid_width = 5,
 860         .parent_map = gcc_parent_map_0,
 861         .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
 862         .clkr.hw.init = &(struct clk_init_data){
 863                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 864                 .parent_data = gcc_parent_data_0,
 865                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 866                 .ops = &clk_rcg2_ops,
 867         },
 868 };
 869
 870 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 871         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
 872         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 873         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 874         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 875         { }
 876 };
 877
 878 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
 879         .cmd_rcgr = 0xf01c,
 880         .mnd_width = 8,
 881         .hid_width = 5,
 882         .parent_map = gcc_parent_map_0,
 883         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 884         .clkr.hw.init = &(struct clk_init_data){
 885                 .name = "gcc_usb30_prim_master_clk_src",
 886                 .parent_data = gcc_parent_data_0,
 887                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 888                 .ops = &clk_rcg2_ops,
 889         },
 890 };
 891
 892 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 893         F(19200000, P_BI_TCXO, 1, 0, 0),
 894         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
 895         F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
 896         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 897         { }
 898 };
 899
 900 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 901         .cmd_rcgr = 0xf034,
 902         .mnd_width = 0,
 903         .hid_width = 5,
 904         .parent_map = gcc_parent_map_0,
 905         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 906         .clkr.hw.init = &(struct clk_init_data){
 907                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
 908                 .parent_data = gcc_parent_data_0,
 909                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 910                 .ops = &clk_rcg2_ops,
 911         },
 912 };
 913
 914 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
 915         F(19200000, P_BI_TCXO, 1, 0, 0),
 916         { }
 917 };
 918
 919 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 920         .cmd_rcgr = 0xf060,
 921         .mnd_width = 0,
 922         .hid_width = 5,
 923         .parent_map = gcc_parent_map_3,
 924         .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
 925         .clkr.hw.init = &(struct clk_init_data){
 926                 .name = "gcc_usb3_prim_phy_aux_clk_src",
 927                 .parent_data = gcc_parent_data_3,
 928                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 929                 .ops = &clk_rcg2_ops,
 930         },
 931 };
 932
 933 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
 934         .cmd_rcgr = 0x7a030,
 935         .mnd_width = 0,
 936         .hid_width = 5,
 937         .parent_map = gcc_parent_map_2,
 938         .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
 939         .clkr.hw.init = &(struct clk_init_data){
 940                 .name = "gcc_vs_ctrl_clk_src",
 941                 .parent_data = gcc_parent_data_2,
 942                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 943                 .ops = &clk_rcg2_ops,
 944         },
 945 };
 946
 947 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
 948         F(19200000, P_BI_TCXO, 1, 0, 0),
 949         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 950         F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
 951         { }
 952 };
 953
 954 static struct clk_rcg2 gcc_vsensor_clk_src = {
 955         .cmd_rcgr = 0x7a018,
 956         .mnd_width = 0,
 957         .hid_width = 5,
 958         .parent_map = gcc_parent_map_8,
 959         .freq_tbl = ftbl_gcc_vsensor_clk_src,
 960         .clkr.hw.init = &(struct clk_init_data){
 961                 .name = "gcc_vsensor_clk_src",
 962                 .parent_data = gcc_parent_data_8,
 963                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 964                 .ops = &clk_rcg2_ops,
 965         },
 966 };
 967
 968 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
 969         .halt_reg = 0x2800c,
 970         .halt_check = BRANCH_HALT,
 971         .clkr = {
 972                 .enable_reg = 0x2800c,
 973                 .enable_mask = BIT(0),
 974                 .hw.init = &(struct clk_init_data){
 975                         .name = "gcc_aggre_noc_pcie_tbu_clk",
 976                         .ops = &clk_branch2_ops,
 977                 },
 978         },
 979 };
 980
 981 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
 982         .halt_reg = 0x82024,
 983         .halt_check = BRANCH_HALT,
 984         .hwcg_reg = 0x82024,
 985         .hwcg_bit = 1,
 986         .clkr = {
 987                 .enable_reg = 0x82024,
 988                 .enable_mask = BIT(0),
 989                 .hw.init = &(struct clk_init_data){
 990                         .name = "gcc_aggre_ufs_phy_axi_clk",
 991                         .parent_hws = (const struct clk_hw*[]){
 992                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 993                         },
 994                         .num_parents = 1,
 995                         .flags = CLK_SET_RATE_PARENT,
 996                         .ops = &clk_branch2_ops,
 997                 },
 998         },
 999 };
1000
1001 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1002         .halt_reg = 0x82024,
1003         .halt_check = BRANCH_HALT,
1004         .hwcg_reg = 0x82024,
1005         .hwcg_bit = 1,
1006         .clkr = {
1007                 .enable_reg = 0x82024,
1008                 .enable_mask = BIT(1),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1011                         .parent_hws = (const struct clk_hw*[]){
1012                                 &gcc_aggre_ufs_phy_axi_clk.clkr.hw,
1013                         },
1014                         .num_parents = 1,
1015                         .flags = CLK_SET_RATE_PARENT,
1016                         .ops = &clk_branch_simple_ops,
1017                 },
1018         },
1019 };
1020
1021 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1022         .halt_reg = 0x8201c,
1023         .halt_check = BRANCH_HALT,
1024         .clkr = {
1025                 .enable_reg = 0x8201c,
1026                 .enable_mask = BIT(0),
1027                 .hw.init = &(struct clk_init_data){
1028                         .name = "gcc_aggre_usb3_prim_axi_clk",
1029                         .parent_hws = (const struct clk_hw*[]){
1030                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1031                         },
1032                         .num_parents = 1,
1033                         .flags = CLK_SET_RATE_PARENT,
1034                         .ops = &clk_branch2_ops,
1035                 },
1036         },
1037 };
1038
1039 static struct clk_branch gcc_apc_vs_clk = {
1040         .halt_reg = 0x7a050,
1041         .halt_check = BRANCH_HALT,
1042         .clkr = {
1043                 .enable_reg = 0x7a050,
1044                 .enable_mask = BIT(0),
1045                 .hw.init = &(struct clk_init_data){
1046                         .name = "gcc_apc_vs_clk",
1047                         .parent_hws = (const struct clk_hw*[]){
1048                                 &gcc_vsensor_clk_src.clkr.hw,
1049                         },
1050                         .num_parents = 1,
1051                         .flags = CLK_SET_RATE_PARENT,
1052                         .ops = &clk_branch2_ops,
1053                 },
1054         },
1055 };
1056
1057 static struct clk_branch gcc_boot_rom_ahb_clk = {
1058         .halt_reg = 0x38004,
1059         .halt_check = BRANCH_HALT_VOTED,
1060         .hwcg_reg = 0x38004,
1061         .hwcg_bit = 1,
1062         .clkr = {
1063                 .enable_reg = 0x52004,
1064                 .enable_mask = BIT(10),
1065                 .hw.init = &(struct clk_init_data){
1066                         .name = "gcc_boot_rom_ahb_clk",
1067                         .ops = &clk_branch2_ops,
1068                 },
1069         },
1070 };
1071
1072 static struct clk_branch gcc_camera_hf_axi_clk = {
1073         .halt_reg = 0xb020,
1074         .halt_check = BRANCH_HALT,
1075         .clkr = {
1076                 .enable_reg = 0xb020,
1077                 .enable_mask = BIT(0),
1078                 .hw.init = &(struct clk_init_data){
1079                         .name = "gcc_camera_hf_axi_clk",
1080                         .ops = &clk_branch2_ops,
1081                 },
1082         },
1083 };
1084
1085 static struct clk_branch gcc_camera_sf_axi_clk = {
1086         .halt_reg = 0xb06c,
1087         .halt_check = BRANCH_HALT,
1088         .clkr = {
1089                 .enable_reg = 0xb06c,
1090                 .enable_mask = BIT(0),
1091                 .hw.init = &(struct clk_init_data){
1092                         .name = "gcc_camera_sf_axi_clk",
1093                         .ops = &clk_branch2_ops,
1094                 },
1095         },
1096 };
1097
1098 static struct clk_branch gcc_ce1_ahb_clk = {
1099         .halt_reg = 0x4100c,
1100         .halt_check = BRANCH_HALT_VOTED,
1101         .hwcg_reg = 0x4100c,
1102         .hwcg_bit = 1,
1103         .clkr = {
1104                 .enable_reg = 0x52004,
1105                 .enable_mask = BIT(3),
1106                 .hw.init = &(struct clk_init_data){
1107                         .name = "gcc_ce1_ahb_clk",
1108                         .ops = &clk_branch2_ops,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_branch gcc_ce1_axi_clk = {
1114         .halt_reg = 0x41008,
1115         .halt_check = BRANCH_HALT_VOTED,
1116         .clkr = {
1117                 .enable_reg = 0x52004,
1118                 .enable_mask = BIT(4),
1119                 .hw.init = &(struct clk_init_data){
1120                         .name = "gcc_ce1_axi_clk",
1121                         .ops = &clk_branch2_ops,
1122                 },
1123         },
1124 };
1125
1126 static struct clk_branch gcc_ce1_clk = {
1127         .halt_reg = 0x41004,
1128         .halt_check = BRANCH_HALT_VOTED,
1129         .clkr = {
1130                 .enable_reg = 0x52004,
1131                 .enable_mask = BIT(5),
1132                 .hw.init = &(struct clk_init_data){
1133                         .name = "gcc_ce1_clk",
1134                         .ops = &clk_branch2_ops,
1135                 },
1136         },
1137 };
1138
1139 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1140         .halt_reg = 0x502c,
1141         .halt_check = BRANCH_HALT,
1142         .clkr = {
1143                 .enable_reg = 0x502c,
1144                 .enable_mask = BIT(0),
1145                 .hw.init = &(struct clk_init_data){
1146                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1147                         .parent_hws = (const struct clk_hw*[]){
1148                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1149                         },
1150                         .num_parents = 1,
1151                         .flags = CLK_SET_RATE_PARENT,
1152                         .ops = &clk_branch2_ops,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_branch gcc_cpuss_ahb_clk = {
1158         .halt_reg = 0x48000,
1159         .halt_check = BRANCH_HALT_VOTED,
1160         .clkr = {
1161                 .enable_reg = 0x52004,
1162                 .enable_mask = BIT(21),
1163                 .hw.init = &(struct clk_init_data){
1164                         .name = "gcc_cpuss_ahb_clk",
1165                         .parent_hws = (const struct clk_hw*[]){
1166                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1167                         },
1168                         .num_parents = 1,
1169                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1170                         .ops = &clk_branch2_ops,
1171                 },
1172         },
1173 };
1174
1175 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1176         .halt_reg = 0x48008,
1177         .halt_check = BRANCH_HALT,
1178         .clkr = {
1179                 .enable_reg = 0x48008,
1180                 .enable_mask = BIT(0),
1181                 .hw.init = &(struct clk_init_data){
1182                         .name = "gcc_cpuss_rbcpr_clk",
1183                         .parent_hws = (const struct clk_hw*[]){
1184                                 &gcc_cpuss_rbcpr_clk_src.clkr.hw,
1185                         },
1186                         .num_parents = 1,
1187                         .flags = CLK_SET_RATE_PARENT,
1188                         .ops = &clk_branch2_ops,
1189                 },
1190         },
1191 };
1192
1193 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1194         .halt_reg = 0x4452c,
1195         .halt_check = BRANCH_VOTED,
1196         .clkr = {
1197                 .enable_reg = 0x4452c,
1198                 .enable_mask = BIT(0),
1199                 .hw.init = &(struct clk_init_data){
1200                         .name = "gcc_ddrss_gpu_axi_clk",
1201                         .ops = &clk_branch2_ops,
1202                 },
1203         },
1204 };
1205
1206
1207 static struct clk_branch gcc_disp_gpll0_clk_src = {
1208         .halt_check = BRANCH_HALT_DELAY,
1209         .clkr = {
1210                 .enable_reg = 0x52004,
1211                 .enable_mask = BIT(18),
1212                 .hw.init = &(struct clk_init_data){
1213                         .name = "gcc_disp_gpll0_clk_src",
1214                         .parent_hws = (const struct clk_hw*[]){
1215                                 &gpll0.clkr.hw,
1216                         },
1217                         .num_parents = 1,
1218                         .ops = &clk_branch2_aon_ops,
1219                 },
1220         },
1221 };
1222
1223 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1224         .halt_check = BRANCH_HALT_DELAY,
1225         .clkr = {
1226                 .enable_reg = 0x52004,
1227                 .enable_mask = BIT(19),
1228                 .hw.init = &(struct clk_init_data){
1229                         .name = "gcc_disp_gpll0_div_clk_src",
1230                         .parent_hws = (const struct clk_hw*[]){
1231                                 &gcc_pll0_main_div_cdiv.hw,
1232                         },
1233                         .num_parents = 1,
1234                         .ops = &clk_branch2_ops,
1235                 },
1236         },
1237 };
1238
1239 static struct clk_branch gcc_disp_hf_axi_clk = {
1240         .halt_reg = 0xb024,
1241         .halt_check = BRANCH_HALT,
1242         .clkr = {
1243                 .enable_reg = 0xb024,
1244                 .enable_mask = BIT(0),
1245                 .hw.init = &(struct clk_init_data){
1246                         .name = "gcc_disp_hf_axi_clk",
1247                         .ops = &clk_branch2_ops,
1248                 },
1249         },
1250 };
1251
1252 static struct clk_branch gcc_disp_sf_axi_clk = {
1253         .halt_reg = 0xb070,
1254         .halt_check = BRANCH_HALT,
1255         .clkr = {
1256                 .enable_reg = 0xb070,
1257                 .enable_mask = BIT(0),
1258                 .hw.init = &(struct clk_init_data){
1259                         .name = "gcc_disp_sf_axi_clk",
1260                         .ops = &clk_branch2_ops,
1261                 },
1262         },
1263 };
1264
1265
1266 static struct clk_branch gcc_gp1_clk = {
1267         .halt_reg = 0x64000,
1268         .halt_check = BRANCH_HALT,
1269         .clkr = {
1270                 .enable_reg = 0x64000,
1271                 .enable_mask = BIT(0),
1272                 .hw.init = &(struct clk_init_data){
1273                         .name = "gcc_gp1_clk",
1274                         .parent_hws = (const struct clk_hw*[]){
1275                                 &gcc_gp1_clk_src.clkr.hw,
1276                         },
1277                         .num_parents = 1,
1278                         .flags = CLK_SET_RATE_PARENT,
1279                         .ops = &clk_branch2_ops,
1280                 },
1281         },
1282 };
1283
1284 static struct clk_branch gcc_gp2_clk = {
1285         .halt_reg = 0x65000,
1286         .halt_check = BRANCH_HALT,
1287         .clkr = {
1288                 .enable_reg = 0x65000,
1289                 .enable_mask = BIT(0),
1290                 .hw.init = &(struct clk_init_data){
1291                         .name = "gcc_gp2_clk",
1292                         .parent_hws = (const struct clk_hw*[]){
1293                                 &gcc_gp2_clk_src.clkr.hw,
1294                         },
1295                         .num_parents = 1,
1296                         .flags = CLK_SET_RATE_PARENT,
1297                         .ops = &clk_branch2_ops,
1298                 },
1299         },
1300 };
1301
1302 static struct clk_branch gcc_gp3_clk = {
1303         .halt_reg = 0x66000,
1304         .halt_check = BRANCH_HALT,
1305         .clkr = {
1306                 .enable_reg = 0x66000,
1307                 .enable_mask = BIT(0),
1308                 .hw.init = &(struct clk_init_data){
1309                         .name = "gcc_gp3_clk",
1310                         .parent_hws = (const struct clk_hw*[]){
1311                                 &gcc_gp3_clk_src.clkr.hw,
1312                         },
1313                         .num_parents = 1,
1314                         .flags = CLK_SET_RATE_PARENT,
1315                         .ops = &clk_branch2_ops,
1316                 },
1317         },
1318 };
1319
1320 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1321         .halt_check = BRANCH_HALT_DELAY,
1322         .clkr = {
1323                 .enable_reg = 0x52004,
1324                 .enable_mask = BIT(15),
1325                 .hw.init = &(struct clk_init_data){
1326                         .name = "gcc_gpu_gpll0_clk_src",
1327                         .parent_hws = (const struct clk_hw*[]){
1328                                 &gpll0.clkr.hw,
1329                         },
1330                         .num_parents = 1,
1331                         .ops = &clk_branch2_ops,
1332                 },
1333         },
1334 };
1335
1336 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1337         .halt_check = BRANCH_HALT_DELAY,
1338         .clkr = {
1339                 .enable_reg = 0x52004,
1340                 .enable_mask = BIT(16),
1341                 .hw.init = &(struct clk_init_data){
1342                         .name = "gcc_gpu_gpll0_div_clk_src",
1343                         .parent_hws = (const struct clk_hw*[]){
1344                                 &gcc_pll0_main_div_cdiv.hw,
1345                         },
1346                         .num_parents = 1,
1347                         .ops = &clk_branch2_ops,
1348                 },
1349         },
1350 };
1351
1352 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1353         .halt_reg = 0x7100c,
1354         .halt_check = BRANCH_VOTED,
1355         .clkr = {
1356                 .enable_reg = 0x7100c,
1357                 .enable_mask = BIT(0),
1358                 .hw.init = &(struct clk_init_data){
1359                         .name = "gcc_gpu_memnoc_gfx_clk",
1360                         .ops = &clk_branch2_ops,
1361                 },
1362         },
1363 };
1364
1365 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1366         .halt_reg = 0x71018,
1367         .halt_check = BRANCH_HALT,
1368         .clkr = {
1369                 .enable_reg = 0x71018,
1370                 .enable_mask = BIT(0),
1371                 .hw.init = &(struct clk_init_data){
1372                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1373                         .ops = &clk_branch2_ops,
1374                 },
1375         },
1376 };
1377
1378 static struct clk_branch gcc_gpu_vs_clk = {
1379         .halt_reg = 0x7a04c,
1380         .halt_check = BRANCH_HALT,
1381         .clkr = {
1382                 .enable_reg = 0x7a04c,
1383                 .enable_mask = BIT(0),
1384                 .hw.init = &(struct clk_init_data){
1385                         .name = "gcc_gpu_vs_clk",
1386                         .parent_hws = (const struct clk_hw*[]){
1387                                 &gcc_vsensor_clk_src.clkr.hw,
1388                         },
1389                         .num_parents = 1,
1390                         .flags = CLK_SET_RATE_PARENT,
1391                         .ops = &clk_branch2_ops,
1392                 },
1393         },
1394 };
1395
1396 static struct clk_branch gcc_npu_axi_clk = {
1397         .halt_reg = 0x4d008,
1398         .halt_check = BRANCH_HALT,
1399         .clkr = {
1400                 .enable_reg = 0x4d008,
1401                 .enable_mask = BIT(0),
1402                 .hw.init = &(struct clk_init_data){
1403                         .name = "gcc_npu_axi_clk",
1404                         .ops = &clk_branch2_ops,
1405                 },
1406         },
1407 };
1408
1409 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1410         .halt_reg = 0x4d004,
1411         .halt_check = BRANCH_HALT,
1412         .hwcg_reg = 0x4d004,
1413         .hwcg_bit = 1,
1414         .clkr = {
1415                 .enable_reg = 0x4d004,
1416                 .enable_mask = BIT(0),
1417                 .hw.init = &(struct clk_init_data){
1418                         .name = "gcc_npu_cfg_ahb_clk",
1419                         .flags = CLK_IS_CRITICAL,
1420                         .ops = &clk_branch2_ops,
1421                 },
1422         },
1423 };
1424
1425 static struct clk_branch gcc_npu_gpll0_clk_src = {
1426         .halt_check = BRANCH_HALT_DELAY,
1427         .clkr = {
1428                 .enable_reg = 0x52004,
1429                 .enable_mask = BIT(25),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gcc_npu_gpll0_clk_src",
1432                         .parent_hws = (const struct clk_hw*[]){
1433                                 &gpll0.clkr.hw,
1434                         },
1435                         .num_parents = 1,
1436                         .ops = &clk_branch2_ops,
1437                 },
1438         },
1439 };
1440
1441 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1442         .halt_check = BRANCH_HALT_DELAY,
1443         .clkr = {
1444                 .enable_reg = 0x52004,
1445                 .enable_mask = BIT(26),
1446                 .hw.init = &(struct clk_init_data){
1447                         .name = "gcc_npu_gpll0_div_clk_src",
1448                         .parent_hws = (const struct clk_hw*[]){
1449                                 &gcc_pll0_main_div_cdiv.hw,
1450                         },
1451                         .num_parents = 1,
1452                         .flags = CLK_SET_RATE_PARENT,
1453                         .ops = &clk_branch2_ops,
1454                 },
1455         },
1456 };
1457
1458 static struct clk_branch gcc_pcie_0_aux_clk = {
1459         .halt_reg = 0x6b01c,
1460         .halt_check = BRANCH_HALT_VOTED,
1461         .clkr = {
1462                 .enable_reg = 0x5200c,
1463                 .enable_mask = BIT(3),
1464                 .hw.init = &(struct clk_init_data){
1465                         .name = "gcc_pcie_0_aux_clk",
1466                         .parent_hws = (const struct clk_hw*[]){
1467                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1468                         },
1469                         .num_parents = 1,
1470                         .flags = CLK_SET_RATE_PARENT,
1471                         .ops = &clk_branch2_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1477         .halt_reg = 0x6b018,
1478         .halt_check = BRANCH_HALT_VOTED,
1479         .hwcg_reg = 0x6b018,
1480         .hwcg_bit = 1,
1481         .clkr = {
1482                 .enable_reg = 0x5200c,
1483                 .enable_mask = BIT(2),
1484                 .hw.init = &(struct clk_init_data){
1485                         .name = "gcc_pcie_0_cfg_ahb_clk",
1486                         .ops = &clk_branch2_ops,
1487                 },
1488         },
1489 };
1490
1491 static struct clk_branch gcc_pcie_0_clkref_clk = {
1492         .halt_reg = 0x8c008,
1493         .halt_check = BRANCH_HALT,
1494         .clkr = {
1495                 .enable_reg = 0x8c008,
1496                 .enable_mask = BIT(0),
1497                 .hw.init = &(struct clk_init_data){
1498                         .name = "gcc_pcie_0_clkref_clk",
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1505         .halt_reg = 0x6b014,
1506         .halt_check = BRANCH_HALT_VOTED,
1507         .clkr = {
1508                 .enable_reg = 0x5200c,
1509                 .enable_mask = BIT(1),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "gcc_pcie_0_mstr_axi_clk",
1512                         .ops = &clk_branch2_ops,
1513                 },
1514         },
1515 };
1516
1517 static struct clk_branch gcc_pcie_0_pipe_clk = {
1518         .halt_reg = 0x6b020,
1519         .halt_check = BRANCH_HALT_SKIP,
1520         .clkr = {
1521                 .enable_reg = 0x5200c,
1522                 .enable_mask = BIT(4),
1523                 .hw.init = &(struct clk_init_data){
1524                         .name = "gcc_pcie_0_pipe_clk",
1525                         .ops = &clk_branch2_ops,
1526                 },
1527         },
1528 };
1529
1530 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1531         .halt_reg = 0x6b010,
1532         .halt_check = BRANCH_HALT_VOTED,
1533         .hwcg_reg = 0x6b010,
1534         .hwcg_bit = 1,
1535         .clkr = {
1536                 .enable_reg = 0x5200c,
1537                 .enable_mask = BIT(0),
1538                 .hw.init = &(struct clk_init_data){
1539                         .name = "gcc_pcie_0_slv_axi_clk",
1540                         .ops = &clk_branch2_ops,
1541                 },
1542         },
1543 };
1544
1545 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1546         .halt_reg = 0x6b00c,
1547         .halt_check = BRANCH_HALT_VOTED,
1548         .clkr = {
1549                 .enable_reg = 0x5200c,
1550                 .enable_mask = BIT(5),
1551                 .hw.init = &(struct clk_init_data){
1552                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1553                         .ops = &clk_branch2_ops,
1554                 },
1555         },
1556 };
1557
1558 static struct clk_branch gcc_pcie_phy_aux_clk = {
1559         .halt_reg = 0x6f004,
1560         .halt_check = BRANCH_HALT,
1561         .clkr = {
1562                 .enable_reg = 0x6f004,
1563                 .enable_mask = BIT(0),
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "gcc_pcie_phy_aux_clk",
1566                         .parent_hws = (const struct clk_hw*[]){
1567                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1568                         },
1569                         .num_parents = 1,
1570                         .flags = CLK_SET_RATE_PARENT,
1571                         .ops = &clk_branch2_ops,
1572                 },
1573         },
1574 };
1575
1576 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1577         .halt_reg = 0x6f02c,
1578         .halt_check = BRANCH_HALT,
1579         .clkr = {
1580                 .enable_reg = 0x6f02c,
1581                 .enable_mask = BIT(0),
1582                 .hw.init = &(struct clk_init_data){
1583                         .name = "gcc_pcie_phy_refgen_clk",
1584                         .parent_hws = (const struct clk_hw*[]){
1585                                 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
1586                         },
1587                         .num_parents = 1,
1588                         .flags = CLK_SET_RATE_PARENT,
1589                         .ops = &clk_branch2_ops,
1590                 },
1591         },
1592 };
1593
1594 static struct clk_branch gcc_pdm2_clk = {
1595         .halt_reg = 0x3300c,
1596         .halt_check = BRANCH_HALT,
1597         .clkr = {
1598                 .enable_reg = 0x3300c,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "gcc_pdm2_clk",
1602                         .parent_hws = (const struct clk_hw*[]){
1603                                 &gcc_pdm2_clk_src.clkr.hw,
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch gcc_pdm_ahb_clk = {
1613         .halt_reg = 0x33004,
1614         .halt_check = BRANCH_HALT,
1615         .hwcg_reg = 0x33004,
1616         .hwcg_bit = 1,
1617         .clkr = {
1618                 .enable_reg = 0x33004,
1619                 .enable_mask = BIT(0),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "gcc_pdm_ahb_clk",
1622                         .ops = &clk_branch2_ops,
1623                 },
1624         },
1625 };
1626
1627 static struct clk_branch gcc_pdm_xo4_clk = {
1628         .halt_reg = 0x33008,
1629         .halt_check = BRANCH_HALT,
1630         .clkr = {
1631                 .enable_reg = 0x33008,
1632                 .enable_mask = BIT(0),
1633                 .hw.init = &(struct clk_init_data){
1634                         .name = "gcc_pdm_xo4_clk",
1635                         .ops = &clk_branch2_ops,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_branch gcc_prng_ahb_clk = {
1641         .halt_reg = 0x34004,
1642         .halt_check = BRANCH_HALT_VOTED,
1643         .hwcg_reg = 0x34004,
1644         .hwcg_bit = 1,
1645         .clkr = {
1646                 .enable_reg = 0x52004,
1647                 .enable_mask = BIT(13),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "gcc_prng_ahb_clk",
1650                         .ops = &clk_branch2_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1656         .halt_reg = 0x17014,
1657         .halt_check = BRANCH_HALT_VOTED,
1658         .clkr = {
1659                 .enable_reg = 0x5200c,
1660                 .enable_mask = BIT(9),
1661                 .hw.init = &(struct clk_init_data){
1662                         .name = "gcc_qupv3_wrap0_core_2x_clk",
1663                         .ops = &clk_branch2_ops,
1664                 },
1665         },
1666 };
1667
1668 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1669         .halt_reg = 0x1700c,
1670         .halt_check = BRANCH_HALT_VOTED,
1671         .clkr = {
1672                 .enable_reg = 0x5200c,
1673                 .enable_mask = BIT(8),
1674                 .hw.init = &(struct clk_init_data){
1675                         .name = "gcc_qupv3_wrap0_core_clk",
1676                         .ops = &clk_branch2_ops,
1677                 },
1678         },
1679 };
1680
1681 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1682         .halt_reg = 0x17030,
1683         .halt_check = BRANCH_HALT_VOTED,
1684         .clkr = {
1685                 .enable_reg = 0x5200c,
1686                 .enable_mask = BIT(10),
1687                 .hw.init = &(struct clk_init_data){
1688                         .name = "gcc_qupv3_wrap0_s0_clk",
1689                         .parent_hws = (const struct clk_hw*[]){
1690                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1691                         },
1692                         .num_parents = 1,
1693                         .flags = CLK_SET_RATE_PARENT,
1694                         .ops = &clk_branch2_ops,
1695                 },
1696         },
1697 };
1698
1699 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1700         .halt_reg = 0x17160,
1701         .halt_check = BRANCH_HALT_VOTED,
1702         .clkr = {
1703                 .enable_reg = 0x5200c,
1704                 .enable_mask = BIT(11),
1705                 .hw.init = &(struct clk_init_data){
1706                         .name = "gcc_qupv3_wrap0_s1_clk",
1707                         .parent_hws = (const struct clk_hw*[]){
1708                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1709                         },
1710                         .num_parents = 1,
1711                         .flags = CLK_SET_RATE_PARENT,
1712                         .ops = &clk_branch2_ops,
1713                 },
1714         },
1715 };
1716
1717 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1718         .halt_reg = 0x17290,
1719         .halt_check = BRANCH_HALT_VOTED,
1720         .clkr = {
1721                 .enable_reg = 0x5200c,
1722                 .enable_mask = BIT(12),
1723                 .hw.init = &(struct clk_init_data){
1724                         .name = "gcc_qupv3_wrap0_s2_clk",
1725                         .parent_hws = (const struct clk_hw*[]){
1726                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1727                         },
1728                         .num_parents = 1,
1729                         .flags = CLK_SET_RATE_PARENT,
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1736         .halt_reg = 0x173c0,
1737         .halt_check = BRANCH_HALT_VOTED,
1738         .clkr = {
1739                 .enable_reg = 0x5200c,
1740                 .enable_mask = BIT(13),
1741                 .hw.init = &(struct clk_init_data){
1742                         .name = "gcc_qupv3_wrap0_s3_clk",
1743                         .parent_hws = (const struct clk_hw*[]){
1744                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1745                         },
1746                         .num_parents = 1,
1747                         .flags = CLK_SET_RATE_PARENT,
1748                         .ops = &clk_branch2_ops,
1749                 },
1750         },
1751 };
1752
1753 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1754         .halt_reg = 0x174f0,
1755         .halt_check = BRANCH_HALT_VOTED,
1756         .clkr = {
1757                 .enable_reg = 0x5200c,
1758                 .enable_mask = BIT(14),
1759                 .hw.init = &(struct clk_init_data){
1760                         .name = "gcc_qupv3_wrap0_s4_clk",
1761                         .parent_hws = (const struct clk_hw*[]){
1762                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1763                         },
1764                         .num_parents = 1,
1765                         .flags = CLK_SET_RATE_PARENT,
1766                         .ops = &clk_branch2_ops,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1772         .halt_reg = 0x17620,
1773         .halt_check = BRANCH_HALT_VOTED,
1774         .clkr = {
1775                 .enable_reg = 0x5200c,
1776                 .enable_mask = BIT(15),
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "gcc_qupv3_wrap0_s5_clk",
1779                         .parent_hws = (const struct clk_hw*[]){
1780                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1781                         },
1782                         .num_parents = 1,
1783                         .flags = CLK_SET_RATE_PARENT,
1784                         .ops = &clk_branch2_ops,
1785                 },
1786         },
1787 };
1788
1789 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
1790         .halt_reg = 0x17750,
1791         .halt_check = BRANCH_HALT_VOTED,
1792         .clkr = {
1793                 .enable_reg = 0x5200c,
1794                 .enable_mask = BIT(16),
1795                 .hw.init = &(struct clk_init_data){
1796                         .name = "gcc_qupv3_wrap0_s6_clk",
1797                         .parent_hws = (const struct clk_hw*[]){
1798                                 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
1799                         },
1800                         .num_parents = 1,
1801                         .flags = CLK_SET_RATE_PARENT,
1802                         .ops = &clk_branch2_ops,
1803                 },
1804         },
1805 };
1806
1807 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
1808         .halt_reg = 0x17880,
1809         .halt_check = BRANCH_HALT_VOTED,
1810         .clkr = {
1811                 .enable_reg = 0x5200c,
1812                 .enable_mask = BIT(17),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "gcc_qupv3_wrap0_s7_clk",
1815                         .parent_hws = (const struct clk_hw*[]){
1816                                 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
1817                         },
1818                         .num_parents = 1,
1819                         .flags = CLK_SET_RATE_PARENT,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1826         .halt_reg = 0x18004,
1827         .halt_check = BRANCH_HALT_VOTED,
1828         .clkr = {
1829                 .enable_reg = 0x5200c,
1830                 .enable_mask = BIT(18),
1831                 .hw.init = &(struct clk_init_data){
1832                         .name = "gcc_qupv3_wrap1_core_2x_clk",
1833                         .ops = &clk_branch2_ops,
1834                 },
1835         },
1836 };
1837
1838 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1839         .halt_reg = 0x18008,
1840         .halt_check = BRANCH_HALT_VOTED,
1841         .clkr = {
1842                 .enable_reg = 0x5200c,
1843                 .enable_mask = BIT(19),
1844                 .hw.init = &(struct clk_init_data){
1845                         .name = "gcc_qupv3_wrap1_core_clk",
1846                         .ops = &clk_branch2_ops,
1847                 },
1848         },
1849 };
1850
1851 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1852         .halt_reg = 0x18014,
1853         .halt_check = BRANCH_HALT_VOTED,
1854         .clkr = {
1855                 .enable_reg = 0x5200c,
1856                 .enable_mask = BIT(22),
1857                 .hw.init = &(struct clk_init_data){
1858                         .name = "gcc_qupv3_wrap1_s0_clk",
1859                         .parent_hws = (const struct clk_hw*[]){
1860                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1861                         },
1862                         .num_parents = 1,
1863                         .flags = CLK_SET_RATE_PARENT,
1864                         .ops = &clk_branch2_ops,
1865                 },
1866         },
1867 };
1868
1869 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1870         .halt_reg = 0x18144,
1871         .halt_check = BRANCH_HALT_VOTED,
1872         .clkr = {
1873                 .enable_reg = 0x5200c,
1874                 .enable_mask = BIT(23),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "gcc_qupv3_wrap1_s1_clk",
1877                         .parent_hws = (const struct clk_hw*[]){
1878                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1879                         },
1880                         .num_parents = 1,
1881                         .flags = CLK_SET_RATE_PARENT,
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1888         .halt_reg = 0x18274,
1889         .halt_check = BRANCH_HALT_VOTED,
1890         .clkr = {
1891                 .enable_reg = 0x5200c,
1892                 .enable_mask = BIT(24),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "gcc_qupv3_wrap1_s2_clk",
1895                         .parent_hws = (const struct clk_hw*[]){
1896                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1897                         },
1898                         .num_parents = 1,
1899                         .flags = CLK_SET_RATE_PARENT,
1900                         .ops = &clk_branch2_ops,
1901                 },
1902         },
1903 };
1904
1905 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1906         .halt_reg = 0x183a4,
1907         .halt_check = BRANCH_HALT_VOTED,
1908         .clkr = {
1909                 .enable_reg = 0x5200c,
1910                 .enable_mask = BIT(25),
1911                 .hw.init = &(struct clk_init_data){
1912                         .name = "gcc_qupv3_wrap1_s3_clk",
1913                         .parent_hws = (const struct clk_hw*[]){
1914                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1915                         },
1916                         .num_parents = 1,
1917                         .flags = CLK_SET_RATE_PARENT,
1918                         .ops = &clk_branch2_ops,
1919                 },
1920         },
1921 };
1922
1923 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1924         .halt_reg = 0x184d4,
1925         .halt_check = BRANCH_HALT_VOTED,
1926         .clkr = {
1927                 .enable_reg = 0x5200c,
1928                 .enable_mask = BIT(26),
1929                 .hw.init = &(struct clk_init_data){
1930                         .name = "gcc_qupv3_wrap1_s4_clk",
1931                         .parent_hws = (const struct clk_hw*[]){
1932                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1933                         },
1934                         .num_parents = 1,
1935                         .flags = CLK_SET_RATE_PARENT,
1936                         .ops = &clk_branch2_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1942         .halt_reg = 0x18604,
1943         .halt_check = BRANCH_HALT_VOTED,
1944         .clkr = {
1945                 .enable_reg = 0x5200c,
1946                 .enable_mask = BIT(27),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "gcc_qupv3_wrap1_s5_clk",
1949                         .parent_hws = (const struct clk_hw*[]){
1950                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1951                         },
1952                         .num_parents = 1,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                         .ops = &clk_branch2_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
1960         .halt_reg = 0x18734,
1961         .halt_check = BRANCH_HALT_VOTED,
1962         .clkr = {
1963                 .enable_reg = 0x5200c,
1964                 .enable_mask = BIT(28),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "gcc_qupv3_wrap1_s6_clk",
1967                         .parent_hws = (const struct clk_hw*[]){
1968                                 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
1969                         },
1970                         .num_parents = 1,
1971                         .flags = CLK_SET_RATE_PARENT,
1972                         .ops = &clk_branch2_ops,
1973                 },
1974         },
1975 };
1976
1977 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
1978         .halt_reg = 0x18864,
1979         .halt_check = BRANCH_HALT_VOTED,
1980         .clkr = {
1981                 .enable_reg = 0x5200c,
1982                 .enable_mask = BIT(29),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "gcc_qupv3_wrap1_s7_clk",
1985                         .parent_hws = (const struct clk_hw*[]){
1986                                 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
1987                         },
1988                         .num_parents = 1,
1989                         .flags = CLK_SET_RATE_PARENT,
1990                         .ops = &clk_branch2_ops,
1991                 },
1992         },
1993 };
1994
1995 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1996         .halt_reg = 0x17004,
1997         .halt_check = BRANCH_HALT_VOTED,
1998         .clkr = {
1999                 .enable_reg = 0x5200c,
2000                 .enable_mask = BIT(6),
2001                 .hw.init = &(struct clk_init_data){
2002                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2003                         .ops = &clk_branch2_ops,
2004                 },
2005         },
2006 };
2007
2008 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2009         .halt_reg = 0x17008,
2010         .halt_check = BRANCH_HALT_VOTED,
2011         .hwcg_reg = 0x17008,
2012         .hwcg_bit = 1,
2013         .clkr = {
2014                 .enable_reg = 0x5200c,
2015                 .enable_mask = BIT(7),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2024         .halt_reg = 0x1800c,
2025         .halt_check = BRANCH_HALT_VOTED,
2026         .clkr = {
2027                 .enable_reg = 0x5200c,
2028                 .enable_mask = BIT(20),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2031                         .ops = &clk_branch2_ops,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2037         .halt_reg = 0x18010,
2038         .halt_check = BRANCH_HALT_VOTED,
2039         .hwcg_reg = 0x18010,
2040         .hwcg_bit = 1,
2041         .clkr = {
2042                 .enable_reg = 0x5200c,
2043                 .enable_mask = BIT(21),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch gcc_sdcc1_ahb_clk = {
2052         .halt_reg = 0x12008,
2053         .halt_check = BRANCH_HALT,
2054         .clkr = {
2055                 .enable_reg = 0x12008,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_sdcc1_ahb_clk",
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_sdcc1_apps_clk = {
2065         .halt_reg = 0x1200c,
2066         .halt_check = BRANCH_HALT,
2067         .clkr = {
2068                 .enable_reg = 0x1200c,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_sdcc1_apps_clk",
2072                         .parent_hws = (const struct clk_hw*[]){
2073                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
2074                         },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2083         .halt_reg = 0x12040,
2084         .halt_check = BRANCH_HALT,
2085         .clkr = {
2086                 .enable_reg = 0x12040,
2087                 .enable_mask = BIT(0),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_sdcc1_ice_core_clk",
2090                         .parent_hws = (const struct clk_hw*[]){
2091                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2092                         },
2093                         .num_parents = 1,
2094                         .flags = CLK_SET_RATE_PARENT,
2095                         .ops = &clk_branch2_ops,
2096                 },
2097         },
2098 };
2099
2100 static struct clk_branch gcc_sdcc2_ahb_clk = {
2101         .halt_reg = 0x14008,
2102         .halt_check = BRANCH_HALT,
2103         .clkr = {
2104                 .enable_reg = 0x14008,
2105                 .enable_mask = BIT(0),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "gcc_sdcc2_ahb_clk",
2108                         .ops = &clk_branch2_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_branch gcc_sdcc2_apps_clk = {
2114         .halt_reg = 0x14004,
2115         .halt_check = BRANCH_HALT,
2116         .clkr = {
2117                 .enable_reg = 0x14004,
2118                 .enable_mask = BIT(0),
2119                 .hw.init = &(struct clk_init_data){
2120                         .name = "gcc_sdcc2_apps_clk",
2121                         .parent_hws = (const struct clk_hw*[]){
2122                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
2123                         },
2124                         .num_parents = 1,
2125                         .flags = CLK_SET_RATE_PARENT,
2126                         .ops = &clk_branch2_ops,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch gcc_sdcc4_ahb_clk = {
2132         .halt_reg = 0x16008,
2133         .halt_check = BRANCH_HALT,
2134         .clkr = {
2135                 .enable_reg = 0x16008,
2136                 .enable_mask = BIT(0),
2137                 .hw.init = &(struct clk_init_data){
2138                         .name = "gcc_sdcc4_ahb_clk",
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_branch gcc_sdcc4_apps_clk = {
2145         .halt_reg = 0x16004,
2146         .halt_check = BRANCH_HALT,
2147         .clkr = {
2148                 .enable_reg = 0x16004,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "gcc_sdcc4_apps_clk",
2152                         .parent_hws = (const struct clk_hw*[]){
2153                                 &gcc_sdcc4_apps_clk_src.clkr.hw,
2154                         },
2155                         .num_parents = 1,
2156                         .flags = CLK_SET_RATE_PARENT,
2157                         .ops = &clk_branch2_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2163         .halt_reg = 0x4144,
2164         .halt_check = BRANCH_HALT_VOTED,
2165         .clkr = {
2166                 .enable_reg = 0x52004,
2167                 .enable_mask = BIT(0),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2170                         .parent_hws = (const struct clk_hw*[]){
2171                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
2172                         },
2173                         .num_parents = 1,
2174                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2175                         .ops = &clk_branch2_ops,
2176                 },
2177         },
2178 };
2179
2180 static struct clk_branch gcc_tsif_ahb_clk = {
2181         .halt_reg = 0x36004,
2182         .halt_check = BRANCH_HALT,
2183         .clkr = {
2184                 .enable_reg = 0x36004,
2185                 .enable_mask = BIT(0),
2186                 .hw.init = &(struct clk_init_data){
2187                         .name = "gcc_tsif_ahb_clk",
2188                         .ops = &clk_branch2_ops,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2194         .halt_reg = 0x3600c,
2195         .halt_check = BRANCH_HALT,
2196         .clkr = {
2197                 .enable_reg = 0x3600c,
2198                 .enable_mask = BIT(0),
2199                 .hw.init = &(struct clk_init_data){
2200                         .name = "gcc_tsif_inactivity_timers_clk",
2201                         .ops = &clk_branch2_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch gcc_tsif_ref_clk = {
2207         .halt_reg = 0x36008,
2208         .halt_check = BRANCH_HALT,
2209         .clkr = {
2210                 .enable_reg = 0x36008,
2211                 .enable_mask = BIT(0),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "gcc_tsif_ref_clk",
2214                         .parent_hws = (const struct clk_hw*[]){
2215                                 &gcc_tsif_ref_clk_src.clkr.hw,
2216                         },
2217                         .num_parents = 1,
2218                         .flags = CLK_SET_RATE_PARENT,
2219                         .ops = &clk_branch2_ops,
2220                 },
2221         },
2222 };
2223
2224 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2225         .halt_reg = 0x8c000,
2226         .halt_check = BRANCH_HALT,
2227         .clkr = {
2228                 .enable_reg = 0x8c000,
2229                 .enable_mask = BIT(0),
2230                 .hw.init = &(struct clk_init_data){
2231                         .name = "gcc_ufs_mem_clkref_clk",
2232                         .ops = &clk_branch2_ops,
2233                 },
2234         },
2235 };
2236
2237 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2238         .halt_reg = 0x77014,
2239         .halt_check = BRANCH_HALT,
2240         .hwcg_reg = 0x77014,
2241         .hwcg_bit = 1,
2242         .clkr = {
2243                 .enable_reg = 0x77014,
2244                 .enable_mask = BIT(0),
2245                 .hw.init = &(struct clk_init_data){
2246                         .name = "gcc_ufs_phy_ahb_clk",
2247                         .ops = &clk_branch2_ops,
2248                 },
2249         },
2250 };
2251
2252 static struct clk_branch gcc_ufs_phy_axi_clk = {
2253         .halt_reg = 0x77038,
2254         .halt_check = BRANCH_HALT,
2255         .hwcg_reg = 0x77038,
2256         .hwcg_bit = 1,
2257         .clkr = {
2258                 .enable_reg = 0x77038,
2259                 .enable_mask = BIT(0),
2260                 .hw.init = &(struct clk_init_data){
2261                         .name = "gcc_ufs_phy_axi_clk",
2262                         .parent_hws = (const struct clk_hw*[]){
2263                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2264                         },
2265                         .num_parents = 1,
2266                         .flags = CLK_SET_RATE_PARENT,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2273         .halt_reg = 0x77038,
2274         .halt_check = BRANCH_HALT,
2275         .hwcg_reg = 0x77038,
2276         .hwcg_bit = 1,
2277         .clkr = {
2278                 .enable_reg = 0x77038,
2279                 .enable_mask = BIT(1),
2280                 .hw.init = &(struct clk_init_data){
2281                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2282                         .parent_hws = (const struct clk_hw*[]){
2283                                 &gcc_ufs_phy_axi_clk.clkr.hw,
2284                         },
2285                         .num_parents = 1,
2286                         .flags = CLK_SET_RATE_PARENT,
2287                         .ops = &clk_branch_simple_ops,
2288                 },
2289         },
2290 };
2291
2292 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2293         .halt_reg = 0x77090,
2294         .halt_check = BRANCH_HALT,
2295         .hwcg_reg = 0x77090,
2296         .hwcg_bit = 1,
2297         .clkr = {
2298                 .enable_reg = 0x77090,
2299                 .enable_mask = BIT(0),
2300                 .hw.init = &(struct clk_init_data){
2301                         .name = "gcc_ufs_phy_ice_core_clk",
2302                         .parent_hws = (const struct clk_hw*[]){
2303                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2304                         },
2305                         .num_parents = 1,
2306                         .flags = CLK_SET_RATE_PARENT,
2307                         .ops = &clk_branch2_ops,
2308                 },
2309         },
2310 };
2311
2312 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2313         .halt_reg = 0x77090,
2314         .halt_check = BRANCH_HALT,
2315         .hwcg_reg = 0x77090,
2316         .hwcg_bit = 1,
2317         .clkr = {
2318                 .enable_reg = 0x77090,
2319                 .enable_mask = BIT(1),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2322                         .parent_hws = (const struct clk_hw*[]){
2323                                 &gcc_ufs_phy_ice_core_clk.clkr.hw,
2324                         },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch_simple_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2333         .halt_reg = 0x77094,
2334         .halt_check = BRANCH_HALT,
2335         .hwcg_reg = 0x77094,
2336         .hwcg_bit = 1,
2337         .clkr = {
2338                 .enable_reg = 0x77094,
2339                 .enable_mask = BIT(0),
2340                 .hw.init = &(struct clk_init_data){
2341                         .name = "gcc_ufs_phy_phy_aux_clk",
2342                         .parent_hws = (const struct clk_hw*[]){
2343                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2344                         },
2345                         .num_parents = 1,
2346                         .flags = CLK_SET_RATE_PARENT,
2347                         .ops = &clk_branch2_ops,
2348                 },
2349         },
2350 };
2351
2352 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2353         .halt_reg = 0x77094,
2354         .halt_check = BRANCH_HALT,
2355         .hwcg_reg = 0x77094,
2356         .hwcg_bit = 1,
2357         .clkr = {
2358                 .enable_reg = 0x77094,
2359                 .enable_mask = BIT(1),
2360                 .hw.init = &(struct clk_init_data){
2361                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2362                         .parent_hws = (const struct clk_hw*[]){
2363                                 &gcc_ufs_phy_phy_aux_clk.clkr.hw,
2364                         },
2365                         .num_parents = 1,
2366                         .flags = CLK_SET_RATE_PARENT,
2367                         .ops = &clk_branch_simple_ops,
2368                 },
2369         },
2370 };
2371
2372 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2373         .halt_reg = 0x7701c,
2374         .halt_check = BRANCH_HALT_SKIP,
2375         .clkr = {
2376                 .enable_reg = 0x7701c,
2377                 .enable_mask = BIT(0),
2378                 .hw.init = &(struct clk_init_data){
2379                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2380                         .ops = &clk_branch2_ops,
2381                 },
2382         },
2383 };
2384
2385 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2386         .halt_reg = 0x77018,
2387         .halt_check = BRANCH_HALT_SKIP,
2388         .clkr = {
2389                 .enable_reg = 0x77018,
2390                 .enable_mask = BIT(0),
2391                 .hw.init = &(struct clk_init_data){
2392                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2393                         .ops = &clk_branch2_ops,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2399         .halt_reg = 0x7708c,
2400         .halt_check = BRANCH_HALT,
2401         .hwcg_reg = 0x7708c,
2402         .hwcg_bit = 1,
2403         .clkr = {
2404                 .enable_reg = 0x7708c,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_ufs_phy_unipro_core_clk",
2408                         .parent_hws = (const struct clk_hw*[]){
2409                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2410                         },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2419         .halt_reg = 0x7708c,
2420         .halt_check = BRANCH_HALT,
2421         .hwcg_reg = 0x7708c,
2422         .hwcg_bit = 1,
2423         .clkr = {
2424                 .enable_reg = 0x7708c,
2425                 .enable_mask = BIT(1),
2426                 .hw.init = &(struct clk_init_data){
2427                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2428                         .parent_hws = (const struct clk_hw*[]){
2429                                 &gcc_ufs_phy_unipro_core_clk.clkr.hw,
2430                         },
2431                         .num_parents = 1,
2432                         .flags = CLK_SET_RATE_PARENT,
2433                         .ops = &clk_branch_simple_ops,
2434                 },
2435         },
2436 };
2437
2438 static struct clk_branch gcc_usb30_prim_master_clk = {
2439         .halt_reg = 0xf010,
2440         .halt_check = BRANCH_HALT,
2441         .clkr = {
2442                 .enable_reg = 0xf010,
2443                 .enable_mask = BIT(0),
2444                 .hw.init = &(struct clk_init_data){
2445                         .name = "gcc_usb30_prim_master_clk",
2446                         .parent_hws = (const struct clk_hw*[]){
2447                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2448                         },
2449                         .num_parents = 1,
2450                         .flags = CLK_SET_RATE_PARENT,
2451                         .ops = &clk_branch2_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2457         .halt_reg = 0xf018,
2458         .halt_check = BRANCH_HALT,
2459         .clkr = {
2460                 .enable_reg = 0xf018,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_usb30_prim_mock_utmi_clk",
2464                         .parent_hws = (const struct clk_hw*[]){
2465                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2466                         },
2467                         .num_parents = 1,
2468                         .flags = CLK_SET_RATE_PARENT,
2469                         .ops = &clk_branch2_ops,
2470                 },
2471         },
2472 };
2473
2474 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2475         .halt_reg = 0xf014,
2476         .halt_check = BRANCH_HALT,
2477         .clkr = {
2478                 .enable_reg = 0xf014,
2479                 .enable_mask = BIT(0),
2480                 .hw.init = &(struct clk_init_data){
2481                         .name = "gcc_usb30_prim_sleep_clk",
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2488         .halt_reg = 0x8c010,
2489         .halt_check = BRANCH_HALT,
2490         .clkr = {
2491                 .enable_reg = 0x8c010,
2492                 .enable_mask = BIT(0),
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "gcc_usb3_prim_clkref_clk",
2495                         .ops = &clk_branch2_ops,
2496                 },
2497         },
2498 };
2499
2500 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2501         .halt_reg = 0xf050,
2502         .halt_check = BRANCH_HALT,
2503         .clkr = {
2504                 .enable_reg = 0xf050,
2505                 .enable_mask = BIT(0),
2506                 .hw.init = &(struct clk_init_data){
2507                         .name = "gcc_usb3_prim_phy_aux_clk",
2508                         .parent_hws = (const struct clk_hw*[]){
2509                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2510                         },
2511                         .num_parents = 1,
2512                         .flags = CLK_SET_RATE_PARENT,
2513                         .ops = &clk_branch2_ops,
2514                 },
2515         },
2516 };
2517
2518 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2519         .halt_reg = 0xf054,
2520         .halt_check = BRANCH_HALT,
2521         .clkr = {
2522                 .enable_reg = 0xf054,
2523                 .enable_mask = BIT(0),
2524                 .hw.init = &(struct clk_init_data){
2525                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2526                         .parent_hws = (const struct clk_hw*[]){
2527                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2528                         },
2529                         .num_parents = 1,
2530                         .flags = CLK_SET_RATE_PARENT,
2531                         .ops = &clk_branch2_ops,
2532                 },
2533         },
2534 };
2535
2536 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2537         .halt_check = BRANCH_HALT_SKIP,
2538         .clkr = {
2539                 .enable_reg = 0xf058,
2540                 .enable_mask = BIT(0),
2541                 .hw.init = &(struct clk_init_data){
2542                         .name = "gcc_usb3_prim_phy_pipe_clk",
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2549         .halt_reg = 0x6a004,
2550         .halt_check = BRANCH_HALT,
2551         .hwcg_reg = 0x6a004,
2552         .hwcg_bit = 1,
2553         .clkr = {
2554                 .enable_reg = 0x6a004,
2555                 .enable_mask = BIT(0),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2558                         .ops = &clk_branch2_ops,
2559                 },
2560         },
2561 };
2562
2563 static struct clk_branch gcc_vdda_vs_clk = {
2564         .halt_reg = 0x7a00c,
2565         .halt_check = BRANCH_HALT,
2566         .clkr = {
2567                 .enable_reg = 0x7a00c,
2568                 .enable_mask = BIT(0),
2569                 .hw.init = &(struct clk_init_data){
2570                         .name = "gcc_vdda_vs_clk",
2571                         .parent_hws = (const struct clk_hw*[]){
2572                                 &gcc_vsensor_clk_src.clkr.hw,
2573                         },
2574                         .num_parents = 1,
2575                         .flags = CLK_SET_RATE_PARENT,
2576                         .ops = &clk_branch2_ops,
2577                 },
2578         },
2579 };
2580
2581 static struct clk_branch gcc_vddcx_vs_clk = {
2582         .halt_reg = 0x7a004,
2583         .halt_check = BRANCH_HALT,
2584         .clkr = {
2585                 .enable_reg = 0x7a004,
2586                 .enable_mask = BIT(0),
2587                 .hw.init = &(struct clk_init_data){
2588                         .name = "gcc_vddcx_vs_clk",
2589                         .parent_hws = (const struct clk_hw*[]){
2590                                 &gcc_vsensor_clk_src.clkr.hw,
2591                         },
2592                         .num_parents = 1,
2593                         .flags = CLK_SET_RATE_PARENT,
2594                         .ops = &clk_branch2_ops,
2595                 },
2596         },
2597 };
2598
2599 static struct clk_branch gcc_vddmx_vs_clk = {
2600         .halt_reg = 0x7a008,
2601         .halt_check = BRANCH_HALT,
2602         .clkr = {
2603                 .enable_reg = 0x7a008,
2604                 .enable_mask = BIT(0),
2605                 .hw.init = &(struct clk_init_data){
2606                         .name = "gcc_vddmx_vs_clk",
2607                         .parent_hws = (const struct clk_hw*[]){
2608                                 &gcc_vsensor_clk_src.clkr.hw,
2609                         },
2610                         .num_parents = 1,
2611                         .flags = CLK_SET_RATE_PARENT,
2612                         .ops = &clk_branch2_ops,
2613                 },
2614         },
2615 };
2616
2617
2618 static struct clk_branch gcc_video_axi_clk = {
2619         .halt_reg = 0xb01c,
2620         .halt_check = BRANCH_HALT,
2621         .clkr = {
2622                 .enable_reg = 0xb01c,
2623                 .enable_mask = BIT(0),
2624                 .hw.init = &(struct clk_init_data){
2625                         .name = "gcc_video_axi_clk",
2626                         .ops = &clk_branch2_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
2632         .halt_reg = 0x7a014,
2633         .halt_check = BRANCH_HALT,
2634         .hwcg_reg = 0x7a014,
2635         .hwcg_bit = 1,
2636         .clkr = {
2637                 .enable_reg = 0x7a014,
2638                 .enable_mask = BIT(0),
2639                 .hw.init = &(struct clk_init_data){
2640                         .name = "gcc_vs_ctrl_ahb_clk",
2641                         .ops = &clk_branch2_ops,
2642                 },
2643         },
2644 };
2645
2646 static struct clk_branch gcc_vs_ctrl_clk = {
2647         .halt_reg = 0x7a010,
2648         .halt_check = BRANCH_HALT,
2649         .clkr = {
2650                 .enable_reg = 0x7a010,
2651                 .enable_mask = BIT(0),
2652                 .hw.init = &(struct clk_init_data){
2653                         .name = "gcc_vs_ctrl_clk",
2654                         .parent_hws = (const struct clk_hw*[]){
2655                                 &gcc_vs_ctrl_clk_src.clkr.hw,
2656                         },
2657                         .num_parents = 1,
2658                         .flags = CLK_SET_RATE_PARENT,
2659                         .ops = &clk_branch2_ops,
2660                 },
2661         },
2662 };
2663
2664 static struct gdsc pcie_0_gdsc = {
2665         .gdscr = 0x6b004,
2666         .pd = {
2667                 .name = "pcie_0_gdsc",
2668         },
2669         .pwrsts = PWRSTS_OFF_ON,
2670 };
2671
2672 static struct gdsc ufs_phy_gdsc = {
2673         .gdscr = 0x77004,
2674         .pd = {
2675                 .name = "ufs_phy_gdsc",
2676         },
2677         .pwrsts = PWRSTS_OFF_ON,
2678 };
2679
2680 static struct gdsc usb30_prim_gdsc = {
2681         .gdscr = 0xf004,
2682         .pd = {
2683                 .name = "usb30_prim_gdsc",
2684         },
2685         .pwrsts = PWRSTS_OFF_ON,
2686 };
2687
2688 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
2689         .gdscr = 0x7d030,
2690         .pd = {
2691                 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
2692         },
2693         .pwrsts = PWRSTS_OFF_ON,
2694         .flags = VOTABLE,
2695 };
2696
2697 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
2698         .gdscr = 0x7d03c,
2699         .pd = {
2700                 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
2701         },
2702         .pwrsts = PWRSTS_OFF_ON,
2703         .flags = VOTABLE,
2704 };
2705
2706 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
2707         .gdscr = 0x7d034,
2708         .pd = {
2709                 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
2710         },
2711         .pwrsts = PWRSTS_OFF_ON,
2712         .flags = VOTABLE,
2713 };
2714
2715 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
2716         .gdscr = 0x7d038,
2717         .pd = {
2718                 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
2719         },
2720         .pwrsts = PWRSTS_OFF_ON,
2721         .flags = VOTABLE,
2722 };
2723
2724 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2725         .gdscr = 0x7d040,
2726         .pd = {
2727                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2728         },
2729         .pwrsts = PWRSTS_OFF_ON,
2730         .flags = VOTABLE,
2731 };
2732
2733 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2734         .gdscr = 0x7d048,
2735         .pd = {
2736                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2737         },
2738         .pwrsts = PWRSTS_OFF_ON,
2739         .flags = VOTABLE,
2740 };
2741
2742 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2743         .gdscr = 0x7d044,
2744         .pd = {
2745                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2746         },
2747         .pwrsts = PWRSTS_OFF_ON,
2748         .flags = VOTABLE,
2749 };
2750
2751 static struct clk_hw *gcc_sm7150_hws[] = {
2752         [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2753 };
2754
2755 static struct clk_regmap *gcc_sm7150_clocks[] = {
2756         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
2757         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2758         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
2759                 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2760         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2761         [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
2762         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2763         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2764         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2765         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2766         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2767         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2768         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2769         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2770         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2771         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2772         [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
2773         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2774         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2775         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2776         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2777         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
2778         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2779         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2780         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2781         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2782         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2783         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2784         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2785         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2786         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2787         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2788         [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
2789         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2790         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2791         [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2792         [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2793         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2794         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2795         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2796         [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
2797         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2798         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2799         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2800         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2801         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2802         [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
2803         [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
2804         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2805         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2806         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2807         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2808         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2809         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2810         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2811         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2812         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2813         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2814         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2815         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2816         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2817         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2818         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2819         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2820         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2821         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2822         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2823         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
2824         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
2825         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
2826         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
2827         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2828         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2829         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2830         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2831         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2832         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2833         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2834         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2835         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2836         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2837         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2838         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2839         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2840         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2841         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
2842         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
2843         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
2844         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
2845         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2846         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2847         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2848         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2849         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2850         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2851         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2852         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2853         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2854         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2855         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2856         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2857         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2858         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2859         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
2860         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2861         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2862         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2863         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2864         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
2865         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2866         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2867         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2868         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2869         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2870         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2871         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2872         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
2873                 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2874         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2875         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2876         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2877         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2878         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2879         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2880         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2881                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2882         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
2883                 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2884         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2885         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2886         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2887         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2888                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2889         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2890         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2891         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2892         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2893         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2894         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2895         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2896         [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
2897         [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
2898         [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
2899         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2900         [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
2901         [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
2902         [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
2903         [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
2904         [GPLL0] = &gpll0.clkr,
2905         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2906         [GPLL6] = &gpll6.clkr,
2907         [GPLL7] = &gpll7.clkr,
2908 };
2909
2910 static const struct qcom_reset_map gcc_sm7150_resets[] = {
2911         [GCC_PCIE_0_BCR] = { 0x6b000 },
2912         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
2913         [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
2914         [GCC_UFS_PHY_BCR] = { 0x77000 },
2915         [GCC_USB30_PRIM_BCR] = { 0xf000 },
2916         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2917         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2918         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2919         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2920         [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2921         [GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 },
2922 };
2923
2924 static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = {
2925         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2926         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2927         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2928         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2929         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2930         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2931         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
2932         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
2933         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2934         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2935         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2936         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2937         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2938         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2939         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
2940         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
2941 };
2942
2943 static struct gdsc *gcc_sm7150_gdscs[] = {
2944         [PCIE_0_GDSC] = &pcie_0_gdsc,
2945         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2946         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2947         [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
2948                         &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
2949         [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
2950                         &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
2951         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
2952                         &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
2953         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
2954                         &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
2955         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2956                         &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2957         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
2958                         &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2959         [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2960 };
2961
2962 static const struct regmap_config gcc_sm7150_regmap_config = {
2963         .reg_bits       = 32,
2964         .reg_stride     = 4,
2965         .val_bits       = 32,
2966         .max_register   = 0x1820b0,
2967         .fast_io        = true,
2968 };
2969
2970 static const struct qcom_cc_desc gcc_sm7150_desc = {
2971         .config = &gcc_sm7150_regmap_config,
2972         .clk_hws = gcc_sm7150_hws,
2973         .num_clk_hws = ARRAY_SIZE(gcc_sm7150_hws),
2974         .clks = gcc_sm7150_clocks,
2975         .num_clks = ARRAY_SIZE(gcc_sm7150_clocks),
2976         .resets = gcc_sm7150_resets,
2977         .num_resets = ARRAY_SIZE(gcc_sm7150_resets),
2978         .gdscs = gcc_sm7150_gdscs,
2979         .num_gdscs = ARRAY_SIZE(gcc_sm7150_gdscs),
2980 };
2981
2982 static const struct of_device_id gcc_sm7150_match_table[] = {
2983         { .compatible = "qcom,sm7150-gcc" },
2984         { }
2985 };
2986 MODULE_DEVICE_TABLE(of, gcc_sm7150_match_table);
2987
2988 static int gcc_sm7150_probe(struct platform_device *pdev)
2989 {
2990         struct regmap *regmap;
2991         int ret;
2992
2993         regmap = qcom_cc_map(pdev, &gcc_sm7150_desc);
2994         if (IS_ERR(regmap))
2995                 return PTR_ERR(regmap);
2996
2997         /*
2998          * Disable the GPLL0 active input to MM blocks, NPU
2999          * and GPU via MISC registers.
3000          */
3001         regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3002         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3003         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3004
3005         /*
3006          * Keep the critical clocks always-ON
3007          * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
3008          * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK,
3009          * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK
3010          */
3011         regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
3012         regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
3013         regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
3014         regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
3015         regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
3016         regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
3017         regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
3018         regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3019
3020         ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc,
3021                                         ARRAY_SIZE(gcc_sm7150_dfs_desc));
3022         if (ret)
3023                 return ret;
3024
3025         return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap);
3026 }
3027
3028 static struct platform_driver gcc_sm7150_driver = {
3029         .probe = gcc_sm7150_probe,
3030         .driver = {
3031                 .name = "gcc-sm7150",
3032                 .of_match_table = gcc_sm7150_match_table,
3033         },
3034 };
3035
3036 static int __init gcc_sm7150_init(void)
3037 {
3038         return platform_driver_register(&gcc_sm7150_driver);
3039 }
3040 subsys_initcall(gcc_sm7150_init);
3041
3042 static void __exit gcc_sm7150_exit(void)
3043 {
3044         platform_driver_unregister(&gcc_sm7150_driver);
3045 }
3046 module_exit(gcc_sm7150_exit);
3047
3048 MODULE_DESCRIPTION("Qualcomm SM7150 Global Clock Controller");
3049 MODULE_LICENSE("GPL");