1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
19 #include "clk-regmap.h"
22 #include "clk-branch.h"
23 #include "clk-alpha-pll.h"
37 static struct clk_alpha_pll gpll0 = {
39 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
43 .hw.init = &(struct clk_init_data){
45 .parent_data = &(const struct clk_parent_data){
46 .fw_name = "bi_tcxo", .name = "bi_tcxo",
49 .ops = &clk_alpha_pll_fixed_fabia_ops,
54 static struct clk_alpha_pll gpll4 = {
56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
58 .enable_reg = 0x52000,
59 .enable_mask = BIT(4),
60 .hw.init = &(struct clk_init_data){
62 .parent_data = &(const struct clk_parent_data){
63 .fw_name = "bi_tcxo", .name = "bi_tcxo",
66 .ops = &clk_alpha_pll_fixed_fabia_ops,
71 static struct clk_alpha_pll gpll6 = {
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
75 .enable_reg = 0x52000,
76 .enable_mask = BIT(6),
77 .hw.init = &(struct clk_init_data){
79 .parent_data = &(const struct clk_parent_data){
80 .fw_name = "bi_tcxo", .name = "bi_tcxo",
83 .ops = &clk_alpha_pll_fixed_fabia_ops,
88 static const struct clk_div_table post_div_table_fabia_even[] = {
96 static struct clk_alpha_pll_postdiv gpll0_out_even = {
99 .post_div_table = post_div_table_fabia_even,
100 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
103 .clkr.hw.init = &(struct clk_init_data){
104 .name = "gpll0_out_even",
105 .parent_hws = (const struct clk_hw*[]){
109 .ops = &clk_alpha_pll_postdiv_fabia_ops,
113 static const struct parent_map gcc_parent_map_0[] = {
115 { P_GPLL0_OUT_MAIN, 1 },
116 { P_GPLL0_OUT_EVEN, 6 },
119 static const struct clk_parent_data gcc_parent_data_0[] = {
120 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
121 { .hw = &gpll0.clkr.hw },
122 { .hw = &gpll0_out_even.clkr.hw },
125 static const struct parent_map gcc_parent_map_1[] = {
127 { P_GPLL0_OUT_MAIN, 1 },
129 { P_GPLL0_OUT_EVEN, 6 },
132 static const struct clk_parent_data gcc_parent_data_1[] = {
133 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
134 { .hw = &gpll0.clkr.hw },
135 { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
136 { .hw = &gpll0_out_even.clkr.hw },
139 static const struct parent_map gcc_parent_map_2[] = {
144 static const struct clk_parent_data gcc_parent_data_2[] = {
145 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
146 { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
149 static const struct parent_map gcc_parent_map_3[] = {
151 { P_GPLL0_OUT_MAIN, 1 },
154 static const struct clk_parent_data gcc_parent_data_3[] = {
155 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
156 { .hw = &gpll0.clkr.hw },
159 static const struct parent_map gcc_parent_map_4[] = {
163 static const struct clk_parent_data gcc_parent_data_4[] = {
164 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
167 static const struct parent_map gcc_parent_map_6[] = {
169 { P_GPLL0_OUT_MAIN, 1 },
170 { P_AUD_REF_CLK, 2 },
171 { P_GPLL0_OUT_EVEN, 6 },
174 static const struct clk_parent_data gcc_parent_data_6[] = {
175 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
176 { .hw = &gpll0.clkr.hw },
177 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
178 { .hw = &gpll0_out_even.clkr.hw },
181 static const struct clk_parent_data gcc_parent_data_7_ao[] = {
182 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
183 { .hw = &gpll0.clkr.hw },
184 { .hw = &gpll0_out_even.clkr.hw },
185 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
188 static const struct clk_parent_data gcc_parent_data_8[] = {
189 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
190 { .hw = &gpll0.clkr.hw },
191 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
194 static const struct clk_parent_data gcc_parent_data_8_ao[] = {
195 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
196 { .hw = &gpll0.clkr.hw },
197 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
200 static const struct parent_map gcc_parent_map_10[] = {
202 { P_GPLL0_OUT_MAIN, 1 },
203 { P_GPLL4_OUT_MAIN, 5 },
204 { P_GPLL0_OUT_EVEN, 6 },
207 static const struct clk_parent_data gcc_parent_data_10[] = {
208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
209 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll4.clkr.hw },
211 { .hw = &gpll0_out_even.clkr.hw },
214 static const struct parent_map gcc_parent_map_11[] = {
216 { P_GPLL0_OUT_MAIN, 1 },
217 { P_GPLL6_OUT_MAIN, 2 },
218 { P_GPLL0_OUT_EVEN, 6 },
221 static const struct clk_parent_data gcc_parent_data_11[] = {
222 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
223 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll6.clkr.hw },
225 { .hw = &gpll0_out_even.clkr.hw },
228 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
229 F(19200000, P_BI_TCXO, 1, 0, 0),
233 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
237 .parent_map = gcc_parent_map_0,
238 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "gcc_cpuss_ahb_clk_src",
241 .parent_data = gcc_parent_data_7_ao,
242 .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao),
243 .ops = &clk_rcg2_ops,
247 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
248 F(19200000, P_BI_TCXO, 1, 0, 0),
252 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
256 .parent_map = gcc_parent_map_3,
257 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
258 .clkr.hw.init = &(struct clk_init_data){
259 .name = "gcc_cpuss_rbcpr_clk_src",
260 .parent_data = gcc_parent_data_8_ao,
261 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
262 .ops = &clk_rcg2_ops,
266 static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = {
267 F(19200000, P_BI_TCXO, 1, 0, 0),
268 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
272 static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
276 .parent_map = gcc_parent_map_3,
277 .freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src,
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gcc_cpuss_rbcpr_clk_src",
280 .parent_data = gcc_parent_data_8_ao,
281 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
282 .ops = &clk_rcg2_ops,
286 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
287 F(19200000, P_BI_TCXO, 1, 0, 0),
288 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
289 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
290 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
291 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
295 static struct clk_rcg2 gcc_gp1_clk_src = {
299 .parent_map = gcc_parent_map_1,
300 .freq_tbl = ftbl_gcc_gp1_clk_src,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "gcc_gp1_clk_src",
303 .parent_data = gcc_parent_data_1,
304 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
305 .ops = &clk_rcg2_ops,
309 static struct clk_rcg2 gcc_gp2_clk_src = {
313 .parent_map = gcc_parent_map_1,
314 .freq_tbl = ftbl_gcc_gp1_clk_src,
315 .clkr.hw.init = &(struct clk_init_data){
316 .name = "gcc_gp2_clk_src",
317 .parent_data = gcc_parent_data_1,
318 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
319 .ops = &clk_rcg2_ops,
323 static struct clk_rcg2 gcc_gp3_clk_src = {
327 .parent_map = gcc_parent_map_1,
328 .freq_tbl = ftbl_gcc_gp1_clk_src,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "gcc_gp3_clk_src",
331 .parent_data = gcc_parent_data_1,
332 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
333 .ops = &clk_rcg2_ops,
337 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
338 F(9600000, P_BI_TCXO, 2, 0, 0),
339 F(19200000, P_BI_TCXO, 1, 0, 0),
343 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
347 .parent_map = gcc_parent_map_2,
348 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
349 .clkr.hw.init = &(struct clk_init_data){
350 .name = "gcc_pcie_0_aux_clk_src",
351 .parent_data = gcc_parent_data_2,
352 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
353 .ops = &clk_rcg2_ops,
357 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
361 .parent_map = gcc_parent_map_2,
362 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
363 .clkr.hw.init = &(struct clk_init_data){
364 .name = "gcc_pcie_1_aux_clk_src",
365 .parent_data = gcc_parent_data_2,
366 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
367 .ops = &clk_rcg2_ops,
371 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
372 F(19200000, P_BI_TCXO, 1, 0, 0),
373 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
377 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
381 .parent_map = gcc_parent_map_0,
382 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "gcc_pcie_phy_refgen_clk_src",
385 .parent_data = gcc_parent_data_0,
386 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
387 .ops = &clk_rcg2_ops,
391 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
392 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
394 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
395 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
399 static struct clk_rcg2 gcc_qspi_core_clk_src = {
403 .parent_map = gcc_parent_map_0,
404 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "gcc_qspi_core_clk_src",
407 .parent_data = gcc_parent_data_0,
408 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
409 .ops = &clk_rcg2_floor_ops,
413 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
414 F(9600000, P_BI_TCXO, 2, 0, 0),
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
420 static struct clk_rcg2 gcc_pdm2_clk_src = {
424 .parent_map = gcc_parent_map_0,
425 .freq_tbl = ftbl_gcc_pdm2_clk_src,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "gcc_pdm2_clk_src",
428 .parent_data = gcc_parent_data_0,
429 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
430 .ops = &clk_rcg2_ops,
434 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
435 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
436 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
437 F(19200000, P_BI_TCXO, 1, 0, 0),
438 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
439 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
440 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
441 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
442 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
443 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
444 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
445 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
446 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
447 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
448 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
449 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
453 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
454 .name = "gcc_qupv3_wrap0_s0_clk_src",
455 .parent_data = gcc_parent_data_0,
456 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
457 .ops = &clk_rcg2_shared_ops,
460 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
464 .parent_map = gcc_parent_map_0,
465 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
466 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
469 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
470 .name = "gcc_qupv3_wrap0_s1_clk_src",
471 .parent_data = gcc_parent_data_0,
472 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
473 .ops = &clk_rcg2_shared_ops,
476 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
480 .parent_map = gcc_parent_map_0,
481 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
482 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
485 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
486 .name = "gcc_qupv3_wrap0_s2_clk_src",
487 .parent_data = gcc_parent_data_0,
488 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
489 .ops = &clk_rcg2_shared_ops,
492 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
496 .parent_map = gcc_parent_map_0,
497 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
498 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
501 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
502 .name = "gcc_qupv3_wrap0_s3_clk_src",
503 .parent_data = gcc_parent_data_0,
504 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
505 .ops = &clk_rcg2_shared_ops,
508 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
512 .parent_map = gcc_parent_map_0,
513 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
514 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
517 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
518 .name = "gcc_qupv3_wrap0_s4_clk_src",
519 .parent_data = gcc_parent_data_0,
520 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
521 .ops = &clk_rcg2_shared_ops,
524 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
528 .parent_map = gcc_parent_map_0,
529 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
530 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
533 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
534 .name = "gcc_qupv3_wrap0_s5_clk_src",
535 .parent_data = gcc_parent_data_0,
536 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
537 .ops = &clk_rcg2_shared_ops,
540 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
544 .parent_map = gcc_parent_map_0,
545 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
546 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
549 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
550 .name = "gcc_qupv3_wrap0_s6_clk_src",
551 .parent_data = gcc_parent_data_0,
552 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
553 .ops = &clk_rcg2_shared_ops,
556 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
562 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
565 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
566 .name = "gcc_qupv3_wrap0_s7_clk_src",
567 .parent_data = gcc_parent_data_0,
568 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
569 .ops = &clk_rcg2_shared_ops,
572 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
576 .parent_map = gcc_parent_map_0,
577 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
578 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
581 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
582 .name = "gcc_qupv3_wrap1_s0_clk_src",
583 .parent_data = gcc_parent_data_0,
584 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
585 .ops = &clk_rcg2_shared_ops,
588 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
592 .parent_map = gcc_parent_map_0,
593 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
594 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
597 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
598 .name = "gcc_qupv3_wrap1_s1_clk_src",
599 .parent_data = gcc_parent_data_0,
600 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
601 .ops = &clk_rcg2_shared_ops,
604 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
613 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
614 .name = "gcc_qupv3_wrap1_s2_clk_src",
615 .parent_data = gcc_parent_data_0,
616 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
617 .ops = &clk_rcg2_shared_ops,
620 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
624 .parent_map = gcc_parent_map_0,
625 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
626 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
629 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
630 .name = "gcc_qupv3_wrap1_s3_clk_src",
631 .parent_data = gcc_parent_data_0,
632 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
633 .ops = &clk_rcg2_shared_ops,
636 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
640 .parent_map = gcc_parent_map_0,
641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
642 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
645 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
646 .name = "gcc_qupv3_wrap1_s4_clk_src",
647 .parent_data = gcc_parent_data_0,
648 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
649 .ops = &clk_rcg2_shared_ops,
652 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
656 .parent_map = gcc_parent_map_0,
657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
658 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
661 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
662 .name = "gcc_qupv3_wrap1_s5_clk_src",
663 .parent_data = gcc_parent_data_0,
664 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
665 .ops = &clk_rcg2_shared_ops,
668 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
672 .parent_map = gcc_parent_map_0,
673 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
674 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
677 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
678 .name = "gcc_qupv3_wrap1_s6_clk_src",
679 .parent_data = gcc_parent_data_0,
680 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
681 .ops = &clk_rcg2_shared_ops,
684 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
688 .parent_map = gcc_parent_map_0,
689 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
690 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
693 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
694 .name = "gcc_qupv3_wrap1_s7_clk_src",
695 .parent_data = gcc_parent_data_0,
696 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
697 .ops = &clk_rcg2_shared_ops,
700 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
704 .parent_map = gcc_parent_map_0,
705 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
706 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
709 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
710 F(144000, P_BI_TCXO, 16, 3, 25),
711 F(400000, P_BI_TCXO, 12, 1, 4),
712 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
713 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
714 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
715 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
716 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
717 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
721 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
725 .parent_map = gcc_parent_map_11,
726 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "gcc_sdcc1_apps_clk_src",
729 .parent_data = gcc_parent_data_11,
730 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
731 .ops = &clk_rcg2_floor_ops,
735 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
736 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
737 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
738 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
739 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
743 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
747 .parent_map = gcc_parent_map_0,
748 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "gcc_sdcc1_ice_core_clk_src",
751 .parent_data = gcc_parent_data_0,
752 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
753 .ops = &clk_rcg2_ops,
757 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
758 F(400000, P_BI_TCXO, 12, 1, 4),
759 F(9600000, P_BI_TCXO, 2, 0, 0),
760 F(19200000, P_BI_TCXO, 1, 0, 0),
761 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
762 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
763 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
764 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
768 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
772 .parent_map = gcc_parent_map_10,
773 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "gcc_sdcc2_apps_clk_src",
776 .parent_data = gcc_parent_data_10,
777 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
778 .ops = &clk_rcg2_floor_ops,
782 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
783 F(400000, P_BI_TCXO, 12, 1, 4),
784 F(9600000, P_BI_TCXO, 2, 0, 0),
785 F(19200000, P_BI_TCXO, 1, 0, 0),
786 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
787 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
788 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
792 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
796 .parent_map = gcc_parent_map_0,
797 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "gcc_sdcc4_apps_clk_src",
800 .parent_data = gcc_parent_data_0,
801 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
802 .ops = &clk_rcg2_floor_ops,
806 static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = {
807 F(400000, P_BI_TCXO, 12, 1, 4),
808 F(9600000, P_BI_TCXO, 2, 0, 0),
809 F(19200000, P_BI_TCXO, 1, 0, 0),
810 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
811 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
812 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
813 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
817 static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = {
821 .parent_map = gcc_parent_map_0,
822 .freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "gcc_sdcc4_apps_clk_src",
825 .parent_data = gcc_parent_data_0,
826 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
827 .ops = &clk_rcg2_floor_ops,
831 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
832 F(105495, P_BI_TCXO, 2, 1, 91),
836 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
840 .parent_map = gcc_parent_map_6,
841 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "gcc_tsif_ref_clk_src",
844 .parent_data = gcc_parent_data_6,
845 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
846 .ops = &clk_rcg2_ops,
850 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
851 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
852 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
853 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
854 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
855 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
859 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
863 .parent_map = gcc_parent_map_0,
864 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
865 .clkr.hw.init = &(struct clk_init_data){
866 .name = "gcc_ufs_card_axi_clk_src",
867 .parent_data = gcc_parent_data_0,
868 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
869 .ops = &clk_rcg2_shared_ops,
873 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
874 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
875 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
876 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
877 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
881 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
885 .parent_map = gcc_parent_map_0,
886 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "gcc_ufs_card_ice_core_clk_src",
889 .parent_data = gcc_parent_data_0,
890 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
891 .ops = &clk_rcg2_shared_ops,
895 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
899 .parent_map = gcc_parent_map_4,
900 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "gcc_ufs_card_phy_aux_clk_src",
903 .parent_data = gcc_parent_data_4,
904 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
905 .ops = &clk_rcg2_ops,
909 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
910 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
911 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
912 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
916 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
920 .parent_map = gcc_parent_map_0,
921 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "gcc_ufs_card_unipro_core_clk_src",
924 .parent_data = gcc_parent_data_0,
925 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
926 .ops = &clk_rcg2_shared_ops,
930 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
931 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
932 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
933 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
934 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
935 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
939 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
943 .parent_map = gcc_parent_map_0,
944 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "gcc_ufs_phy_axi_clk_src",
947 .parent_data = gcc_parent_data_0,
948 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
949 .ops = &clk_rcg2_shared_ops,
953 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
957 .parent_map = gcc_parent_map_0,
958 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "gcc_ufs_phy_ice_core_clk_src",
961 .parent_data = gcc_parent_data_0,
962 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
963 .ops = &clk_rcg2_shared_ops,
967 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
971 .parent_map = gcc_parent_map_4,
972 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
973 .clkr.hw.init = &(struct clk_init_data){
974 .name = "gcc_ufs_phy_phy_aux_clk_src",
975 .parent_data = gcc_parent_data_4,
976 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
977 .ops = &clk_rcg2_shared_ops,
981 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
985 .parent_map = gcc_parent_map_0,
986 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "gcc_ufs_phy_unipro_core_clk_src",
989 .parent_data = gcc_parent_data_0,
990 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
991 .ops = &clk_rcg2_shared_ops,
995 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
996 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
997 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
998 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
999 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1000 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1004 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1008 .parent_map = gcc_parent_map_0,
1009 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1010 .clkr.hw.init = &(struct clk_init_data){
1011 .name = "gcc_usb30_prim_master_clk_src",
1012 .parent_data = gcc_parent_data_0,
1013 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1014 .ops = &clk_rcg2_shared_ops,
1018 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1019 F(19200000, P_BI_TCXO, 1, 0, 0),
1020 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1021 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1022 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1026 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1030 .parent_map = gcc_parent_map_0,
1031 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1032 .clkr.hw.init = &(struct clk_init_data){
1033 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1034 .parent_data = gcc_parent_data_0,
1035 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1036 .ops = &clk_rcg2_shared_ops,
1040 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1041 .cmd_rcgr = 0x10018,
1044 .parent_map = gcc_parent_map_0,
1045 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1046 .clkr.hw.init = &(struct clk_init_data){
1047 .name = "gcc_usb30_sec_master_clk_src",
1048 .parent_data = gcc_parent_data_0,
1049 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1050 .ops = &clk_rcg2_ops,
1054 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1055 .cmd_rcgr = 0x10030,
1058 .parent_map = gcc_parent_map_0,
1059 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1060 .clkr.hw.init = &(struct clk_init_data){
1061 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1062 .parent_data = gcc_parent_data_0,
1063 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1064 .ops = &clk_rcg2_ops,
1068 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1072 .parent_map = gcc_parent_map_2,
1073 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1074 .clkr.hw.init = &(struct clk_init_data){
1075 .name = "gcc_usb3_prim_phy_aux_clk_src",
1076 .parent_data = gcc_parent_data_2,
1077 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1078 .ops = &clk_rcg2_ops,
1082 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1083 .cmd_rcgr = 0x1005c,
1086 .parent_map = gcc_parent_map_2,
1087 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1088 .clkr.hw.init = &(struct clk_init_data){
1089 .name = "gcc_usb3_sec_phy_aux_clk_src",
1090 .parent_data = gcc_parent_data_2,
1091 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1092 .ops = &clk_rcg2_shared_ops,
1096 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
1097 .cmd_rcgr = 0x7a030,
1100 .parent_map = gcc_parent_map_3,
1101 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1102 .clkr.hw.init = &(struct clk_init_data){
1103 .name = "gcc_vs_ctrl_clk_src",
1104 .parent_data = gcc_parent_data_3,
1105 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1106 .ops = &clk_rcg2_ops,
1110 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1111 F(19200000, P_BI_TCXO, 1, 0, 0),
1112 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1113 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1117 static struct clk_rcg2 gcc_vsensor_clk_src = {
1118 .cmd_rcgr = 0x7a018,
1121 .parent_map = gcc_parent_map_3,
1122 .freq_tbl = ftbl_gcc_vsensor_clk_src,
1123 .clkr.hw.init = &(struct clk_init_data){
1124 .name = "gcc_vsensor_clk_src",
1125 .parent_data = gcc_parent_data_8,
1126 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1127 .ops = &clk_rcg2_ops,
1131 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1132 .halt_reg = 0x90014,
1133 .halt_check = BRANCH_HALT,
1135 .enable_reg = 0x90014,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "gcc_aggre_noc_pcie_tbu_clk",
1139 .ops = &clk_branch2_ops,
1144 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1145 .halt_reg = 0x82028,
1146 .halt_check = BRANCH_HALT,
1147 .hwcg_reg = 0x82028,
1150 .enable_reg = 0x82028,
1151 .enable_mask = BIT(0),
1152 .hw.init = &(struct clk_init_data){
1153 .name = "gcc_aggre_ufs_card_axi_clk",
1154 .parent_hws = (const struct clk_hw*[]){
1155 &gcc_ufs_card_axi_clk_src.clkr.hw,
1158 .flags = CLK_SET_RATE_PARENT,
1159 .ops = &clk_branch2_ops,
1164 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1165 .halt_reg = 0x82024,
1166 .halt_check = BRANCH_HALT,
1167 .hwcg_reg = 0x82024,
1170 .enable_reg = 0x82024,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "gcc_aggre_ufs_phy_axi_clk",
1174 .parent_hws = (const struct clk_hw*[]){
1175 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1178 .flags = CLK_SET_RATE_PARENT,
1179 .ops = &clk_branch2_ops,
1184 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1185 .halt_reg = 0x8201c,
1186 .halt_check = BRANCH_HALT,
1188 .enable_reg = 0x8201c,
1189 .enable_mask = BIT(0),
1190 .hw.init = &(struct clk_init_data){
1191 .name = "gcc_aggre_usb3_prim_axi_clk",
1192 .parent_hws = (const struct clk_hw*[]){
1193 &gcc_usb30_prim_master_clk_src.clkr.hw,
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1202 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1203 .halt_reg = 0x82020,
1204 .halt_check = BRANCH_HALT,
1206 .enable_reg = 0x82020,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "gcc_aggre_usb3_sec_axi_clk",
1210 .parent_hws = (const struct clk_hw*[]){
1211 &gcc_usb30_sec_master_clk_src.clkr.hw,
1214 .flags = CLK_SET_RATE_PARENT,
1215 .ops = &clk_branch2_ops,
1220 static struct clk_branch gcc_apc_vs_clk = {
1221 .halt_reg = 0x7a050,
1222 .halt_check = BRANCH_HALT,
1224 .enable_reg = 0x7a050,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "gcc_apc_vs_clk",
1228 .parent_hws = (const struct clk_hw*[]){
1229 &gcc_vsensor_clk_src.clkr.hw,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1238 static struct clk_branch gcc_boot_rom_ahb_clk = {
1239 .halt_reg = 0x38004,
1240 .halt_check = BRANCH_HALT_VOTED,
1241 .hwcg_reg = 0x38004,
1244 .enable_reg = 0x52004,
1245 .enable_mask = BIT(10),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "gcc_boot_rom_ahb_clk",
1248 .ops = &clk_branch2_ops,
1253 static struct clk_branch gcc_camera_ahb_clk = {
1255 .halt_check = BRANCH_HALT,
1259 .enable_reg = 0xb008,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "gcc_camera_ahb_clk",
1263 .flags = CLK_IS_CRITICAL,
1264 .ops = &clk_branch2_ops,
1269 static struct clk_branch gcc_camera_axi_clk = {
1271 .halt_check = BRANCH_VOTED,
1273 .enable_reg = 0xb020,
1274 .enable_mask = BIT(0),
1275 .hw.init = &(struct clk_init_data){
1276 .name = "gcc_camera_axi_clk",
1277 .ops = &clk_branch2_ops,
1282 static struct clk_branch gcc_camera_xo_clk = {
1284 .halt_check = BRANCH_HALT,
1286 .enable_reg = 0xb02c,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data){
1289 .name = "gcc_camera_xo_clk",
1290 .flags = CLK_IS_CRITICAL,
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch gcc_ce1_ahb_clk = {
1297 .halt_reg = 0x4100c,
1298 .halt_check = BRANCH_HALT_VOTED,
1299 .hwcg_reg = 0x4100c,
1302 .enable_reg = 0x52004,
1303 .enable_mask = BIT(3),
1304 .hw.init = &(struct clk_init_data){
1305 .name = "gcc_ce1_ahb_clk",
1306 .ops = &clk_branch2_ops,
1311 static struct clk_branch gcc_ce1_axi_clk = {
1312 .halt_reg = 0x41008,
1313 .halt_check = BRANCH_HALT_VOTED,
1315 .enable_reg = 0x52004,
1316 .enable_mask = BIT(4),
1317 .hw.init = &(struct clk_init_data){
1318 .name = "gcc_ce1_axi_clk",
1319 .ops = &clk_branch2_ops,
1324 static struct clk_branch gcc_ce1_clk = {
1325 .halt_reg = 0x41004,
1326 .halt_check = BRANCH_HALT_VOTED,
1328 .enable_reg = 0x52004,
1329 .enable_mask = BIT(5),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_ce1_clk",
1332 .ops = &clk_branch2_ops,
1337 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1339 .halt_check = BRANCH_HALT,
1341 .enable_reg = 0x502c,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1345 .parent_hws = (const struct clk_hw*[]){
1346 &gcc_usb30_prim_master_clk_src.clkr.hw,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1355 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1357 .halt_check = BRANCH_HALT,
1359 .enable_reg = 0x5030,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data){
1362 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1363 .parent_hws = (const struct clk_hw*[]){
1364 &gcc_usb30_sec_master_clk_src.clkr.hw,
1367 .flags = CLK_SET_RATE_PARENT,
1368 .ops = &clk_branch2_ops,
1373 static struct clk_branch gcc_cpuss_ahb_clk = {
1374 .halt_reg = 0x48000,
1375 .halt_check = BRANCH_HALT_VOTED,
1377 .enable_reg = 0x52004,
1378 .enable_mask = BIT(21),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_cpuss_ahb_clk",
1381 .parent_hws = (const struct clk_hw*[]){
1382 &gcc_cpuss_ahb_clk_src.clkr.hw,
1385 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1392 .halt_reg = 0x48008,
1393 .halt_check = BRANCH_HALT,
1395 .enable_reg = 0x48008,
1396 .enable_mask = BIT(0),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "gcc_cpuss_rbcpr_clk",
1399 .parent_hws = (const struct clk_hw*[]){
1400 &gcc_cpuss_rbcpr_clk_src.clkr.hw,
1403 .flags = CLK_SET_RATE_PARENT,
1404 .ops = &clk_branch2_ops,
1410 * The source clock frequencies are different for SDM670; define a child clock
1411 * pointing to the source clock that uses SDM670 frequencies.
1413 static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = {
1414 .halt_reg = 0x48008,
1415 .halt_check = BRANCH_HALT,
1417 .enable_reg = 0x48008,
1418 .enable_mask = BIT(0),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "gcc_cpuss_rbcpr_clk",
1421 .parent_hws = (const struct clk_hw*[]){
1422 &gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw,
1425 .flags = CLK_SET_RATE_PARENT,
1426 .ops = &clk_branch2_ops,
1431 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1432 .halt_reg = 0x44038,
1433 .halt_check = BRANCH_VOTED,
1435 .enable_reg = 0x44038,
1436 .enable_mask = BIT(0),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "gcc_ddrss_gpu_axi_clk",
1439 .ops = &clk_branch2_ops,
1444 static struct clk_branch gcc_disp_ahb_clk = {
1446 .halt_check = BRANCH_HALT,
1450 .enable_reg = 0xb00c,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gcc_disp_ahb_clk",
1454 .flags = CLK_IS_CRITICAL,
1455 .ops = &clk_branch2_ops,
1460 static struct clk_branch gcc_disp_axi_clk = {
1462 .halt_check = BRANCH_VOTED,
1464 .enable_reg = 0xb024,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_disp_axi_clk",
1468 .ops = &clk_branch2_ops,
1473 static struct clk_branch gcc_disp_gpll0_clk_src = {
1474 .halt_check = BRANCH_HALT_DELAY,
1476 .enable_reg = 0x52004,
1477 .enable_mask = BIT(18),
1478 .hw.init = &(struct clk_init_data){
1479 .name = "gcc_disp_gpll0_clk_src",
1480 .parent_hws = (const struct clk_hw*[]){
1484 .ops = &clk_branch2_aon_ops,
1489 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1490 .halt_check = BRANCH_HALT_DELAY,
1492 .enable_reg = 0x52004,
1493 .enable_mask = BIT(19),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "gcc_disp_gpll0_div_clk_src",
1496 .parent_hws = (const struct clk_hw*[]){
1497 &gpll0_out_even.clkr.hw,
1500 .ops = &clk_branch2_ops,
1505 static struct clk_branch gcc_disp_xo_clk = {
1507 .halt_check = BRANCH_HALT,
1509 .enable_reg = 0xb030,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "gcc_disp_xo_clk",
1513 .flags = CLK_IS_CRITICAL,
1514 .ops = &clk_branch2_ops,
1519 static struct clk_branch gcc_gp1_clk = {
1520 .halt_reg = 0x64000,
1521 .halt_check = BRANCH_HALT,
1523 .enable_reg = 0x64000,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "gcc_gp1_clk",
1527 .parent_hws = (const struct clk_hw*[]){
1528 &gcc_gp1_clk_src.clkr.hw,
1531 .flags = CLK_SET_RATE_PARENT,
1532 .ops = &clk_branch2_ops,
1537 static struct clk_branch gcc_gp2_clk = {
1538 .halt_reg = 0x65000,
1539 .halt_check = BRANCH_HALT,
1541 .enable_reg = 0x65000,
1542 .enable_mask = BIT(0),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "gcc_gp2_clk",
1545 .parent_hws = (const struct clk_hw*[]){
1546 &gcc_gp2_clk_src.clkr.hw,
1549 .flags = CLK_SET_RATE_PARENT,
1550 .ops = &clk_branch2_ops,
1555 static struct clk_branch gcc_gp3_clk = {
1556 .halt_reg = 0x66000,
1557 .halt_check = BRANCH_HALT,
1559 .enable_reg = 0x66000,
1560 .enable_mask = BIT(0),
1561 .hw.init = &(struct clk_init_data){
1562 .name = "gcc_gp3_clk",
1563 .parent_hws = (const struct clk_hw*[]){
1564 &gcc_gp3_clk_src.clkr.hw,
1567 .flags = CLK_SET_RATE_PARENT,
1568 .ops = &clk_branch2_ops,
1573 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1574 .halt_reg = 0x71004,
1575 .halt_check = BRANCH_HALT,
1576 .hwcg_reg = 0x71004,
1579 .enable_reg = 0x71004,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "gcc_gpu_cfg_ahb_clk",
1583 .flags = CLK_IS_CRITICAL,
1584 .ops = &clk_branch2_ops,
1589 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1590 .halt_check = BRANCH_HALT_DELAY,
1592 .enable_reg = 0x52004,
1593 .enable_mask = BIT(15),
1594 .hw.init = &(struct clk_init_data){
1595 .name = "gcc_gpu_gpll0_clk_src",
1596 .parent_hws = (const struct clk_hw*[]){
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1606 .halt_check = BRANCH_HALT_DELAY,
1608 .enable_reg = 0x52004,
1609 .enable_mask = BIT(16),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_gpu_gpll0_div_clk_src",
1612 .parent_hws = (const struct clk_hw*[]){
1613 &gpll0_out_even.clkr.hw,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_gpu_iref_clk = {
1622 .halt_reg = 0x8c010,
1623 .halt_check = BRANCH_HALT,
1625 .enable_reg = 0x8c010,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "gcc_gpu_iref_clk",
1629 .ops = &clk_branch2_ops,
1634 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1635 .halt_reg = 0x7100c,
1636 .halt_check = BRANCH_VOTED,
1638 .enable_reg = 0x7100c,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_gpu_memnoc_gfx_clk",
1642 .ops = &clk_branch2_ops,
1647 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1648 .halt_reg = 0x71018,
1649 .halt_check = BRANCH_HALT,
1651 .enable_reg = 0x71018,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1655 .ops = &clk_branch2_ops,
1660 static struct clk_branch gcc_gpu_vs_clk = {
1661 .halt_reg = 0x7a04c,
1662 .halt_check = BRANCH_HALT,
1664 .enable_reg = 0x7a04c,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_gpu_vs_clk",
1668 .parent_hws = (const struct clk_hw*[]){
1669 &gcc_vsensor_clk_src.clkr.hw,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1678 static struct clk_branch gcc_mss_axis2_clk = {
1679 .halt_reg = 0x8a008,
1680 .halt_check = BRANCH_HALT,
1682 .enable_reg = 0x8a008,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "gcc_mss_axis2_clk",
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1692 .halt_reg = 0x8a000,
1693 .halt_check = BRANCH_HALT,
1694 .hwcg_reg = 0x8a000,
1697 .enable_reg = 0x8a000,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_mss_cfg_ahb_clk",
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1707 .halt_check = BRANCH_HALT_DELAY,
1709 .enable_reg = 0x52004,
1710 .enable_mask = BIT(17),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_mss_gpll0_div_clk_src",
1713 .ops = &clk_branch2_ops,
1718 static struct clk_branch gcc_mss_mfab_axis_clk = {
1719 .halt_reg = 0x8a004,
1720 .halt_check = BRANCH_VOTED,
1721 .hwcg_reg = 0x8a004,
1724 .enable_reg = 0x8a004,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_mss_mfab_axis_clk",
1728 .ops = &clk_branch2_ops,
1733 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1734 .halt_reg = 0x8a154,
1735 .halt_check = BRANCH_VOTED,
1737 .enable_reg = 0x8a154,
1738 .enable_mask = BIT(0),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "gcc_mss_q6_memnoc_axi_clk",
1741 .ops = &clk_branch2_ops,
1746 static struct clk_branch gcc_mss_snoc_axi_clk = {
1747 .halt_reg = 0x8a150,
1748 .halt_check = BRANCH_HALT,
1750 .enable_reg = 0x8a150,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(struct clk_init_data){
1753 .name = "gcc_mss_snoc_axi_clk",
1754 .ops = &clk_branch2_ops,
1759 static struct clk_branch gcc_mss_vs_clk = {
1760 .halt_reg = 0x7a048,
1761 .halt_check = BRANCH_HALT,
1763 .enable_reg = 0x7a048,
1764 .enable_mask = BIT(0),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "gcc_mss_vs_clk",
1767 .parent_hws = (const struct clk_hw*[]){
1768 &gcc_vsensor_clk_src.clkr.hw,
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch gcc_pcie_0_aux_clk = {
1778 .halt_reg = 0x6b01c,
1779 .halt_check = BRANCH_HALT_VOTED,
1781 .enable_reg = 0x5200c,
1782 .enable_mask = BIT(3),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_pcie_0_aux_clk",
1785 .parent_hws = (const struct clk_hw*[]){
1786 &gcc_pcie_0_aux_clk_src.clkr.hw,
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1796 .halt_reg = 0x6b018,
1797 .halt_check = BRANCH_HALT_VOTED,
1798 .hwcg_reg = 0x6b018,
1801 .enable_reg = 0x5200c,
1802 .enable_mask = BIT(2),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "gcc_pcie_0_cfg_ahb_clk",
1805 .ops = &clk_branch2_ops,
1810 static struct clk_branch gcc_pcie_0_clkref_clk = {
1811 .halt_reg = 0x8c00c,
1812 .halt_check = BRANCH_HALT,
1814 .enable_reg = 0x8c00c,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_pcie_0_clkref_clk",
1818 .ops = &clk_branch2_ops,
1823 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1824 .halt_reg = 0x6b014,
1825 .halt_check = BRANCH_HALT_VOTED,
1827 .enable_reg = 0x5200c,
1828 .enable_mask = BIT(1),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "gcc_pcie_0_mstr_axi_clk",
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch gcc_pcie_0_pipe_clk = {
1837 .halt_check = BRANCH_HALT_SKIP,
1839 .enable_reg = 0x5200c,
1840 .enable_mask = BIT(4),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_pcie_0_pipe_clk",
1843 .parent_data = &(const struct clk_parent_data){
1844 .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
1847 .flags = CLK_SET_RATE_PARENT,
1848 .ops = &clk_branch2_ops,
1853 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1854 .halt_reg = 0x6b010,
1855 .halt_check = BRANCH_HALT_VOTED,
1856 .hwcg_reg = 0x6b010,
1859 .enable_reg = 0x5200c,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_pcie_0_slv_axi_clk",
1863 .ops = &clk_branch2_ops,
1868 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1869 .halt_reg = 0x6b00c,
1870 .halt_check = BRANCH_HALT_VOTED,
1872 .enable_reg = 0x5200c,
1873 .enable_mask = BIT(5),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch gcc_pcie_1_aux_clk = {
1882 .halt_reg = 0x8d01c,
1883 .halt_check = BRANCH_HALT_VOTED,
1885 .enable_reg = 0x52004,
1886 .enable_mask = BIT(29),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_pcie_1_aux_clk",
1889 .parent_hws = (const struct clk_hw*[]){
1890 &gcc_pcie_1_aux_clk_src.clkr.hw,
1893 .flags = CLK_SET_RATE_PARENT,
1894 .ops = &clk_branch2_ops,
1899 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1900 .halt_reg = 0x8d018,
1901 .halt_check = BRANCH_HALT_VOTED,
1902 .hwcg_reg = 0x8d018,
1905 .enable_reg = 0x52004,
1906 .enable_mask = BIT(28),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_pcie_1_cfg_ahb_clk",
1909 .ops = &clk_branch2_ops,
1914 static struct clk_branch gcc_pcie_1_clkref_clk = {
1915 .halt_reg = 0x8c02c,
1916 .halt_check = BRANCH_HALT,
1918 .enable_reg = 0x8c02c,
1919 .enable_mask = BIT(0),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "gcc_pcie_1_clkref_clk",
1922 .ops = &clk_branch2_ops,
1927 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1928 .halt_reg = 0x8d014,
1929 .halt_check = BRANCH_HALT_VOTED,
1931 .enable_reg = 0x52004,
1932 .enable_mask = BIT(27),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "gcc_pcie_1_mstr_axi_clk",
1935 .ops = &clk_branch2_ops,
1940 static struct clk_branch gcc_pcie_1_pipe_clk = {
1941 .halt_check = BRANCH_HALT_SKIP,
1943 .enable_reg = 0x52004,
1944 .enable_mask = BIT(30),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "gcc_pcie_1_pipe_clk",
1947 .parent_data = &(const struct clk_parent_data){
1948 .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
1951 .ops = &clk_branch2_ops,
1956 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1957 .halt_reg = 0x8d010,
1958 .halt_check = BRANCH_HALT_VOTED,
1959 .hwcg_reg = 0x8d010,
1962 .enable_reg = 0x52004,
1963 .enable_mask = BIT(26),
1964 .hw.init = &(struct clk_init_data){
1965 .name = "gcc_pcie_1_slv_axi_clk",
1966 .ops = &clk_branch2_ops,
1971 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1972 .halt_reg = 0x8d00c,
1973 .halt_check = BRANCH_HALT_VOTED,
1975 .enable_reg = 0x52004,
1976 .enable_mask = BIT(25),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1979 .ops = &clk_branch2_ops,
1984 static struct clk_branch gcc_pcie_phy_aux_clk = {
1985 .halt_reg = 0x6f004,
1986 .halt_check = BRANCH_HALT,
1988 .enable_reg = 0x6f004,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_pcie_phy_aux_clk",
1992 .parent_hws = (const struct clk_hw*[]){
1993 &gcc_pcie_0_aux_clk_src.clkr.hw,
1996 .flags = CLK_SET_RATE_PARENT,
1997 .ops = &clk_branch2_ops,
2002 static struct clk_branch gcc_pcie_phy_refgen_clk = {
2003 .halt_reg = 0x6f02c,
2004 .halt_check = BRANCH_HALT,
2006 .enable_reg = 0x6f02c,
2007 .enable_mask = BIT(0),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "gcc_pcie_phy_refgen_clk",
2010 .parent_hws = (const struct clk_hw*[]){
2011 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
2014 .flags = CLK_SET_RATE_PARENT,
2015 .ops = &clk_branch2_ops,
2020 static struct clk_branch gcc_pdm2_clk = {
2021 .halt_reg = 0x3300c,
2022 .halt_check = BRANCH_HALT,
2024 .enable_reg = 0x3300c,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_pdm2_clk",
2028 .parent_hws = (const struct clk_hw*[]){
2029 &gcc_pdm2_clk_src.clkr.hw,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2038 static struct clk_branch gcc_pdm_ahb_clk = {
2039 .halt_reg = 0x33004,
2040 .halt_check = BRANCH_HALT,
2041 .hwcg_reg = 0x33004,
2044 .enable_reg = 0x33004,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_pdm_ahb_clk",
2048 .ops = &clk_branch2_ops,
2053 static struct clk_branch gcc_pdm_xo4_clk = {
2054 .halt_reg = 0x33008,
2055 .halt_check = BRANCH_HALT,
2057 .enable_reg = 0x33008,
2058 .enable_mask = BIT(0),
2059 .hw.init = &(struct clk_init_data){
2060 .name = "gcc_pdm_xo4_clk",
2061 .ops = &clk_branch2_ops,
2066 static struct clk_branch gcc_prng_ahb_clk = {
2067 .halt_reg = 0x34004,
2068 .halt_check = BRANCH_HALT_VOTED,
2069 .hwcg_reg = 0x34004,
2072 .enable_reg = 0x52004,
2073 .enable_mask = BIT(13),
2074 .hw.init = &(struct clk_init_data){
2075 .name = "gcc_prng_ahb_clk",
2076 .ops = &clk_branch2_ops,
2081 static struct clk_branch gcc_qmip_camera_ahb_clk = {
2083 .halt_check = BRANCH_HALT,
2087 .enable_reg = 0xb014,
2088 .enable_mask = BIT(0),
2089 .hw.init = &(struct clk_init_data){
2090 .name = "gcc_qmip_camera_ahb_clk",
2091 .ops = &clk_branch2_ops,
2096 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2098 .halt_check = BRANCH_HALT,
2102 .enable_reg = 0xb018,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_qmip_disp_ahb_clk",
2106 .ops = &clk_branch2_ops,
2111 static struct clk_branch gcc_qmip_video_ahb_clk = {
2113 .halt_check = BRANCH_HALT,
2117 .enable_reg = 0xb010,
2118 .enable_mask = BIT(0),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_qmip_video_ahb_clk",
2121 .ops = &clk_branch2_ops,
2126 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2127 .halt_reg = 0x4b000,
2128 .halt_check = BRANCH_HALT,
2130 .enable_reg = 0x4b000,
2131 .enable_mask = BIT(0),
2132 .hw.init = &(struct clk_init_data){
2133 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2134 .ops = &clk_branch2_ops,
2139 static struct clk_branch gcc_qspi_core_clk = {
2140 .halt_reg = 0x4b004,
2141 .halt_check = BRANCH_HALT,
2143 .enable_reg = 0x4b004,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "gcc_qspi_core_clk",
2147 .parent_hws = (const struct clk_hw*[]){
2148 &gcc_qspi_core_clk_src.clkr.hw,
2151 .flags = CLK_SET_RATE_PARENT,
2152 .ops = &clk_branch2_ops,
2157 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2158 .halt_reg = 0x17030,
2159 .halt_check = BRANCH_HALT_VOTED,
2161 .enable_reg = 0x5200c,
2162 .enable_mask = BIT(10),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "gcc_qupv3_wrap0_s0_clk",
2165 .parent_hws = (const struct clk_hw*[]){
2166 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2169 .flags = CLK_SET_RATE_PARENT,
2170 .ops = &clk_branch2_ops,
2175 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2176 .halt_reg = 0x17160,
2177 .halt_check = BRANCH_HALT_VOTED,
2179 .enable_reg = 0x5200c,
2180 .enable_mask = BIT(11),
2181 .hw.init = &(struct clk_init_data){
2182 .name = "gcc_qupv3_wrap0_s1_clk",
2183 .parent_hws = (const struct clk_hw*[]){
2184 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2187 .flags = CLK_SET_RATE_PARENT,
2188 .ops = &clk_branch2_ops,
2193 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2194 .halt_reg = 0x17290,
2195 .halt_check = BRANCH_HALT_VOTED,
2197 .enable_reg = 0x5200c,
2198 .enable_mask = BIT(12),
2199 .hw.init = &(struct clk_init_data){
2200 .name = "gcc_qupv3_wrap0_s2_clk",
2201 .parent_hws = (const struct clk_hw*[]){
2202 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2205 .flags = CLK_SET_RATE_PARENT,
2206 .ops = &clk_branch2_ops,
2211 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2212 .halt_reg = 0x173c0,
2213 .halt_check = BRANCH_HALT_VOTED,
2215 .enable_reg = 0x5200c,
2216 .enable_mask = BIT(13),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "gcc_qupv3_wrap0_s3_clk",
2219 .parent_hws = (const struct clk_hw*[]){
2220 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2223 .flags = CLK_SET_RATE_PARENT,
2224 .ops = &clk_branch2_ops,
2229 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2230 .halt_reg = 0x174f0,
2231 .halt_check = BRANCH_HALT_VOTED,
2233 .enable_reg = 0x5200c,
2234 .enable_mask = BIT(14),
2235 .hw.init = &(struct clk_init_data){
2236 .name = "gcc_qupv3_wrap0_s4_clk",
2237 .parent_hws = (const struct clk_hw*[]){
2238 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2247 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2248 .halt_reg = 0x17620,
2249 .halt_check = BRANCH_HALT_VOTED,
2251 .enable_reg = 0x5200c,
2252 .enable_mask = BIT(15),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "gcc_qupv3_wrap0_s5_clk",
2255 .parent_hws = (const struct clk_hw*[]){
2256 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2259 .flags = CLK_SET_RATE_PARENT,
2260 .ops = &clk_branch2_ops,
2265 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2266 .halt_reg = 0x17750,
2267 .halt_check = BRANCH_HALT_VOTED,
2269 .enable_reg = 0x5200c,
2270 .enable_mask = BIT(16),
2271 .hw.init = &(struct clk_init_data){
2272 .name = "gcc_qupv3_wrap0_s6_clk",
2273 .parent_hws = (const struct clk_hw*[]){
2274 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2277 .flags = CLK_SET_RATE_PARENT,
2278 .ops = &clk_branch2_ops,
2283 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2284 .halt_reg = 0x17880,
2285 .halt_check = BRANCH_HALT_VOTED,
2287 .enable_reg = 0x5200c,
2288 .enable_mask = BIT(17),
2289 .hw.init = &(struct clk_init_data){
2290 .name = "gcc_qupv3_wrap0_s7_clk",
2291 .parent_hws = (const struct clk_hw*[]){
2292 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2295 .flags = CLK_SET_RATE_PARENT,
2296 .ops = &clk_branch2_ops,
2301 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2302 .halt_reg = 0x18014,
2303 .halt_check = BRANCH_HALT_VOTED,
2305 .enable_reg = 0x5200c,
2306 .enable_mask = BIT(22),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "gcc_qupv3_wrap1_s0_clk",
2309 .parent_hws = (const struct clk_hw*[]){
2310 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2319 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2320 .halt_reg = 0x18144,
2321 .halt_check = BRANCH_HALT_VOTED,
2323 .enable_reg = 0x5200c,
2324 .enable_mask = BIT(23),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_qupv3_wrap1_s1_clk",
2327 .parent_hws = (const struct clk_hw*[]){
2328 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2338 .halt_reg = 0x18274,
2339 .halt_check = BRANCH_HALT_VOTED,
2341 .enable_reg = 0x5200c,
2342 .enable_mask = BIT(24),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_qupv3_wrap1_s2_clk",
2345 .parent_hws = (const struct clk_hw*[]){
2346 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2349 .flags = CLK_SET_RATE_PARENT,
2350 .ops = &clk_branch2_ops,
2355 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2356 .halt_reg = 0x183a4,
2357 .halt_check = BRANCH_HALT_VOTED,
2359 .enable_reg = 0x5200c,
2360 .enable_mask = BIT(25),
2361 .hw.init = &(struct clk_init_data){
2362 .name = "gcc_qupv3_wrap1_s3_clk",
2363 .parent_hws = (const struct clk_hw*[]){
2364 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2373 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2374 .halt_reg = 0x184d4,
2375 .halt_check = BRANCH_HALT_VOTED,
2377 .enable_reg = 0x5200c,
2378 .enable_mask = BIT(26),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "gcc_qupv3_wrap1_s4_clk",
2381 .parent_hws = (const struct clk_hw*[]){
2382 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2391 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2392 .halt_reg = 0x18604,
2393 .halt_check = BRANCH_HALT_VOTED,
2395 .enable_reg = 0x5200c,
2396 .enable_mask = BIT(27),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "gcc_qupv3_wrap1_s5_clk",
2399 .parent_hws = (const struct clk_hw*[]){
2400 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2403 .flags = CLK_SET_RATE_PARENT,
2404 .ops = &clk_branch2_ops,
2409 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2410 .halt_reg = 0x18734,
2411 .halt_check = BRANCH_HALT_VOTED,
2413 .enable_reg = 0x5200c,
2414 .enable_mask = BIT(28),
2415 .hw.init = &(struct clk_init_data){
2416 .name = "gcc_qupv3_wrap1_s6_clk",
2417 .parent_hws = (const struct clk_hw*[]){
2418 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2421 .flags = CLK_SET_RATE_PARENT,
2422 .ops = &clk_branch2_ops,
2427 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2428 .halt_reg = 0x18864,
2429 .halt_check = BRANCH_HALT_VOTED,
2431 .enable_reg = 0x5200c,
2432 .enable_mask = BIT(29),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_qupv3_wrap1_s7_clk",
2435 .parent_hws = (const struct clk_hw*[]){
2436 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2439 .flags = CLK_SET_RATE_PARENT,
2440 .ops = &clk_branch2_ops,
2445 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2446 .halt_reg = 0x17004,
2447 .halt_check = BRANCH_HALT_VOTED,
2449 .enable_reg = 0x5200c,
2450 .enable_mask = BIT(6),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2453 .ops = &clk_branch2_ops,
2458 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2459 .halt_reg = 0x17008,
2460 .halt_check = BRANCH_HALT_VOTED,
2461 .hwcg_reg = 0x17008,
2464 .enable_reg = 0x5200c,
2465 .enable_mask = BIT(7),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2468 .ops = &clk_branch2_ops,
2473 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2474 .halt_reg = 0x1800c,
2475 .halt_check = BRANCH_HALT_VOTED,
2477 .enable_reg = 0x5200c,
2478 .enable_mask = BIT(20),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2481 .ops = &clk_branch2_ops,
2486 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2487 .halt_reg = 0x18010,
2488 .halt_check = BRANCH_HALT_VOTED,
2489 .hwcg_reg = 0x18010,
2492 .enable_reg = 0x5200c,
2493 .enable_mask = BIT(21),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2496 .ops = &clk_branch2_ops,
2501 static struct clk_branch gcc_sdcc1_ahb_clk = {
2502 .halt_reg = 0x26008,
2503 .halt_check = BRANCH_HALT,
2505 .enable_reg = 0x26008,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "gcc_sdcc1_ahb_clk",
2509 .ops = &clk_branch2_ops,
2514 static struct clk_branch gcc_sdcc1_apps_clk = {
2515 .halt_reg = 0x26004,
2516 .halt_check = BRANCH_HALT,
2518 .enable_reg = 0x26004,
2519 .enable_mask = BIT(0),
2520 .hw.init = &(struct clk_init_data){
2521 .name = "gcc_sdcc1_apps_clk",
2522 .parent_hws = (const struct clk_hw*[]){
2523 &gcc_sdcc1_apps_clk_src.clkr.hw,
2526 .flags = CLK_SET_RATE_PARENT,
2527 .ops = &clk_branch2_ops,
2532 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2533 .halt_reg = 0x2600c,
2534 .halt_check = BRANCH_HALT,
2536 .enable_reg = 0x2600c,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(struct clk_init_data){
2539 .name = "gcc_sdcc1_ice_core_clk",
2540 .parent_hws = (const struct clk_hw*[]){
2541 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2544 .flags = CLK_SET_RATE_PARENT,
2545 .ops = &clk_branch2_ops,
2550 static struct clk_branch gcc_sdcc2_ahb_clk = {
2551 .halt_reg = 0x14008,
2552 .halt_check = BRANCH_HALT,
2554 .enable_reg = 0x14008,
2555 .enable_mask = BIT(0),
2556 .hw.init = &(struct clk_init_data){
2557 .name = "gcc_sdcc2_ahb_clk",
2558 .ops = &clk_branch2_ops,
2563 static struct clk_branch gcc_sdcc2_apps_clk = {
2564 .halt_reg = 0x14004,
2565 .halt_check = BRANCH_HALT,
2567 .enable_reg = 0x14004,
2568 .enable_mask = BIT(0),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gcc_sdcc2_apps_clk",
2571 .parent_hws = (const struct clk_hw*[]){
2572 &gcc_sdcc2_apps_clk_src.clkr.hw,
2575 .flags = CLK_SET_RATE_PARENT,
2576 .ops = &clk_branch2_ops,
2581 static struct clk_branch gcc_sdcc4_ahb_clk = {
2582 .halt_reg = 0x16008,
2583 .halt_check = BRANCH_HALT,
2585 .enable_reg = 0x16008,
2586 .enable_mask = BIT(0),
2587 .hw.init = &(struct clk_init_data){
2588 .name = "gcc_sdcc4_ahb_clk",
2589 .ops = &clk_branch2_ops,
2594 static struct clk_branch gcc_sdcc4_apps_clk = {
2595 .halt_reg = 0x16004,
2596 .halt_check = BRANCH_HALT,
2598 .enable_reg = 0x16004,
2599 .enable_mask = BIT(0),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_sdcc4_apps_clk",
2602 .parent_hws = (const struct clk_hw*[]){
2603 &gcc_sdcc4_apps_clk_src.clkr.hw,
2606 .flags = CLK_SET_RATE_PARENT,
2607 .ops = &clk_branch2_ops,
2613 * The source clock frequencies are different for SDM670; define a child clock
2614 * pointing to the source clock that uses SDM670 frequencies.
2616 static struct clk_branch gcc_sdm670_sdcc4_apps_clk = {
2617 .halt_reg = 0x16004,
2618 .halt_check = BRANCH_HALT,
2620 .enable_reg = 0x16004,
2621 .enable_mask = BIT(0),
2622 .hw.init = &(struct clk_init_data){
2623 .name = "gcc_sdcc4_apps_clk",
2624 .parent_hws = (const struct clk_hw*[]){
2625 &gcc_sdm670_sdcc4_apps_clk_src.clkr.hw,
2628 .flags = CLK_SET_RATE_PARENT,
2629 .ops = &clk_branch2_ops,
2634 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2636 .halt_check = BRANCH_HALT_VOTED,
2638 .enable_reg = 0x52004,
2639 .enable_mask = BIT(0),
2640 .hw.init = &(struct clk_init_data){
2641 .name = "gcc_sys_noc_cpuss_ahb_clk",
2642 .parent_hws = (const struct clk_hw*[]){
2643 &gcc_cpuss_ahb_clk_src.clkr.hw,
2646 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2647 .ops = &clk_branch2_ops,
2652 static struct clk_branch gcc_tsif_ahb_clk = {
2653 .halt_reg = 0x36004,
2654 .halt_check = BRANCH_HALT,
2656 .enable_reg = 0x36004,
2657 .enable_mask = BIT(0),
2658 .hw.init = &(struct clk_init_data){
2659 .name = "gcc_tsif_ahb_clk",
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2666 .halt_reg = 0x3600c,
2667 .halt_check = BRANCH_HALT,
2669 .enable_reg = 0x3600c,
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_tsif_inactivity_timers_clk",
2673 .ops = &clk_branch2_ops,
2678 static struct clk_branch gcc_tsif_ref_clk = {
2679 .halt_reg = 0x36008,
2680 .halt_check = BRANCH_HALT,
2682 .enable_reg = 0x36008,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "gcc_tsif_ref_clk",
2686 .parent_hws = (const struct clk_hw*[]){
2687 &gcc_tsif_ref_clk_src.clkr.hw,
2690 .flags = CLK_SET_RATE_PARENT,
2691 .ops = &clk_branch2_ops,
2696 static struct clk_branch gcc_ufs_card_ahb_clk = {
2697 .halt_reg = 0x75010,
2698 .halt_check = BRANCH_HALT,
2699 .hwcg_reg = 0x75010,
2702 .enable_reg = 0x75010,
2703 .enable_mask = BIT(0),
2704 .hw.init = &(struct clk_init_data){
2705 .name = "gcc_ufs_card_ahb_clk",
2706 .ops = &clk_branch2_ops,
2711 static struct clk_branch gcc_ufs_card_axi_clk = {
2712 .halt_reg = 0x7500c,
2713 .halt_check = BRANCH_HALT,
2714 .hwcg_reg = 0x7500c,
2717 .enable_reg = 0x7500c,
2718 .enable_mask = BIT(0),
2719 .hw.init = &(struct clk_init_data){
2720 .name = "gcc_ufs_card_axi_clk",
2721 .parent_hws = (const struct clk_hw*[]){
2722 &gcc_ufs_card_axi_clk_src.clkr.hw,
2725 .flags = CLK_SET_RATE_PARENT,
2726 .ops = &clk_branch2_ops,
2731 static struct clk_branch gcc_ufs_card_clkref_clk = {
2732 .halt_reg = 0x8c004,
2733 .halt_check = BRANCH_HALT,
2735 .enable_reg = 0x8c004,
2736 .enable_mask = BIT(0),
2737 .hw.init = &(struct clk_init_data){
2738 .name = "gcc_ufs_card_clkref_clk",
2739 .ops = &clk_branch2_ops,
2744 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2745 .halt_reg = 0x75058,
2746 .halt_check = BRANCH_HALT,
2747 .hwcg_reg = 0x75058,
2750 .enable_reg = 0x75058,
2751 .enable_mask = BIT(0),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "gcc_ufs_card_ice_core_clk",
2754 .parent_hws = (const struct clk_hw*[]){
2755 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2758 .flags = CLK_SET_RATE_PARENT,
2759 .ops = &clk_branch2_ops,
2764 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2765 .halt_reg = 0x7508c,
2766 .halt_check = BRANCH_HALT,
2767 .hwcg_reg = 0x7508c,
2770 .enable_reg = 0x7508c,
2771 .enable_mask = BIT(0),
2772 .hw.init = &(struct clk_init_data){
2773 .name = "gcc_ufs_card_phy_aux_clk",
2774 .parent_hws = (const struct clk_hw*[]){
2775 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2778 .flags = CLK_SET_RATE_PARENT,
2779 .ops = &clk_branch2_ops,
2784 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2785 .halt_check = BRANCH_HALT_SKIP,
2787 .enable_reg = 0x75018,
2788 .enable_mask = BIT(0),
2789 .hw.init = &(struct clk_init_data){
2790 .name = "gcc_ufs_card_rx_symbol_0_clk",
2791 .ops = &clk_branch2_ops,
2796 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2797 .halt_check = BRANCH_HALT_SKIP,
2799 .enable_reg = 0x750a8,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "gcc_ufs_card_rx_symbol_1_clk",
2803 .ops = &clk_branch2_ops,
2808 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2809 .halt_check = BRANCH_HALT_SKIP,
2811 .enable_reg = 0x75014,
2812 .enable_mask = BIT(0),
2813 .hw.init = &(struct clk_init_data){
2814 .name = "gcc_ufs_card_tx_symbol_0_clk",
2815 .ops = &clk_branch2_ops,
2820 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2821 .halt_reg = 0x75054,
2822 .halt_check = BRANCH_HALT,
2823 .hwcg_reg = 0x75054,
2826 .enable_reg = 0x75054,
2827 .enable_mask = BIT(0),
2828 .hw.init = &(struct clk_init_data){
2829 .name = "gcc_ufs_card_unipro_core_clk",
2830 .parent_hws = (const struct clk_hw*[]){
2831 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2834 .flags = CLK_SET_RATE_PARENT,
2835 .ops = &clk_branch2_ops,
2840 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2841 .halt_reg = 0x8c000,
2842 .halt_check = BRANCH_HALT,
2844 .enable_reg = 0x8c000,
2845 .enable_mask = BIT(0),
2846 .hw.init = &(struct clk_init_data){
2847 .name = "gcc_ufs_mem_clkref_clk",
2848 .ops = &clk_branch2_ops,
2853 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2854 .halt_reg = 0x77010,
2855 .halt_check = BRANCH_HALT,
2856 .hwcg_reg = 0x77010,
2859 .enable_reg = 0x77010,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "gcc_ufs_phy_ahb_clk",
2863 .ops = &clk_branch2_ops,
2868 static struct clk_branch gcc_ufs_phy_axi_clk = {
2869 .halt_reg = 0x7700c,
2870 .halt_check = BRANCH_HALT,
2871 .hwcg_reg = 0x7700c,
2874 .enable_reg = 0x7700c,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "gcc_ufs_phy_axi_clk",
2878 .parent_hws = (const struct clk_hw*[]){
2879 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2882 .flags = CLK_SET_RATE_PARENT,
2883 .ops = &clk_branch2_ops,
2888 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2889 .halt_reg = 0x77058,
2890 .halt_check = BRANCH_HALT,
2891 .hwcg_reg = 0x77058,
2894 .enable_reg = 0x77058,
2895 .enable_mask = BIT(0),
2896 .hw.init = &(struct clk_init_data){
2897 .name = "gcc_ufs_phy_ice_core_clk",
2898 .parent_hws = (const struct clk_hw*[]){
2899 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2902 .flags = CLK_SET_RATE_PARENT,
2903 .ops = &clk_branch2_ops,
2908 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2909 .halt_reg = 0x7708c,
2910 .halt_check = BRANCH_HALT,
2911 .hwcg_reg = 0x7708c,
2914 .enable_reg = 0x7708c,
2915 .enable_mask = BIT(0),
2916 .hw.init = &(struct clk_init_data){
2917 .name = "gcc_ufs_phy_phy_aux_clk",
2918 .parent_hws = (const struct clk_hw*[]){
2919 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2922 .flags = CLK_SET_RATE_PARENT,
2923 .ops = &clk_branch2_ops,
2928 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2929 .halt_check = BRANCH_HALT_SKIP,
2931 .enable_reg = 0x77018,
2932 .enable_mask = BIT(0),
2933 .hw.init = &(struct clk_init_data){
2934 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2935 .ops = &clk_branch2_ops,
2940 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2941 .halt_check = BRANCH_HALT_SKIP,
2943 .enable_reg = 0x770a8,
2944 .enable_mask = BIT(0),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2947 .ops = &clk_branch2_ops,
2952 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2953 .halt_check = BRANCH_HALT_SKIP,
2955 .enable_reg = 0x77014,
2956 .enable_mask = BIT(0),
2957 .hw.init = &(struct clk_init_data){
2958 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2959 .ops = &clk_branch2_ops,
2964 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2965 .halt_reg = 0x77054,
2966 .halt_check = BRANCH_HALT,
2967 .hwcg_reg = 0x77054,
2970 .enable_reg = 0x77054,
2971 .enable_mask = BIT(0),
2972 .hw.init = &(struct clk_init_data){
2973 .name = "gcc_ufs_phy_unipro_core_clk",
2974 .parent_hws = (const struct clk_hw*[]){
2975 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2978 .flags = CLK_SET_RATE_PARENT,
2979 .ops = &clk_branch2_ops,
2984 static struct clk_branch gcc_usb30_prim_master_clk = {
2986 .halt_check = BRANCH_HALT,
2988 .enable_reg = 0xf00c,
2989 .enable_mask = BIT(0),
2990 .hw.init = &(struct clk_init_data){
2991 .name = "gcc_usb30_prim_master_clk",
2992 .parent_hws = (const struct clk_hw*[]){
2993 &gcc_usb30_prim_master_clk_src.clkr.hw,
2996 .flags = CLK_SET_RATE_PARENT,
2997 .ops = &clk_branch2_ops,
3002 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3004 .halt_check = BRANCH_HALT,
3006 .enable_reg = 0xf014,
3007 .enable_mask = BIT(0),
3008 .hw.init = &(struct clk_init_data){
3009 .name = "gcc_usb30_prim_mock_utmi_clk",
3010 .parent_hws = (const struct clk_hw*[]){
3011 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3014 .flags = CLK_SET_RATE_PARENT,
3015 .ops = &clk_branch2_ops,
3020 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3022 .halt_check = BRANCH_HALT,
3024 .enable_reg = 0xf010,
3025 .enable_mask = BIT(0),
3026 .hw.init = &(struct clk_init_data){
3027 .name = "gcc_usb30_prim_sleep_clk",
3028 .ops = &clk_branch2_ops,
3033 static struct clk_branch gcc_usb30_sec_master_clk = {
3034 .halt_reg = 0x1000c,
3035 .halt_check = BRANCH_HALT,
3037 .enable_reg = 0x1000c,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "gcc_usb30_sec_master_clk",
3041 .parent_hws = (const struct clk_hw*[]){
3042 &gcc_usb30_sec_master_clk_src.clkr.hw,
3045 .flags = CLK_SET_RATE_PARENT,
3046 .ops = &clk_branch2_ops,
3051 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3052 .halt_reg = 0x10014,
3053 .halt_check = BRANCH_HALT,
3055 .enable_reg = 0x10014,
3056 .enable_mask = BIT(0),
3057 .hw.init = &(struct clk_init_data){
3058 .name = "gcc_usb30_sec_mock_utmi_clk",
3059 .parent_hws = (const struct clk_hw*[]){
3060 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
3063 .flags = CLK_SET_RATE_PARENT,
3064 .ops = &clk_branch2_ops,
3069 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3070 .halt_reg = 0x10010,
3071 .halt_check = BRANCH_HALT,
3073 .enable_reg = 0x10010,
3074 .enable_mask = BIT(0),
3075 .hw.init = &(struct clk_init_data){
3076 .name = "gcc_usb30_sec_sleep_clk",
3077 .ops = &clk_branch2_ops,
3082 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3083 .halt_reg = 0x8c008,
3084 .halt_check = BRANCH_HALT,
3086 .enable_reg = 0x8c008,
3087 .enable_mask = BIT(0),
3088 .hw.init = &(struct clk_init_data){
3089 .name = "gcc_usb3_prim_clkref_clk",
3090 .ops = &clk_branch2_ops,
3095 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3097 .halt_check = BRANCH_HALT,
3099 .enable_reg = 0xf04c,
3100 .enable_mask = BIT(0),
3101 .hw.init = &(struct clk_init_data){
3102 .name = "gcc_usb3_prim_phy_aux_clk",
3103 .parent_hws = (const struct clk_hw*[]){
3104 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3107 .flags = CLK_SET_RATE_PARENT,
3108 .ops = &clk_branch2_ops,
3113 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3115 .halt_check = BRANCH_HALT,
3117 .enable_reg = 0xf050,
3118 .enable_mask = BIT(0),
3119 .hw.init = &(struct clk_init_data){
3120 .name = "gcc_usb3_prim_phy_com_aux_clk",
3121 .parent_hws = (const struct clk_hw*[]){
3122 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3125 .flags = CLK_SET_RATE_PARENT,
3126 .ops = &clk_branch2_ops,
3131 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3132 .halt_check = BRANCH_HALT_SKIP,
3134 .enable_reg = 0xf054,
3135 .enable_mask = BIT(0),
3136 .hw.init = &(struct clk_init_data){
3137 .name = "gcc_usb3_prim_phy_pipe_clk",
3138 .ops = &clk_branch2_ops,
3143 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3144 .halt_reg = 0x8c028,
3145 .halt_check = BRANCH_HALT,
3147 .enable_reg = 0x8c028,
3148 .enable_mask = BIT(0),
3149 .hw.init = &(struct clk_init_data){
3150 .name = "gcc_usb3_sec_clkref_clk",
3151 .ops = &clk_branch2_ops,
3156 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3157 .halt_reg = 0x1004c,
3158 .halt_check = BRANCH_HALT,
3160 .enable_reg = 0x1004c,
3161 .enable_mask = BIT(0),
3162 .hw.init = &(struct clk_init_data){
3163 .name = "gcc_usb3_sec_phy_aux_clk",
3164 .parent_hws = (const struct clk_hw*[]){
3165 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3174 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3175 .halt_reg = 0x10050,
3176 .halt_check = BRANCH_HALT,
3178 .enable_reg = 0x10050,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb3_sec_phy_com_aux_clk",
3182 .parent_hws = (const struct clk_hw*[]){
3183 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3186 .flags = CLK_SET_RATE_PARENT,
3187 .ops = &clk_branch2_ops,
3192 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3193 .halt_check = BRANCH_HALT_SKIP,
3195 .enable_reg = 0x10054,
3196 .enable_mask = BIT(0),
3197 .hw.init = &(struct clk_init_data){
3198 .name = "gcc_usb3_sec_phy_pipe_clk",
3199 .ops = &clk_branch2_ops,
3204 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
3205 .halt_reg = 0x6a004,
3206 .halt_check = BRANCH_HALT,
3207 .hwcg_reg = 0x6a004,
3210 .enable_reg = 0x6a004,
3211 .enable_mask = BIT(0),
3212 .hw.init = &(struct clk_init_data){
3213 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
3214 .ops = &clk_branch2_ops,
3219 static struct clk_branch gcc_vdda_vs_clk = {
3220 .halt_reg = 0x7a00c,
3221 .halt_check = BRANCH_HALT,
3223 .enable_reg = 0x7a00c,
3224 .enable_mask = BIT(0),
3225 .hw.init = &(struct clk_init_data){
3226 .name = "gcc_vdda_vs_clk",
3227 .parent_hws = (const struct clk_hw*[]){
3228 &gcc_vsensor_clk_src.clkr.hw,
3231 .flags = CLK_SET_RATE_PARENT,
3232 .ops = &clk_branch2_ops,
3237 static struct clk_branch gcc_vddcx_vs_clk = {
3238 .halt_reg = 0x7a004,
3239 .halt_check = BRANCH_HALT,
3241 .enable_reg = 0x7a004,
3242 .enable_mask = BIT(0),
3243 .hw.init = &(struct clk_init_data){
3244 .name = "gcc_vddcx_vs_clk",
3245 .parent_hws = (const struct clk_hw*[]){
3246 &gcc_vsensor_clk_src.clkr.hw,
3249 .flags = CLK_SET_RATE_PARENT,
3250 .ops = &clk_branch2_ops,
3255 static struct clk_branch gcc_vddmx_vs_clk = {
3256 .halt_reg = 0x7a008,
3257 .halt_check = BRANCH_HALT,
3259 .enable_reg = 0x7a008,
3260 .enable_mask = BIT(0),
3261 .hw.init = &(struct clk_init_data){
3262 .name = "gcc_vddmx_vs_clk",
3263 .parent_hws = (const struct clk_hw*[]){
3264 &gcc_vsensor_clk_src.clkr.hw,
3267 .flags = CLK_SET_RATE_PARENT,
3268 .ops = &clk_branch2_ops,
3273 static struct clk_branch gcc_video_ahb_clk = {
3275 .halt_check = BRANCH_HALT,
3279 .enable_reg = 0xb004,
3280 .enable_mask = BIT(0),
3281 .hw.init = &(struct clk_init_data){
3282 .name = "gcc_video_ahb_clk",
3283 .flags = CLK_IS_CRITICAL,
3284 .ops = &clk_branch2_ops,
3289 static struct clk_branch gcc_video_axi_clk = {
3291 .halt_check = BRANCH_VOTED,
3293 .enable_reg = 0xb01c,
3294 .enable_mask = BIT(0),
3295 .hw.init = &(struct clk_init_data){
3296 .name = "gcc_video_axi_clk",
3297 .ops = &clk_branch2_ops,
3302 static struct clk_branch gcc_video_xo_clk = {
3304 .halt_check = BRANCH_HALT,
3306 .enable_reg = 0xb028,
3307 .enable_mask = BIT(0),
3308 .hw.init = &(struct clk_init_data){
3309 .name = "gcc_video_xo_clk",
3310 .flags = CLK_IS_CRITICAL,
3311 .ops = &clk_branch2_ops,
3316 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3317 .halt_reg = 0x7a014,
3318 .halt_check = BRANCH_HALT,
3319 .hwcg_reg = 0x7a014,
3322 .enable_reg = 0x7a014,
3323 .enable_mask = BIT(0),
3324 .hw.init = &(struct clk_init_data){
3325 .name = "gcc_vs_ctrl_ahb_clk",
3326 .ops = &clk_branch2_ops,
3331 static struct clk_branch gcc_vs_ctrl_clk = {
3332 .halt_reg = 0x7a010,
3333 .halt_check = BRANCH_HALT,
3335 .enable_reg = 0x7a010,
3336 .enable_mask = BIT(0),
3337 .hw.init = &(struct clk_init_data){
3338 .name = "gcc_vs_ctrl_clk",
3339 .parent_hws = (const struct clk_hw*[]){
3340 &gcc_vs_ctrl_clk_src.clkr.hw,
3343 .flags = CLK_SET_RATE_PARENT,
3344 .ops = &clk_branch2_ops,
3349 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3350 .halt_reg = 0x48190,
3351 .halt_check = BRANCH_HALT,
3353 .enable_reg = 0x48190,
3354 .enable_mask = BIT(0),
3355 .hw.init = &(struct clk_init_data){
3356 .name = "gcc_cpuss_dvm_bus_clk",
3357 .flags = CLK_IS_CRITICAL,
3358 .ops = &clk_branch2_ops,
3363 static struct clk_branch gcc_cpuss_gnoc_clk = {
3364 .halt_reg = 0x48004,
3365 .halt_check = BRANCH_HALT_VOTED,
3366 .hwcg_reg = 0x48004,
3369 .enable_reg = 0x52004,
3370 .enable_mask = BIT(22),
3371 .hw.init = &(struct clk_init_data){
3372 .name = "gcc_cpuss_gnoc_clk",
3373 .flags = CLK_IS_CRITICAL,
3374 .ops = &clk_branch2_ops,
3379 /* TODO: Remove after DTS updated to protect these */
3380 #ifdef CONFIG_SDM_LPASSCC_845
3381 static struct clk_branch gcc_lpass_q6_axi_clk = {
3382 .halt_reg = 0x47000,
3383 .halt_check = BRANCH_HALT,
3385 .enable_reg = 0x47000,
3386 .enable_mask = BIT(0),
3387 .hw.init = &(struct clk_init_data){
3388 .name = "gcc_lpass_q6_axi_clk",
3389 .flags = CLK_IS_CRITICAL,
3390 .ops = &clk_branch2_ops,
3395 static struct clk_branch gcc_lpass_sway_clk = {
3396 .halt_reg = 0x47008,
3397 .halt_check = BRANCH_HALT,
3399 .enable_reg = 0x47008,
3400 .enable_mask = BIT(0),
3401 .hw.init = &(struct clk_init_data){
3402 .name = "gcc_lpass_sway_clk",
3403 .flags = CLK_IS_CRITICAL,
3404 .ops = &clk_branch2_ops,
3410 static struct gdsc pcie_0_gdsc = {
3413 .name = "pcie_0_gdsc",
3415 .pwrsts = PWRSTS_OFF_ON,
3416 .flags = POLL_CFG_GDSCR,
3419 static struct gdsc pcie_1_gdsc = {
3422 .name = "pcie_1_gdsc",
3424 .pwrsts = PWRSTS_OFF_ON,
3425 .flags = POLL_CFG_GDSCR,
3428 static struct gdsc ufs_card_gdsc = {
3431 .name = "ufs_card_gdsc",
3433 .pwrsts = PWRSTS_OFF_ON,
3434 .flags = POLL_CFG_GDSCR,
3437 static struct gdsc ufs_phy_gdsc = {
3440 .name = "ufs_phy_gdsc",
3442 .pwrsts = PWRSTS_OFF_ON,
3443 .flags = POLL_CFG_GDSCR,
3446 static struct gdsc usb30_prim_gdsc = {
3449 .name = "usb30_prim_gdsc",
3451 .pwrsts = PWRSTS_OFF_ON,
3452 .flags = POLL_CFG_GDSCR,
3455 static struct gdsc usb30_sec_gdsc = {
3458 .name = "usb30_sec_gdsc",
3460 .pwrsts = PWRSTS_OFF_ON,
3461 .flags = POLL_CFG_GDSCR,
3464 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3467 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3469 .pwrsts = PWRSTS_OFF_ON,
3473 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3476 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3478 .pwrsts = PWRSTS_OFF_ON,
3482 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3485 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3487 .pwrsts = PWRSTS_OFF_ON,
3491 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3494 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3496 .pwrsts = PWRSTS_OFF_ON,
3500 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3503 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3505 .pwrsts = PWRSTS_OFF_ON,
3509 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3512 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3514 .pwrsts = PWRSTS_OFF_ON,
3518 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3521 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3523 .pwrsts = PWRSTS_OFF_ON,
3527 static struct clk_regmap *gcc_sdm670_clocks[] = {
3528 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3529 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3530 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3531 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3532 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3533 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3534 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3535 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3536 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3537 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3538 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3539 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3540 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3541 [GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr,
3542 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr,
3543 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3544 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3545 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3546 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3547 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3548 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3549 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3550 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3551 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3552 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3553 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3554 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3555 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3556 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3557 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3558 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3559 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3560 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3561 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3562 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3563 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3564 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3565 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3566 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3567 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3568 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3569 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3570 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3571 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3572 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3573 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3574 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3575 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3576 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3577 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3578 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3579 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3580 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3581 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3582 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3583 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3584 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3585 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3586 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3587 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3588 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3589 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3590 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3591 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3592 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3593 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3594 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3595 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3596 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3597 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3598 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3599 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3600 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3601 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3602 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3603 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3604 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3605 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3606 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3607 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3608 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3609 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3610 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3611 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3612 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3613 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3614 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3615 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3616 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3617 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3618 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3619 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3620 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3621 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3622 [GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr,
3623 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr,
3624 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3625 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3626 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3627 &gcc_tsif_inactivity_timers_clk.clkr,
3628 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3629 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3630 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3631 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3632 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3633 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3634 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3635 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3636 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3637 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3638 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3639 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3640 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3641 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3642 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3643 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3644 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3645 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3646 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3647 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3648 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3649 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3650 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3651 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3652 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3653 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3654 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3655 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3656 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3657 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3658 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3659 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3660 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3661 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3662 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3663 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3664 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3665 [GPLL0] = &gpll0.clkr,
3666 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3667 [GPLL4] = &gpll4.clkr,
3668 [GPLL6] = &gpll6.clkr,
3669 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3670 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3671 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3672 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3673 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3676 static struct clk_regmap *gcc_sdm845_clocks[] = {
3677 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3678 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3679 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3680 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3681 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3682 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3683 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3684 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3685 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3686 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3687 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3688 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3689 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3690 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3691 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3692 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3693 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3694 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3695 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3696 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3697 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3698 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3699 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3700 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3701 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3702 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3703 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3704 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3705 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3706 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3707 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3708 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3709 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3710 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3711 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3712 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3713 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3714 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3715 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3716 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3717 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3718 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3719 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3720 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3721 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3722 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3723 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3724 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3725 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3726 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3727 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3728 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3729 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3730 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3731 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3732 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3733 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3734 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3735 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3736 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3737 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3738 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3739 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3740 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3741 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3742 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3743 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3744 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3745 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3746 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3747 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3748 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3749 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3750 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3751 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3752 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3753 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3754 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3755 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3756 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3757 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3758 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3759 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3760 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3761 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3762 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3763 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3764 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3765 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3766 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3767 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3768 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3769 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3770 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3771 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3772 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3773 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3774 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3775 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3776 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3777 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3778 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3779 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3780 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3781 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3782 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3783 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3784 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3785 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3786 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3787 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3788 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3789 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3790 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3791 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3792 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3793 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3794 &gcc_tsif_inactivity_timers_clk.clkr,
3795 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3796 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3797 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3798 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3799 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3800 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3801 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3802 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3803 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3804 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3805 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3806 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3807 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3808 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3809 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3810 &gcc_ufs_card_unipro_core_clk_src.clkr,
3811 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3812 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3813 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3814 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3815 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3816 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3817 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3818 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3819 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3820 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3821 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3822 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3823 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3824 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3825 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3826 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3827 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3828 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3829 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3830 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3831 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3832 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3833 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3834 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3835 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3836 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3837 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3838 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3839 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3840 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3841 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3842 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3843 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3844 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3845 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3846 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3847 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3848 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3849 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3850 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3851 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3852 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3853 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3854 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3855 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3856 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3857 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3858 [GPLL0] = &gpll0.clkr,
3859 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3860 [GPLL4] = &gpll4.clkr,
3861 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3862 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3863 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3864 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3865 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3866 #ifdef CONFIG_SDM_LPASSCC_845
3867 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3868 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3872 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3873 [GCC_MMSS_BCR] = { 0xb000 },
3874 [GCC_PCIE_0_BCR] = { 0x6b000 },
3875 [GCC_PCIE_1_BCR] = { 0x8d000 },
3876 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3877 [GCC_PDM_BCR] = { 0x33000 },
3878 [GCC_PRNG_BCR] = { 0x34000 },
3879 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3880 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3881 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3882 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3883 [GCC_SDCC2_BCR] = { 0x14000 },
3884 [GCC_SDCC4_BCR] = { 0x16000 },
3885 [GCC_TSIF_BCR] = { 0x36000 },
3886 [GCC_UFS_CARD_BCR] = { 0x75000 },
3887 [GCC_UFS_PHY_BCR] = { 0x77000 },
3888 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3889 [GCC_USB30_SEC_BCR] = { 0x10000 },
3890 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3891 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3892 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3893 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3894 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3895 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3896 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3897 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3898 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3901 static struct gdsc *gcc_sdm670_gdscs[] = {
3902 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3903 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3904 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3905 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3906 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3907 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3908 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3909 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3910 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3911 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3912 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3913 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3914 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3917 static struct gdsc *gcc_sdm845_gdscs[] = {
3918 [PCIE_0_GDSC] = &pcie_0_gdsc,
3919 [PCIE_1_GDSC] = &pcie_1_gdsc,
3920 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3921 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3922 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3923 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3924 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3925 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3926 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3927 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3928 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3929 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3930 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3931 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3932 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3933 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3934 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3935 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3936 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3939 static const struct regmap_config gcc_sdm845_regmap_config = {
3943 .max_register = 0x182090,
3947 static const struct qcom_cc_desc gcc_sdm670_desc = {
3948 .config = &gcc_sdm845_regmap_config,
3949 .clks = gcc_sdm670_clocks,
3950 .num_clks = ARRAY_SIZE(gcc_sdm670_clocks),
3951 /* Snapdragon 670 can function without its own exclusive resets. */
3952 .resets = gcc_sdm845_resets,
3953 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3954 .gdscs = gcc_sdm670_gdscs,
3955 .num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
3958 static const struct qcom_cc_desc gcc_sdm845_desc = {
3959 .config = &gcc_sdm845_regmap_config,
3960 .clks = gcc_sdm845_clocks,
3961 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3962 .resets = gcc_sdm845_resets,
3963 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3964 .gdscs = gcc_sdm845_gdscs,
3965 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3968 static const struct of_device_id gcc_sdm845_match_table[] = {
3969 { .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc },
3970 { .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc },
3973 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3975 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3976 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3977 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3978 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3979 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3980 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3981 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3982 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3983 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3984 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3985 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3986 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3987 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3988 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3989 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3990 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3991 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3994 static int gcc_sdm845_probe(struct platform_device *pdev)
3996 const struct qcom_cc_desc *gcc_desc;
3997 struct regmap *regmap;
4000 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
4002 return PTR_ERR(regmap);
4004 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
4005 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
4006 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4008 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4009 ARRAY_SIZE(gcc_dfs_clocks));
4013 gcc_desc = of_device_get_match_data(&pdev->dev);
4014 return qcom_cc_really_probe(pdev, gcc_desc, regmap);
4017 static struct platform_driver gcc_sdm845_driver = {
4018 .probe = gcc_sdm845_probe,
4020 .name = "gcc-sdm845",
4021 .of_match_table = gcc_sdm845_match_table,
4025 static int __init gcc_sdm845_init(void)
4027 return platform_driver_register(&gcc_sdm845_driver);
4029 core_initcall(gcc_sdm845_init);
4031 static void __exit gcc_sdm845_exit(void)
4033 platform_driver_unregister(&gcc_sdm845_driver);
4035 module_exit(gcc_sdm845_exit);
4037 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
4038 MODULE_LICENSE("GPL v2");
4039 MODULE_ALIAS("platform:gcc-sdm845");