1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
20 #include "clk-regmap.h"
23 #include "clk-branch.h"
24 #include "clk-alpha-pll.h"
31 P_CORE_BI_PLL_TEST_SE,
38 static const struct parent_map gcc_parent_map_0[] = {
40 { P_GPLL0_OUT_MAIN, 1 },
41 { P_GPLL0_OUT_EVEN, 6 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
45 static const char * const gcc_parent_names_0[] = {
49 "core_bi_pll_test_se",
52 static const struct parent_map gcc_parent_map_1[] = {
54 { P_GPLL0_OUT_MAIN, 1 },
56 { P_GPLL0_OUT_EVEN, 6 },
57 { P_CORE_BI_PLL_TEST_SE, 7 },
60 static const char * const gcc_parent_names_1[] = {
65 "core_bi_pll_test_se",
68 static const struct parent_map gcc_parent_map_2[] = {
71 { P_CORE_BI_PLL_TEST_SE, 7 },
74 static const char * const gcc_parent_names_2[] = {
77 "core_bi_pll_test_se",
80 static const struct parent_map gcc_parent_map_3[] = {
82 { P_GPLL0_OUT_MAIN, 1 },
83 { P_CORE_BI_PLL_TEST_SE, 7 },
86 static const char * const gcc_parent_names_3[] = {
89 "core_bi_pll_test_se",
92 static const struct parent_map gcc_parent_map_4[] = {
94 { P_CORE_BI_PLL_TEST_SE, 7 },
97 static const char * const gcc_parent_names_4[] = {
99 "core_bi_pll_test_se",
102 static const struct parent_map gcc_parent_map_5[] = {
104 { P_GPLL0_OUT_MAIN, 1 },
105 { P_GPLL4_OUT_MAIN, 5 },
106 { P_GPLL0_OUT_EVEN, 6 },
107 { P_CORE_BI_PLL_TEST_SE, 7 },
110 static const char * const gcc_parent_names_5[] = {
115 "core_bi_pll_test_se",
118 static const struct parent_map gcc_parent_map_6[] = {
120 { P_GPLL0_OUT_MAIN, 1 },
121 { P_AUD_REF_CLK, 2 },
122 { P_GPLL0_OUT_EVEN, 6 },
123 { P_CORE_BI_PLL_TEST_SE, 7 },
126 static const char * const gcc_parent_names_6[] = {
131 "core_bi_pll_test_se",
134 static const char * const gcc_parent_names_7_ao[] = {
138 "core_bi_pll_test_se",
141 static const char * const gcc_parent_names_8[] = {
144 "core_bi_pll_test_se",
147 static const char * const gcc_parent_names_8_ao[] = {
150 "core_bi_pll_test_se",
153 static const struct parent_map gcc_parent_map_10[] = {
155 { P_GPLL0_OUT_MAIN, 1 },
156 { P_GPLL4_OUT_MAIN, 5 },
157 { P_GPLL0_OUT_EVEN, 6 },
158 { P_CORE_BI_PLL_TEST_SE, 7 },
161 static const char * const gcc_parent_names_10[] = {
166 "core_bi_pll_test_se",
169 static struct clk_alpha_pll gpll0 = {
171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
173 .enable_reg = 0x52000,
174 .enable_mask = BIT(0),
175 .hw.init = &(struct clk_init_data){
177 .parent_names = (const char *[]){ "bi_tcxo" },
179 .ops = &clk_alpha_pll_fixed_fabia_ops,
184 static struct clk_alpha_pll gpll4 = {
186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
188 .enable_reg = 0x52000,
189 .enable_mask = BIT(4),
190 .hw.init = &(struct clk_init_data){
192 .parent_names = (const char *[]){ "bi_tcxo" },
194 .ops = &clk_alpha_pll_fixed_fabia_ops,
199 static const struct clk_div_table post_div_table_fabia_even[] = {
207 static struct clk_alpha_pll_postdiv gpll0_out_even = {
210 .post_div_table = post_div_table_fabia_even,
211 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "gpll0_out_even",
216 .parent_names = (const char *[]){ "gpll0" },
218 .ops = &clk_alpha_pll_postdiv_fabia_ops,
222 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
223 F(19200000, P_BI_TCXO, 1, 0, 0),
227 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
231 .parent_map = gcc_parent_map_0,
232 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
233 .clkr.hw.init = &(struct clk_init_data){
234 .name = "gcc_cpuss_ahb_clk_src",
235 .parent_names = gcc_parent_names_7_ao,
237 .ops = &clk_rcg2_ops,
241 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
242 F(19200000, P_BI_TCXO, 1, 0, 0),
246 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
250 .parent_map = gcc_parent_map_3,
251 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
252 .clkr.hw.init = &(struct clk_init_data){
253 .name = "gcc_cpuss_rbcpr_clk_src",
254 .parent_names = gcc_parent_names_8_ao,
256 .ops = &clk_rcg2_ops,
260 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
261 F(19200000, P_BI_TCXO, 1, 0, 0),
262 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
263 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
264 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
265 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
269 static struct clk_rcg2 gcc_gp1_clk_src = {
273 .parent_map = gcc_parent_map_1,
274 .freq_tbl = ftbl_gcc_gp1_clk_src,
275 .clkr.hw.init = &(struct clk_init_data){
276 .name = "gcc_gp1_clk_src",
277 .parent_names = gcc_parent_names_1,
279 .ops = &clk_rcg2_ops,
283 static struct clk_rcg2 gcc_gp2_clk_src = {
287 .parent_map = gcc_parent_map_1,
288 .freq_tbl = ftbl_gcc_gp1_clk_src,
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "gcc_gp2_clk_src",
291 .parent_names = gcc_parent_names_1,
293 .ops = &clk_rcg2_ops,
297 static struct clk_rcg2 gcc_gp3_clk_src = {
301 .parent_map = gcc_parent_map_1,
302 .freq_tbl = ftbl_gcc_gp1_clk_src,
303 .clkr.hw.init = &(struct clk_init_data){
304 .name = "gcc_gp3_clk_src",
305 .parent_names = gcc_parent_names_1,
307 .ops = &clk_rcg2_ops,
311 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
312 F(9600000, P_BI_TCXO, 2, 0, 0),
313 F(19200000, P_BI_TCXO, 1, 0, 0),
317 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
321 .parent_map = gcc_parent_map_2,
322 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "gcc_pcie_0_aux_clk_src",
325 .parent_names = gcc_parent_names_2,
327 .ops = &clk_rcg2_ops,
331 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
335 .parent_map = gcc_parent_map_2,
336 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "gcc_pcie_1_aux_clk_src",
339 .parent_names = gcc_parent_names_2,
341 .ops = &clk_rcg2_ops,
345 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
351 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
355 .parent_map = gcc_parent_map_0,
356 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "gcc_pcie_phy_refgen_clk_src",
359 .parent_names = gcc_parent_names_0,
361 .ops = &clk_rcg2_ops,
365 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
366 F(9600000, P_BI_TCXO, 2, 0, 0),
367 F(19200000, P_BI_TCXO, 1, 0, 0),
368 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
372 static struct clk_rcg2 gcc_pdm2_clk_src = {
376 .parent_map = gcc_parent_map_0,
377 .freq_tbl = ftbl_gcc_pdm2_clk_src,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "gcc_pdm2_clk_src",
380 .parent_names = gcc_parent_names_0,
382 .ops = &clk_rcg2_ops,
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
389 F(19200000, P_BI_TCXO, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
393 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
394 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
395 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
396 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
397 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
398 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
399 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
400 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
401 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
405 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
409 .parent_map = gcc_parent_map_0,
410 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gcc_qupv3_wrap0_s0_clk_src",
413 .parent_names = gcc_parent_names_0,
415 .ops = &clk_rcg2_shared_ops,
419 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
423 .parent_map = gcc_parent_map_0,
424 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
425 .clkr.hw.init = &(struct clk_init_data){
426 .name = "gcc_qupv3_wrap0_s1_clk_src",
427 .parent_names = gcc_parent_names_0,
429 .ops = &clk_rcg2_shared_ops,
433 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
437 .parent_map = gcc_parent_map_0,
438 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
439 .clkr.hw.init = &(struct clk_init_data){
440 .name = "gcc_qupv3_wrap0_s2_clk_src",
441 .parent_names = gcc_parent_names_0,
443 .ops = &clk_rcg2_shared_ops,
447 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
451 .parent_map = gcc_parent_map_0,
452 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
453 .clkr.hw.init = &(struct clk_init_data){
454 .name = "gcc_qupv3_wrap0_s3_clk_src",
455 .parent_names = gcc_parent_names_0,
457 .ops = &clk_rcg2_shared_ops,
461 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
465 .parent_map = gcc_parent_map_0,
466 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
467 .clkr.hw.init = &(struct clk_init_data){
468 .name = "gcc_qupv3_wrap0_s4_clk_src",
469 .parent_names = gcc_parent_names_0,
471 .ops = &clk_rcg2_shared_ops,
475 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
479 .parent_map = gcc_parent_map_0,
480 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "gcc_qupv3_wrap0_s5_clk_src",
483 .parent_names = gcc_parent_names_0,
485 .ops = &clk_rcg2_shared_ops,
489 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
493 .parent_map = gcc_parent_map_0,
494 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
495 .clkr.hw.init = &(struct clk_init_data){
496 .name = "gcc_qupv3_wrap0_s6_clk_src",
497 .parent_names = gcc_parent_names_0,
499 .ops = &clk_rcg2_shared_ops,
503 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
507 .parent_map = gcc_parent_map_0,
508 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "gcc_qupv3_wrap0_s7_clk_src",
511 .parent_names = gcc_parent_names_0,
513 .ops = &clk_rcg2_shared_ops,
517 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
521 .parent_map = gcc_parent_map_0,
522 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
523 .clkr.hw.init = &(struct clk_init_data){
524 .name = "gcc_qupv3_wrap1_s0_clk_src",
525 .parent_names = gcc_parent_names_0,
527 .ops = &clk_rcg2_shared_ops,
531 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
535 .parent_map = gcc_parent_map_0,
536 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
537 .clkr.hw.init = &(struct clk_init_data){
538 .name = "gcc_qupv3_wrap1_s1_clk_src",
539 .parent_names = gcc_parent_names_0,
541 .ops = &clk_rcg2_shared_ops,
545 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
549 .parent_map = gcc_parent_map_0,
550 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "gcc_qupv3_wrap1_s2_clk_src",
553 .parent_names = gcc_parent_names_0,
555 .ops = &clk_rcg2_shared_ops,
559 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "gcc_qupv3_wrap1_s3_clk_src",
567 .parent_names = gcc_parent_names_0,
569 .ops = &clk_rcg2_shared_ops,
573 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
577 .parent_map = gcc_parent_map_0,
578 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
579 .clkr.hw.init = &(struct clk_init_data){
580 .name = "gcc_qupv3_wrap1_s4_clk_src",
581 .parent_names = gcc_parent_names_0,
583 .ops = &clk_rcg2_shared_ops,
587 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
591 .parent_map = gcc_parent_map_0,
592 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
593 .clkr.hw.init = &(struct clk_init_data){
594 .name = "gcc_qupv3_wrap1_s5_clk_src",
595 .parent_names = gcc_parent_names_0,
597 .ops = &clk_rcg2_shared_ops,
601 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
605 .parent_map = gcc_parent_map_0,
606 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "gcc_qupv3_wrap1_s6_clk_src",
609 .parent_names = gcc_parent_names_0,
611 .ops = &clk_rcg2_shared_ops,
615 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
619 .parent_map = gcc_parent_map_0,
620 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "gcc_qupv3_wrap1_s7_clk_src",
623 .parent_names = gcc_parent_names_0,
625 .ops = &clk_rcg2_shared_ops,
629 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
630 F(400000, P_BI_TCXO, 12, 1, 4),
631 F(9600000, P_BI_TCXO, 2, 0, 0),
632 F(19200000, P_BI_TCXO, 1, 0, 0),
633 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
634 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
635 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
636 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
640 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
644 .parent_map = gcc_parent_map_10,
645 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
646 .clkr.hw.init = &(struct clk_init_data){
647 .name = "gcc_sdcc2_apps_clk_src",
648 .parent_names = gcc_parent_names_10,
650 .ops = &clk_rcg2_floor_ops,
654 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
655 F(400000, P_BI_TCXO, 12, 1, 4),
656 F(9600000, P_BI_TCXO, 2, 0, 0),
657 F(19200000, P_BI_TCXO, 1, 0, 0),
658 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
659 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
660 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
664 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
668 .parent_map = gcc_parent_map_0,
669 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "gcc_sdcc4_apps_clk_src",
672 .parent_names = gcc_parent_names_0,
674 .ops = &clk_rcg2_floor_ops,
678 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
679 F(105495, P_BI_TCXO, 2, 1, 91),
683 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
687 .parent_map = gcc_parent_map_6,
688 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "gcc_tsif_ref_clk_src",
691 .parent_names = gcc_parent_names_6,
693 .ops = &clk_rcg2_ops,
697 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
698 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
699 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
700 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
701 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
702 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
706 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
710 .parent_map = gcc_parent_map_0,
711 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "gcc_ufs_card_axi_clk_src",
714 .parent_names = gcc_parent_names_0,
716 .ops = &clk_rcg2_shared_ops,
720 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
721 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
722 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
723 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
724 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
728 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
732 .parent_map = gcc_parent_map_0,
733 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
734 .clkr.hw.init = &(struct clk_init_data){
735 .name = "gcc_ufs_card_ice_core_clk_src",
736 .parent_names = gcc_parent_names_0,
738 .ops = &clk_rcg2_shared_ops,
742 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
746 .parent_map = gcc_parent_map_4,
747 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "gcc_ufs_card_phy_aux_clk_src",
750 .parent_names = gcc_parent_names_4,
752 .ops = &clk_rcg2_ops,
756 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
757 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
758 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
759 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
763 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
767 .parent_map = gcc_parent_map_0,
768 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "gcc_ufs_card_unipro_core_clk_src",
771 .parent_names = gcc_parent_names_0,
773 .ops = &clk_rcg2_shared_ops,
777 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
778 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
779 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
780 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
781 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
782 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
786 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
790 .parent_map = gcc_parent_map_0,
791 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
792 .clkr.hw.init = &(struct clk_init_data){
793 .name = "gcc_ufs_phy_axi_clk_src",
794 .parent_names = gcc_parent_names_0,
796 .ops = &clk_rcg2_shared_ops,
800 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
804 .parent_map = gcc_parent_map_0,
805 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
806 .clkr.hw.init = &(struct clk_init_data){
807 .name = "gcc_ufs_phy_ice_core_clk_src",
808 .parent_names = gcc_parent_names_0,
810 .ops = &clk_rcg2_shared_ops,
814 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
818 .parent_map = gcc_parent_map_4,
819 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "gcc_ufs_phy_phy_aux_clk_src",
822 .parent_names = gcc_parent_names_4,
824 .ops = &clk_rcg2_shared_ops,
828 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
832 .parent_map = gcc_parent_map_0,
833 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "gcc_ufs_phy_unipro_core_clk_src",
836 .parent_names = gcc_parent_names_0,
838 .ops = &clk_rcg2_shared_ops,
842 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
843 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
844 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
845 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
846 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
847 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
851 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
855 .parent_map = gcc_parent_map_0,
856 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
857 .clkr.hw.init = &(struct clk_init_data){
858 .name = "gcc_usb30_prim_master_clk_src",
859 .parent_names = gcc_parent_names_0,
861 .ops = &clk_rcg2_shared_ops,
865 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
866 F(19200000, P_BI_TCXO, 1, 0, 0),
867 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
868 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
869 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
873 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
877 .parent_map = gcc_parent_map_0,
878 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
879 .clkr.hw.init = &(struct clk_init_data){
880 .name = "gcc_usb30_prim_mock_utmi_clk_src",
881 .parent_names = gcc_parent_names_0,
883 .ops = &clk_rcg2_shared_ops,
887 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
891 .parent_map = gcc_parent_map_0,
892 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "gcc_usb30_sec_master_clk_src",
895 .parent_names = gcc_parent_names_0,
897 .ops = &clk_rcg2_ops,
901 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
905 .parent_map = gcc_parent_map_0,
906 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "gcc_usb30_sec_mock_utmi_clk_src",
909 .parent_names = gcc_parent_names_0,
911 .ops = &clk_rcg2_ops,
915 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
919 .parent_map = gcc_parent_map_2,
920 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
921 .clkr.hw.init = &(struct clk_init_data){
922 .name = "gcc_usb3_prim_phy_aux_clk_src",
923 .parent_names = gcc_parent_names_2,
925 .ops = &clk_rcg2_ops,
929 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
933 .parent_map = gcc_parent_map_2,
934 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "gcc_usb3_sec_phy_aux_clk_src",
937 .parent_names = gcc_parent_names_2,
939 .ops = &clk_rcg2_shared_ops,
943 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
947 .parent_map = gcc_parent_map_3,
948 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "gcc_vs_ctrl_clk_src",
951 .parent_names = gcc_parent_names_3,
953 .ops = &clk_rcg2_ops,
957 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
958 F(19200000, P_BI_TCXO, 1, 0, 0),
959 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
960 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
964 static struct clk_rcg2 gcc_vsensor_clk_src = {
968 .parent_map = gcc_parent_map_3,
969 .freq_tbl = ftbl_gcc_vsensor_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "gcc_vsensor_clk_src",
972 .parent_names = gcc_parent_names_8,
974 .ops = &clk_rcg2_ops,
978 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
980 .halt_check = BRANCH_HALT,
982 .enable_reg = 0x90014,
983 .enable_mask = BIT(0),
984 .hw.init = &(struct clk_init_data){
985 .name = "gcc_aggre_noc_pcie_tbu_clk",
986 .ops = &clk_branch2_ops,
991 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
993 .halt_check = BRANCH_HALT,
997 .enable_reg = 0x82028,
998 .enable_mask = BIT(0),
999 .hw.init = &(struct clk_init_data){
1000 .name = "gcc_aggre_ufs_card_axi_clk",
1001 .parent_names = (const char *[]){
1002 "gcc_ufs_card_axi_clk_src",
1005 .flags = CLK_SET_RATE_PARENT,
1006 .ops = &clk_branch2_ops,
1011 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1012 .halt_reg = 0x82024,
1013 .halt_check = BRANCH_HALT,
1014 .hwcg_reg = 0x82024,
1017 .enable_reg = 0x82024,
1018 .enable_mask = BIT(0),
1019 .hw.init = &(struct clk_init_data){
1020 .name = "gcc_aggre_ufs_phy_axi_clk",
1021 .parent_names = (const char *[]){
1022 "gcc_ufs_phy_axi_clk_src",
1025 .flags = CLK_SET_RATE_PARENT,
1026 .ops = &clk_branch2_ops,
1031 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1032 .halt_reg = 0x8201c,
1033 .halt_check = BRANCH_HALT,
1035 .enable_reg = 0x8201c,
1036 .enable_mask = BIT(0),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "gcc_aggre_usb3_prim_axi_clk",
1039 .parent_names = (const char *[]){
1040 "gcc_usb30_prim_master_clk_src",
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1049 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1050 .halt_reg = 0x82020,
1051 .halt_check = BRANCH_HALT,
1053 .enable_reg = 0x82020,
1054 .enable_mask = BIT(0),
1055 .hw.init = &(struct clk_init_data){
1056 .name = "gcc_aggre_usb3_sec_axi_clk",
1057 .parent_names = (const char *[]){
1058 "gcc_usb30_sec_master_clk_src",
1061 .flags = CLK_SET_RATE_PARENT,
1062 .ops = &clk_branch2_ops,
1067 static struct clk_branch gcc_apc_vs_clk = {
1068 .halt_reg = 0x7a050,
1069 .halt_check = BRANCH_HALT,
1071 .enable_reg = 0x7a050,
1072 .enable_mask = BIT(0),
1073 .hw.init = &(struct clk_init_data){
1074 .name = "gcc_apc_vs_clk",
1075 .parent_names = (const char *[]){
1076 "gcc_vsensor_clk_src",
1079 .flags = CLK_SET_RATE_PARENT,
1080 .ops = &clk_branch2_ops,
1085 static struct clk_branch gcc_boot_rom_ahb_clk = {
1086 .halt_reg = 0x38004,
1087 .halt_check = BRANCH_HALT_VOTED,
1088 .hwcg_reg = 0x38004,
1091 .enable_reg = 0x52004,
1092 .enable_mask = BIT(10),
1093 .hw.init = &(struct clk_init_data){
1094 .name = "gcc_boot_rom_ahb_clk",
1095 .ops = &clk_branch2_ops,
1100 static struct clk_branch gcc_camera_ahb_clk = {
1102 .halt_check = BRANCH_HALT,
1106 .enable_reg = 0xb008,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data){
1109 .name = "gcc_camera_ahb_clk",
1110 .flags = CLK_IS_CRITICAL,
1111 .ops = &clk_branch2_ops,
1116 static struct clk_branch gcc_camera_axi_clk = {
1118 .halt_check = BRANCH_VOTED,
1120 .enable_reg = 0xb020,
1121 .enable_mask = BIT(0),
1122 .hw.init = &(struct clk_init_data){
1123 .name = "gcc_camera_axi_clk",
1124 .ops = &clk_branch2_ops,
1129 static struct clk_branch gcc_camera_xo_clk = {
1131 .halt_check = BRANCH_HALT,
1133 .enable_reg = 0xb02c,
1134 .enable_mask = BIT(0),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "gcc_camera_xo_clk",
1137 .flags = CLK_IS_CRITICAL,
1138 .ops = &clk_branch2_ops,
1143 static struct clk_branch gcc_ce1_ahb_clk = {
1144 .halt_reg = 0x4100c,
1145 .halt_check = BRANCH_HALT_VOTED,
1146 .hwcg_reg = 0x4100c,
1149 .enable_reg = 0x52004,
1150 .enable_mask = BIT(3),
1151 .hw.init = &(struct clk_init_data){
1152 .name = "gcc_ce1_ahb_clk",
1153 .ops = &clk_branch2_ops,
1158 static struct clk_branch gcc_ce1_axi_clk = {
1159 .halt_reg = 0x41008,
1160 .halt_check = BRANCH_HALT_VOTED,
1162 .enable_reg = 0x52004,
1163 .enable_mask = BIT(4),
1164 .hw.init = &(struct clk_init_data){
1165 .name = "gcc_ce1_axi_clk",
1166 .ops = &clk_branch2_ops,
1171 static struct clk_branch gcc_ce1_clk = {
1172 .halt_reg = 0x41004,
1173 .halt_check = BRANCH_HALT_VOTED,
1175 .enable_reg = 0x52004,
1176 .enable_mask = BIT(5),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_ce1_clk",
1179 .ops = &clk_branch2_ops,
1184 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1186 .halt_check = BRANCH_HALT,
1188 .enable_reg = 0x502c,
1189 .enable_mask = BIT(0),
1190 .hw.init = &(struct clk_init_data){
1191 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1192 .parent_names = (const char *[]){
1193 "gcc_usb30_prim_master_clk_src",
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1202 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1204 .halt_check = BRANCH_HALT,
1206 .enable_reg = 0x5030,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1210 .parent_names = (const char *[]){
1211 "gcc_usb30_sec_master_clk_src",
1214 .flags = CLK_SET_RATE_PARENT,
1215 .ops = &clk_branch2_ops,
1220 static struct clk_branch gcc_cpuss_ahb_clk = {
1221 .halt_reg = 0x48000,
1222 .halt_check = BRANCH_HALT_VOTED,
1224 .enable_reg = 0x52004,
1225 .enable_mask = BIT(21),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "gcc_cpuss_ahb_clk",
1228 .parent_names = (const char *[]){
1229 "gcc_cpuss_ahb_clk_src",
1232 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1233 .ops = &clk_branch2_ops,
1238 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1239 .halt_reg = 0x48008,
1240 .halt_check = BRANCH_HALT,
1242 .enable_reg = 0x48008,
1243 .enable_mask = BIT(0),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "gcc_cpuss_rbcpr_clk",
1246 .parent_names = (const char *[]){
1247 "gcc_cpuss_rbcpr_clk_src",
1250 .flags = CLK_SET_RATE_PARENT,
1251 .ops = &clk_branch2_ops,
1256 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1257 .halt_reg = 0x44038,
1258 .halt_check = BRANCH_VOTED,
1260 .enable_reg = 0x44038,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_ddrss_gpu_axi_clk",
1264 .ops = &clk_branch2_ops,
1269 static struct clk_branch gcc_disp_ahb_clk = {
1271 .halt_check = BRANCH_HALT,
1275 .enable_reg = 0xb00c,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gcc_disp_ahb_clk",
1279 .flags = CLK_IS_CRITICAL,
1280 .ops = &clk_branch2_ops,
1285 static struct clk_branch gcc_disp_axi_clk = {
1287 .halt_check = BRANCH_VOTED,
1289 .enable_reg = 0xb024,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "gcc_disp_axi_clk",
1293 .ops = &clk_branch2_ops,
1298 static struct clk_branch gcc_disp_gpll0_clk_src = {
1299 .halt_check = BRANCH_HALT_DELAY,
1301 .enable_reg = 0x52004,
1302 .enable_mask = BIT(18),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "gcc_disp_gpll0_clk_src",
1305 .parent_names = (const char *[]){
1309 .ops = &clk_branch2_ops,
1314 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1315 .halt_check = BRANCH_HALT_DELAY,
1317 .enable_reg = 0x52004,
1318 .enable_mask = BIT(19),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_disp_gpll0_div_clk_src",
1321 .parent_names = (const char *[]){
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch gcc_disp_xo_clk = {
1332 .halt_check = BRANCH_HALT,
1334 .enable_reg = 0xb030,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "gcc_disp_xo_clk",
1338 .flags = CLK_IS_CRITICAL,
1339 .ops = &clk_branch2_ops,
1344 static struct clk_branch gcc_gp1_clk = {
1345 .halt_reg = 0x64000,
1346 .halt_check = BRANCH_HALT,
1348 .enable_reg = 0x64000,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "gcc_gp1_clk",
1352 .parent_names = (const char *[]){
1356 .flags = CLK_SET_RATE_PARENT,
1357 .ops = &clk_branch2_ops,
1362 static struct clk_branch gcc_gp2_clk = {
1363 .halt_reg = 0x65000,
1364 .halt_check = BRANCH_HALT,
1366 .enable_reg = 0x65000,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gcc_gp2_clk",
1370 .parent_names = (const char *[]){
1374 .flags = CLK_SET_RATE_PARENT,
1375 .ops = &clk_branch2_ops,
1380 static struct clk_branch gcc_gp3_clk = {
1381 .halt_reg = 0x66000,
1382 .halt_check = BRANCH_HALT,
1384 .enable_reg = 0x66000,
1385 .enable_mask = BIT(0),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "gcc_gp3_clk",
1388 .parent_names = (const char *[]){
1392 .flags = CLK_SET_RATE_PARENT,
1393 .ops = &clk_branch2_ops,
1398 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1399 .halt_reg = 0x71004,
1400 .halt_check = BRANCH_HALT,
1401 .hwcg_reg = 0x71004,
1404 .enable_reg = 0x71004,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "gcc_gpu_cfg_ahb_clk",
1408 .flags = CLK_IS_CRITICAL,
1409 .ops = &clk_branch2_ops,
1414 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1415 .halt_check = BRANCH_HALT_DELAY,
1417 .enable_reg = 0x52004,
1418 .enable_mask = BIT(15),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "gcc_gpu_gpll0_clk_src",
1421 .parent_names = (const char *[]){
1425 .ops = &clk_branch2_ops,
1430 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1431 .halt_check = BRANCH_HALT_DELAY,
1433 .enable_reg = 0x52004,
1434 .enable_mask = BIT(16),
1435 .hw.init = &(struct clk_init_data){
1436 .name = "gcc_gpu_gpll0_div_clk_src",
1437 .parent_names = (const char *[]){
1441 .ops = &clk_branch2_ops,
1446 static struct clk_branch gcc_gpu_iref_clk = {
1447 .halt_reg = 0x8c010,
1448 .halt_check = BRANCH_HALT,
1450 .enable_reg = 0x8c010,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gcc_gpu_iref_clk",
1454 .ops = &clk_branch2_ops,
1459 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1460 .halt_reg = 0x7100c,
1461 .halt_check = BRANCH_VOTED,
1463 .enable_reg = 0x7100c,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(struct clk_init_data){
1466 .name = "gcc_gpu_memnoc_gfx_clk",
1467 .ops = &clk_branch2_ops,
1472 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1473 .halt_reg = 0x71018,
1474 .halt_check = BRANCH_HALT,
1476 .enable_reg = 0x71018,
1477 .enable_mask = BIT(0),
1478 .hw.init = &(struct clk_init_data){
1479 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1480 .ops = &clk_branch2_ops,
1485 static struct clk_branch gcc_gpu_vs_clk = {
1486 .halt_reg = 0x7a04c,
1487 .halt_check = BRANCH_HALT,
1489 .enable_reg = 0x7a04c,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "gcc_gpu_vs_clk",
1493 .parent_names = (const char *[]){
1494 "gcc_vsensor_clk_src",
1497 .flags = CLK_SET_RATE_PARENT,
1498 .ops = &clk_branch2_ops,
1503 static struct clk_branch gcc_mss_axis2_clk = {
1504 .halt_reg = 0x8a008,
1505 .halt_check = BRANCH_HALT,
1507 .enable_reg = 0x8a008,
1508 .enable_mask = BIT(0),
1509 .hw.init = &(struct clk_init_data){
1510 .name = "gcc_mss_axis2_clk",
1511 .ops = &clk_branch2_ops,
1516 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1517 .halt_reg = 0x8a000,
1518 .halt_check = BRANCH_HALT,
1519 .hwcg_reg = 0x8a000,
1522 .enable_reg = 0x8a000,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "gcc_mss_cfg_ahb_clk",
1526 .ops = &clk_branch2_ops,
1531 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1532 .halt_check = BRANCH_HALT_DELAY,
1534 .enable_reg = 0x52004,
1535 .enable_mask = BIT(17),
1536 .hw.init = &(struct clk_init_data){
1537 .name = "gcc_mss_gpll0_div_clk_src",
1538 .ops = &clk_branch2_ops,
1543 static struct clk_branch gcc_mss_mfab_axis_clk = {
1544 .halt_reg = 0x8a004,
1545 .halt_check = BRANCH_VOTED,
1546 .hwcg_reg = 0x8a004,
1549 .enable_reg = 0x8a004,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "gcc_mss_mfab_axis_clk",
1553 .ops = &clk_branch2_ops,
1558 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1559 .halt_reg = 0x8a154,
1560 .halt_check = BRANCH_VOTED,
1562 .enable_reg = 0x8a154,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "gcc_mss_q6_memnoc_axi_clk",
1566 .ops = &clk_branch2_ops,
1571 static struct clk_branch gcc_mss_snoc_axi_clk = {
1572 .halt_reg = 0x8a150,
1573 .halt_check = BRANCH_HALT,
1575 .enable_reg = 0x8a150,
1576 .enable_mask = BIT(0),
1577 .hw.init = &(struct clk_init_data){
1578 .name = "gcc_mss_snoc_axi_clk",
1579 .ops = &clk_branch2_ops,
1584 static struct clk_branch gcc_mss_vs_clk = {
1585 .halt_reg = 0x7a048,
1586 .halt_check = BRANCH_HALT,
1588 .enable_reg = 0x7a048,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "gcc_mss_vs_clk",
1592 .parent_names = (const char *[]){
1593 "gcc_vsensor_clk_src",
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1602 static struct clk_branch gcc_pcie_0_aux_clk = {
1603 .halt_reg = 0x6b01c,
1604 .halt_check = BRANCH_HALT_VOTED,
1606 .enable_reg = 0x5200c,
1607 .enable_mask = BIT(3),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "gcc_pcie_0_aux_clk",
1610 .parent_names = (const char *[]){
1611 "gcc_pcie_0_aux_clk_src",
1614 .flags = CLK_SET_RATE_PARENT,
1615 .ops = &clk_branch2_ops,
1620 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1621 .halt_reg = 0x6b018,
1622 .halt_check = BRANCH_HALT_VOTED,
1623 .hwcg_reg = 0x6b018,
1626 .enable_reg = 0x5200c,
1627 .enable_mask = BIT(2),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "gcc_pcie_0_cfg_ahb_clk",
1630 .ops = &clk_branch2_ops,
1635 static struct clk_branch gcc_pcie_0_clkref_clk = {
1636 .halt_reg = 0x8c00c,
1637 .halt_check = BRANCH_HALT,
1639 .enable_reg = 0x8c00c,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "gcc_pcie_0_clkref_clk",
1643 .ops = &clk_branch2_ops,
1648 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1649 .halt_reg = 0x6b014,
1650 .halt_check = BRANCH_HALT_VOTED,
1652 .enable_reg = 0x5200c,
1653 .enable_mask = BIT(1),
1654 .hw.init = &(struct clk_init_data){
1655 .name = "gcc_pcie_0_mstr_axi_clk",
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch gcc_pcie_0_pipe_clk = {
1662 .halt_check = BRANCH_HALT_SKIP,
1664 .enable_reg = 0x5200c,
1665 .enable_mask = BIT(4),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_pcie_0_pipe_clk",
1668 .ops = &clk_branch2_ops,
1673 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1674 .halt_reg = 0x6b010,
1675 .halt_check = BRANCH_HALT_VOTED,
1676 .hwcg_reg = 0x6b010,
1679 .enable_reg = 0x5200c,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_pcie_0_slv_axi_clk",
1683 .ops = &clk_branch2_ops,
1688 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1689 .halt_reg = 0x6b00c,
1690 .halt_check = BRANCH_HALT_VOTED,
1692 .enable_reg = 0x5200c,
1693 .enable_mask = BIT(5),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1696 .ops = &clk_branch2_ops,
1701 static struct clk_branch gcc_pcie_1_aux_clk = {
1702 .halt_reg = 0x8d01c,
1703 .halt_check = BRANCH_HALT_VOTED,
1705 .enable_reg = 0x52004,
1706 .enable_mask = BIT(29),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "gcc_pcie_1_aux_clk",
1709 .parent_names = (const char *[]){
1710 "gcc_pcie_1_aux_clk_src",
1713 .flags = CLK_SET_RATE_PARENT,
1714 .ops = &clk_branch2_ops,
1719 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1720 .halt_reg = 0x8d018,
1721 .halt_check = BRANCH_HALT_VOTED,
1722 .hwcg_reg = 0x8d018,
1725 .enable_reg = 0x52004,
1726 .enable_mask = BIT(28),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gcc_pcie_1_cfg_ahb_clk",
1729 .ops = &clk_branch2_ops,
1734 static struct clk_branch gcc_pcie_1_clkref_clk = {
1735 .halt_reg = 0x8c02c,
1736 .halt_check = BRANCH_HALT,
1738 .enable_reg = 0x8c02c,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gcc_pcie_1_clkref_clk",
1742 .ops = &clk_branch2_ops,
1747 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1748 .halt_reg = 0x8d014,
1749 .halt_check = BRANCH_HALT_VOTED,
1751 .enable_reg = 0x52004,
1752 .enable_mask = BIT(27),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_pcie_1_mstr_axi_clk",
1755 .ops = &clk_branch2_ops,
1760 static struct clk_branch gcc_pcie_1_pipe_clk = {
1761 .halt_check = BRANCH_HALT_SKIP,
1763 .enable_reg = 0x52004,
1764 .enable_mask = BIT(30),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "gcc_pcie_1_pipe_clk",
1767 .ops = &clk_branch2_ops,
1772 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1773 .halt_reg = 0x8d010,
1774 .halt_check = BRANCH_HALT_VOTED,
1775 .hwcg_reg = 0x8d010,
1778 .enable_reg = 0x52004,
1779 .enable_mask = BIT(26),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "gcc_pcie_1_slv_axi_clk",
1782 .ops = &clk_branch2_ops,
1787 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1788 .halt_reg = 0x8d00c,
1789 .halt_check = BRANCH_HALT_VOTED,
1791 .enable_reg = 0x52004,
1792 .enable_mask = BIT(25),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1795 .ops = &clk_branch2_ops,
1800 static struct clk_branch gcc_pcie_phy_aux_clk = {
1801 .halt_reg = 0x6f004,
1802 .halt_check = BRANCH_HALT,
1804 .enable_reg = 0x6f004,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "gcc_pcie_phy_aux_clk",
1808 .parent_names = (const char *[]){
1809 "gcc_pcie_0_aux_clk_src",
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1818 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1819 .halt_reg = 0x6f02c,
1820 .halt_check = BRANCH_HALT,
1822 .enable_reg = 0x6f02c,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "gcc_pcie_phy_refgen_clk",
1826 .parent_names = (const char *[]){
1827 "gcc_pcie_phy_refgen_clk_src",
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch gcc_pdm2_clk = {
1837 .halt_reg = 0x3300c,
1838 .halt_check = BRANCH_HALT,
1840 .enable_reg = 0x3300c,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "gcc_pdm2_clk",
1844 .parent_names = (const char *[]){
1848 .flags = CLK_SET_RATE_PARENT,
1849 .ops = &clk_branch2_ops,
1854 static struct clk_branch gcc_pdm_ahb_clk = {
1855 .halt_reg = 0x33004,
1856 .halt_check = BRANCH_HALT,
1857 .hwcg_reg = 0x33004,
1860 .enable_reg = 0x33004,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "gcc_pdm_ahb_clk",
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch gcc_pdm_xo4_clk = {
1870 .halt_reg = 0x33008,
1871 .halt_check = BRANCH_HALT,
1873 .enable_reg = 0x33008,
1874 .enable_mask = BIT(0),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_pdm_xo4_clk",
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_prng_ahb_clk = {
1883 .halt_reg = 0x34004,
1884 .halt_check = BRANCH_HALT_VOTED,
1885 .hwcg_reg = 0x34004,
1888 .enable_reg = 0x52004,
1889 .enable_mask = BIT(13),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_prng_ahb_clk",
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch gcc_qmip_camera_ahb_clk = {
1899 .halt_check = BRANCH_HALT,
1903 .enable_reg = 0xb014,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "gcc_qmip_camera_ahb_clk",
1907 .ops = &clk_branch2_ops,
1912 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1914 .halt_check = BRANCH_HALT,
1918 .enable_reg = 0xb018,
1919 .enable_mask = BIT(0),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "gcc_qmip_disp_ahb_clk",
1922 .ops = &clk_branch2_ops,
1927 static struct clk_branch gcc_qmip_video_ahb_clk = {
1929 .halt_check = BRANCH_HALT,
1933 .enable_reg = 0xb010,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "gcc_qmip_video_ahb_clk",
1937 .ops = &clk_branch2_ops,
1942 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1943 .halt_reg = 0x17030,
1944 .halt_check = BRANCH_HALT_VOTED,
1946 .enable_reg = 0x5200c,
1947 .enable_mask = BIT(10),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "gcc_qupv3_wrap0_s0_clk",
1950 .parent_names = (const char *[]){
1951 "gcc_qupv3_wrap0_s0_clk_src",
1954 .flags = CLK_SET_RATE_PARENT,
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1961 .halt_reg = 0x17160,
1962 .halt_check = BRANCH_HALT_VOTED,
1964 .enable_reg = 0x5200c,
1965 .enable_mask = BIT(11),
1966 .hw.init = &(struct clk_init_data){
1967 .name = "gcc_qupv3_wrap0_s1_clk",
1968 .parent_names = (const char *[]){
1969 "gcc_qupv3_wrap0_s1_clk_src",
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1978 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1979 .halt_reg = 0x17290,
1980 .halt_check = BRANCH_HALT_VOTED,
1982 .enable_reg = 0x5200c,
1983 .enable_mask = BIT(12),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "gcc_qupv3_wrap0_s2_clk",
1986 .parent_names = (const char *[]){
1987 "gcc_qupv3_wrap0_s2_clk_src",
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1996 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1997 .halt_reg = 0x173c0,
1998 .halt_check = BRANCH_HALT_VOTED,
2000 .enable_reg = 0x5200c,
2001 .enable_mask = BIT(13),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "gcc_qupv3_wrap0_s3_clk",
2004 .parent_names = (const char *[]){
2005 "gcc_qupv3_wrap0_s3_clk_src",
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2015 .halt_reg = 0x174f0,
2016 .halt_check = BRANCH_HALT_VOTED,
2018 .enable_reg = 0x5200c,
2019 .enable_mask = BIT(14),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "gcc_qupv3_wrap0_s4_clk",
2022 .parent_names = (const char *[]){
2023 "gcc_qupv3_wrap0_s4_clk_src",
2026 .flags = CLK_SET_RATE_PARENT,
2027 .ops = &clk_branch2_ops,
2032 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2033 .halt_reg = 0x17620,
2034 .halt_check = BRANCH_HALT_VOTED,
2036 .enable_reg = 0x5200c,
2037 .enable_mask = BIT(15),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gcc_qupv3_wrap0_s5_clk",
2040 .parent_names = (const char *[]){
2041 "gcc_qupv3_wrap0_s5_clk_src",
2044 .flags = CLK_SET_RATE_PARENT,
2045 .ops = &clk_branch2_ops,
2050 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2051 .halt_reg = 0x17750,
2052 .halt_check = BRANCH_HALT_VOTED,
2054 .enable_reg = 0x5200c,
2055 .enable_mask = BIT(16),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "gcc_qupv3_wrap0_s6_clk",
2058 .parent_names = (const char *[]){
2059 "gcc_qupv3_wrap0_s6_clk_src",
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2069 .halt_reg = 0x17880,
2070 .halt_check = BRANCH_HALT_VOTED,
2072 .enable_reg = 0x5200c,
2073 .enable_mask = BIT(17),
2074 .hw.init = &(struct clk_init_data){
2075 .name = "gcc_qupv3_wrap0_s7_clk",
2076 .parent_names = (const char *[]){
2077 "gcc_qupv3_wrap0_s7_clk_src",
2080 .flags = CLK_SET_RATE_PARENT,
2081 .ops = &clk_branch2_ops,
2086 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2087 .halt_reg = 0x18014,
2088 .halt_check = BRANCH_HALT_VOTED,
2090 .enable_reg = 0x5200c,
2091 .enable_mask = BIT(22),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "gcc_qupv3_wrap1_s0_clk",
2094 .parent_names = (const char *[]){
2095 "gcc_qupv3_wrap1_s0_clk_src",
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2105 .halt_reg = 0x18144,
2106 .halt_check = BRANCH_HALT_VOTED,
2108 .enable_reg = 0x5200c,
2109 .enable_mask = BIT(23),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "gcc_qupv3_wrap1_s1_clk",
2112 .parent_names = (const char *[]){
2113 "gcc_qupv3_wrap1_s1_clk_src",
2116 .flags = CLK_SET_RATE_PARENT,
2117 .ops = &clk_branch2_ops,
2122 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2123 .halt_reg = 0x18274,
2124 .halt_check = BRANCH_HALT_VOTED,
2126 .enable_reg = 0x5200c,
2127 .enable_mask = BIT(24),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "gcc_qupv3_wrap1_s2_clk",
2130 .parent_names = (const char *[]){
2131 "gcc_qupv3_wrap1_s2_clk_src",
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_branch2_ops,
2140 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2141 .halt_reg = 0x183a4,
2142 .halt_check = BRANCH_HALT_VOTED,
2144 .enable_reg = 0x5200c,
2145 .enable_mask = BIT(25),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "gcc_qupv3_wrap1_s3_clk",
2148 .parent_names = (const char *[]){
2149 "gcc_qupv3_wrap1_s3_clk_src",
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2159 .halt_reg = 0x184d4,
2160 .halt_check = BRANCH_HALT_VOTED,
2162 .enable_reg = 0x5200c,
2163 .enable_mask = BIT(26),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gcc_qupv3_wrap1_s4_clk",
2166 .parent_names = (const char *[]){
2167 "gcc_qupv3_wrap1_s4_clk_src",
2170 .flags = CLK_SET_RATE_PARENT,
2171 .ops = &clk_branch2_ops,
2176 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2177 .halt_reg = 0x18604,
2178 .halt_check = BRANCH_HALT_VOTED,
2180 .enable_reg = 0x5200c,
2181 .enable_mask = BIT(27),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "gcc_qupv3_wrap1_s5_clk",
2184 .parent_names = (const char *[]){
2185 "gcc_qupv3_wrap1_s5_clk_src",
2188 .flags = CLK_SET_RATE_PARENT,
2189 .ops = &clk_branch2_ops,
2194 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2195 .halt_reg = 0x18734,
2196 .halt_check = BRANCH_HALT_VOTED,
2198 .enable_reg = 0x5200c,
2199 .enable_mask = BIT(28),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "gcc_qupv3_wrap1_s6_clk",
2202 .parent_names = (const char *[]){
2203 "gcc_qupv3_wrap1_s6_clk_src",
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2213 .halt_reg = 0x18864,
2214 .halt_check = BRANCH_HALT_VOTED,
2216 .enable_reg = 0x5200c,
2217 .enable_mask = BIT(29),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "gcc_qupv3_wrap1_s7_clk",
2220 .parent_names = (const char *[]){
2221 "gcc_qupv3_wrap1_s7_clk_src",
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2230 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2231 .halt_reg = 0x17004,
2232 .halt_check = BRANCH_HALT_VOTED,
2234 .enable_reg = 0x5200c,
2235 .enable_mask = BIT(6),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2238 .ops = &clk_branch2_ops,
2243 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2244 .halt_reg = 0x17008,
2245 .halt_check = BRANCH_HALT_VOTED,
2246 .hwcg_reg = 0x17008,
2249 .enable_reg = 0x5200c,
2250 .enable_mask = BIT(7),
2251 .hw.init = &(struct clk_init_data){
2252 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2253 .ops = &clk_branch2_ops,
2258 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2259 .halt_reg = 0x1800c,
2260 .halt_check = BRANCH_HALT_VOTED,
2262 .enable_reg = 0x5200c,
2263 .enable_mask = BIT(20),
2264 .hw.init = &(struct clk_init_data){
2265 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2272 .halt_reg = 0x18010,
2273 .halt_check = BRANCH_HALT_VOTED,
2274 .hwcg_reg = 0x18010,
2277 .enable_reg = 0x5200c,
2278 .enable_mask = BIT(21),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2281 .ops = &clk_branch2_ops,
2286 static struct clk_branch gcc_sdcc2_ahb_clk = {
2287 .halt_reg = 0x14008,
2288 .halt_check = BRANCH_HALT,
2290 .enable_reg = 0x14008,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "gcc_sdcc2_ahb_clk",
2294 .ops = &clk_branch2_ops,
2299 static struct clk_branch gcc_sdcc2_apps_clk = {
2300 .halt_reg = 0x14004,
2301 .halt_check = BRANCH_HALT,
2303 .enable_reg = 0x14004,
2304 .enable_mask = BIT(0),
2305 .hw.init = &(struct clk_init_data){
2306 .name = "gcc_sdcc2_apps_clk",
2307 .parent_names = (const char *[]){
2308 "gcc_sdcc2_apps_clk_src",
2311 .flags = CLK_SET_RATE_PARENT,
2312 .ops = &clk_branch2_ops,
2317 static struct clk_branch gcc_sdcc4_ahb_clk = {
2318 .halt_reg = 0x16008,
2319 .halt_check = BRANCH_HALT,
2321 .enable_reg = 0x16008,
2322 .enable_mask = BIT(0),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "gcc_sdcc4_ahb_clk",
2325 .ops = &clk_branch2_ops,
2330 static struct clk_branch gcc_sdcc4_apps_clk = {
2331 .halt_reg = 0x16004,
2332 .halt_check = BRANCH_HALT,
2334 .enable_reg = 0x16004,
2335 .enable_mask = BIT(0),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "gcc_sdcc4_apps_clk",
2338 .parent_names = (const char *[]){
2339 "gcc_sdcc4_apps_clk_src",
2342 .flags = CLK_SET_RATE_PARENT,
2343 .ops = &clk_branch2_ops,
2348 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2350 .halt_check = BRANCH_HALT_VOTED,
2352 .enable_reg = 0x52004,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "gcc_sys_noc_cpuss_ahb_clk",
2356 .parent_names = (const char *[]){
2357 "gcc_cpuss_ahb_clk_src",
2360 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2361 .ops = &clk_branch2_ops,
2366 static struct clk_branch gcc_tsif_ahb_clk = {
2367 .halt_reg = 0x36004,
2368 .halt_check = BRANCH_HALT,
2370 .enable_reg = 0x36004,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_tsif_ahb_clk",
2374 .ops = &clk_branch2_ops,
2379 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2380 .halt_reg = 0x3600c,
2381 .halt_check = BRANCH_HALT,
2383 .enable_reg = 0x3600c,
2384 .enable_mask = BIT(0),
2385 .hw.init = &(struct clk_init_data){
2386 .name = "gcc_tsif_inactivity_timers_clk",
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_tsif_ref_clk = {
2393 .halt_reg = 0x36008,
2394 .halt_check = BRANCH_HALT,
2396 .enable_reg = 0x36008,
2397 .enable_mask = BIT(0),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_tsif_ref_clk",
2400 .parent_names = (const char *[]){
2401 "gcc_tsif_ref_clk_src",
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_ufs_card_ahb_clk = {
2411 .halt_reg = 0x75010,
2412 .halt_check = BRANCH_HALT,
2413 .hwcg_reg = 0x75010,
2416 .enable_reg = 0x75010,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "gcc_ufs_card_ahb_clk",
2420 .ops = &clk_branch2_ops,
2425 static struct clk_branch gcc_ufs_card_axi_clk = {
2426 .halt_reg = 0x7500c,
2427 .halt_check = BRANCH_HALT,
2428 .hwcg_reg = 0x7500c,
2431 .enable_reg = 0x7500c,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_ufs_card_axi_clk",
2435 .parent_names = (const char *[]){
2436 "gcc_ufs_card_axi_clk_src",
2439 .flags = CLK_SET_RATE_PARENT,
2440 .ops = &clk_branch2_ops,
2445 static struct clk_branch gcc_ufs_card_clkref_clk = {
2446 .halt_reg = 0x8c004,
2447 .halt_check = BRANCH_HALT,
2449 .enable_reg = 0x8c004,
2450 .enable_mask = BIT(0),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gcc_ufs_card_clkref_clk",
2453 .ops = &clk_branch2_ops,
2458 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2459 .halt_reg = 0x75058,
2460 .halt_check = BRANCH_HALT,
2461 .hwcg_reg = 0x75058,
2464 .enable_reg = 0x75058,
2465 .enable_mask = BIT(0),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_ufs_card_ice_core_clk",
2468 .parent_names = (const char *[]){
2469 "gcc_ufs_card_ice_core_clk_src",
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2478 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2479 .halt_reg = 0x7508c,
2480 .halt_check = BRANCH_HALT,
2481 .hwcg_reg = 0x7508c,
2484 .enable_reg = 0x7508c,
2485 .enable_mask = BIT(0),
2486 .hw.init = &(struct clk_init_data){
2487 .name = "gcc_ufs_card_phy_aux_clk",
2488 .parent_names = (const char *[]){
2489 "gcc_ufs_card_phy_aux_clk_src",
2492 .flags = CLK_SET_RATE_PARENT,
2493 .ops = &clk_branch2_ops,
2498 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2499 .halt_check = BRANCH_HALT_SKIP,
2501 .enable_reg = 0x75018,
2502 .enable_mask = BIT(0),
2503 .hw.init = &(struct clk_init_data){
2504 .name = "gcc_ufs_card_rx_symbol_0_clk",
2505 .ops = &clk_branch2_ops,
2510 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2511 .halt_check = BRANCH_HALT_SKIP,
2513 .enable_reg = 0x750a8,
2514 .enable_mask = BIT(0),
2515 .hw.init = &(struct clk_init_data){
2516 .name = "gcc_ufs_card_rx_symbol_1_clk",
2517 .ops = &clk_branch2_ops,
2522 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2523 .halt_check = BRANCH_HALT_SKIP,
2525 .enable_reg = 0x75014,
2526 .enable_mask = BIT(0),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "gcc_ufs_card_tx_symbol_0_clk",
2529 .ops = &clk_branch2_ops,
2534 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2535 .halt_reg = 0x75054,
2536 .halt_check = BRANCH_HALT,
2537 .hwcg_reg = 0x75054,
2540 .enable_reg = 0x75054,
2541 .enable_mask = BIT(0),
2542 .hw.init = &(struct clk_init_data){
2543 .name = "gcc_ufs_card_unipro_core_clk",
2544 .parent_names = (const char *[]){
2545 "gcc_ufs_card_unipro_core_clk_src",
2548 .flags = CLK_SET_RATE_PARENT,
2549 .ops = &clk_branch2_ops,
2554 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2555 .halt_reg = 0x8c000,
2556 .halt_check = BRANCH_HALT,
2558 .enable_reg = 0x8c000,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(struct clk_init_data){
2561 .name = "gcc_ufs_mem_clkref_clk",
2562 .ops = &clk_branch2_ops,
2567 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2568 .halt_reg = 0x77010,
2569 .halt_check = BRANCH_HALT,
2570 .hwcg_reg = 0x77010,
2573 .enable_reg = 0x77010,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "gcc_ufs_phy_ahb_clk",
2577 .ops = &clk_branch2_ops,
2582 static struct clk_branch gcc_ufs_phy_axi_clk = {
2583 .halt_reg = 0x7700c,
2584 .halt_check = BRANCH_HALT,
2585 .hwcg_reg = 0x7700c,
2588 .enable_reg = 0x7700c,
2589 .enable_mask = BIT(0),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "gcc_ufs_phy_axi_clk",
2592 .parent_names = (const char *[]){
2593 "gcc_ufs_phy_axi_clk_src",
2596 .flags = CLK_SET_RATE_PARENT,
2597 .ops = &clk_branch2_ops,
2602 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2603 .halt_reg = 0x77058,
2604 .halt_check = BRANCH_HALT,
2605 .hwcg_reg = 0x77058,
2608 .enable_reg = 0x77058,
2609 .enable_mask = BIT(0),
2610 .hw.init = &(struct clk_init_data){
2611 .name = "gcc_ufs_phy_ice_core_clk",
2612 .parent_names = (const char *[]){
2613 "gcc_ufs_phy_ice_core_clk_src",
2616 .flags = CLK_SET_RATE_PARENT,
2617 .ops = &clk_branch2_ops,
2622 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2623 .halt_reg = 0x7708c,
2624 .halt_check = BRANCH_HALT,
2625 .hwcg_reg = 0x7708c,
2628 .enable_reg = 0x7708c,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gcc_ufs_phy_phy_aux_clk",
2632 .parent_names = (const char *[]){
2633 "gcc_ufs_phy_phy_aux_clk_src",
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2642 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2643 .halt_check = BRANCH_HALT_SKIP,
2645 .enable_reg = 0x77018,
2646 .enable_mask = BIT(0),
2647 .hw.init = &(struct clk_init_data){
2648 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2649 .ops = &clk_branch2_ops,
2654 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2655 .halt_check = BRANCH_HALT_SKIP,
2657 .enable_reg = 0x770a8,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2661 .ops = &clk_branch2_ops,
2666 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2667 .halt_check = BRANCH_HALT_SKIP,
2669 .enable_reg = 0x77014,
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2673 .ops = &clk_branch2_ops,
2678 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2679 .halt_reg = 0x77054,
2680 .halt_check = BRANCH_HALT,
2681 .hwcg_reg = 0x77054,
2684 .enable_reg = 0x77054,
2685 .enable_mask = BIT(0),
2686 .hw.init = &(struct clk_init_data){
2687 .name = "gcc_ufs_phy_unipro_core_clk",
2688 .parent_names = (const char *[]){
2689 "gcc_ufs_phy_unipro_core_clk_src",
2692 .flags = CLK_SET_RATE_PARENT,
2693 .ops = &clk_branch2_ops,
2698 static struct clk_branch gcc_usb30_prim_master_clk = {
2700 .halt_check = BRANCH_HALT,
2702 .enable_reg = 0xf00c,
2703 .enable_mask = BIT(0),
2704 .hw.init = &(struct clk_init_data){
2705 .name = "gcc_usb30_prim_master_clk",
2706 .parent_names = (const char *[]){
2707 "gcc_usb30_prim_master_clk_src",
2710 .flags = CLK_SET_RATE_PARENT,
2711 .ops = &clk_branch2_ops,
2716 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2718 .halt_check = BRANCH_HALT,
2720 .enable_reg = 0xf014,
2721 .enable_mask = BIT(0),
2722 .hw.init = &(struct clk_init_data){
2723 .name = "gcc_usb30_prim_mock_utmi_clk",
2724 .parent_names = (const char *[]){
2725 "gcc_usb30_prim_mock_utmi_clk_src",
2728 .flags = CLK_SET_RATE_PARENT,
2729 .ops = &clk_branch2_ops,
2734 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2736 .halt_check = BRANCH_HALT,
2738 .enable_reg = 0xf010,
2739 .enable_mask = BIT(0),
2740 .hw.init = &(struct clk_init_data){
2741 .name = "gcc_usb30_prim_sleep_clk",
2742 .ops = &clk_branch2_ops,
2747 static struct clk_branch gcc_usb30_sec_master_clk = {
2748 .halt_reg = 0x1000c,
2749 .halt_check = BRANCH_HALT,
2751 .enable_reg = 0x1000c,
2752 .enable_mask = BIT(0),
2753 .hw.init = &(struct clk_init_data){
2754 .name = "gcc_usb30_sec_master_clk",
2755 .parent_names = (const char *[]){
2756 "gcc_usb30_sec_master_clk_src",
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2766 .halt_reg = 0x10014,
2767 .halt_check = BRANCH_HALT,
2769 .enable_reg = 0x10014,
2770 .enable_mask = BIT(0),
2771 .hw.init = &(struct clk_init_data){
2772 .name = "gcc_usb30_sec_mock_utmi_clk",
2773 .parent_names = (const char *[]){
2774 "gcc_usb30_sec_mock_utmi_clk_src",
2777 .flags = CLK_SET_RATE_PARENT,
2778 .ops = &clk_branch2_ops,
2783 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2784 .halt_reg = 0x10010,
2785 .halt_check = BRANCH_HALT,
2787 .enable_reg = 0x10010,
2788 .enable_mask = BIT(0),
2789 .hw.init = &(struct clk_init_data){
2790 .name = "gcc_usb30_sec_sleep_clk",
2791 .ops = &clk_branch2_ops,
2796 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2797 .halt_reg = 0x8c008,
2798 .halt_check = BRANCH_HALT,
2800 .enable_reg = 0x8c008,
2801 .enable_mask = BIT(0),
2802 .hw.init = &(struct clk_init_data){
2803 .name = "gcc_usb3_prim_clkref_clk",
2804 .ops = &clk_branch2_ops,
2809 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2811 .halt_check = BRANCH_HALT,
2813 .enable_reg = 0xf04c,
2814 .enable_mask = BIT(0),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "gcc_usb3_prim_phy_aux_clk",
2817 .parent_names = (const char *[]){
2818 "gcc_usb3_prim_phy_aux_clk_src",
2821 .flags = CLK_SET_RATE_PARENT,
2822 .ops = &clk_branch2_ops,
2827 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2829 .halt_check = BRANCH_HALT,
2831 .enable_reg = 0xf050,
2832 .enable_mask = BIT(0),
2833 .hw.init = &(struct clk_init_data){
2834 .name = "gcc_usb3_prim_phy_com_aux_clk",
2835 .parent_names = (const char *[]){
2836 "gcc_usb3_prim_phy_aux_clk_src",
2839 .flags = CLK_SET_RATE_PARENT,
2840 .ops = &clk_branch2_ops,
2845 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2846 .halt_check = BRANCH_HALT_SKIP,
2848 .enable_reg = 0xf054,
2849 .enable_mask = BIT(0),
2850 .hw.init = &(struct clk_init_data){
2851 .name = "gcc_usb3_prim_phy_pipe_clk",
2852 .ops = &clk_branch2_ops,
2857 static struct clk_branch gcc_usb3_sec_clkref_clk = {
2858 .halt_reg = 0x8c028,
2859 .halt_check = BRANCH_HALT,
2861 .enable_reg = 0x8c028,
2862 .enable_mask = BIT(0),
2863 .hw.init = &(struct clk_init_data){
2864 .name = "gcc_usb3_sec_clkref_clk",
2865 .ops = &clk_branch2_ops,
2870 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2871 .halt_reg = 0x1004c,
2872 .halt_check = BRANCH_HALT,
2874 .enable_reg = 0x1004c,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "gcc_usb3_sec_phy_aux_clk",
2878 .parent_names = (const char *[]){
2879 "gcc_usb3_sec_phy_aux_clk_src",
2882 .flags = CLK_SET_RATE_PARENT,
2883 .ops = &clk_branch2_ops,
2888 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2889 .halt_reg = 0x10050,
2890 .halt_check = BRANCH_HALT,
2892 .enable_reg = 0x10050,
2893 .enable_mask = BIT(0),
2894 .hw.init = &(struct clk_init_data){
2895 .name = "gcc_usb3_sec_phy_com_aux_clk",
2896 .parent_names = (const char *[]){
2897 "gcc_usb3_sec_phy_aux_clk_src",
2900 .flags = CLK_SET_RATE_PARENT,
2901 .ops = &clk_branch2_ops,
2906 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
2907 .halt_check = BRANCH_HALT_SKIP,
2909 .enable_reg = 0x10054,
2910 .enable_mask = BIT(0),
2911 .hw.init = &(struct clk_init_data){
2912 .name = "gcc_usb3_sec_phy_pipe_clk",
2913 .ops = &clk_branch2_ops,
2918 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2919 .halt_reg = 0x6a004,
2920 .halt_check = BRANCH_HALT,
2921 .hwcg_reg = 0x6a004,
2924 .enable_reg = 0x6a004,
2925 .enable_mask = BIT(0),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2928 .ops = &clk_branch2_ops,
2933 static struct clk_branch gcc_vdda_vs_clk = {
2934 .halt_reg = 0x7a00c,
2935 .halt_check = BRANCH_HALT,
2937 .enable_reg = 0x7a00c,
2938 .enable_mask = BIT(0),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "gcc_vdda_vs_clk",
2941 .parent_names = (const char *[]){
2942 "gcc_vsensor_clk_src",
2945 .flags = CLK_SET_RATE_PARENT,
2946 .ops = &clk_branch2_ops,
2951 static struct clk_branch gcc_vddcx_vs_clk = {
2952 .halt_reg = 0x7a004,
2953 .halt_check = BRANCH_HALT,
2955 .enable_reg = 0x7a004,
2956 .enable_mask = BIT(0),
2957 .hw.init = &(struct clk_init_data){
2958 .name = "gcc_vddcx_vs_clk",
2959 .parent_names = (const char *[]){
2960 "gcc_vsensor_clk_src",
2963 .flags = CLK_SET_RATE_PARENT,
2964 .ops = &clk_branch2_ops,
2969 static struct clk_branch gcc_vddmx_vs_clk = {
2970 .halt_reg = 0x7a008,
2971 .halt_check = BRANCH_HALT,
2973 .enable_reg = 0x7a008,
2974 .enable_mask = BIT(0),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "gcc_vddmx_vs_clk",
2977 .parent_names = (const char *[]){
2978 "gcc_vsensor_clk_src",
2981 .flags = CLK_SET_RATE_PARENT,
2982 .ops = &clk_branch2_ops,
2987 static struct clk_branch gcc_video_ahb_clk = {
2989 .halt_check = BRANCH_HALT,
2993 .enable_reg = 0xb004,
2994 .enable_mask = BIT(0),
2995 .hw.init = &(struct clk_init_data){
2996 .name = "gcc_video_ahb_clk",
2997 .flags = CLK_IS_CRITICAL,
2998 .ops = &clk_branch2_ops,
3003 static struct clk_branch gcc_video_axi_clk = {
3005 .halt_check = BRANCH_VOTED,
3007 .enable_reg = 0xb01c,
3008 .enable_mask = BIT(0),
3009 .hw.init = &(struct clk_init_data){
3010 .name = "gcc_video_axi_clk",
3011 .ops = &clk_branch2_ops,
3016 static struct clk_branch gcc_video_xo_clk = {
3018 .halt_check = BRANCH_HALT,
3020 .enable_reg = 0xb028,
3021 .enable_mask = BIT(0),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "gcc_video_xo_clk",
3024 .flags = CLK_IS_CRITICAL,
3025 .ops = &clk_branch2_ops,
3030 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3031 .halt_reg = 0x7a014,
3032 .halt_check = BRANCH_HALT,
3033 .hwcg_reg = 0x7a014,
3036 .enable_reg = 0x7a014,
3037 .enable_mask = BIT(0),
3038 .hw.init = &(struct clk_init_data){
3039 .name = "gcc_vs_ctrl_ahb_clk",
3040 .ops = &clk_branch2_ops,
3045 static struct clk_branch gcc_vs_ctrl_clk = {
3046 .halt_reg = 0x7a010,
3047 .halt_check = BRANCH_HALT,
3049 .enable_reg = 0x7a010,
3050 .enable_mask = BIT(0),
3051 .hw.init = &(struct clk_init_data){
3052 .name = "gcc_vs_ctrl_clk",
3053 .parent_names = (const char *[]){
3054 "gcc_vs_ctrl_clk_src",
3057 .flags = CLK_SET_RATE_PARENT,
3058 .ops = &clk_branch2_ops,
3063 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3064 .halt_reg = 0x48190,
3065 .halt_check = BRANCH_HALT,
3067 .enable_reg = 0x48190,
3068 .enable_mask = BIT(0),
3069 .hw.init = &(struct clk_init_data){
3070 .name = "gcc_cpuss_dvm_bus_clk",
3071 .flags = CLK_IS_CRITICAL,
3072 .ops = &clk_branch2_ops,
3077 static struct clk_branch gcc_cpuss_gnoc_clk = {
3078 .halt_reg = 0x48004,
3079 .halt_check = BRANCH_HALT_VOTED,
3080 .hwcg_reg = 0x48004,
3083 .enable_reg = 0x52004,
3084 .enable_mask = BIT(22),
3085 .hw.init = &(struct clk_init_data){
3086 .name = "gcc_cpuss_gnoc_clk",
3087 .flags = CLK_IS_CRITICAL,
3088 .ops = &clk_branch2_ops,
3093 static struct gdsc pcie_0_gdsc = {
3096 .name = "pcie_0_gdsc",
3098 .pwrsts = PWRSTS_OFF_ON,
3099 .flags = POLL_CFG_GDSCR,
3102 static struct gdsc pcie_1_gdsc = {
3105 .name = "pcie_1_gdsc",
3107 .pwrsts = PWRSTS_OFF_ON,
3108 .flags = POLL_CFG_GDSCR,
3111 static struct gdsc ufs_card_gdsc = {
3114 .name = "ufs_card_gdsc",
3116 .pwrsts = PWRSTS_OFF_ON,
3117 .flags = POLL_CFG_GDSCR,
3120 static struct gdsc ufs_phy_gdsc = {
3123 .name = "ufs_phy_gdsc",
3125 .pwrsts = PWRSTS_OFF_ON,
3126 .flags = POLL_CFG_GDSCR,
3129 static struct gdsc usb30_prim_gdsc = {
3132 .name = "usb30_prim_gdsc",
3134 .pwrsts = PWRSTS_OFF_ON,
3135 .flags = POLL_CFG_GDSCR,
3138 static struct gdsc usb30_sec_gdsc = {
3141 .name = "usb30_sec_gdsc",
3143 .pwrsts = PWRSTS_OFF_ON,
3144 .flags = POLL_CFG_GDSCR,
3147 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3150 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3152 .pwrsts = PWRSTS_OFF_ON,
3156 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3159 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3161 .pwrsts = PWRSTS_OFF_ON,
3165 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3168 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3170 .pwrsts = PWRSTS_OFF_ON,
3174 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3177 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3179 .pwrsts = PWRSTS_OFF_ON,
3183 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3186 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3188 .pwrsts = PWRSTS_OFF_ON,
3192 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3195 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3197 .pwrsts = PWRSTS_OFF_ON,
3201 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3204 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3206 .pwrsts = PWRSTS_OFF_ON,
3210 static struct clk_regmap *gcc_sdm845_clocks[] = {
3211 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3212 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3213 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3214 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3215 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3216 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3217 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3218 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3219 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3220 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3221 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3222 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3223 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3224 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3225 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3226 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3227 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3228 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3229 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3230 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3231 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3232 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3233 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3234 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3235 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3236 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3237 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3238 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3239 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3240 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3241 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3242 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3243 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3244 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3245 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3246 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3247 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3248 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3249 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3250 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3251 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3252 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3253 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3254 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3255 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3256 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3257 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3258 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3259 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3260 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3261 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3262 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3263 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3264 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3265 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3266 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3267 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3268 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3269 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3270 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3271 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3272 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3273 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3274 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3275 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3276 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3277 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3278 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3279 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3280 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3281 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3282 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3283 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3284 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3285 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3286 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3287 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3288 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3289 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3290 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3291 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3292 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3293 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3294 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3295 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3296 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3297 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3298 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3299 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3300 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3301 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3302 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3303 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3304 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3305 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3306 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3307 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3308 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3309 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3310 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3311 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3312 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3313 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3314 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3315 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3316 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3317 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3318 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3319 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3320 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3321 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3322 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3323 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3324 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3325 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3326 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3327 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3328 &gcc_tsif_inactivity_timers_clk.clkr,
3329 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3330 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3331 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3332 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3333 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3334 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3335 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3336 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3337 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3338 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3339 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3340 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3341 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3342 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3343 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3344 &gcc_ufs_card_unipro_core_clk_src.clkr,
3345 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3346 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3347 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3348 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3349 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3350 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3351 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3352 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3353 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3354 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3355 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3356 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3357 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3358 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3359 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3360 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3361 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3362 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3363 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3364 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3365 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3366 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3367 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3368 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3369 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3370 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3371 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3372 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3373 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3374 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3375 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3376 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3377 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3378 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3379 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3380 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3381 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3382 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3383 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3384 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3385 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3386 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3387 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3388 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3389 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3390 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3391 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3392 [GPLL0] = &gpll0.clkr,
3393 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3394 [GPLL4] = &gpll4.clkr,
3395 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3396 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3399 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3400 [GCC_MMSS_BCR] = { 0xb000 },
3401 [GCC_PCIE_0_BCR] = { 0x6b000 },
3402 [GCC_PCIE_1_BCR] = { 0x8d000 },
3403 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3404 [GCC_PDM_BCR] = { 0x33000 },
3405 [GCC_PRNG_BCR] = { 0x34000 },
3406 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3407 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3408 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3409 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3410 [GCC_SDCC2_BCR] = { 0x14000 },
3411 [GCC_SDCC4_BCR] = { 0x16000 },
3412 [GCC_TSIF_BCR] = { 0x36000 },
3413 [GCC_UFS_CARD_BCR] = { 0x75000 },
3414 [GCC_UFS_PHY_BCR] = { 0x77000 },
3415 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3416 [GCC_USB30_SEC_BCR] = { 0x10000 },
3417 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3418 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3419 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3420 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3421 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3422 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3423 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3424 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3425 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3428 static struct gdsc *gcc_sdm845_gdscs[] = {
3429 [PCIE_0_GDSC] = &pcie_0_gdsc,
3430 [PCIE_1_GDSC] = &pcie_1_gdsc,
3431 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3432 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3433 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3434 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3435 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3436 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3437 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3438 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3439 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3440 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3441 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3442 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3443 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3444 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3445 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3446 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3447 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3450 static const struct regmap_config gcc_sdm845_regmap_config = {
3454 .max_register = 0x182090,
3458 static const struct qcom_cc_desc gcc_sdm845_desc = {
3459 .config = &gcc_sdm845_regmap_config,
3460 .clks = gcc_sdm845_clocks,
3461 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3462 .resets = gcc_sdm845_resets,
3463 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3464 .gdscs = gcc_sdm845_gdscs,
3465 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3468 static const struct of_device_id gcc_sdm845_match_table[] = {
3469 { .compatible = "qcom,gcc-sdm845" },
3472 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3474 static int gcc_sdm845_probe(struct platform_device *pdev)
3476 struct regmap *regmap;
3478 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3480 return PTR_ERR(regmap);
3482 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
3483 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3484 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3486 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3489 static struct platform_driver gcc_sdm845_driver = {
3490 .probe = gcc_sdm845_probe,
3492 .name = "gcc-sdm845",
3493 .of_match_table = gcc_sdm845_match_table,
3497 static int __init gcc_sdm845_init(void)
3499 return platform_driver_register(&gcc_sdm845_driver);
3501 subsys_initcall(gcc_sdm845_init);
3503 static void __exit gcc_sdm845_exit(void)
3505 platform_driver_unregister(&gcc_sdm845_driver);
3507 module_exit(gcc_sdm845_exit);
3509 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
3510 MODULE_LICENSE("GPL v2");
3511 MODULE_ALIAS("platform:gcc-sdm845");