1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
19 #include "clk-regmap.h"
26 P_CORE_BI_PLL_TEST_SE,
36 static struct clk_alpha_pll gpll0 = {
38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
42 .hw.init = &(struct clk_init_data){
44 .parent_data = &(const struct clk_parent_data){
49 .ops = &clk_alpha_pll_fixed_fabia_ops,
54 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
59 static struct clk_alpha_pll_postdiv gpll0_out_even = {
62 .post_div_table = post_div_table_gpll0_out_even,
63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "gpll0_out_even",
68 .parent_data = &(const struct clk_parent_data){
72 .ops = &clk_alpha_pll_postdiv_fabia_ops,
76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
79 .hw.init = &(struct clk_init_data){
80 .name = "gcc_pll0_main_div_cdiv",
81 .parent_data = &(const struct clk_parent_data){
85 .ops = &clk_fixed_factor_ops,
89 static struct clk_alpha_pll gpll1 = {
91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
93 .enable_reg = 0x52010,
94 .enable_mask = BIT(1),
95 .hw.init = &(struct clk_init_data){
97 .parent_data = &(const struct clk_parent_data){
102 .ops = &clk_alpha_pll_fixed_fabia_ops,
107 static struct clk_alpha_pll gpll4 = {
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
111 .enable_reg = 0x52010,
112 .enable_mask = BIT(4),
113 .hw.init = &(struct clk_init_data){
115 .parent_data = &(const struct clk_parent_data){
116 .fw_name = "bi_tcxo",
120 .ops = &clk_alpha_pll_fixed_fabia_ops,
125 static struct clk_alpha_pll gpll6 = {
127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
129 .enable_reg = 0x52010,
130 .enable_mask = BIT(6),
131 .hw.init = &(struct clk_init_data){
133 .parent_data = &(const struct clk_parent_data){
134 .fw_name = "bi_tcxo",
138 .ops = &clk_alpha_pll_fixed_fabia_ops,
143 static struct clk_alpha_pll gpll7 = {
145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
147 .enable_reg = 0x52010,
148 .enable_mask = BIT(7),
149 .hw.init = &(struct clk_init_data){
151 .parent_data = &(const struct clk_parent_data){
152 .fw_name = "bi_tcxo",
156 .ops = &clk_alpha_pll_fixed_fabia_ops,
161 static const struct parent_map gcc_parent_map_0[] = {
163 { P_GPLL0_OUT_MAIN, 1 },
164 { P_GPLL0_OUT_EVEN, 6 },
165 { P_CORE_BI_PLL_TEST_SE, 7 },
168 static const struct clk_parent_data gcc_parent_data_0[] = {
169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
170 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0_out_even.clkr.hw },
172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
175 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
177 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0_out_even.clkr.hw },
179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
182 static const struct parent_map gcc_parent_map_1[] = {
184 { P_GPLL0_OUT_MAIN, 1 },
185 { P_GPLL6_OUT_MAIN, 2 },
186 { P_GPLL0_OUT_EVEN, 6 },
187 { P_CORE_BI_PLL_TEST_SE, 7 },
190 static const struct clk_parent_data gcc_parent_data_1[] = {
191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
192 { .hw = &gpll0.clkr.hw },
193 { .hw = &gpll6.clkr.hw },
194 { .hw = &gpll0_out_even.clkr.hw },
195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
198 static const struct parent_map gcc_parent_map_2[] = {
200 { P_GPLL0_OUT_MAIN, 1 },
201 { P_GPLL1_OUT_MAIN, 4 },
202 { P_GPLL4_OUT_MAIN, 5 },
203 { P_GPLL0_OUT_EVEN, 6 },
204 { P_CORE_BI_PLL_TEST_SE, 7 },
207 static const struct clk_parent_data gcc_parent_data_2[] = {
208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
209 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll1.clkr.hw },
211 { .hw = &gpll4.clkr.hw },
212 { .hw = &gpll0_out_even.clkr.hw },
213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
216 static const struct parent_map gcc_parent_map_3[] = {
218 { P_GPLL0_OUT_MAIN, 1 },
219 { P_CORE_BI_PLL_TEST_SE, 7 },
222 static const struct clk_parent_data gcc_parent_data_3[] = {
223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
224 { .hw = &gpll0.clkr.hw },
225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
228 static const struct parent_map gcc_parent_map_4[] = {
230 { P_GPLL0_OUT_MAIN, 1 },
232 { P_GPLL0_OUT_EVEN, 6 },
233 { P_CORE_BI_PLL_TEST_SE, 7 },
236 static const struct clk_parent_data gcc_parent_data_4[] = {
237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
238 { .hw = &gpll0.clkr.hw },
239 { .fw_name = "sleep_clk", .name = "sleep_clk" },
240 { .hw = &gpll0_out_even.clkr.hw },
241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
244 static const struct parent_map gcc_parent_map_5[] = {
246 { P_GPLL0_OUT_MAIN, 1 },
247 { P_GPLL7_OUT_MAIN, 3 },
248 { P_GPLL0_OUT_EVEN, 6 },
249 { P_CORE_BI_PLL_TEST_SE, 7 },
252 static const struct clk_parent_data gcc_parent_data_5[] = {
253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
254 { .hw = &gpll0.clkr.hw },
255 { .hw = &gpll7.clkr.hw },
256 { .hw = &gpll0_out_even.clkr.hw },
257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
260 static const struct parent_map gcc_parent_map_6[] = {
262 { P_GPLL0_OUT_MAIN, 1 },
264 { P_CORE_BI_PLL_TEST_SE, 7 },
267 static const struct clk_parent_data gcc_parent_data_6[] = {
268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
269 { .hw = &gpll0.clkr.hw },
270 { .fw_name = "sleep_clk", .name = "sleep_clk" },
271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
275 F(19200000, P_BI_TCXO, 1, 0, 0),
279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
283 .parent_map = gcc_parent_map_0,
284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "gcc_cpuss_ahb_clk_src",
287 .parent_data = gcc_parent_data_0_ao,
288 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
289 .flags = CLK_SET_RATE_PARENT,
290 .ops = &clk_rcg2_ops,
294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
303 static struct clk_rcg2 gcc_gp1_clk_src = {
307 .parent_map = gcc_parent_map_4,
308 .freq_tbl = ftbl_gcc_gp1_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "gcc_gp1_clk_src",
311 .parent_data = gcc_parent_data_4,
312 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
313 .ops = &clk_rcg2_ops,
317 static struct clk_rcg2 gcc_gp2_clk_src = {
321 .parent_map = gcc_parent_map_4,
322 .freq_tbl = ftbl_gcc_gp1_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "gcc_gp2_clk_src",
325 .parent_data = gcc_parent_data_4,
326 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
327 .ops = &clk_rcg2_ops,
331 static struct clk_rcg2 gcc_gp3_clk_src = {
335 .parent_map = gcc_parent_map_4,
336 .freq_tbl = ftbl_gcc_gp1_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "gcc_gp3_clk_src",
339 .parent_data = gcc_parent_data_4,
340 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
341 .ops = &clk_rcg2_ops,
345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
351 static struct clk_rcg2 gcc_pdm2_clk_src = {
355 .parent_map = gcc_parent_map_0,
356 .freq_tbl = ftbl_gcc_pdm2_clk_src,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "gcc_pdm2_clk_src",
359 .parent_data = gcc_parent_data_0,
360 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
361 .ops = &clk_rcg2_ops,
365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
372 static struct clk_rcg2 gcc_qspi_core_clk_src = {
376 .parent_map = gcc_parent_map_2,
377 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "gcc_qspi_core_clk_src",
380 .parent_data = gcc_parent_data_2,
381 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
382 .ops = &clk_rcg2_ops,
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
389 F(19200000, P_BI_TCXO, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
394 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
396 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
397 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
399 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
400 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
401 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
408 .name = "gcc_qupv3_wrap0_s0_clk_src",
409 .parent_data = gcc_parent_data_1,
410 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
411 .ops = &clk_rcg2_ops,
414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
418 .parent_map = gcc_parent_map_1,
419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
420 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
424 .name = "gcc_qupv3_wrap0_s1_clk_src",
425 .parent_data = gcc_parent_data_1,
426 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
427 .ops = &clk_rcg2_ops,
430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
434 .parent_map = gcc_parent_map_1,
435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
436 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
440 .name = "gcc_qupv3_wrap0_s2_clk_src",
441 .parent_data = gcc_parent_data_1,
442 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
443 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
450 .parent_map = gcc_parent_map_1,
451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
452 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
456 .name = "gcc_qupv3_wrap0_s3_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .ops = &clk_rcg2_ops,
462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
466 .parent_map = gcc_parent_map_1,
467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
468 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
472 .name = "gcc_qupv3_wrap0_s4_clk_src",
473 .parent_data = gcc_parent_data_1,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
475 .ops = &clk_rcg2_ops,
478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
484 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
488 .name = "gcc_qupv3_wrap0_s5_clk_src",
489 .parent_data = gcc_parent_data_1,
490 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
491 .ops = &clk_rcg2_ops,
494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
498 .parent_map = gcc_parent_map_1,
499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
500 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
504 .name = "gcc_qupv3_wrap1_s0_clk_src",
505 .parent_data = gcc_parent_data_1,
506 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
507 .ops = &clk_rcg2_ops,
510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
514 .parent_map = gcc_parent_map_1,
515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
516 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
520 .name = "gcc_qupv3_wrap1_s1_clk_src",
521 .parent_data = gcc_parent_data_1,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
523 .ops = &clk_rcg2_ops,
526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
530 .parent_map = gcc_parent_map_1,
531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
532 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
536 .name = "gcc_qupv3_wrap1_s2_clk_src",
537 .parent_data = gcc_parent_data_1,
538 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
539 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
548 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
552 .name = "gcc_qupv3_wrap1_s3_clk_src",
553 .parent_data = gcc_parent_data_1,
554 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
555 .ops = &clk_rcg2_ops,
558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
562 .parent_map = gcc_parent_map_1,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
568 .name = "gcc_qupv3_wrap1_s4_clk_src",
569 .parent_data = gcc_parent_data_1,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
571 .ops = &clk_rcg2_ops,
574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
578 .parent_map = gcc_parent_map_1,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
584 .name = "gcc_qupv3_wrap1_s5_clk_src",
585 .parent_data = gcc_parent_data_1,
586 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
587 .ops = &clk_rcg2_ops,
590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
594 .parent_map = gcc_parent_map_1,
595 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
596 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
601 F(144000, P_BI_TCXO, 16, 3, 25),
602 F(400000, P_BI_TCXO, 12, 1, 4),
603 F(19200000, P_BI_TCXO, 1, 0, 0),
604 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
605 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
617 .parent_map = gcc_parent_map_1,
618 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "gcc_sdcc1_apps_clk_src",
621 .parent_data = gcc_parent_data_1,
622 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
623 .ops = &clk_rcg2_floor_ops,
627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
639 .parent_map = gcc_parent_map_0,
640 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "gcc_sdcc1_ice_core_clk_src",
643 .parent_data = gcc_parent_data_0,
644 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
645 .ops = &clk_rcg2_ops,
649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
650 F(400000, P_BI_TCXO, 12, 1, 4),
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
655 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
659 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
663 .parent_map = gcc_parent_map_5,
664 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "gcc_sdcc2_apps_clk_src",
667 .parent_data = gcc_parent_data_5,
668 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
669 .flags = CLK_OPS_PARENT_ENABLE,
670 .ops = &clk_rcg2_floor_ops,
674 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
675 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
676 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
677 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
678 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
679 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
683 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
687 .parent_map = gcc_parent_map_0,
688 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "gcc_ufs_phy_axi_clk_src",
691 .parent_data = gcc_parent_data_0,
692 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
693 .ops = &clk_rcg2_ops,
697 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
698 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
700 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
701 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
705 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
709 .parent_map = gcc_parent_map_0,
710 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "gcc_ufs_phy_ice_core_clk_src",
713 .parent_data = gcc_parent_data_0,
714 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
715 .ops = &clk_rcg2_ops,
719 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
720 F(9600000, P_BI_TCXO, 2, 0, 0),
721 F(19200000, P_BI_TCXO, 1, 0, 0),
725 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
729 .parent_map = gcc_parent_map_3,
730 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
731 .clkr.hw.init = &(struct clk_init_data){
732 .name = "gcc_ufs_phy_phy_aux_clk_src",
733 .parent_data = gcc_parent_data_3,
734 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
735 .ops = &clk_rcg2_ops,
739 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
740 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
741 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
742 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
746 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
750 .parent_map = gcc_parent_map_0,
751 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "gcc_ufs_phy_unipro_core_clk_src",
754 .parent_data = gcc_parent_data_0,
755 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
756 .ops = &clk_rcg2_ops,
760 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
761 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
762 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
763 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
764 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
768 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
772 .parent_map = gcc_parent_map_0,
773 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "gcc_usb30_prim_master_clk_src",
776 .parent_data = gcc_parent_data_0,
777 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
778 .ops = &clk_rcg2_ops,
782 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
783 F(19200000, P_BI_TCXO, 1, 0, 0),
784 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
788 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
792 .parent_map = gcc_parent_map_0,
793 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "gcc_usb30_prim_mock_utmi_clk_src",
796 .parent_data = gcc_parent_data_0,
797 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
798 .ops = &clk_rcg2_ops,
802 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
803 F(19200000, P_BI_TCXO, 1, 0, 0),
807 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
811 .parent_map = gcc_parent_map_6,
812 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "gcc_usb3_prim_phy_aux_clk_src",
815 .parent_data = gcc_parent_data_6,
816 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
817 .ops = &clk_rcg2_ops,
821 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
822 F(4800000, P_BI_TCXO, 4, 0, 0),
823 F(19200000, P_BI_TCXO, 1, 0, 0),
827 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
831 .parent_map = gcc_parent_map_3,
832 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "gcc_sec_ctrl_clk_src",
835 .parent_data = gcc_parent_data_3,
836 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
837 .ops = &clk_rcg2_ops,
841 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
843 .halt_check = BRANCH_HALT_DELAY,
847 .enable_reg = 0x82024,
848 .enable_mask = BIT(0),
849 .hw.init = &(struct clk_init_data){
850 .name = "gcc_aggre_ufs_phy_axi_clk",
851 .parent_data = &(const struct clk_parent_data){
852 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
855 .flags = CLK_SET_RATE_PARENT,
856 .ops = &clk_branch2_ops,
861 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
863 .halt_check = BRANCH_HALT,
865 .enable_reg = 0x8201c,
866 .enable_mask = BIT(0),
867 .hw.init = &(struct clk_init_data){
868 .name = "gcc_aggre_usb3_prim_axi_clk",
869 .parent_data = &(const struct clk_parent_data){
870 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
873 .flags = CLK_SET_RATE_PARENT,
874 .ops = &clk_branch2_ops,
879 static struct clk_branch gcc_boot_rom_ahb_clk = {
881 .halt_check = BRANCH_HALT_VOTED,
885 .enable_reg = 0x52000,
886 .enable_mask = BIT(10),
887 .hw.init = &(struct clk_init_data){
888 .name = "gcc_boot_rom_ahb_clk",
889 .ops = &clk_branch2_ops,
894 static struct clk_branch gcc_camera_ahb_clk = {
896 .halt_check = BRANCH_HALT,
900 .enable_reg = 0xb008,
901 .enable_mask = BIT(0),
902 .hw.init = &(struct clk_init_data){
903 .name = "gcc_camera_ahb_clk",
904 .ops = &clk_branch2_ops,
909 static struct clk_branch gcc_camera_hf_axi_clk = {
911 .halt_check = BRANCH_HALT,
913 .enable_reg = 0xb020,
914 .enable_mask = BIT(0),
915 .hw.init = &(struct clk_init_data){
916 .name = "gcc_camera_hf_axi_clk",
917 .ops = &clk_branch2_ops,
922 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
924 .halt_check = BRANCH_HALT,
928 .enable_reg = 0xb080,
929 .enable_mask = BIT(0),
930 .hw.init = &(struct clk_init_data){
931 .name = "gcc_camera_throttle_hf_axi_clk",
932 .ops = &clk_branch2_ops,
937 static struct clk_branch gcc_camera_xo_clk = {
939 .halt_check = BRANCH_HALT,
941 .enable_reg = 0xb02c,
942 .enable_mask = BIT(0),
943 .hw.init = &(struct clk_init_data){
944 .name = "gcc_camera_xo_clk",
945 .ops = &clk_branch2_ops,
950 static struct clk_branch gcc_ce1_ahb_clk = {
952 .halt_check = BRANCH_HALT_VOTED,
956 .enable_reg = 0x52000,
957 .enable_mask = BIT(3),
958 .hw.init = &(struct clk_init_data){
959 .name = "gcc_ce1_ahb_clk",
960 .ops = &clk_branch2_ops,
965 static struct clk_branch gcc_ce1_axi_clk = {
967 .halt_check = BRANCH_HALT_VOTED,
969 .enable_reg = 0x52000,
970 .enable_mask = BIT(4),
971 .hw.init = &(struct clk_init_data){
972 .name = "gcc_ce1_axi_clk",
973 .ops = &clk_branch2_ops,
978 static struct clk_branch gcc_ce1_clk = {
980 .halt_check = BRANCH_HALT_VOTED,
982 .enable_reg = 0x52000,
983 .enable_mask = BIT(5),
984 .hw.init = &(struct clk_init_data){
985 .name = "gcc_ce1_clk",
986 .ops = &clk_branch2_ops,
991 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
993 .halt_check = BRANCH_HALT,
995 .enable_reg = 0x502c,
996 .enable_mask = BIT(0),
997 .hw.init = &(struct clk_init_data){
998 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
999 .parent_data = &(const struct clk_parent_data){
1000 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1003 .flags = CLK_SET_RATE_PARENT,
1004 .ops = &clk_branch2_ops,
1009 /* For CPUSS functionality the AHB clock needs to be left enabled */
1010 static struct clk_branch gcc_cpuss_ahb_clk = {
1011 .halt_reg = 0x48000,
1012 .halt_check = BRANCH_HALT_VOTED,
1014 .enable_reg = 0x52000,
1015 .enable_mask = BIT(21),
1016 .hw.init = &(struct clk_init_data){
1017 .name = "gcc_cpuss_ahb_clk",
1018 .parent_data = &(const struct clk_parent_data){
1019 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
1022 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1023 .ops = &clk_branch2_ops,
1028 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1029 .halt_reg = 0x48008,
1030 .halt_check = BRANCH_HALT,
1032 .enable_reg = 0x48008,
1033 .enable_mask = BIT(0),
1034 .hw.init = &(struct clk_init_data){
1035 .name = "gcc_cpuss_rbcpr_clk",
1036 .ops = &clk_branch2_ops,
1041 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1042 .halt_reg = 0x4452c,
1043 .halt_check = BRANCH_VOTED,
1045 .enable_reg = 0x4452c,
1046 .enable_mask = BIT(0),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gcc_ddrss_gpu_axi_clk",
1049 .ops = &clk_branch2_ops,
1054 static struct clk_branch gcc_disp_gpll0_clk_src = {
1055 .halt_check = BRANCH_HALT_DELAY,
1057 .enable_reg = 0x52000,
1058 .enable_mask = BIT(18),
1059 .hw.init = &(struct clk_init_data){
1060 .name = "gcc_disp_gpll0_clk_src",
1061 .parent_data = &(const struct clk_parent_data){
1062 .hw = &gpll0.clkr.hw,
1065 .ops = &clk_branch2_aon_ops,
1070 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1071 .halt_check = BRANCH_HALT_DELAY,
1073 .enable_reg = 0x52000,
1074 .enable_mask = BIT(19),
1075 .hw.init = &(struct clk_init_data){
1076 .name = "gcc_disp_gpll0_div_clk_src",
1077 .parent_data = &(const struct clk_parent_data){
1078 .hw = &gcc_pll0_main_div_cdiv.hw,
1081 .ops = &clk_branch2_ops,
1086 static struct clk_branch gcc_disp_hf_axi_clk = {
1088 .halt_check = BRANCH_HALT,
1090 .enable_reg = 0xb024,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(struct clk_init_data){
1093 .name = "gcc_disp_hf_axi_clk",
1094 .ops = &clk_branch2_ops,
1099 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1101 .halt_check = BRANCH_HALT,
1105 .enable_reg = 0xb084,
1106 .enable_mask = BIT(0),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "gcc_disp_throttle_hf_axi_clk",
1109 .ops = &clk_branch2_ops,
1114 static struct clk_branch gcc_disp_xo_clk = {
1116 .halt_check = BRANCH_HALT,
1118 .enable_reg = 0xb030,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "gcc_disp_xo_clk",
1122 .ops = &clk_branch2_ops,
1127 static struct clk_branch gcc_gp1_clk = {
1128 .halt_reg = 0x64000,
1129 .halt_check = BRANCH_HALT,
1131 .enable_reg = 0x64000,
1132 .enable_mask = BIT(0),
1133 .hw.init = &(struct clk_init_data){
1134 .name = "gcc_gp1_clk",
1135 .parent_data = &(const struct clk_parent_data){
1136 .hw = &gcc_gp1_clk_src.clkr.hw,
1139 .flags = CLK_SET_RATE_PARENT,
1140 .ops = &clk_branch2_ops,
1145 static struct clk_branch gcc_gp2_clk = {
1146 .halt_reg = 0x65000,
1147 .halt_check = BRANCH_HALT,
1149 .enable_reg = 0x65000,
1150 .enable_mask = BIT(0),
1151 .hw.init = &(struct clk_init_data){
1152 .name = "gcc_gp2_clk",
1153 .parent_data = &(const struct clk_parent_data){
1154 .hw = &gcc_gp2_clk_src.clkr.hw,
1157 .flags = CLK_SET_RATE_PARENT,
1158 .ops = &clk_branch2_ops,
1163 static struct clk_branch gcc_gp3_clk = {
1164 .halt_reg = 0x66000,
1165 .halt_check = BRANCH_HALT,
1167 .enable_reg = 0x66000,
1168 .enable_mask = BIT(0),
1169 .hw.init = &(struct clk_init_data){
1170 .name = "gcc_gp3_clk",
1171 .parent_data = &(const struct clk_parent_data){
1172 .hw = &gcc_gp3_clk_src.clkr.hw,
1175 .flags = CLK_SET_RATE_PARENT,
1176 .ops = &clk_branch2_ops,
1181 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1182 .halt_check = BRANCH_HALT_DELAY,
1184 .enable_reg = 0x52000,
1185 .enable_mask = BIT(15),
1186 .hw.init = &(struct clk_init_data){
1187 .name = "gcc_gpu_gpll0_clk_src",
1188 .parent_data = &(const struct clk_parent_data){
1189 .hw = &gpll0.clkr.hw,
1192 .ops = &clk_branch2_ops,
1197 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1198 .halt_check = BRANCH_HALT_DELAY,
1200 .enable_reg = 0x52000,
1201 .enable_mask = BIT(16),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_gpu_gpll0_div_clk_src",
1204 .parent_data = &(const struct clk_parent_data){
1205 .hw = &gcc_pll0_main_div_cdiv.hw,
1208 .ops = &clk_branch2_ops,
1213 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1214 .halt_reg = 0x7100c,
1215 .halt_check = BRANCH_VOTED,
1217 .enable_reg = 0x7100c,
1218 .enable_mask = BIT(0),
1219 .hw.init = &(struct clk_init_data){
1220 .name = "gcc_gpu_memnoc_gfx_clk",
1221 .ops = &clk_branch2_ops,
1226 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1227 .halt_reg = 0x71018,
1228 .halt_check = BRANCH_HALT,
1230 .enable_reg = 0x71018,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1234 .ops = &clk_branch2_ops,
1239 static struct clk_branch gcc_npu_axi_clk = {
1240 .halt_reg = 0x4d008,
1241 .halt_check = BRANCH_HALT,
1243 .enable_reg = 0x4d008,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "gcc_npu_axi_clk",
1247 .ops = &clk_branch2_ops,
1252 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1253 .halt_reg = 0x73008,
1254 .halt_check = BRANCH_HALT,
1256 .enable_reg = 0x73008,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "gcc_npu_bwmon_axi_clk",
1260 .ops = &clk_branch2_ops,
1265 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1266 .halt_reg = 0x73018,
1267 .halt_check = BRANCH_HALT,
1269 .enable_reg = 0x73018,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1273 .ops = &clk_branch2_ops,
1278 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1279 .halt_reg = 0x7301c,
1280 .halt_check = BRANCH_HALT,
1282 .enable_reg = 0x7301c,
1283 .enable_mask = BIT(0),
1284 .hw.init = &(struct clk_init_data){
1285 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1286 .ops = &clk_branch2_ops,
1291 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1292 .halt_reg = 0x4d004,
1293 .halt_check = BRANCH_HALT,
1294 .hwcg_reg = 0x4d004,
1297 .enable_reg = 0x4d004,
1298 .enable_mask = BIT(0),
1299 .hw.init = &(struct clk_init_data){
1300 .name = "gcc_npu_cfg_ahb_clk",
1301 .ops = &clk_branch2_ops,
1306 static struct clk_branch gcc_npu_dma_clk = {
1307 .halt_reg = 0x4d1a0,
1308 .halt_check = BRANCH_HALT,
1309 .hwcg_reg = 0x4d1a0,
1312 .enable_reg = 0x4d1a0,
1313 .enable_mask = BIT(0),
1314 .hw.init = &(struct clk_init_data){
1315 .name = "gcc_npu_dma_clk",
1316 .ops = &clk_branch2_ops,
1321 static struct clk_branch gcc_npu_gpll0_clk_src = {
1322 .halt_check = BRANCH_HALT_DELAY,
1324 .enable_reg = 0x52000,
1325 .enable_mask = BIT(25),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "gcc_npu_gpll0_clk_src",
1328 .parent_data = &(const struct clk_parent_data){
1329 .hw = &gpll0.clkr.hw,
1332 .ops = &clk_branch2_ops,
1337 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1338 .halt_check = BRANCH_HALT_DELAY,
1340 .enable_reg = 0x52000,
1341 .enable_mask = BIT(26),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "gcc_npu_gpll0_div_clk_src",
1344 .parent_data = &(const struct clk_parent_data){
1345 .hw = &gcc_pll0_main_div_cdiv.hw,
1348 .flags = CLK_SET_RATE_PARENT,
1349 .ops = &clk_branch2_ops,
1354 static struct clk_branch gcc_pdm2_clk = {
1355 .halt_reg = 0x3300c,
1356 .halt_check = BRANCH_HALT,
1358 .enable_reg = 0x3300c,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "gcc_pdm2_clk",
1362 .parent_data = &(const struct clk_parent_data){
1363 .hw = &gcc_pdm2_clk_src.clkr.hw,
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1372 static struct clk_branch gcc_pdm_ahb_clk = {
1373 .halt_reg = 0x33004,
1374 .halt_check = BRANCH_HALT,
1375 .hwcg_reg = 0x33004,
1378 .enable_reg = 0x33004,
1379 .enable_mask = BIT(0),
1380 .hw.init = &(struct clk_init_data){
1381 .name = "gcc_pdm_ahb_clk",
1382 .ops = &clk_branch2_ops,
1387 static struct clk_branch gcc_pdm_xo4_clk = {
1388 .halt_reg = 0x33008,
1389 .halt_check = BRANCH_HALT,
1391 .enable_reg = 0x33008,
1392 .enable_mask = BIT(0),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gcc_pdm_xo4_clk",
1395 .ops = &clk_branch2_ops,
1400 static struct clk_branch gcc_prng_ahb_clk = {
1401 .halt_reg = 0x34004,
1402 .halt_check = BRANCH_HALT_VOTED,
1403 .hwcg_reg = 0x34004,
1406 .enable_reg = 0x52000,
1407 .enable_mask = BIT(13),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_prng_ahb_clk",
1410 .ops = &clk_branch2_ops,
1415 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1416 .halt_reg = 0x4b004,
1417 .halt_check = BRANCH_HALT,
1418 .hwcg_reg = 0x4b004,
1421 .enable_reg = 0x4b004,
1422 .enable_mask = BIT(0),
1423 .hw.init = &(struct clk_init_data){
1424 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1425 .ops = &clk_branch2_ops,
1430 static struct clk_branch gcc_qspi_core_clk = {
1431 .halt_reg = 0x4b008,
1432 .halt_check = BRANCH_HALT,
1434 .enable_reg = 0x4b008,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gcc_qspi_core_clk",
1438 .parent_data = &(const struct clk_parent_data){
1439 .hw = &gcc_qspi_core_clk_src.clkr.hw,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1448 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1449 .halt_reg = 0x17014,
1450 .halt_check = BRANCH_HALT_VOTED,
1452 .enable_reg = 0x52008,
1453 .enable_mask = BIT(9),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_qupv3_wrap0_core_2x_clk",
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1462 .halt_reg = 0x1700c,
1463 .halt_check = BRANCH_HALT_VOTED,
1465 .enable_reg = 0x52008,
1466 .enable_mask = BIT(8),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_qupv3_wrap0_core_clk",
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1475 .halt_reg = 0x17030,
1476 .halt_check = BRANCH_HALT_VOTED,
1478 .enable_reg = 0x52008,
1479 .enable_mask = BIT(10),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_qupv3_wrap0_s0_clk",
1482 .parent_data = &(const struct clk_parent_data){
1483 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1493 .halt_reg = 0x17160,
1494 .halt_check = BRANCH_HALT_VOTED,
1496 .enable_reg = 0x52008,
1497 .enable_mask = BIT(11),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "gcc_qupv3_wrap0_s1_clk",
1500 .parent_data = &(const struct clk_parent_data){
1501 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1511 .halt_reg = 0x17290,
1512 .halt_check = BRANCH_HALT_VOTED,
1514 .enable_reg = 0x52008,
1515 .enable_mask = BIT(12),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_qupv3_wrap0_s2_clk",
1518 .parent_data = &(const struct clk_parent_data){
1519 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1528 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1529 .halt_reg = 0x173c0,
1530 .halt_check = BRANCH_HALT_VOTED,
1532 .enable_reg = 0x52008,
1533 .enable_mask = BIT(13),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_qupv3_wrap0_s3_clk",
1536 .parent_data = &(const struct clk_parent_data){
1537 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1546 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1547 .halt_reg = 0x174f0,
1548 .halt_check = BRANCH_HALT_VOTED,
1550 .enable_reg = 0x52008,
1551 .enable_mask = BIT(14),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "gcc_qupv3_wrap0_s4_clk",
1554 .parent_data = &(const struct clk_parent_data){
1555 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1558 .flags = CLK_SET_RATE_PARENT,
1559 .ops = &clk_branch2_ops,
1564 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1565 .halt_reg = 0x17620,
1566 .halt_check = BRANCH_HALT_VOTED,
1568 .enable_reg = 0x52008,
1569 .enable_mask = BIT(15),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "gcc_qupv3_wrap0_s5_clk",
1572 .parent_data = &(const struct clk_parent_data){
1573 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1576 .flags = CLK_SET_RATE_PARENT,
1577 .ops = &clk_branch2_ops,
1582 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1583 .halt_reg = 0x18004,
1584 .halt_check = BRANCH_HALT_VOTED,
1586 .enable_reg = 0x52008,
1587 .enable_mask = BIT(18),
1588 .hw.init = &(struct clk_init_data){
1589 .name = "gcc_qupv3_wrap1_core_2x_clk",
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1596 .halt_reg = 0x18008,
1597 .halt_check = BRANCH_HALT_VOTED,
1599 .enable_reg = 0x52008,
1600 .enable_mask = BIT(19),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "gcc_qupv3_wrap1_core_clk",
1603 .ops = &clk_branch2_ops,
1608 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1609 .halt_reg = 0x18014,
1610 .halt_check = BRANCH_HALT_VOTED,
1612 .enable_reg = 0x52008,
1613 .enable_mask = BIT(22),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "gcc_qupv3_wrap1_s0_clk",
1616 .parent_data = &(const struct clk_parent_data){
1617 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_branch2_ops,
1626 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1627 .halt_reg = 0x18144,
1628 .halt_check = BRANCH_HALT_VOTED,
1630 .enable_reg = 0x52008,
1631 .enable_mask = BIT(23),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gcc_qupv3_wrap1_s1_clk",
1634 .parent_data = &(const struct clk_parent_data){
1635 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1644 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1645 .halt_reg = 0x18274,
1646 .halt_check = BRANCH_HALT_VOTED,
1648 .enable_reg = 0x52008,
1649 .enable_mask = BIT(24),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_qupv3_wrap1_s2_clk",
1652 .parent_data = &(const struct clk_parent_data){
1653 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1656 .flags = CLK_SET_RATE_PARENT,
1657 .ops = &clk_branch2_ops,
1662 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1663 .halt_reg = 0x183a4,
1664 .halt_check = BRANCH_HALT_VOTED,
1666 .enable_reg = 0x52008,
1667 .enable_mask = BIT(25),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "gcc_qupv3_wrap1_s3_clk",
1670 .parent_data = &(const struct clk_parent_data){
1671 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1681 .halt_reg = 0x184d4,
1682 .halt_check = BRANCH_HALT_VOTED,
1684 .enable_reg = 0x52008,
1685 .enable_mask = BIT(26),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_qupv3_wrap1_s4_clk",
1688 .parent_data = &(const struct clk_parent_data){
1689 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1692 .flags = CLK_SET_RATE_PARENT,
1693 .ops = &clk_branch2_ops,
1698 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1699 .halt_reg = 0x18604,
1700 .halt_check = BRANCH_HALT_VOTED,
1702 .enable_reg = 0x52008,
1703 .enable_mask = BIT(27),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "gcc_qupv3_wrap1_s5_clk",
1706 .parent_data = &(const struct clk_parent_data){
1707 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1717 .halt_reg = 0x17004,
1718 .halt_check = BRANCH_HALT_VOTED,
1720 .enable_reg = 0x52008,
1721 .enable_mask = BIT(6),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1724 .ops = &clk_branch2_ops,
1729 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1730 .halt_reg = 0x17008,
1731 .halt_check = BRANCH_HALT_VOTED,
1732 .hwcg_reg = 0x17008,
1735 .enable_reg = 0x52008,
1736 .enable_mask = BIT(7),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1745 .halt_reg = 0x1800c,
1746 .halt_check = BRANCH_HALT_VOTED,
1748 .enable_reg = 0x52008,
1749 .enable_mask = BIT(20),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1758 .halt_reg = 0x18010,
1759 .halt_check = BRANCH_HALT_VOTED,
1760 .hwcg_reg = 0x18010,
1763 .enable_reg = 0x52008,
1764 .enable_mask = BIT(21),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1767 .ops = &clk_branch2_ops,
1772 static struct clk_branch gcc_sdcc1_ahb_clk = {
1773 .halt_reg = 0x12008,
1774 .halt_check = BRANCH_HALT,
1776 .enable_reg = 0x12008,
1777 .enable_mask = BIT(0),
1778 .hw.init = &(struct clk_init_data){
1779 .name = "gcc_sdcc1_ahb_clk",
1780 .ops = &clk_branch2_ops,
1785 static struct clk_branch gcc_sdcc1_apps_clk = {
1786 .halt_reg = 0x1200c,
1787 .halt_check = BRANCH_HALT,
1789 .enable_reg = 0x1200c,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "gcc_sdcc1_apps_clk",
1793 .parent_data = &(const struct clk_parent_data){
1794 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
1797 .flags = CLK_SET_RATE_PARENT,
1798 .ops = &clk_branch2_ops,
1803 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1804 .halt_reg = 0x12040,
1805 .halt_check = BRANCH_HALT,
1807 .enable_reg = 0x12040,
1808 .enable_mask = BIT(0),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "gcc_sdcc1_ice_core_clk",
1811 .parent_data = &(const struct clk_parent_data){
1812 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1821 static struct clk_branch gcc_sdcc2_ahb_clk = {
1822 .halt_reg = 0x14008,
1823 .halt_check = BRANCH_HALT,
1825 .enable_reg = 0x14008,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "gcc_sdcc2_ahb_clk",
1829 .ops = &clk_branch2_ops,
1834 static struct clk_branch gcc_sdcc2_apps_clk = {
1835 .halt_reg = 0x14004,
1836 .halt_check = BRANCH_HALT,
1838 .enable_reg = 0x14004,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "gcc_sdcc2_apps_clk",
1842 .parent_data = &(const struct clk_parent_data){
1843 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
1846 .flags = CLK_SET_RATE_PARENT,
1847 .ops = &clk_branch2_ops,
1852 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1853 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1855 .halt_check = BRANCH_HALT_VOTED,
1857 .enable_reg = 0x52000,
1858 .enable_mask = BIT(0),
1859 .hw.init = &(struct clk_init_data){
1860 .name = "gcc_sys_noc_cpuss_ahb_clk",
1861 .parent_data = &(const struct clk_parent_data){
1862 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
1865 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1871 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1872 .halt_reg = 0x8c000,
1873 .halt_check = BRANCH_HALT,
1875 .enable_reg = 0x8c000,
1876 .enable_mask = BIT(0),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "gcc_ufs_mem_clkref_clk",
1879 .ops = &clk_branch2_ops,
1884 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1885 .halt_reg = 0x77014,
1886 .halt_check = BRANCH_HALT,
1887 .hwcg_reg = 0x77014,
1890 .enable_reg = 0x77014,
1891 .enable_mask = BIT(0),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "gcc_ufs_phy_ahb_clk",
1894 .ops = &clk_branch2_ops,
1899 static struct clk_branch gcc_ufs_phy_axi_clk = {
1900 .halt_reg = 0x77038,
1901 .halt_check = BRANCH_HALT,
1902 .hwcg_reg = 0x77038,
1905 .enable_reg = 0x77038,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_ufs_phy_axi_clk",
1909 .parent_data = &(const struct clk_parent_data){
1910 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1913 .flags = CLK_SET_RATE_PARENT,
1914 .ops = &clk_branch2_ops,
1919 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1920 .halt_reg = 0x77090,
1921 .halt_check = BRANCH_HALT,
1922 .hwcg_reg = 0x77090,
1925 .enable_reg = 0x77090,
1926 .enable_mask = BIT(0),
1927 .hw.init = &(struct clk_init_data){
1928 .name = "gcc_ufs_phy_ice_core_clk",
1929 .parent_data = &(const struct clk_parent_data){
1930 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1933 .flags = CLK_SET_RATE_PARENT,
1934 .ops = &clk_branch2_ops,
1939 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1940 .halt_reg = 0x77094,
1941 .halt_check = BRANCH_HALT,
1942 .hwcg_reg = 0x77094,
1945 .enable_reg = 0x77094,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "gcc_ufs_phy_phy_aux_clk",
1949 .parent_data = &(const struct clk_parent_data){
1950 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1953 .flags = CLK_SET_RATE_PARENT,
1954 .ops = &clk_branch2_ops,
1959 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1960 .halt_reg = 0x7701c,
1961 .halt_check = BRANCH_HALT_SKIP,
1963 .enable_reg = 0x7701c,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_ufs_phy_rx_symbol_0_clk",
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1973 .halt_reg = 0x77018,
1974 .halt_check = BRANCH_HALT_SKIP,
1976 .enable_reg = 0x77018,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_ufs_phy_tx_symbol_0_clk",
1980 .ops = &clk_branch2_ops,
1985 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1986 .halt_reg = 0x7708c,
1987 .halt_check = BRANCH_HALT,
1988 .hwcg_reg = 0x7708c,
1991 .enable_reg = 0x7708c,
1992 .enable_mask = BIT(0),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_ufs_phy_unipro_core_clk",
1995 .parent_data = &(const struct clk_parent_data){
1996 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_usb30_prim_master_clk = {
2007 .halt_check = BRANCH_HALT,
2009 .enable_reg = 0xf010,
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_usb30_prim_master_clk",
2013 .parent_data = &(const struct clk_parent_data){
2014 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2023 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2025 .halt_check = BRANCH_HALT,
2027 .enable_reg = 0xf018,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_usb30_prim_mock_utmi_clk",
2031 .parent_data = &(const struct clk_parent_data){
2033 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2036 .flags = CLK_SET_RATE_PARENT,
2037 .ops = &clk_branch2_ops,
2042 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2044 .halt_check = BRANCH_HALT,
2046 .enable_reg = 0xf014,
2047 .enable_mask = BIT(0),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "gcc_usb30_prim_sleep_clk",
2050 .ops = &clk_branch2_ops,
2055 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2056 .halt_reg = 0x8c010,
2057 .halt_check = BRANCH_HALT,
2059 .enable_reg = 0x8c010,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "gcc_usb3_prim_clkref_clk",
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2070 .halt_check = BRANCH_HALT,
2072 .enable_reg = 0xf050,
2073 .enable_mask = BIT(0),
2074 .hw.init = &(struct clk_init_data){
2075 .name = "gcc_usb3_prim_phy_aux_clk",
2076 .parent_data = &(const struct clk_parent_data){
2077 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2080 .flags = CLK_SET_RATE_PARENT,
2081 .ops = &clk_branch2_ops,
2086 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2088 .halt_check = BRANCH_HALT,
2090 .enable_reg = 0xf054,
2091 .enable_mask = BIT(0),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "gcc_usb3_prim_phy_com_aux_clk",
2094 .parent_data = &(const struct clk_parent_data){
2095 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2106 .halt_check = BRANCH_HALT_SKIP,
2108 .enable_reg = 0xf058,
2109 .enable_mask = BIT(0),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "gcc_usb3_prim_phy_pipe_clk",
2112 .ops = &clk_branch2_ops,
2117 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2118 .halt_reg = 0x6a004,
2119 .halt_check = BRANCH_HALT,
2120 .hwcg_reg = 0x6a004,
2123 .enable_reg = 0x6a004,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2127 .ops = &clk_branch2_ops,
2132 static struct clk_branch gcc_video_axi_clk = {
2134 .halt_check = BRANCH_HALT,
2136 .enable_reg = 0xb01c,
2137 .enable_mask = BIT(0),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_video_axi_clk",
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2146 .halt_check = BRANCH_HALT_DELAY,
2148 .enable_reg = 0x52000,
2149 .enable_mask = BIT(20),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "gcc_video_gpll0_div_clk_src",
2152 .parent_data = &(const struct clk_parent_data){
2153 .hw = &gcc_pll0_main_div_cdiv.hw,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2162 static struct clk_branch gcc_video_throttle_axi_clk = {
2164 .halt_check = BRANCH_HALT,
2168 .enable_reg = 0xb07c,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "gcc_video_throttle_axi_clk",
2172 .ops = &clk_branch2_ops,
2177 static struct clk_branch gcc_video_xo_clk = {
2179 .halt_check = BRANCH_HALT,
2181 .enable_reg = 0xb028,
2182 .enable_mask = BIT(0),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_video_xo_clk",
2185 .ops = &clk_branch2_ops,
2190 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2191 .halt_reg = 0x8a000,
2192 .halt_check = BRANCH_HALT,
2194 .enable_reg = 0x8a000,
2195 .enable_mask = BIT(0),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "gcc_mss_cfg_ahb_clk",
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_mss_mfab_axis_clk = {
2204 .halt_reg = 0x8a004,
2205 .halt_check = BRANCH_HALT_VOTED,
2207 .enable_reg = 0x8a004,
2208 .enable_mask = BIT(0),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_mss_mfab_axis_clk",
2211 .ops = &clk_branch2_ops,
2216 static struct clk_branch gcc_mss_nav_axi_clk = {
2217 .halt_reg = 0x8a00c,
2218 .halt_check = BRANCH_HALT_VOTED,
2220 .enable_reg = 0x8a00c,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "gcc_mss_nav_axi_clk",
2224 .ops = &clk_branch2_ops,
2229 static struct clk_branch gcc_mss_snoc_axi_clk = {
2230 .halt_reg = 0x8a150,
2231 .halt_check = BRANCH_HALT,
2233 .enable_reg = 0x8a150,
2234 .enable_mask = BIT(0),
2235 .hw.init = &(struct clk_init_data){
2236 .name = "gcc_mss_snoc_axi_clk",
2237 .ops = &clk_branch2_ops,
2242 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2243 .halt_reg = 0x8a154,
2244 .halt_check = BRANCH_HALT,
2246 .enable_reg = 0x8a154,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "gcc_mss_q6_memnoc_axi_clk",
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2256 .halt_reg = 0x47018,
2257 .halt_check = BRANCH_HALT_DELAY,
2259 .enable_reg = 0x47018,
2260 .enable_mask = BIT(0),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "gcc_lpass_cfg_noc_sway_clk",
2263 .ops = &clk_branch2_ops,
2268 static struct gdsc ufs_phy_gdsc = {
2271 .name = "ufs_phy_gdsc",
2273 .pwrsts = PWRSTS_OFF_ON,
2276 static struct gdsc usb30_prim_gdsc = {
2279 .name = "usb30_prim_gdsc",
2281 .pwrsts = PWRSTS_OFF_ON,
2284 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2287 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2289 .pwrsts = PWRSTS_OFF_ON,
2293 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2296 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2298 .pwrsts = PWRSTS_OFF_ON,
2302 static struct gdsc *gcc_sc7180_gdscs[] = {
2303 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2304 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2305 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2306 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2307 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2308 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2312 static struct clk_hw *gcc_sc7180_hws[] = {
2313 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2316 static struct clk_regmap *gcc_sc7180_clocks[] = {
2317 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2318 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2319 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2320 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2321 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2322 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2323 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2324 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2325 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2326 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2327 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2328 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2329 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2330 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2331 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2332 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2333 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2334 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2335 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2336 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2337 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2338 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2339 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2340 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2341 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2342 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2343 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2344 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2345 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2346 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2347 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2348 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2349 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2350 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2351 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2352 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2353 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2354 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2355 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2356 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2357 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2358 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2359 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2360 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2361 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2362 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2363 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2364 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2365 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2366 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2367 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2368 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2369 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2370 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2371 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2372 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2373 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2374 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2375 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2376 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2377 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2378 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2379 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2380 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2381 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2382 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2383 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2384 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2385 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2386 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2387 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2388 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2389 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2390 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2391 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2392 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2393 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2394 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2395 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2396 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2397 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2398 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2399 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2400 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2401 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2402 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2403 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2404 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2405 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2406 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2407 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2408 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2409 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2410 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2411 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2412 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2413 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2414 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2415 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2416 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2417 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2418 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2419 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2420 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2421 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2422 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2423 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2424 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2425 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2426 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2427 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2428 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2429 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2430 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2431 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2432 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2433 [GPLL0] = &gpll0.clkr,
2434 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2435 [GPLL6] = &gpll6.clkr,
2436 [GPLL7] = &gpll7.clkr,
2437 [GPLL4] = &gpll4.clkr,
2438 [GPLL1] = &gpll1.clkr,
2439 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2440 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2441 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2442 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2443 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2444 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2445 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2448 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2449 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2450 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2451 [GCC_UFS_PHY_BCR] = { 0x77000 },
2452 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2453 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2454 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2455 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2456 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2457 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2458 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2459 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2462 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2463 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2464 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2465 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2466 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2467 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2468 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2469 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2470 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2471 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2472 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2473 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2474 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2477 static const struct regmap_config gcc_sc7180_regmap_config = {
2481 .max_register = 0x18208c,
2485 static const struct qcom_cc_desc gcc_sc7180_desc = {
2486 .config = &gcc_sc7180_regmap_config,
2487 .clk_hws = gcc_sc7180_hws,
2488 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2489 .clks = gcc_sc7180_clocks,
2490 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2491 .resets = gcc_sc7180_resets,
2492 .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2493 .gdscs = gcc_sc7180_gdscs,
2494 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2497 static const struct of_device_id gcc_sc7180_match_table[] = {
2498 { .compatible = "qcom,gcc-sc7180" },
2501 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2503 static int gcc_sc7180_probe(struct platform_device *pdev)
2505 struct regmap *regmap;
2508 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2510 return PTR_ERR(regmap);
2513 * Disable the GPLL0 active input to MM blocks, NPU
2514 * and GPU via MISC registers.
2516 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2517 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2518 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2521 * Keep the clocks always-ON
2522 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_DISP_AHB_CLK
2523 * GCC_GPU_CFG_AHB_CLK
2525 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2526 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2527 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2528 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2530 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2531 ARRAY_SIZE(gcc_dfs_clocks));
2535 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2538 static struct platform_driver gcc_sc7180_driver = {
2539 .probe = gcc_sc7180_probe,
2541 .name = "gcc-sc7180",
2542 .of_match_table = gcc_sc7180_match_table,
2546 static int __init gcc_sc7180_init(void)
2548 return platform_driver_register(&gcc_sc7180_driver);
2550 core_initcall(gcc_sc7180_init);
2552 static void __exit gcc_sc7180_exit(void)
2554 platform_driver_unregister(&gcc_sc7180_driver);
2556 module_exit(gcc_sc7180_exit);
2558 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2559 MODULE_LICENSE("GPL v2");