drivers/clk/qcom/gcc-qcs404.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/regmap.h>
  12 #include <linux/reset-controller.h>
  13
  14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-pll.h"
  19 #include "clk-rcg.h"
  20 #include "clk-regmap.h"
  21 #include "common.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_CORE_BI_PLL_TEST_SE,
  26         P_DSI0_PHY_PLL_OUT_BYTECLK,
  27         P_DSI0_PHY_PLL_OUT_DSICLK,
  28         P_GPLL0_OUT_MAIN,
  29         P_GPLL1_OUT_MAIN,
  30         P_GPLL3_OUT_MAIN,
  31         P_GPLL4_OUT_MAIN,
  32         P_GPLL6_OUT_AUX,
  33         P_HDMI_PHY_PLL_CLK,
  34         P_PCIE_0_PIPE_CLK,
  35         P_SLEEP_CLK,
  36         P_XO,
  37 };
  38
  39 static const struct parent_map gcc_parent_map_0[] = {
  40         { P_XO, 0 },
  41         { P_GPLL0_OUT_MAIN, 1 },
  42         { P_CORE_BI_PLL_TEST_SE, 7 },
  43 };
  44
  45 static const char * const gcc_parent_names_0[] = {
  46         "cxo",
  47         "gpll0_out_main",
  48         "core_bi_pll_test_se",
  49 };
  50
  51 static const char * const gcc_parent_names_ao_0[] = {
  52         "cxo",
  53         "gpll0_ao_out_main",
  54         "core_bi_pll_test_se",
  55 };
  56
  57 static const struct parent_map gcc_parent_map_1[] = {
  58         { P_XO, 0 },
  59         { P_CORE_BI_PLL_TEST_SE, 7 },
  60 };
  61
  62 static const char * const gcc_parent_names_1[] = {
  63         "cxo",
  64         "core_bi_pll_test_se",
  65 };
  66
  67 static const struct parent_map gcc_parent_map_2[] = {
  68         { P_XO, 0 },
  69         { P_GPLL0_OUT_MAIN, 1 },
  70         { P_GPLL6_OUT_AUX, 2 },
  71         { P_SLEEP_CLK, 6 },
  72 };
  73
  74 static const char * const gcc_parent_names_2[] = {
  75         "cxo",
  76         "gpll0_out_main",
  77         "gpll6_out_aux",
  78         "sleep_clk",
  79 };
  80
  81 static const struct parent_map gcc_parent_map_3[] = {
  82         { P_XO, 0 },
  83         { P_GPLL0_OUT_MAIN, 1 },
  84         { P_GPLL6_OUT_AUX, 2 },
  85         { P_CORE_BI_PLL_TEST_SE, 7 },
  86 };
  87
  88 static const char * const gcc_parent_names_3[] = {
  89         "cxo",
  90         "gpll0_out_main",
  91         "gpll6_out_aux",
  92         "core_bi_pll_test_se",
  93 };
  94
  95 static const struct parent_map gcc_parent_map_4[] = {
  96         { P_XO, 0 },
  97         { P_GPLL1_OUT_MAIN, 1 },
  98         { P_CORE_BI_PLL_TEST_SE, 7 },
  99 };
 100
 101 static const char * const gcc_parent_names_4[] = {
 102         "cxo",
 103         "gpll1_out_main",
 104         "core_bi_pll_test_se",
 105 };
 106
 107 static const struct parent_map gcc_parent_map_5[] = {
 108         { P_XO, 0 },
 109         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 110         { P_CORE_BI_PLL_TEST_SE, 7 },
 111 };
 112
 113 static const char * const gcc_parent_names_5[] = {
 114         "cxo",
 115         "dsi0pllbyte",
 116         "core_bi_pll_test_se",
 117 };
 118
 119 static const struct parent_map gcc_parent_map_6[] = {
 120         { P_XO, 0 },
 121         { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 122         { P_CORE_BI_PLL_TEST_SE, 7 },
 123 };
 124
 125 static const char * const gcc_parent_names_6[] = {
 126         "cxo",
 127         "dsi0pllbyte",
 128         "core_bi_pll_test_se",
 129 };
 130
 131 static const struct parent_map gcc_parent_map_7[] = {
 132         { P_XO, 0 },
 133         { P_GPLL0_OUT_MAIN, 1 },
 134         { P_GPLL3_OUT_MAIN, 2 },
 135         { P_GPLL6_OUT_AUX, 3 },
 136         { P_CORE_BI_PLL_TEST_SE, 7 },
 137 };
 138
 139 static const char * const gcc_parent_names_7[] = {
 140         "cxo",
 141         "gpll0_out_main",
 142         "gpll3_out_main",
 143         "gpll6_out_aux",
 144         "core_bi_pll_test_se",
 145 };
 146
 147 static const struct parent_map gcc_parent_map_8[] = {
 148         { P_XO, 0 },
 149         { P_HDMI_PHY_PLL_CLK, 1 },
 150         { P_CORE_BI_PLL_TEST_SE, 7 },
 151 };
 152
 153 static const char * const gcc_parent_names_8[] = {
 154         "cxo",
 155         "hdmi_phy_pll_clk",
 156         "core_bi_pll_test_se",
 157 };
 158
 159 static const struct parent_map gcc_parent_map_9[] = {
 160         { P_XO, 0 },
 161         { P_GPLL0_OUT_MAIN, 1 },
 162         { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
 163         { P_GPLL6_OUT_AUX, 3 },
 164         { P_CORE_BI_PLL_TEST_SE, 7 },
 165 };
 166
 167 static const char * const gcc_parent_names_9[] = {
 168         "cxo",
 169         "gpll0_out_main",
 170         "dsi0pll",
 171         "gpll6_out_aux",
 172         "core_bi_pll_test_se",
 173 };
 174
 175 static const struct parent_map gcc_parent_map_10[] = {
 176         { P_XO, 0 },
 177         { P_SLEEP_CLK, 1 },
 178         { P_CORE_BI_PLL_TEST_SE, 7 },
 179 };
 180
 181 static const char * const gcc_parent_names_10[] = {
 182         "cxo",
 183         "sleep_clk",
 184         "core_bi_pll_test_se",
 185 };
 186
 187 static const struct parent_map gcc_parent_map_11[] = {
 188         { P_XO, 0 },
 189         { P_PCIE_0_PIPE_CLK, 1 },
 190         { P_CORE_BI_PLL_TEST_SE, 7 },
 191 };
 192
 193 static const char * const gcc_parent_names_11[] = {
 194         "cxo",
 195         "pcie_0_pipe_clk",
 196         "core_bi_pll_test_se",
 197 };
 198
 199 static const struct parent_map gcc_parent_map_12[] = {
 200         { P_XO, 0 },
 201         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 202         { P_CORE_BI_PLL_TEST_SE, 7 },
 203 };
 204
 205 static const char * const gcc_parent_names_12[] = {
 206         "cxo",
 207         "dsi0pll",
 208         "core_bi_pll_test_se",
 209 };
 210
 211 static const struct parent_map gcc_parent_map_13[] = {
 212         { P_XO, 0 },
 213         { P_GPLL0_OUT_MAIN, 1 },
 214         { P_GPLL4_OUT_MAIN, 2 },
 215         { P_GPLL6_OUT_AUX, 3 },
 216         { P_CORE_BI_PLL_TEST_SE, 7 },
 217 };
 218
 219 static const char * const gcc_parent_names_13[] = {
 220         "cxo",
 221         "gpll0_out_main",
 222         "gpll4_out_main",
 223         "gpll6_out_aux",
 224         "core_bi_pll_test_se",
 225 };
 226
 227 static const struct parent_map gcc_parent_map_14[] = {
 228         { P_XO, 0 },
 229         { P_GPLL0_OUT_MAIN, 1 },
 230         { P_CORE_BI_PLL_TEST_SE, 7 },
 231 };
 232
 233 static const char * const gcc_parent_names_14[] = {
 234         "cxo",
 235         "gpll0_out_main",
 236         "core_bi_pll_test_se",
 237 };
 238
 239 static const struct parent_map gcc_parent_map_15[] = {
 240         { P_XO, 0 },
 241         { P_CORE_BI_PLL_TEST_SE, 7 },
 242 };
 243
 244 static const char * const gcc_parent_names_15[] = {
 245         "cxo",
 246         "core_bi_pll_test_se",
 247 };
 248
 249 static const struct parent_map gcc_parent_map_16[] = {
 250         { P_XO, 0 },
 251         { P_GPLL0_OUT_MAIN, 1 },
 252         { P_CORE_BI_PLL_TEST_SE, 7 },
 253 };
 254
 255 static const char * const gcc_parent_names_16[] = {
 256         "cxo",
 257         "gpll0_out_main",
 258         "core_bi_pll_test_se",
 259 };
 260
 261 static struct clk_fixed_factor cxo = {
 262         .mult = 1,
 263         .div = 1,
 264         .hw.init = &(struct clk_init_data){
 265                 .name = "cxo",
 266                 .parent_names = (const char *[]){ "xo-board" },
 267                 .num_parents = 1,
 268                 .ops = &clk_fixed_factor_ops,
 269         },
 270 };
 271
 272 static struct clk_alpha_pll gpll0_sleep_clk_src = {
 273         .offset = 0x21000,
 274         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 275         .clkr = {
 276                 .enable_reg = 0x45008,
 277                 .enable_mask = BIT(23),
 278                 .enable_is_inverted = true,
 279                 .hw.init = &(struct clk_init_data){
 280                         .name = "gpll0_sleep_clk_src",
 281                         .parent_names = (const char *[]){ "cxo" },
 282                         .num_parents = 1,
 283                         .ops = &clk_alpha_pll_ops,
 284                 },
 285         },
 286 };
 287
 288 static struct clk_alpha_pll gpll0_out_main = {
 289         .offset = 0x21000,
 290         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 291         .flags = SUPPORTS_FSM_MODE,
 292         .clkr = {
 293                 .enable_reg = 0x45000,
 294                 .enable_mask = BIT(0),
 295                 .hw.init = &(struct clk_init_data){
 296                         .name = "gpll0_out_main",
 297                         .parent_names = (const char *[])
 298                                         { "cxo" },
 299                         .num_parents = 1,
 300                         .ops = &clk_alpha_pll_ops,
 301                 },
 302         },
 303 };
 304
 305 static struct clk_alpha_pll gpll0_ao_out_main = {
 306         .offset = 0x21000,
 307         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 308         .flags = SUPPORTS_FSM_MODE,
 309         .clkr = {
 310                 .enable_reg = 0x45000,
 311                 .enable_mask = BIT(0),
 312                 .hw.init = &(struct clk_init_data){
 313                         .name = "gpll0_ao_out_main",
 314                         .parent_names = (const char *[]){ "cxo" },
 315                         .num_parents = 1,
 316                         .flags = CLK_IS_CRITICAL,
 317                         .ops = &clk_alpha_pll_fixed_ops,
 318                 },
 319         },
 320 };
 321
 322 static struct clk_alpha_pll gpll1_out_main = {
 323         .offset = 0x20000,
 324         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 325         .clkr = {
 326                 .enable_reg = 0x45000,
 327                 .enable_mask = BIT(1),
 328                 .hw.init = &(struct clk_init_data){
 329                         .name = "gpll1_out_main",
 330                         .parent_names = (const char *[]){ "cxo" },
 331                         .num_parents = 1,
 332                         .ops = &clk_alpha_pll_ops,
 333                 },
 334         },
 335 };
 336
 337 /* 930MHz configuration */
 338 static const struct alpha_pll_config gpll3_config = {
 339         .l = 48,
 340         .alpha = 0x0,
 341         .alpha_en_mask = BIT(24),
 342         .post_div_mask = 0xf << 8,
 343         .post_div_val = 0x1 << 8,
 344         .vco_mask = 0x3 << 20,
 345         .main_output_mask = 0x1,
 346         .config_ctl_val = 0x4001055b,
 347 };
 348
 349 static const struct pll_vco gpll3_vco[] = {
 350         { 700000000, 1400000000, 0 },
 351 };
 352
 353 static struct clk_alpha_pll gpll3_out_main = {
 354         .offset = 0x22000,
 355         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 356         .vco_table = gpll3_vco,
 357         .num_vco = ARRAY_SIZE(gpll3_vco),
 358         .clkr = {
 359                 .hw.init = &(struct clk_init_data){
 360                         .name = "gpll3_out_main",
 361                         .parent_names = (const char *[]){ "cxo" },
 362                         .num_parents = 1,
 363                         .ops = &clk_alpha_pll_ops,
 364                 },
 365         },
 366 };
 367
 368 static struct clk_alpha_pll gpll4_out_main = {
 369         .offset = 0x24000,
 370         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 371         .clkr = {
 372                 .enable_reg = 0x45000,
 373                 .enable_mask = BIT(5),
 374                 .hw.init = &(struct clk_init_data){
 375                         .name = "gpll4_out_main",
 376                         .parent_names = (const char *[]){ "cxo" },
 377                         .num_parents = 1,
 378                         .ops = &clk_alpha_pll_ops,
 379                 },
 380         },
 381 };
 382
 383 static struct clk_pll gpll6 = {
 384         .l_reg = 0x37004,
 385         .m_reg = 0x37008,
 386         .n_reg = 0x3700C,
 387         .config_reg = 0x37014,
 388         .mode_reg = 0x37000,
 389         .status_reg = 0x3701C,
 390         .status_bit = 17,
 391         .clkr.hw.init = &(struct clk_init_data){
 392                 .name = "gpll6",
 393                 .parent_names = (const char *[]){ "cxo" },
 394                 .num_parents = 1,
 395                 .ops = &clk_pll_ops,
 396         },
 397 };
 398
 399 static struct clk_regmap gpll6_out_aux = {
 400         .enable_reg = 0x45000,
 401         .enable_mask = BIT(7),
 402         .hw.init = &(struct clk_init_data){
 403                 .name = "gpll6_out_aux",
 404                 .parent_names = (const char *[]){ "gpll6" },
 405                 .num_parents = 1,
 406                 .ops = &clk_pll_vote_ops,
 407         },
 408 };
 409
 410 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 411         F(19200000, P_XO, 1, 0, 0),
 412         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 413         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 414         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 415         { }
 416 };
 417
 418 static struct clk_rcg2 apss_ahb_clk_src = {
 419         .cmd_rcgr = 0x46000,
 420         .mnd_width = 0,
 421         .hid_width = 5,
 422         .parent_map = gcc_parent_map_0,
 423         .freq_tbl = ftbl_apss_ahb_clk_src,
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "apss_ahb_clk_src",
 426                 .parent_names = gcc_parent_names_ao_0,
 427                 .num_parents = 3,
 428                 .flags = CLK_IS_CRITICAL,
 429                 .ops = &clk_rcg2_ops,
 430         },
 431 };
 432
 433 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
 434         F(19200000, P_XO, 1, 0, 0),
 435         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 436         { }
 437 };
 438
 439 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
 440         .cmd_rcgr = 0x602c,
 441         .mnd_width = 0,
 442         .hid_width = 5,
 443         .parent_map = gcc_parent_map_0,
 444         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 445         .clkr.hw.init = &(struct clk_init_data){
 446                 .name = "blsp1_qup0_i2c_apps_clk_src",
 447                 .parent_names = gcc_parent_names_0,
 448                 .num_parents = 3,
 449                 .ops = &clk_rcg2_ops,
 450         },
 451 };
 452
 453 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
 454         F(960000, P_XO, 10, 1, 2),
 455         F(4800000, P_XO, 4, 0, 0),
 456         F(9600000, P_XO, 2, 0, 0),
 457         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 458         F(19200000, P_XO, 1, 0, 0),
 459         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 460         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 461         { }
 462 };
 463
 464 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
 465         .cmd_rcgr = 0x6034,
 466         .mnd_width = 8,
 467         .hid_width = 5,
 468         .parent_map = gcc_parent_map_0,
 469         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 470         .clkr.hw.init = &(struct clk_init_data){
 471                 .name = "blsp1_qup0_spi_apps_clk_src",
 472                 .parent_names = gcc_parent_names_0,
 473                 .num_parents = 3,
 474                 .ops = &clk_rcg2_ops,
 475         },
 476 };
 477
 478 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 479         .cmd_rcgr = 0x200c,
 480         .mnd_width = 0,
 481         .hid_width = 5,
 482         .parent_map = gcc_parent_map_0,
 483         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 484         .clkr.hw.init = &(struct clk_init_data){
 485                 .name = "blsp1_qup1_i2c_apps_clk_src",
 486                 .parent_names = gcc_parent_names_0,
 487                 .num_parents = 3,
 488                 .ops = &clk_rcg2_ops,
 489         },
 490 };
 491
 492 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 493         F(960000,   P_XO, 10, 1, 2),
 494         F(4800000,  P_XO, 4, 0, 0),
 495         F(9600000,  P_XO, 2, 0, 0),
 496         F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
 497         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 498         F(19200000, P_XO, 1, 0, 0),
 499         F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
 500         { }
 501 };
 502
 503 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 504         .cmd_rcgr = 0x2024,
 505         .mnd_width = 8,
 506         .hid_width = 5,
 507         .parent_map = gcc_parent_map_0,
 508         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "blsp1_qup1_spi_apps_clk_src",
 511                 .parent_names = gcc_parent_names_0,
 512                 .num_parents = 3,
 513                 .ops = &clk_rcg2_ops,
 514         },
 515 };
 516
 517 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 518         .cmd_rcgr = 0x3000,
 519         .mnd_width = 0,
 520         .hid_width = 5,
 521         .parent_map = gcc_parent_map_0,
 522         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 523         .clkr.hw.init = &(struct clk_init_data){
 524                 .name = "blsp1_qup2_i2c_apps_clk_src",
 525                 .parent_names = gcc_parent_names_0,
 526                 .num_parents = 3,
 527                 .ops = &clk_rcg2_ops,
 528         },
 529 };
 530
 531 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
 532         F(960000,   P_XO, 10, 1, 2),
 533         F(4800000,  P_XO, 4, 0, 0),
 534         F(9600000,  P_XO, 2, 0, 0),
 535         F(15000000, P_GPLL0_OUT_MAIN, 1,  3, 160),
 536         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 537         F(19200000, P_XO, 1, 0, 0),
 538         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 539         F(30000000, P_GPLL0_OUT_MAIN, 1,  3, 80),
 540         { }
 541 };
 542
 543 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 544         .cmd_rcgr = 0x3014,
 545         .mnd_width = 8,
 546         .hid_width = 5,
 547         .parent_map = gcc_parent_map_0,
 548         .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
 549         .clkr.hw.init = &(struct clk_init_data){
 550                 .name = "blsp1_qup2_spi_apps_clk_src",
 551                 .parent_names = gcc_parent_names_0,
 552                 .num_parents = 3,
 553                 .ops = &clk_rcg2_ops,
 554         },
 555 };
 556
 557 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 558         .cmd_rcgr = 0x4000,
 559         .mnd_width = 0,
 560         .hid_width = 5,
 561         .parent_map = gcc_parent_map_0,
 562         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 563         .clkr.hw.init = &(struct clk_init_data){
 564                 .name = "blsp1_qup3_i2c_apps_clk_src",
 565                 .parent_names = gcc_parent_names_0,
 566                 .num_parents = 3,
 567                 .ops = &clk_rcg2_ops,
 568         },
 569 };
 570
 571 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 572         .cmd_rcgr = 0x4024,
 573         .mnd_width = 8,
 574         .hid_width = 5,
 575         .parent_map = gcc_parent_map_0,
 576         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 577         .clkr.hw.init = &(struct clk_init_data){
 578                 .name = "blsp1_qup3_spi_apps_clk_src",
 579                 .parent_names = gcc_parent_names_0,
 580                 .num_parents = 3,
 581                 .ops = &clk_rcg2_ops,
 582         },
 583 };
 584
 585 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 586         .cmd_rcgr = 0x5000,
 587         .mnd_width = 0,
 588         .hid_width = 5,
 589         .parent_map = gcc_parent_map_0,
 590         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 591         .clkr.hw.init = &(struct clk_init_data){
 592                 .name = "blsp1_qup4_i2c_apps_clk_src",
 593                 .parent_names = gcc_parent_names_0,
 594                 .num_parents = 3,
 595                 .ops = &clk_rcg2_ops,
 596         },
 597 };
 598
 599 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 600         .cmd_rcgr = 0x5024,
 601         .mnd_width = 8,
 602         .hid_width = 5,
 603         .parent_map = gcc_parent_map_0,
 604         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 605         .clkr.hw.init = &(struct clk_init_data){
 606                 .name = "blsp1_qup4_spi_apps_clk_src",
 607                 .parent_names = gcc_parent_names_0,
 608                 .num_parents = 3,
 609                 .ops = &clk_rcg2_ops,
 610         },
 611 };
 612
 613 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
 614         F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
 615         F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
 616         F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
 617         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 618         F(19200000, P_XO, 1, 0, 0),
 619         F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
 620         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 621         F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
 622         F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
 623         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
 624         F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
 625         F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
 626         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
 627         F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
 628         F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
 629         F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
 630         { }
 631 };
 632
 633 static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
 634         .cmd_rcgr = 0x600c,
 635         .mnd_width = 16,
 636         .hid_width = 5,
 637         .parent_map = gcc_parent_map_0,
 638         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 639         .clkr.hw.init = &(struct clk_init_data){
 640                 .name = "blsp1_uart0_apps_clk_src",
 641                 .parent_names = gcc_parent_names_0,
 642                 .num_parents = 3,
 643                 .ops = &clk_rcg2_ops,
 644         },
 645 };
 646
 647 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 648         .cmd_rcgr = 0x2044,
 649         .mnd_width = 16,
 650         .hid_width = 5,
 651         .parent_map = gcc_parent_map_0,
 652         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 653         .clkr.hw.init = &(struct clk_init_data){
 654                 .name = "blsp1_uart1_apps_clk_src",
 655                 .parent_names = gcc_parent_names_0,
 656                 .num_parents = 3,
 657                 .ops = &clk_rcg2_ops,
 658         },
 659 };
 660
 661 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 662         .cmd_rcgr = 0x3034,
 663         .mnd_width = 16,
 664         .hid_width = 5,
 665         .parent_map = gcc_parent_map_0,
 666         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 667         .clkr.hw.init = &(struct clk_init_data){
 668                 .name = "blsp1_uart2_apps_clk_src",
 669                 .parent_names = gcc_parent_names_0,
 670                 .num_parents = 3,
 671                 .ops = &clk_rcg2_ops,
 672         },
 673 };
 674
 675 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 676         .cmd_rcgr = 0x4014,
 677         .mnd_width = 16,
 678         .hid_width = 5,
 679         .cfg_off = 0x20,
 680         .parent_map = gcc_parent_map_0,
 681         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 682         .clkr.hw.init = &(struct clk_init_data){
 683                 .name = "blsp1_uart3_apps_clk_src",
 684                 .parent_names = gcc_parent_names_0,
 685                 .num_parents = 3,
 686                 .ops = &clk_rcg2_ops,
 687         },
 688 };
 689
 690 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
 691         .cmd_rcgr = 0xc00c,
 692         .mnd_width = 0,
 693         .hid_width = 5,
 694         .parent_map = gcc_parent_map_0,
 695         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 696         .clkr.hw.init = &(struct clk_init_data){
 697                 .name = "blsp2_qup0_i2c_apps_clk_src",
 698                 .parent_names = gcc_parent_names_0,
 699                 .num_parents = 3,
 700                 .ops = &clk_rcg2_ops,
 701         },
 702 };
 703
 704 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
 705         .cmd_rcgr = 0xc024,
 706         .mnd_width = 8,
 707         .hid_width = 5,
 708         .parent_map = gcc_parent_map_0,
 709         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 710         .clkr.hw.init = &(struct clk_init_data){
 711                 .name = "blsp2_qup0_spi_apps_clk_src",
 712                 .parent_names = gcc_parent_names_0,
 713                 .num_parents = 3,
 714                 .ops = &clk_rcg2_ops,
 715         },
 716 };
 717
 718 static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
 719         .cmd_rcgr = 0xc044,
 720         .mnd_width = 16,
 721         .hid_width = 5,
 722         .parent_map = gcc_parent_map_0,
 723         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "blsp2_uart0_apps_clk_src",
 726                 .parent_names = gcc_parent_names_0,
 727                 .num_parents = 3,
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static struct clk_rcg2 byte0_clk_src = {
 733         .cmd_rcgr = 0x4d044,
 734         .mnd_width = 0,
 735         .hid_width = 5,
 736         .parent_map = gcc_parent_map_5,
 737         .clkr.hw.init = &(struct clk_init_data){
 738                 .name = "byte0_clk_src",
 739                 .parent_names = gcc_parent_names_5,
 740                 .num_parents = 4,
 741                 .flags = CLK_SET_RATE_PARENT,
 742                 .ops = &clk_byte2_ops,
 743         },
 744 };
 745
 746 static const struct freq_tbl ftbl_emac_clk_src[] = {
 747         F(5000000,   P_GPLL1_OUT_MAIN, 2, 1, 50),
 748         F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
 749         F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
 750         F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
 751         { }
 752 };
 753
 754 static struct clk_rcg2 emac_clk_src = {
 755         .cmd_rcgr = 0x4e01c,
 756         .mnd_width = 8,
 757         .hid_width = 5,
 758         .parent_map = gcc_parent_map_4,
 759         .freq_tbl = ftbl_emac_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "emac_clk_src",
 762                 .parent_names = gcc_parent_names_4,
 763                 .num_parents = 3,
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
 769         F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
 770         F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
 771         F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
 772         { }
 773 };
 774
 775 static struct clk_rcg2 emac_ptp_clk_src = {
 776         .cmd_rcgr = 0x4e014,
 777         .mnd_width = 0,
 778         .hid_width = 5,
 779         .parent_map = gcc_parent_map_4,
 780         .freq_tbl = ftbl_emac_ptp_clk_src,
 781         .clkr.hw.init = &(struct clk_init_data){
 782                 .name = "emac_ptp_clk_src",
 783                 .parent_names = gcc_parent_names_4,
 784                 .num_parents = 3,
 785                 .ops = &clk_rcg2_ops,
 786         },
 787 };
 788
 789 static const struct freq_tbl ftbl_esc0_clk_src[] = {
 790         F(19200000, P_XO, 1, 0, 0),
 791         { }
 792 };
 793
 794 static struct clk_rcg2 esc0_clk_src = {
 795         .cmd_rcgr = 0x4d05c,
 796         .mnd_width = 0,
 797         .hid_width = 5,
 798         .parent_map = gcc_parent_map_6,
 799         .freq_tbl = ftbl_esc0_clk_src,
 800         .clkr.hw.init = &(struct clk_init_data){
 801                 .name = "esc0_clk_src",
 802                 .parent_names = gcc_parent_names_6,
 803                 .num_parents = 4,
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
 809         F(19200000,  P_XO, 1, 0, 0),
 810         F(50000000,  P_GPLL0_OUT_MAIN, 16, 0, 0),
 811         F(80000000,  P_GPLL0_OUT_MAIN, 10, 0, 0),
 812         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 813         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
 814         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 815         F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
 816         F(240000000, P_GPLL6_OUT_AUX,  4.5, 0, 0),
 817         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
 818         F(270000000, P_GPLL6_OUT_AUX,  4, 0, 0),
 819         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 820         F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 821         F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 822         F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 823         F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 824         F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 825         { }
 826 };
 827
 828 static struct clk_rcg2 gfx3d_clk_src = {
 829         .cmd_rcgr = 0x59000,
 830         .mnd_width = 0,
 831         .hid_width = 5,
 832         .parent_map = gcc_parent_map_7,
 833         .freq_tbl = ftbl_gfx3d_clk_src,
 834         .clkr.hw.init = &(struct clk_init_data){
 835                 .name = "gfx3d_clk_src",
 836                 .parent_names = gcc_parent_names_7,
 837                 .num_parents = 6,
 838                 .ops = &clk_rcg2_ops,
 839         },
 840 };
 841
 842 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 843         F(19200000, P_XO, 1, 0, 0),
 844         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 845         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 846         { }
 847 };
 848
 849 static struct clk_rcg2 gp1_clk_src = {
 850         .cmd_rcgr = 0x8004,
 851         .mnd_width = 8,
 852         .hid_width = 5,
 853         .parent_map = gcc_parent_map_2,
 854         .freq_tbl = ftbl_gp1_clk_src,
 855         .clkr.hw.init = &(struct clk_init_data){
 856                 .name = "gp1_clk_src",
 857                 .parent_names = gcc_parent_names_2,
 858                 .num_parents = 4,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static struct clk_rcg2 gp2_clk_src = {
 864         .cmd_rcgr = 0x9004,
 865         .mnd_width = 8,
 866         .hid_width = 5,
 867         .parent_map = gcc_parent_map_2,
 868         .freq_tbl = ftbl_gp1_clk_src,
 869         .clkr.hw.init = &(struct clk_init_data){
 870                 .name = "gp2_clk_src",
 871                 .parent_names = gcc_parent_names_2,
 872                 .num_parents = 4,
 873                 .ops = &clk_rcg2_ops,
 874         },
 875 };
 876
 877 static struct clk_rcg2 gp3_clk_src = {
 878         .cmd_rcgr = 0xa004,
 879         .mnd_width = 8,
 880         .hid_width = 5,
 881         .parent_map = gcc_parent_map_2,
 882         .freq_tbl = ftbl_gp1_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "gp3_clk_src",
 885                 .parent_names = gcc_parent_names_2,
 886                 .num_parents = 4,
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct clk_rcg2 hdmi_app_clk_src = {
 892         .cmd_rcgr = 0x4d0e4,
 893         .mnd_width = 0,
 894         .hid_width = 5,
 895         .parent_map = gcc_parent_map_1,
 896         .freq_tbl = ftbl_esc0_clk_src,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "hdmi_app_clk_src",
 899                 .parent_names = gcc_parent_names_1,
 900                 .num_parents = 2,
 901                 .ops = &clk_rcg2_ops,
 902         },
 903 };
 904
 905 static struct clk_rcg2 hdmi_pclk_clk_src = {
 906         .cmd_rcgr = 0x4d0dc,
 907         .mnd_width = 0,
 908         .hid_width = 5,
 909         .parent_map = gcc_parent_map_8,
 910         .freq_tbl = ftbl_esc0_clk_src,
 911         .clkr.hw.init = &(struct clk_init_data){
 912                 .name = "hdmi_pclk_clk_src",
 913                 .parent_names = gcc_parent_names_8,
 914                 .num_parents = 3,
 915                 .ops = &clk_rcg2_ops,
 916         },
 917 };
 918
 919 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 920         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 921         F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 922         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 923         F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
 924         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
 925         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 926         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 927         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
 928         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 929         { }
 930 };
 931
 932 static struct clk_rcg2 mdp_clk_src = {
 933         .cmd_rcgr = 0x4d014,
 934         .mnd_width = 0,
 935         .hid_width = 5,
 936         .parent_map = gcc_parent_map_9,
 937         .freq_tbl = ftbl_mdp_clk_src,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "mdp_clk_src",
 940                 .parent_names = gcc_parent_names_9,
 941                 .num_parents = 5,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 947         F(1200000, P_XO, 16, 0, 0),
 948         { }
 949 };
 950
 951 static struct clk_rcg2 pcie_0_aux_clk_src = {
 952         .cmd_rcgr = 0x3e024,
 953         .mnd_width = 16,
 954         .hid_width = 5,
 955         .parent_map = gcc_parent_map_10,
 956         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 957         .clkr.hw.init = &(struct clk_init_data){
 958                 .name = "pcie_0_aux_clk_src",
 959                 .parent_names = gcc_parent_names_10,
 960                 .num_parents = 3,
 961                 .ops = &clk_rcg2_ops,
 962         },
 963 };
 964
 965 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
 966         F(19200000, P_XO, 1, 0, 0),
 967         F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
 968         F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
 969         { }
 970 };
 971
 972 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 973         .cmd_rcgr = 0x3e01c,
 974         .mnd_width = 0,
 975         .hid_width = 5,
 976         .parent_map = gcc_parent_map_11,
 977         .freq_tbl = ftbl_pcie_0_pipe_clk_src,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "pcie_0_pipe_clk_src",
 980                 .parent_names = gcc_parent_names_11,
 981                 .num_parents = 3,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static struct clk_rcg2 pclk0_clk_src = {
 987         .cmd_rcgr = 0x4d000,
 988         .mnd_width = 8,
 989         .hid_width = 5,
 990         .parent_map = gcc_parent_map_12,
 991         .clkr.hw.init = &(struct clk_init_data){
 992                 .name = "pclk0_clk_src",
 993                 .parent_names = gcc_parent_names_12,
 994                 .num_parents = 4,
 995                 .flags = CLK_SET_RATE_PARENT,
 996                 .ops = &clk_pixel_ops,
 997         },
 998 };
 999
1000 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1001         F(19200000, P_XO, 1, 0, 0),
1002         F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1003         { }
1004 };
1005
1006 static struct clk_rcg2 pdm2_clk_src = {
1007         .cmd_rcgr = 0x44010,
1008         .mnd_width = 0,
1009         .hid_width = 5,
1010         .parent_map = gcc_parent_map_0,
1011         .freq_tbl = ftbl_pdm2_clk_src,
1012         .clkr.hw.init = &(struct clk_init_data){
1013                 .name = "pdm2_clk_src",
1014                 .parent_names = gcc_parent_names_0,
1015                 .num_parents = 3,
1016                 .ops = &clk_rcg2_ops,
1017         },
1018 };
1019
1020 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1021         F(144000, P_XO, 16, 3, 25),
1022         F(400000, P_XO, 12, 1, 4),
1023         F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1024         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1025         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1026         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1027         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1028         F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1029         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1030         F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1031         { }
1032 };
1033
1034 static struct clk_rcg2 sdcc1_apps_clk_src = {
1035         .cmd_rcgr = 0x42004,
1036         .mnd_width = 8,
1037         .hid_width = 5,
1038         .parent_map = gcc_parent_map_13,
1039         .freq_tbl = ftbl_sdcc1_apps_clk_src,
1040         .clkr.hw.init = &(struct clk_init_data){
1041                 .name = "sdcc1_apps_clk_src",
1042                 .parent_names = gcc_parent_names_13,
1043                 .num_parents = 5,
1044                 .ops = &clk_rcg2_floor_ops,
1045         },
1046 };
1047
1048 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1049         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1050         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1051         { }
1052 };
1053
1054 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1055         .cmd_rcgr = 0x5d000,
1056         .mnd_width = 8,
1057         .hid_width = 5,
1058         .parent_map = gcc_parent_map_3,
1059         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1060         .clkr.hw.init = &(struct clk_init_data){
1061                 .name = "sdcc1_ice_core_clk_src",
1062                 .parent_names = gcc_parent_names_3,
1063                 .num_parents = 4,
1064                 .ops = &clk_rcg2_ops,
1065         },
1066 };
1067
1068 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1069         F(144000, P_XO, 16, 3, 25),
1070         F(400000, P_XO, 12, 1, 4),
1071         F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1072         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1073         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1074         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1075         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1076         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1077         { }
1078 };
1079
1080 static struct clk_rcg2 sdcc2_apps_clk_src = {
1081         .cmd_rcgr = 0x43004,
1082         .mnd_width = 8,
1083         .hid_width = 5,
1084         .parent_map = gcc_parent_map_14,
1085         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1086         .clkr.hw.init = &(struct clk_init_data){
1087                 .name = "sdcc2_apps_clk_src",
1088                 .parent_names = gcc_parent_names_14,
1089                 .num_parents = 4,
1090                 .ops = &clk_rcg2_floor_ops,
1091         },
1092 };
1093
1094 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1095         .cmd_rcgr = 0x41048,
1096         .mnd_width = 0,
1097         .hid_width = 5,
1098         .parent_map = gcc_parent_map_1,
1099         .freq_tbl = ftbl_esc0_clk_src,
1100         .clkr.hw.init = &(struct clk_init_data){
1101                 .name = "usb20_mock_utmi_clk_src",
1102                 .parent_names = gcc_parent_names_1,
1103                 .num_parents = 2,
1104                 .ops = &clk_rcg2_ops,
1105         },
1106 };
1107
1108 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1109         F(19200000, P_XO, 1, 0, 0),
1110         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1111         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1112         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1113         { }
1114 };
1115
1116 static struct clk_rcg2 usb30_master_clk_src = {
1117         .cmd_rcgr = 0x39028,
1118         .mnd_width = 8,
1119         .hid_width = 5,
1120         .parent_map = gcc_parent_map_0,
1121         .freq_tbl = ftbl_usb30_master_clk_src,
1122         .clkr.hw.init = &(struct clk_init_data){
1123                 .name = "usb30_master_clk_src",
1124                 .parent_names = gcc_parent_names_0,
1125                 .num_parents = 3,
1126                 .ops = &clk_rcg2_ops,
1127         },
1128 };
1129
1130 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1131         .cmd_rcgr = 0x3901c,
1132         .mnd_width = 0,
1133         .hid_width = 5,
1134         .parent_map = gcc_parent_map_1,
1135         .freq_tbl = ftbl_esc0_clk_src,
1136         .clkr.hw.init = &(struct clk_init_data){
1137                 .name = "usb30_mock_utmi_clk_src",
1138                 .parent_names = gcc_parent_names_1,
1139                 .num_parents = 2,
1140                 .ops = &clk_rcg2_ops,
1141         },
1142 };
1143
1144 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1145         .cmd_rcgr = 0x3903c,
1146         .mnd_width = 0,
1147         .hid_width = 5,
1148         .parent_map = gcc_parent_map_1,
1149         .freq_tbl = ftbl_pcie_0_aux_clk_src,
1150         .clkr.hw.init = &(struct clk_init_data){
1151                 .name = "usb3_phy_aux_clk_src",
1152                 .parent_names = gcc_parent_names_1,
1153                 .num_parents = 2,
1154                 .ops = &clk_rcg2_ops,
1155         },
1156 };
1157
1158 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1159         F(19200000, P_XO, 1, 0, 0),
1160         F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1161         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1162         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1163         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1164         { }
1165 };
1166
1167 static struct clk_rcg2 usb_hs_system_clk_src = {
1168         .cmd_rcgr = 0x41010,
1169         .mnd_width = 0,
1170         .hid_width = 5,
1171         .parent_map = gcc_parent_map_3,
1172         .freq_tbl = ftbl_usb_hs_system_clk_src,
1173         .clkr.hw.init = &(struct clk_init_data){
1174                 .name = "usb_hs_system_clk_src",
1175                 .parent_names = gcc_parent_names_3,
1176                 .num_parents = 4,
1177                 .ops = &clk_rcg2_ops,
1178         },
1179 };
1180
1181 static struct clk_rcg2 vsync_clk_src = {
1182         .cmd_rcgr = 0x4d02c,
1183         .mnd_width = 0,
1184         .hid_width = 5,
1185         .parent_map = gcc_parent_map_15,
1186         .freq_tbl = ftbl_esc0_clk_src,
1187         .clkr.hw.init = &(struct clk_init_data){
1188                 .name = "vsync_clk_src",
1189                 .parent_names = gcc_parent_names_15,
1190                 .num_parents = 3,
1191                 .ops = &clk_rcg2_ops,
1192         },
1193 };
1194
1195 static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
1196         F(19200000, P_XO, 1, 0, 0),
1197         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1198         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1199         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1200         { }
1201 };
1202
1203 static struct clk_rcg2 cdsp_bimc_clk_src = {
1204         .cmd_rcgr = 0x5e010,
1205         .mnd_width = 0,
1206         .hid_width = 5,
1207         .parent_map = gcc_parent_map_16,
1208         .freq_tbl = ftbl_cdsp_bimc_clk_src,
1209         .clkr.hw.init = &(struct clk_init_data) {
1210                 .name = "cdsp_bimc_clk_src",
1211                 .parent_names = gcc_parent_names_16,
1212                 .num_parents = 4,
1213                 .ops = &clk_rcg2_ops,
1214         },
1215 };
1216
1217 static struct clk_branch gcc_apss_ahb_clk = {
1218         .halt_reg = 0x4601c,
1219         .halt_check = BRANCH_HALT_VOTED,
1220         .clkr = {
1221                 .enable_reg = 0x45004,
1222                 .enable_mask = BIT(14),
1223                 .hw.init = &(struct clk_init_data){
1224                         .name = "gcc_apss_ahb_clk",
1225                         .parent_names = (const char *[]){
1226                                 "apss_ahb_clk_src",
1227                         },
1228                         .num_parents = 1,
1229                         .flags = CLK_SET_RATE_PARENT,
1230                         .ops = &clk_branch2_ops,
1231                 },
1232         },
1233 };
1234
1235 static struct clk_branch gcc_apss_tcu_clk = {
1236         .halt_reg = 0x5b004,
1237         .halt_check = BRANCH_VOTED,
1238         .clkr = {
1239                 .enable_reg = 0x4500c,
1240                 .enable_mask = BIT(1),
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "gcc_apss_tcu_clk",
1243                         .ops = &clk_branch2_ops,
1244                 },
1245         },
1246 };
1247
1248 static struct clk_branch gcc_bimc_gfx_clk = {
1249         .halt_reg = 0x59034,
1250         .halt_check = BRANCH_HALT,
1251         .clkr = {
1252                 .enable_reg = 0x59034,
1253                 .enable_mask = BIT(0),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gcc_bimc_gfx_clk",
1256                         .ops = &clk_branch2_ops,
1257                         .parent_names = (const char *[]){
1258                                 "gcc_apss_tcu_clk",
1259                         },
1260
1261                 },
1262         },
1263 };
1264
1265 static struct clk_branch gcc_bimc_gpu_clk = {
1266         .halt_reg = 0x59030,
1267         .halt_check = BRANCH_HALT,
1268         .clkr = {
1269                 .enable_reg = 0x59030,
1270                 .enable_mask = BIT(0),
1271                 .hw.init = &(struct clk_init_data){
1272                         .name = "gcc_bimc_gpu_clk",
1273                         .ops = &clk_branch2_ops,
1274                 },
1275         },
1276 };
1277
1278 static struct clk_branch gcc_bimc_cdsp_clk = {
1279         .halt_reg = 0x31030,
1280         .halt_check = BRANCH_HALT,
1281         .clkr = {
1282                 .enable_reg = 0x31030,
1283                 .enable_mask = BIT(0),
1284                 .hw.init = &(struct clk_init_data) {
1285                         .name = "gcc_bimc_cdsp_clk",
1286                         .parent_names = (const char *[]) {
1287                                 "cdsp_bimc_clk_src",
1288                         },
1289                         .num_parents = 1,
1290                         .flags = CLK_SET_RATE_PARENT,
1291                         .ops = &clk_branch2_ops,
1292                 },
1293         },
1294 };
1295
1296 static struct clk_branch gcc_bimc_mdss_clk = {
1297         .halt_reg = 0x31038,
1298         .halt_check = BRANCH_HALT,
1299         .clkr = {
1300                 .enable_reg = 0x31038,
1301                 .enable_mask = BIT(0),
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "gcc_bimc_mdss_clk",
1304                         .ops = &clk_branch2_ops,
1305                 },
1306         },
1307 };
1308
1309 static struct clk_branch gcc_blsp1_ahb_clk = {
1310         .halt_reg = 0x1008,
1311         .halt_check = BRANCH_HALT_VOTED,
1312         .clkr = {
1313                 .enable_reg = 0x45004,
1314                 .enable_mask = BIT(10),
1315                 .hw.init = &(struct clk_init_data){
1316                         .name = "gcc_blsp1_ahb_clk",
1317                         .ops = &clk_branch2_ops,
1318                 },
1319         },
1320 };
1321
1322 static struct clk_branch gcc_dcc_clk = {
1323         .halt_reg = 0x77004,
1324         .halt_check = BRANCH_HALT,
1325         .clkr = {
1326                 .enable_reg = 0x77004,
1327                 .enable_mask = BIT(0),
1328                 .hw.init = &(struct clk_init_data){
1329                         .name = "gcc_dcc_clk",
1330                         .ops = &clk_branch2_ops,
1331                 },
1332         },
1333 };
1334
1335 static struct clk_branch gcc_dcc_xo_clk = {
1336         .halt_reg = 0x77008,
1337         .halt_check = BRANCH_HALT,
1338         .clkr = {
1339                 .enable_reg = 0x77008,
1340                 .enable_mask = BIT(0),
1341                 .hw.init = &(struct clk_init_data){
1342                         .name = "gcc_dcc_xo_clk",
1343                         .ops = &clk_branch2_ops,
1344                 },
1345         },
1346 };
1347
1348 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1349         .halt_reg = 0x6028,
1350         .halt_check = BRANCH_HALT,
1351         .clkr = {
1352                 .enable_reg = 0x6028,
1353                 .enable_mask = BIT(0),
1354                 .hw.init = &(struct clk_init_data){
1355                         .name = "gcc_blsp1_qup0_i2c_apps_clk",
1356                         .parent_names = (const char *[]){
1357                                 "blsp1_qup0_i2c_apps_clk_src",
1358                         },
1359                         .num_parents = 1,
1360                         .flags = CLK_SET_RATE_PARENT,
1361                         .ops = &clk_branch2_ops,
1362                 },
1363         },
1364 };
1365
1366 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1367         .halt_reg = 0x6024,
1368         .halt_check = BRANCH_HALT,
1369         .clkr = {
1370                 .enable_reg = 0x6024,
1371                 .enable_mask = BIT(0),
1372                 .hw.init = &(struct clk_init_data){
1373                         .name = "gcc_blsp1_qup0_spi_apps_clk",
1374                         .parent_names = (const char *[]){
1375                                 "blsp1_qup0_spi_apps_clk_src",
1376                         },
1377                         .num_parents = 1,
1378                         .flags = CLK_SET_RATE_PARENT,
1379                         .ops = &clk_branch2_ops,
1380                 },
1381         },
1382 };
1383
1384 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1385         .halt_reg = 0x2008,
1386         .halt_check = BRANCH_HALT,
1387         .clkr = {
1388                 .enable_reg = 0x2008,
1389                 .enable_mask = BIT(0),
1390                 .hw.init = &(struct clk_init_data){
1391                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1392                         .parent_names = (const char *[]){
1393                                 "blsp1_qup1_i2c_apps_clk_src",
1394                         },
1395                         .num_parents = 1,
1396                         .flags = CLK_SET_RATE_PARENT,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1403         .halt_reg = 0x2004,
1404         .halt_check = BRANCH_HALT,
1405         .clkr = {
1406                 .enable_reg = 0x2004,
1407                 .enable_mask = BIT(0),
1408                 .hw.init = &(struct clk_init_data){
1409                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1410                         .parent_names = (const char *[]){
1411                                 "blsp1_qup1_spi_apps_clk_src",
1412                         },
1413                         .num_parents = 1,
1414                         .flags = CLK_SET_RATE_PARENT,
1415                         .ops = &clk_branch2_ops,
1416                 },
1417         },
1418 };
1419
1420 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1421         .halt_reg = 0x3010,
1422         .halt_check = BRANCH_HALT,
1423         .clkr = {
1424                 .enable_reg = 0x3010,
1425                 .enable_mask = BIT(0),
1426                 .hw.init = &(struct clk_init_data){
1427                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1428                         .parent_names = (const char *[]){
1429                                 "blsp1_qup2_i2c_apps_clk_src",
1430                         },
1431                         .num_parents = 1,
1432                         .flags = CLK_SET_RATE_PARENT,
1433                         .ops = &clk_branch2_ops,
1434                 },
1435         },
1436 };
1437
1438 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1439         .halt_reg = 0x300c,
1440         .halt_check = BRANCH_HALT,
1441         .clkr = {
1442                 .enable_reg = 0x300c,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1446                         .parent_names = (const char *[]){
1447                                 "blsp1_qup2_spi_apps_clk_src",
1448                         },
1449                         .num_parents = 1,
1450                         .flags = CLK_SET_RATE_PARENT,
1451                         .ops = &clk_branch2_ops,
1452                 },
1453         },
1454 };
1455
1456 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1457         .halt_reg = 0x4020,
1458         .halt_check = BRANCH_HALT,
1459         .clkr = {
1460                 .enable_reg = 0x4020,
1461                 .enable_mask = BIT(0),
1462                 .hw.init = &(struct clk_init_data){
1463                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1464                         .parent_names = (const char *[]){
1465                                 "blsp1_qup3_i2c_apps_clk_src",
1466                         },
1467                         .num_parents = 1,
1468                         .flags = CLK_SET_RATE_PARENT,
1469                         .ops = &clk_branch2_ops,
1470                 },
1471         },
1472 };
1473
1474 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1475         .halt_reg = 0x401c,
1476         .halt_check = BRANCH_HALT,
1477         .clkr = {
1478                 .enable_reg = 0x401c,
1479                 .enable_mask = BIT(0),
1480                 .hw.init = &(struct clk_init_data){
1481                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1482                         .parent_names = (const char *[]){
1483                                 "blsp1_qup3_spi_apps_clk_src",
1484                         },
1485                         .num_parents = 1,
1486                         .flags = CLK_SET_RATE_PARENT,
1487                         .ops = &clk_branch2_ops,
1488                 },
1489         },
1490 };
1491
1492 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1493         .halt_reg = 0x5020,
1494         .halt_check = BRANCH_HALT,
1495         .clkr = {
1496                 .enable_reg = 0x5020,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1500                         .parent_names = (const char *[]){
1501                                 "blsp1_qup4_i2c_apps_clk_src",
1502                         },
1503                         .num_parents = 1,
1504                         .flags = CLK_SET_RATE_PARENT,
1505                         .ops = &clk_branch2_ops,
1506                 },
1507         },
1508 };
1509
1510 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1511         .halt_reg = 0x501c,
1512         .halt_check = BRANCH_HALT,
1513         .clkr = {
1514                 .enable_reg = 0x501c,
1515                 .enable_mask = BIT(0),
1516                 .hw.init = &(struct clk_init_data){
1517                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1518                         .parent_names = (const char *[]){
1519                                 "blsp1_qup4_spi_apps_clk_src",
1520                         },
1521                         .num_parents = 1,
1522                         .flags = CLK_SET_RATE_PARENT,
1523                         .ops = &clk_branch2_ops,
1524                 },
1525         },
1526 };
1527
1528 static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1529         .halt_reg = 0x6004,
1530         .halt_check = BRANCH_HALT,
1531         .clkr = {
1532                 .enable_reg = 0x6004,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "gcc_blsp1_uart0_apps_clk",
1536                         .parent_names = (const char *[]){
1537                                 "blsp1_uart0_apps_clk_src",
1538                         },
1539                         .num_parents = 1,
1540                         .flags = CLK_SET_RATE_PARENT,
1541                         .ops = &clk_branch2_ops,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1547         .halt_reg = 0x203c,
1548         .halt_check = BRANCH_HALT,
1549         .clkr = {
1550                 .enable_reg = 0x203c,
1551                 .enable_mask = BIT(0),
1552                 .hw.init = &(struct clk_init_data){
1553                         .name = "gcc_blsp1_uart1_apps_clk",
1554                         .parent_names = (const char *[]){
1555                                 "blsp1_uart1_apps_clk_src",
1556                         },
1557                         .num_parents = 1,
1558                         .flags = CLK_SET_RATE_PARENT,
1559                         .ops = &clk_branch2_ops,
1560                 },
1561         },
1562 };
1563
1564 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1565         .halt_reg = 0x302c,
1566         .halt_check = BRANCH_HALT,
1567         .clkr = {
1568                 .enable_reg = 0x302c,
1569                 .enable_mask = BIT(0),
1570                 .hw.init = &(struct clk_init_data){
1571                         .name = "gcc_blsp1_uart2_apps_clk",
1572                         .parent_names = (const char *[]){
1573                                 "blsp1_uart2_apps_clk_src",
1574                         },
1575                         .num_parents = 1,
1576                         .flags = CLK_SET_RATE_PARENT,
1577                         .ops = &clk_branch2_ops,
1578                 },
1579         },
1580 };
1581
1582 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1583         .halt_reg = 0x400c,
1584         .halt_check = BRANCH_HALT,
1585         .clkr = {
1586                 .enable_reg = 0x400c,
1587                 .enable_mask = BIT(0),
1588                 .hw.init = &(struct clk_init_data){
1589                         .name = "gcc_blsp1_uart3_apps_clk",
1590                         .parent_names = (const char *[]){
1591                                 "blsp1_uart3_apps_clk_src",
1592                         },
1593                         .num_parents = 1,
1594                         .flags = CLK_SET_RATE_PARENT,
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_blsp2_ahb_clk = {
1601         .halt_reg = 0xb008,
1602         .halt_check = BRANCH_HALT_VOTED,
1603         .clkr = {
1604                 .enable_reg = 0x45004,
1605                 .enable_mask = BIT(20),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "gcc_blsp2_ahb_clk",
1608                         .ops = &clk_branch2_ops,
1609                 },
1610         },
1611 };
1612
1613 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1614         .halt_reg = 0xc008,
1615         .halt_check = BRANCH_HALT,
1616         .clkr = {
1617                 .enable_reg = 0xc008,
1618                 .enable_mask = BIT(0),
1619                 .hw.init = &(struct clk_init_data){
1620                         .name = "gcc_blsp2_qup0_i2c_apps_clk",
1621                         .parent_names = (const char *[]){
1622                                 "blsp2_qup0_i2c_apps_clk_src",
1623                         },
1624                         .num_parents = 1,
1625                         .flags = CLK_SET_RATE_PARENT,
1626                         .ops = &clk_branch2_ops,
1627                 },
1628         },
1629 };
1630
1631 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1632         .halt_reg = 0xc004,
1633         .halt_check = BRANCH_HALT,
1634         .clkr = {
1635                 .enable_reg = 0xc004,
1636                 .enable_mask = BIT(0),
1637                 .hw.init = &(struct clk_init_data){
1638                         .name = "gcc_blsp2_qup0_spi_apps_clk",
1639                         .parent_names = (const char *[]){
1640                                 "blsp2_qup0_spi_apps_clk_src",
1641                         },
1642                         .num_parents = 1,
1643                         .flags = CLK_SET_RATE_PARENT,
1644                         .ops = &clk_branch2_ops,
1645                 },
1646         },
1647 };
1648
1649 static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1650         .halt_reg = 0xc03c,
1651         .halt_check = BRANCH_HALT,
1652         .clkr = {
1653                 .enable_reg = 0xc03c,
1654                 .enable_mask = BIT(0),
1655                 .hw.init = &(struct clk_init_data){
1656                         .name = "gcc_blsp2_uart0_apps_clk",
1657                         .parent_names = (const char *[]){
1658                                 "blsp2_uart0_apps_clk_src",
1659                         },
1660                         .num_parents = 1,
1661                         .flags = CLK_SET_RATE_PARENT,
1662                         .ops = &clk_branch2_ops,
1663                 },
1664         },
1665 };
1666
1667 static struct clk_branch gcc_boot_rom_ahb_clk = {
1668         .halt_reg = 0x1300c,
1669         .halt_check = BRANCH_HALT_VOTED,
1670         .clkr = {
1671                 .enable_reg = 0x45004,
1672                 .enable_mask = BIT(7),
1673                 .hw.init = &(struct clk_init_data){
1674                         .name = "gcc_boot_rom_ahb_clk",
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch gcc_crypto_ahb_clk = {
1681         .halt_reg = 0x16024,
1682         .halt_check = BRANCH_VOTED,
1683         .clkr = {
1684                 .enable_reg = 0x45004,
1685                 .enable_mask = BIT(0),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "gcc_crypto_ahb_clk",
1688                         .ops = &clk_branch2_ops,
1689                 },
1690         },
1691 };
1692
1693 static struct clk_branch gcc_crypto_axi_clk = {
1694         .halt_reg = 0x16020,
1695         .halt_check = BRANCH_VOTED,
1696         .clkr = {
1697                 .enable_reg = 0x45004,
1698                 .enable_mask = BIT(1),
1699                 .hw.init = &(struct clk_init_data){
1700                         .name = "gcc_crypto_axi_clk",
1701                         .ops = &clk_branch2_ops,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch gcc_crypto_clk = {
1707         .halt_reg = 0x1601c,
1708         .halt_check = BRANCH_VOTED,
1709         .clkr = {
1710                 .enable_reg = 0x45004,
1711                 .enable_mask = BIT(2),
1712                 .hw.init = &(struct clk_init_data){
1713                         .name = "gcc_crypto_clk",
1714                         .ops = &clk_branch2_ops,
1715                 },
1716         },
1717 };
1718
1719 static struct clk_branch gcc_eth_axi_clk = {
1720         .halt_reg = 0x4e010,
1721         .halt_check = BRANCH_HALT,
1722         .clkr = {
1723                 .enable_reg = 0x4e010,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_eth_axi_clk",
1727                         .ops = &clk_branch2_ops,
1728                 },
1729         },
1730 };
1731
1732 static struct clk_branch gcc_eth_ptp_clk = {
1733         .halt_reg = 0x4e004,
1734         .halt_check = BRANCH_HALT,
1735         .clkr = {
1736                 .enable_reg = 0x4e004,
1737                 .enable_mask = BIT(0),
1738                 .hw.init = &(struct clk_init_data){
1739                         .name = "gcc_eth_ptp_clk",
1740                         .parent_names = (const char *[]){
1741                                 "emac_ptp_clk_src",
1742                         },
1743                         .num_parents = 1,
1744                         .flags = CLK_SET_RATE_PARENT,
1745                         .ops = &clk_branch2_ops,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_branch gcc_eth_rgmii_clk = {
1751         .halt_reg = 0x4e008,
1752         .halt_check = BRANCH_HALT,
1753         .clkr = {
1754                 .enable_reg = 0x4e008,
1755                 .enable_mask = BIT(0),
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "gcc_eth_rgmii_clk",
1758                         .parent_names = (const char *[]){
1759                                 "emac_clk_src",
1760                         },
1761                         .num_parents = 1,
1762                         .flags = CLK_SET_RATE_PARENT,
1763                         .ops = &clk_branch2_ops,
1764                 },
1765         },
1766 };
1767
1768 static struct clk_branch gcc_eth_slave_ahb_clk = {
1769         .halt_reg = 0x4e00c,
1770         .halt_check = BRANCH_HALT,
1771         .clkr = {
1772                 .enable_reg = 0x4e00c,
1773                 .enable_mask = BIT(0),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "gcc_eth_slave_ahb_clk",
1776                         .ops = &clk_branch2_ops,
1777                 },
1778         },
1779 };
1780
1781 static struct clk_branch gcc_geni_ir_s_clk = {
1782         .halt_reg = 0xf008,
1783         .halt_check = BRANCH_HALT,
1784         .clkr = {
1785                 .enable_reg = 0xf008,
1786                 .enable_mask = BIT(0),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "gcc_geni_ir_s_clk",
1789                         .ops = &clk_branch2_ops,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch gcc_geni_ir_h_clk = {
1795         .halt_reg = 0xf004,
1796         .halt_check = BRANCH_HALT,
1797         .clkr = {
1798                 .enable_reg = 0xf004,
1799                 .enable_mask = BIT(0),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "gcc_geni_ir_h_clk",
1802                         .ops = &clk_branch2_ops,
1803                 },
1804         },
1805 };
1806
1807 static struct clk_branch gcc_gfx_tcu_clk = {
1808         .halt_reg = 0x12020,
1809         .halt_check = BRANCH_VOTED,
1810         .clkr = {
1811                 .enable_reg = 0x4500C,
1812                 .enable_mask = BIT(2),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "gcc_gfx_tcu_clk",
1815                         .ops = &clk_branch2_ops,
1816                 },
1817         },
1818 };
1819
1820 static struct clk_branch gcc_gfx_tbu_clk = {
1821         .halt_reg = 0x12010,
1822         .halt_check = BRANCH_VOTED,
1823         .clkr = {
1824                 .enable_reg = 0x4500C,
1825                 .enable_mask = BIT(3),
1826                 .hw.init = &(struct clk_init_data){
1827                         .name = "gcc_gfx_tbu_clk",
1828                         .ops = &clk_branch2_ops,
1829                 },
1830         },
1831 };
1832
1833 static struct clk_branch gcc_cdsp_tbu_clk = {
1834         .halt_reg = 0x1203c,
1835         .halt_check = BRANCH_VOTED,
1836         .clkr = {
1837                 .enable_reg = 0x13020,
1838                 .enable_mask = BIT(9),
1839                 .hw.init = &(struct clk_init_data) {
1840                         .name = "gcc_cdsp_tbu_clk",
1841                         .parent_names = (const char *[]) {
1842                                 "cdsp_bimc_clk_src",
1843                         },
1844                         .num_parents = 1,
1845                         .flags = CLK_SET_RATE_PARENT,
1846                         .ops = &clk_branch2_ops,
1847                 },
1848         },
1849 };
1850
1851 static struct clk_branch gcc_gp1_clk = {
1852         .halt_reg = 0x8000,
1853         .halt_check = BRANCH_HALT,
1854         .clkr = {
1855                 .enable_reg = 0x8000,
1856                 .enable_mask = BIT(0),
1857                 .hw.init = &(struct clk_init_data){
1858                         .name = "gcc_gp1_clk",
1859                         .parent_names = (const char *[]){
1860                                 "gp1_clk_src",
1861                         },
1862                         .num_parents = 1,
1863                         .flags = CLK_SET_RATE_PARENT,
1864                         .ops = &clk_branch2_ops,
1865                 },
1866         },
1867 };
1868
1869 static struct clk_branch gcc_gp2_clk = {
1870         .halt_reg = 0x9000,
1871         .halt_check = BRANCH_HALT,
1872         .clkr = {
1873                 .enable_reg = 0x9000,
1874                 .enable_mask = BIT(0),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "gcc_gp2_clk",
1877                         .parent_names = (const char *[]){
1878                                 "gp2_clk_src",
1879                         },
1880                         .num_parents = 1,
1881                         .flags = CLK_SET_RATE_PARENT,
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_gp3_clk = {
1888         .halt_reg = 0xa000,
1889         .halt_check = BRANCH_HALT,
1890         .clkr = {
1891                 .enable_reg = 0xa000,
1892                 .enable_mask = BIT(0),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "gcc_gp3_clk",
1895                         .parent_names = (const char *[]){
1896                                 "gp3_clk_src",
1897                         },
1898                         .num_parents = 1,
1899                         .flags = CLK_SET_RATE_PARENT,
1900                         .ops = &clk_branch2_ops,
1901                 },
1902         },
1903 };
1904
1905 static struct clk_branch gcc_gtcu_ahb_clk = {
1906         .halt_reg = 0x12044,
1907         .halt_check = BRANCH_VOTED,
1908         .clkr = {
1909                 .enable_reg = 0x4500c,
1910                 .enable_mask = BIT(13),
1911                 .hw.init = &(struct clk_init_data){
1912                         .name = "gcc_gtcu_ahb_clk",
1913                         .ops = &clk_branch2_ops,
1914                 },
1915         },
1916 };
1917
1918 static struct clk_branch gcc_mdp_tbu_clk = {
1919         .halt_reg = 0x1201c,
1920         .halt_check = BRANCH_VOTED,
1921         .clkr = {
1922                 .enable_reg = 0x4500c,
1923                 .enable_mask = BIT(4),
1924                 .hw.init = &(struct clk_init_data){
1925                         .name = "gcc_mdp_tbu_clk",
1926                         .ops = &clk_branch2_ops,
1927                 },
1928         },
1929 };
1930
1931 static struct clk_branch gcc_mdss_ahb_clk = {
1932         .halt_reg = 0x4d07c,
1933         .halt_check = BRANCH_HALT,
1934         .clkr = {
1935                 .enable_reg = 0x4d07c,
1936                 .enable_mask = BIT(0),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "gcc_mdss_ahb_clk",
1939                         .ops = &clk_branch2_ops,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_branch gcc_mdss_axi_clk = {
1945         .halt_reg = 0x4d080,
1946         .halt_check = BRANCH_HALT,
1947         .clkr = {
1948                 .enable_reg = 0x4d080,
1949                 .enable_mask = BIT(0),
1950                 .hw.init = &(struct clk_init_data){
1951                         .name = "gcc_mdss_axi_clk",
1952                         .ops = &clk_branch2_ops,
1953                 },
1954         },
1955 };
1956
1957 static struct clk_branch gcc_mdss_byte0_clk = {
1958         .halt_reg = 0x4d094,
1959         .halt_check = BRANCH_HALT,
1960         .clkr = {
1961                 .enable_reg = 0x4d094,
1962                 .enable_mask = BIT(0),
1963                 .hw.init = &(struct clk_init_data){
1964                         .name = "gcc_mdss_byte0_clk",
1965                         .parent_names = (const char *[]){
1966                                 "byte0_clk_src",
1967                         },
1968                         .num_parents = 1,
1969                         .flags = CLK_SET_RATE_PARENT,
1970                         .ops = &clk_branch2_ops,
1971                 },
1972         },
1973 };
1974
1975 static struct clk_branch gcc_mdss_esc0_clk = {
1976         .halt_reg = 0x4d098,
1977         .halt_check = BRANCH_HALT,
1978         .clkr = {
1979                 .enable_reg = 0x4d098,
1980                 .enable_mask = BIT(0),
1981                 .hw.init = &(struct clk_init_data){
1982                         .name = "gcc_mdss_esc0_clk",
1983                         .parent_names = (const char *[]){
1984                                 "esc0_clk_src",
1985                         },
1986                         .num_parents = 1,
1987                         .flags = CLK_SET_RATE_PARENT,
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch gcc_mdss_hdmi_app_clk = {
1994         .halt_reg = 0x4d0d8,
1995         .halt_check = BRANCH_HALT,
1996         .clkr = {
1997                 .enable_reg = 0x4d0d8,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "gcc_mdss_hdmi_app_clk",
2001                         .parent_names = (const char *[]){
2002                                 "hdmi_app_clk_src",
2003                         },
2004                         .num_parents = 1,
2005                         .flags = CLK_SET_RATE_PARENT,
2006                         .ops = &clk_branch2_ops,
2007                 },
2008         },
2009 };
2010
2011 static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
2012         .halt_reg = 0x4d0d4,
2013         .halt_check = BRANCH_HALT,
2014         .clkr = {
2015                 .enable_reg = 0x4d0d4,
2016                 .enable_mask = BIT(0),
2017                 .hw.init = &(struct clk_init_data){
2018                         .name = "gcc_mdss_hdmi_pclk_clk",
2019                         .parent_names = (const char *[]){
2020                                 "hdmi_pclk_clk_src",
2021                         },
2022                         .num_parents = 1,
2023                         .flags = CLK_SET_RATE_PARENT,
2024                         .ops = &clk_branch2_ops,
2025                 },
2026         },
2027 };
2028
2029 static struct clk_branch gcc_mdss_mdp_clk = {
2030         .halt_reg = 0x4d088,
2031         .halt_check = BRANCH_HALT,
2032         .clkr = {
2033                 .enable_reg = 0x4d088,
2034                 .enable_mask = BIT(0),
2035                 .hw.init = &(struct clk_init_data){
2036                         .name = "gcc_mdss_mdp_clk",
2037                         .parent_names = (const char *[]){
2038                                 "mdp_clk_src",
2039                         },
2040                         .num_parents = 1,
2041                         .flags = CLK_SET_RATE_PARENT,
2042                         .ops = &clk_branch2_ops,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch gcc_mdss_pclk0_clk = {
2048         .halt_reg = 0x4d084,
2049         .halt_check = BRANCH_HALT,
2050         .clkr = {
2051                 .enable_reg = 0x4d084,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_mdss_pclk0_clk",
2055                         .parent_names = (const char *[]){
2056                                 "pclk0_clk_src",
2057                         },
2058                         .num_parents = 1,
2059                         .flags = CLK_SET_RATE_PARENT,
2060                         .ops = &clk_branch2_ops,
2061                 },
2062         },
2063 };
2064
2065 static struct clk_branch gcc_mdss_vsync_clk = {
2066         .halt_reg = 0x4d090,
2067         .halt_check = BRANCH_HALT,
2068         .clkr = {
2069                 .enable_reg = 0x4d090,
2070                 .enable_mask = BIT(0),
2071                 .hw.init = &(struct clk_init_data){
2072                         .name = "gcc_mdss_vsync_clk",
2073                         .parent_names = (const char *[]){
2074                                 "vsync_clk_src",
2075                         },
2076                         .num_parents = 1,
2077                         .flags = CLK_SET_RATE_PARENT,
2078                         .ops = &clk_branch2_ops,
2079                 },
2080         },
2081 };
2082
2083 static struct clk_branch gcc_oxili_ahb_clk = {
2084         .halt_reg = 0x59028,
2085         .halt_check = BRANCH_HALT,
2086         .clkr = {
2087                 .enable_reg = 0x59028,
2088                 .enable_mask = BIT(0),
2089                 .hw.init = &(struct clk_init_data){
2090                         .name = "gcc_oxili_ahb_clk",
2091                         .ops = &clk_branch2_ops,
2092                 },
2093         },
2094 };
2095
2096 static struct clk_branch gcc_oxili_gfx3d_clk = {
2097         .halt_reg = 0x59020,
2098         .halt_check = BRANCH_HALT,
2099         .clkr = {
2100                 .enable_reg = 0x59020,
2101                 .enable_mask = BIT(0),
2102                 .hw.init = &(struct clk_init_data){
2103                         .name = "gcc_oxili_gfx3d_clk",
2104                         .parent_names = (const char *[]){
2105                                 "gfx3d_clk_src",
2106                         },
2107                         .num_parents = 1,
2108                         .flags = CLK_SET_RATE_PARENT,
2109                         .ops = &clk_branch2_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_branch gcc_pcie_0_aux_clk = {
2115         .halt_reg = 0x3e014,
2116         .halt_check = BRANCH_HALT_VOTED,
2117         .clkr = {
2118                 .enable_reg = 0x45004,
2119                 .enable_mask = BIT(27),
2120                 .hw.init = &(struct clk_init_data){
2121                         .name = "gcc_pcie_0_aux_clk",
2122                         .parent_names = (const char *[]){
2123                                 "pcie_0_aux_clk_src",
2124                         },
2125                         .num_parents = 1,
2126                         .flags = CLK_SET_RATE_PARENT,
2127                         .ops = &clk_branch2_ops,
2128                 },
2129         },
2130 };
2131
2132 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2133         .halt_reg = 0x3e008,
2134         .halt_check = BRANCH_HALT_VOTED,
2135         .clkr = {
2136                 .enable_reg = 0x45004,
2137                 .enable_mask = BIT(11),
2138                 .hw.init = &(struct clk_init_data){
2139                         .name = "gcc_pcie_0_cfg_ahb_clk",
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2146         .halt_reg = 0x3e018,
2147         .halt_check = BRANCH_HALT_VOTED,
2148         .clkr = {
2149                 .enable_reg = 0x45004,
2150                 .enable_mask = BIT(18),
2151                 .hw.init = &(struct clk_init_data){
2152                         .name = "gcc_pcie_0_mstr_axi_clk",
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch gcc_pcie_0_pipe_clk = {
2159         .halt_reg = 0x3e00c,
2160         .halt_check = BRANCH_HALT_VOTED,
2161         .clkr = {
2162                 .enable_reg = 0x45004,
2163                 .enable_mask = BIT(28),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_pcie_0_pipe_clk",
2166                         .parent_names = (const char *[]){
2167                                 "pcie_0_pipe_clk_src",
2168                         },
2169                         .num_parents = 1,
2170                         .flags = CLK_SET_RATE_PARENT,
2171                         .ops = &clk_branch2_ops,
2172                 },
2173         },
2174 };
2175
2176 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2177         .halt_reg = 0x3e010,
2178         .halt_check = BRANCH_HALT_VOTED,
2179         .clkr = {
2180                 .enable_reg = 0x45004,
2181                 .enable_mask = BIT(22),
2182                 .hw.init = &(struct clk_init_data){
2183                         .name = "gcc_pcie_0_slv_axi_clk",
2184                         .ops = &clk_branch2_ops,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_branch gcc_pcnoc_usb2_clk = {
2190         .halt_reg = 0x27008,
2191         .halt_check = BRANCH_HALT,
2192         .clkr = {
2193                 .enable_reg = 0x27008,
2194                 .enable_mask = BIT(0),
2195                 .hw.init = &(struct clk_init_data){
2196                         .name = "gcc_pcnoc_usb2_clk",
2197                         .flags = CLK_IS_CRITICAL,
2198                         .ops = &clk_branch2_ops,
2199                 },
2200         },
2201 };
2202
2203 static struct clk_branch gcc_pcnoc_usb3_clk = {
2204         .halt_reg = 0x2700c,
2205         .halt_check = BRANCH_HALT,
2206         .clkr = {
2207                 .enable_reg = 0x2700c,
2208                 .enable_mask = BIT(0),
2209                 .hw.init = &(struct clk_init_data){
2210                         .name = "gcc_pcnoc_usb3_clk",
2211                         .flags = CLK_IS_CRITICAL,
2212                         .ops = &clk_branch2_ops,
2213                 },
2214         },
2215 };
2216
2217 static struct clk_branch gcc_pdm2_clk = {
2218         .halt_reg = 0x4400c,
2219         .halt_check = BRANCH_HALT,
2220         .clkr = {
2221                 .enable_reg = 0x4400c,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_pdm2_clk",
2225                         .parent_names = (const char *[]){
2226                                 "pdm2_clk_src",
2227                         },
2228                         .num_parents = 1,
2229                         .flags = CLK_SET_RATE_PARENT,
2230                         .ops = &clk_branch2_ops,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch gcc_pdm_ahb_clk = {
2236         .halt_reg = 0x44004,
2237         .halt_check = BRANCH_HALT,
2238         .clkr = {
2239                 .enable_reg = 0x44004,
2240                 .enable_mask = BIT(0),
2241                 .hw.init = &(struct clk_init_data){
2242                         .name = "gcc_pdm_ahb_clk",
2243                         .ops = &clk_branch2_ops,
2244                 },
2245         },
2246 };
2247
2248 static struct clk_branch gcc_prng_ahb_clk = {
2249         .halt_reg = 0x13004,
2250         .halt_check = BRANCH_HALT_VOTED,
2251         .clkr = {
2252                 .enable_reg = 0x45004,
2253                 .enable_mask = BIT(8),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "gcc_prng_ahb_clk",
2256                         .ops = &clk_branch2_ops,
2257                 },
2258         },
2259 };
2260
2261 /* PWM clks do not have XO as parent as src clk is a balance root */
2262 static struct clk_branch gcc_pwm0_xo512_clk = {
2263         .halt_reg = 0x44018,
2264         .halt_check = BRANCH_HALT,
2265         .clkr = {
2266                 .enable_reg = 0x44018,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gcc_pwm0_xo512_clk",
2270                         .ops = &clk_branch2_ops,
2271                 },
2272         },
2273 };
2274
2275 static struct clk_branch gcc_pwm1_xo512_clk = {
2276         .halt_reg = 0x49004,
2277         .halt_check = BRANCH_HALT,
2278         .clkr = {
2279                 .enable_reg = 0x49004,
2280                 .enable_mask = BIT(0),
2281                 .hw.init = &(struct clk_init_data){
2282                         .name = "gcc_pwm1_xo512_clk",
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_pwm2_xo512_clk = {
2289         .halt_reg = 0x4a004,
2290         .halt_check = BRANCH_HALT,
2291         .clkr = {
2292                 .enable_reg = 0x4a004,
2293                 .enable_mask = BIT(0),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "gcc_pwm2_xo512_clk",
2296                         .ops = &clk_branch2_ops,
2297                 },
2298         },
2299 };
2300
2301 static struct clk_branch gcc_qdss_dap_clk = {
2302         .halt_reg = 0x29084,
2303         .halt_check = BRANCH_VOTED,
2304         .clkr = {
2305                 .enable_reg = 0x45004,
2306                 .enable_mask = BIT(21),
2307                 .hw.init = &(struct clk_init_data){
2308                         .name = "gcc_qdss_dap_clk",
2309                         .ops = &clk_branch2_ops,
2310                 },
2311         },
2312 };
2313
2314 static struct clk_branch gcc_sdcc1_ahb_clk = {
2315         .halt_reg = 0x4201c,
2316         .halt_check = BRANCH_HALT,
2317         .clkr = {
2318                 .enable_reg = 0x4201c,
2319                 .enable_mask = BIT(0),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_sdcc1_ahb_clk",
2322                         .ops = &clk_branch2_ops,
2323                 },
2324         },
2325 };
2326
2327 static struct clk_branch gcc_sdcc1_apps_clk = {
2328         .halt_reg = 0x42018,
2329         .halt_check = BRANCH_HALT,
2330         .clkr = {
2331                 .enable_reg = 0x42018,
2332                 .enable_mask = BIT(0),
2333                 .hw.init = &(struct clk_init_data){
2334                         .name = "gcc_sdcc1_apps_clk",
2335                         .parent_names = (const char *[]){
2336                                 "sdcc1_apps_clk_src",
2337                         },
2338                         .num_parents = 1,
2339                         .flags = CLK_SET_RATE_PARENT,
2340                         .ops = &clk_branch2_ops,
2341                 },
2342         },
2343 };
2344
2345 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2346         .halt_reg = 0x5d014,
2347         .halt_check = BRANCH_HALT,
2348         .clkr = {
2349                 .enable_reg = 0x5d014,
2350                 .enable_mask = BIT(0),
2351                 .hw.init = &(struct clk_init_data){
2352                         .name = "gcc_sdcc1_ice_core_clk",
2353                         .parent_names = (const char *[]){
2354                                 "sdcc1_ice_core_clk_src",
2355                         },
2356                         .num_parents = 1,
2357                         .flags = CLK_SET_RATE_PARENT,
2358                         .ops = &clk_branch2_ops,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
2364         .halt_reg = 0x5e004,
2365         .halt_check = BRANCH_HALT,
2366         .clkr = {
2367                 .enable_reg = 0x5e004,
2368                 .enable_mask = BIT(0),
2369                 .hw.init = &(struct clk_init_data) {
2370                         .name = "gcc_cdsp_cfg_ahb_cbcr",
2371                         .ops = &clk_branch2_ops,
2372                 },
2373         },
2374 };
2375
2376 static struct clk_branch gcc_sdcc2_ahb_clk = {
2377         .halt_reg = 0x4301c,
2378         .halt_check = BRANCH_HALT,
2379         .clkr = {
2380                 .enable_reg = 0x4301c,
2381                 .enable_mask = BIT(0),
2382                 .hw.init = &(struct clk_init_data){
2383                         .name = "gcc_sdcc2_ahb_clk",
2384                         .ops = &clk_branch2_ops,
2385                 },
2386         },
2387 };
2388
2389 static struct clk_branch gcc_sdcc2_apps_clk = {
2390         .halt_reg = 0x43018,
2391         .halt_check = BRANCH_HALT,
2392         .clkr = {
2393                 .enable_reg = 0x43018,
2394                 .enable_mask = BIT(0),
2395                 .hw.init = &(struct clk_init_data){
2396                         .name = "gcc_sdcc2_apps_clk",
2397                         .parent_names = (const char *[]){
2398                                 "sdcc2_apps_clk_src",
2399                         },
2400                         .num_parents = 1,
2401                         .flags = CLK_SET_RATE_PARENT,
2402                         .ops = &clk_branch2_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch gcc_smmu_cfg_clk = {
2408         .halt_reg = 0x12038,
2409         .halt_check = BRANCH_VOTED,
2410         .clkr = {
2411                 .enable_reg = 0x3600C,
2412                 .enable_mask = BIT(12),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_smmu_cfg_clk",
2415                         .ops = &clk_branch2_ops,
2416                 },
2417         },
2418 };
2419
2420 static struct clk_branch gcc_sys_noc_usb3_clk = {
2421         .halt_reg = 0x26014,
2422         .halt_check = BRANCH_HALT,
2423         .clkr = {
2424                 .enable_reg = 0x26014,
2425                 .enable_mask = BIT(0),
2426                 .hw.init = &(struct clk_init_data){
2427                         .name = "gcc_sys_noc_usb3_clk",
2428                         .parent_names = (const char *[]){
2429                                 "usb30_master_clk_src",
2430                         },
2431                         .num_parents = 1,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2438         .halt_reg = 0x4100C,
2439         .halt_check = BRANCH_HALT,
2440         .clkr = {
2441                 .enable_reg = 0x4100C,
2442                 .enable_mask = BIT(0),
2443                 .hw.init = &(struct clk_init_data){
2444                         .name = "gcc_usb_hs_inactivity_timers_clk",
2445                         .ops = &clk_branch2_ops,
2446                 },
2447         },
2448 };
2449
2450 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2451         .halt_reg = 0x41044,
2452         .halt_check = BRANCH_HALT,
2453         .clkr = {
2454                 .enable_reg = 0x41044,
2455                 .enable_mask = BIT(0),
2456                 .hw.init = &(struct clk_init_data){
2457                         .name = "gcc_usb20_mock_utmi_clk",
2458                         .parent_names = (const char *[]){
2459                                 "usb20_mock_utmi_clk_src",
2460                         },
2461                         .num_parents = 1,
2462                         .flags = CLK_SET_RATE_PARENT,
2463                         .ops = &clk_branch2_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2469         .halt_reg = 0x4102c,
2470         .halt_check = BRANCH_HALT,
2471         .clkr = {
2472                 .enable_reg = 0x4102c,
2473                 .enable_mask = BIT(0),
2474                 .hw.init = &(struct clk_init_data){
2475                         .name = "gcc_usb2a_phy_sleep_clk",
2476                         .ops = &clk_branch2_ops,
2477                 },
2478         },
2479 };
2480
2481 static struct clk_branch gcc_usb30_master_clk = {
2482         .halt_reg = 0x3900c,
2483         .halt_check = BRANCH_HALT,
2484         .clkr = {
2485                 .enable_reg = 0x3900c,
2486                 .enable_mask = BIT(0),
2487                 .hw.init = &(struct clk_init_data){
2488                         .name = "gcc_usb30_master_clk",
2489                         .parent_names = (const char *[]){
2490                                 "usb30_master_clk_src",
2491                         },
2492                         .num_parents = 1,
2493                         .flags = CLK_SET_RATE_PARENT,
2494                         .ops = &clk_branch2_ops,
2495                 },
2496         },
2497 };
2498
2499 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2500         .halt_reg = 0x39014,
2501         .halt_check = BRANCH_HALT,
2502         .clkr = {
2503                 .enable_reg = 0x39014,
2504                 .enable_mask = BIT(0),
2505                 .hw.init = &(struct clk_init_data){
2506                         .name = "gcc_usb30_mock_utmi_clk",
2507                         .parent_names = (const char *[]){
2508                                 "usb30_mock_utmi_clk_src",
2509                         },
2510                         .num_parents = 1,
2511                         .flags = CLK_SET_RATE_PARENT,
2512                         .ops = &clk_branch2_ops,
2513                 },
2514         },
2515 };
2516
2517 static struct clk_branch gcc_usb30_sleep_clk = {
2518         .halt_reg = 0x39010,
2519         .halt_check = BRANCH_HALT,
2520         .clkr = {
2521                 .enable_reg = 0x39010,
2522                 .enable_mask = BIT(0),
2523                 .hw.init = &(struct clk_init_data){
2524                         .name = "gcc_usb30_sleep_clk",
2525                         .ops = &clk_branch2_ops,
2526                 },
2527         },
2528 };
2529
2530 static struct clk_branch gcc_usb3_phy_aux_clk = {
2531         .halt_reg = 0x39044,
2532         .halt_check = BRANCH_HALT,
2533         .clkr = {
2534                 .enable_reg = 0x39044,
2535                 .enable_mask = BIT(0),
2536                 .hw.init = &(struct clk_init_data){
2537                         .name = "gcc_usb3_phy_aux_clk",
2538                         .parent_names = (const char *[]){
2539                                 "usb3_phy_aux_clk_src",
2540                         },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2549         .halt_check = BRANCH_HALT_SKIP,
2550         .clkr = {
2551                 .enable_reg = 0x39018,
2552                 .enable_mask = BIT(0),
2553                 .hw.init = &(struct clk_init_data){
2554                         .name = "gcc_usb3_phy_pipe_clk",
2555                         .ops = &clk_branch2_ops,
2556                 },
2557         },
2558 };
2559
2560 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2561         .halt_reg = 0x41030,
2562         .halt_check = BRANCH_HALT,
2563         .clkr = {
2564                 .enable_reg = 0x41030,
2565                 .enable_mask = BIT(0),
2566                 .hw.init = &(struct clk_init_data){
2567                         .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2568                         .ops = &clk_branch2_ops,
2569                 },
2570         },
2571 };
2572
2573 static struct clk_branch gcc_usb_hs_system_clk = {
2574         .halt_reg = 0x41004,
2575         .halt_check = BRANCH_HALT,
2576         .clkr = {
2577                 .enable_reg = 0x41004,
2578                 .enable_mask = BIT(0),
2579                 .hw.init = &(struct clk_init_data){
2580                         .name = "gcc_usb_hs_system_clk",
2581                         .parent_names = (const char *[]){
2582                                 "usb_hs_system_clk_src",
2583                         },
2584                         .num_parents = 1,
2585                         .flags = CLK_SET_RATE_PARENT,
2586                         .ops = &clk_branch2_ops,
2587                 },
2588         },
2589 };
2590
2591 static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2592         .halt_reg = 0x1e004,
2593         .halt_check = BRANCH_HALT,
2594         .clkr = {
2595                 .enable_reg = 0x1e004,
2596                 .enable_mask = BIT(0),
2597                 .hw.init = &(struct clk_init_data){
2598                         .name = "gcc_wdsp_q6ss_ahbs_clk",
2599                         .ops = &clk_branch2_ops,
2600                 },
2601         },
2602 };
2603
2604 static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2605         .halt_reg = 0x1e008,
2606         .halt_check = BRANCH_HALT,
2607         .clkr = {
2608                 .enable_reg = 0x1e008,
2609                 .enable_mask = BIT(0),
2610                 .hw.init = &(struct clk_init_data){
2611                         .name = "gcc_wdsp_q6ss_axim_clk",
2612                         .ops = &clk_branch2_ops,
2613                 },
2614         },
2615 };
2616
2617 static struct clk_hw *gcc_qcs404_hws[] = {
2618         &cxo.hw,
2619 };
2620
2621 static struct clk_regmap *gcc_qcs404_clocks[] = {
2622         [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2623         [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2624         [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2625         [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2626         [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2627         [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2628         [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2629         [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2630         [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2631         [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2632         [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2633         [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2634         [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2635         [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2636         [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2637         [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2638         [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2639         [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2640         [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2641         [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2642         [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2643         [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2644         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2645         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2646         [GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2647         [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2648         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2649         [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2650         [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2651         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2652         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2653         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2654         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2655         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2656         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2657         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2658         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2659         [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2660         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2661         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2662         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2663         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2664         [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2665         [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2666         [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2667         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2668         [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2669         [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2670         [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2671         [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2672         [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2673         [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2674         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2675         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2676         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2677         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2678         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2679         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2680         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2681         [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2682         [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2683         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2684         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2685         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2686         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2687         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2688         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2689         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2690         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2691         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2692         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2693         [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2694         [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2695         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2696         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2697         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2698         [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2699         [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2700         [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2701         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2702         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2703         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2704         [GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2705         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2706         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2707         [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2708         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2709         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2710         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2711         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2712         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2713         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2714         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2715         [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2716         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2717         [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2718         [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2719         [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2720         [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2721         [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2722         [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2723         [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2724         [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2725         [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2726         [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2727         [GCC_GPLL6] = &gpll6.clkr,
2728         [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2729         [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2730         [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2731         [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2732         [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2733         [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2734         [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2735         [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2736         [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2737         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2738         [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2739         [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2740         [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2741         [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2742         [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2743         [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2744         [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2745         [GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2746         [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2747                         &gcc_usb_hs_inactivity_timers_clk.clkr,
2748         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2749         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2750         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2751         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2752         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2753         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2754         [GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2755         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2756         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2757         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2758         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2759         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2760         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2761         [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2762         [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2763         [GCC_WCSS_Q6_AXIM_CLK] =  &gcc_wdsp_q6ss_axim_clk.clkr,
2764
2765 };
2766
2767 static const struct qcom_reset_map gcc_qcs404_resets[] = {
2768         [GCC_GENI_IR_BCR] = { 0x0F000 },
2769         [GCC_CDSP_RESTART] = { 0x18000 },
2770         [GCC_USB_HS_BCR] = { 0x41000 },
2771         [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2772         [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2773         [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2774         [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2775         [GCC_USB3_PHY_BCR] = { 0x39004 },
2776         [GCC_USB_30_BCR] = { 0x39000 },
2777         [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2778         [GCC_PCIE_0_BCR] = { 0x3e000 },
2779         [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2780         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2781         [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2782         [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2783         [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2784         [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2785         [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2786         [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2787         [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2788         [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2789         [GCC_EMAC_BCR] = { 0x4e000 },
2790         [GCC_WDSP_RESTART] = {0x19000},
2791 };
2792
2793 static const struct regmap_config gcc_qcs404_regmap_config = {
2794         .reg_bits       = 32,
2795         .reg_stride     = 4,
2796         .val_bits       = 32,
2797         .max_register   = 0x7f000,
2798         .fast_io        = true,
2799 };
2800
2801 static const struct qcom_cc_desc gcc_qcs404_desc = {
2802         .config = &gcc_qcs404_regmap_config,
2803         .clks = gcc_qcs404_clocks,
2804         .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2805         .resets = gcc_qcs404_resets,
2806         .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2807         .clk_hws = gcc_qcs404_hws,
2808         .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
2809 };
2810
2811 static const struct of_device_id gcc_qcs404_match_table[] = {
2812         { .compatible = "qcom,gcc-qcs404" },
2813         { }
2814 };
2815 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2816
2817 static int gcc_qcs404_probe(struct platform_device *pdev)
2818 {
2819         struct regmap *regmap;
2820
2821         regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2822         if (IS_ERR(regmap))
2823                 return PTR_ERR(regmap);
2824
2825         clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2826
2827         return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
2828 }
2829
2830 static struct platform_driver gcc_qcs404_driver = {
2831         .probe = gcc_qcs404_probe,
2832         .driver = {
2833                 .name = "gcc-qcs404",
2834                 .of_match_table = gcc_qcs404_match_table,
2835         },
2836 };
2837
2838 static int __init gcc_qcs404_init(void)
2839 {
2840         return platform_driver_register(&gcc_qcs404_driver);
2841 }
2842 core_initcall(gcc_qcs404_init);
2843
2844 static void __exit gcc_qcs404_exit(void)
2845 {
2846         platform_driver_unregister(&gcc_qcs404_driver);
2847 }
2848 module_exit(gcc_qcs404_exit);
2849
2850 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2851 MODULE_LICENSE("GPL v2");