1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
10 #include <linux/clk-provider.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
20 #include "clk-regmap.h"
25 P_CORE_BI_PLL_TEST_SE,
26 P_DSI0_PHY_PLL_OUT_BYTECLK,
27 P_DSI0_PHY_PLL_OUT_DSICLK,
39 static const struct parent_map gcc_parent_map_0[] = {
41 { P_GPLL0_OUT_MAIN, 1 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
45 static const char * const gcc_parent_names_0[] = {
48 "core_bi_pll_test_se",
51 static const char * const gcc_parent_names_ao_0[] = {
54 "core_bi_pll_test_se",
57 static const struct parent_map gcc_parent_map_1[] = {
59 { P_CORE_BI_PLL_TEST_SE, 7 },
62 static const char * const gcc_parent_names_1[] = {
64 "core_bi_pll_test_se",
67 static const struct parent_map gcc_parent_map_2[] = {
69 { P_GPLL0_OUT_MAIN, 1 },
70 { P_GPLL6_OUT_AUX, 2 },
74 static const char * const gcc_parent_names_2[] = {
81 static const struct parent_map gcc_parent_map_3[] = {
83 { P_GPLL0_OUT_MAIN, 1 },
84 { P_GPLL6_OUT_AUX, 2 },
85 { P_CORE_BI_PLL_TEST_SE, 7 },
88 static const char * const gcc_parent_names_3[] = {
92 "core_bi_pll_test_se",
95 static const struct parent_map gcc_parent_map_4[] = {
97 { P_GPLL1_OUT_MAIN, 1 },
98 { P_CORE_BI_PLL_TEST_SE, 7 },
101 static const char * const gcc_parent_names_4[] = {
104 "core_bi_pll_test_se",
107 static const struct parent_map gcc_parent_map_5[] = {
109 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
110 { P_CORE_BI_PLL_TEST_SE, 7 },
113 static const char * const gcc_parent_names_5[] = {
116 "core_bi_pll_test_se",
119 static const struct parent_map gcc_parent_map_6[] = {
121 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
122 { P_CORE_BI_PLL_TEST_SE, 7 },
125 static const char * const gcc_parent_names_6[] = {
128 "core_bi_pll_test_se",
131 static const struct parent_map gcc_parent_map_7[] = {
133 { P_GPLL0_OUT_MAIN, 1 },
134 { P_GPLL3_OUT_MAIN, 2 },
135 { P_GPLL6_OUT_AUX, 3 },
136 { P_CORE_BI_PLL_TEST_SE, 7 },
139 static const char * const gcc_parent_names_7[] = {
144 "core_bi_pll_test_se",
147 static const struct parent_map gcc_parent_map_8[] = {
149 { P_HDMI_PHY_PLL_CLK, 1 },
150 { P_CORE_BI_PLL_TEST_SE, 7 },
153 static const char * const gcc_parent_names_8[] = {
156 "core_bi_pll_test_se",
159 static const struct parent_map gcc_parent_map_9[] = {
161 { P_GPLL0_OUT_MAIN, 1 },
162 { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
163 { P_GPLL6_OUT_AUX, 3 },
164 { P_CORE_BI_PLL_TEST_SE, 7 },
167 static const char * const gcc_parent_names_9[] = {
172 "core_bi_pll_test_se",
175 static const struct parent_map gcc_parent_map_10[] = {
178 { P_CORE_BI_PLL_TEST_SE, 7 },
181 static const char * const gcc_parent_names_10[] = {
184 "core_bi_pll_test_se",
187 static const struct parent_map gcc_parent_map_11[] = {
189 { P_PCIE_0_PIPE_CLK, 1 },
190 { P_CORE_BI_PLL_TEST_SE, 7 },
193 static const char * const gcc_parent_names_11[] = {
196 "core_bi_pll_test_se",
199 static const struct parent_map gcc_parent_map_12[] = {
201 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
202 { P_CORE_BI_PLL_TEST_SE, 7 },
205 static const char * const gcc_parent_names_12[] = {
208 "core_bi_pll_test_se",
211 static const struct parent_map gcc_parent_map_13[] = {
213 { P_GPLL0_OUT_MAIN, 1 },
214 { P_GPLL4_OUT_MAIN, 2 },
215 { P_GPLL6_OUT_AUX, 3 },
216 { P_CORE_BI_PLL_TEST_SE, 7 },
219 static const char * const gcc_parent_names_13[] = {
224 "core_bi_pll_test_se",
227 static const struct parent_map gcc_parent_map_14[] = {
229 { P_GPLL0_OUT_MAIN, 1 },
230 { P_CORE_BI_PLL_TEST_SE, 7 },
233 static const char * const gcc_parent_names_14[] = {
236 "core_bi_pll_test_se",
239 static const struct parent_map gcc_parent_map_15[] = {
241 { P_CORE_BI_PLL_TEST_SE, 7 },
244 static const char * const gcc_parent_names_15[] = {
246 "core_bi_pll_test_se",
249 static const struct parent_map gcc_parent_map_16[] = {
251 { P_GPLL0_OUT_MAIN, 1 },
252 { P_CORE_BI_PLL_TEST_SE, 7 },
255 static const char * const gcc_parent_names_16[] = {
258 "core_bi_pll_test_se",
261 static struct clk_fixed_factor cxo = {
264 .hw.init = &(struct clk_init_data){
266 .parent_names = (const char *[]){ "xo-board" },
268 .ops = &clk_fixed_factor_ops,
272 static struct clk_alpha_pll gpll0_sleep_clk_src = {
274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
276 .enable_reg = 0x45008,
277 .enable_mask = BIT(23),
278 .enable_is_inverted = true,
279 .hw.init = &(struct clk_init_data){
280 .name = "gpll0_sleep_clk_src",
281 .parent_names = (const char *[]){ "cxo" },
283 .ops = &clk_alpha_pll_ops,
288 static struct clk_alpha_pll gpll0_out_main = {
290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
291 .flags = SUPPORTS_FSM_MODE,
293 .enable_reg = 0x45000,
294 .enable_mask = BIT(0),
295 .hw.init = &(struct clk_init_data){
296 .name = "gpll0_out_main",
297 .parent_names = (const char *[])
300 .ops = &clk_alpha_pll_ops,
305 static struct clk_alpha_pll gpll0_ao_out_main = {
307 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
308 .flags = SUPPORTS_FSM_MODE,
310 .enable_reg = 0x45000,
311 .enable_mask = BIT(0),
312 .hw.init = &(struct clk_init_data){
313 .name = "gpll0_ao_out_main",
314 .parent_names = (const char *[]){ "cxo" },
316 .flags = CLK_IS_CRITICAL,
317 .ops = &clk_alpha_pll_fixed_ops,
322 static struct clk_alpha_pll gpll1_out_main = {
324 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
326 .enable_reg = 0x45000,
327 .enable_mask = BIT(1),
328 .hw.init = &(struct clk_init_data){
329 .name = "gpll1_out_main",
330 .parent_names = (const char *[]){ "cxo" },
332 .ops = &clk_alpha_pll_ops,
337 /* 930MHz configuration */
338 static const struct alpha_pll_config gpll3_config = {
341 .alpha_en_mask = BIT(24),
342 .post_div_mask = 0xf << 8,
343 .post_div_val = 0x1 << 8,
344 .vco_mask = 0x3 << 20,
345 .main_output_mask = 0x1,
346 .config_ctl_val = 0x4001055b,
349 static const struct pll_vco gpll3_vco[] = {
350 { 700000000, 1400000000, 0 },
353 static struct clk_alpha_pll gpll3_out_main = {
355 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
356 .vco_table = gpll3_vco,
357 .num_vco = ARRAY_SIZE(gpll3_vco),
359 .hw.init = &(struct clk_init_data){
360 .name = "gpll3_out_main",
361 .parent_names = (const char *[]){ "cxo" },
363 .ops = &clk_alpha_pll_ops,
368 static struct clk_alpha_pll gpll4_out_main = {
370 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
372 .enable_reg = 0x45000,
373 .enable_mask = BIT(5),
374 .hw.init = &(struct clk_init_data){
375 .name = "gpll4_out_main",
376 .parent_names = (const char *[]){ "cxo" },
378 .ops = &clk_alpha_pll_ops,
383 static struct clk_pll gpll6 = {
387 .config_reg = 0x37014,
389 .status_reg = 0x3701C,
391 .clkr.hw.init = &(struct clk_init_data){
393 .parent_names = (const char *[]){ "cxo" },
399 static struct clk_regmap gpll6_out_aux = {
400 .enable_reg = 0x45000,
401 .enable_mask = BIT(7),
402 .hw.init = &(struct clk_init_data){
403 .name = "gpll6_out_aux",
404 .parent_names = (const char *[]){ "gpll6" },
406 .ops = &clk_pll_vote_ops,
410 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
411 F(19200000, P_XO, 1, 0, 0),
412 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
413 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
414 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
418 static struct clk_rcg2 apss_ahb_clk_src = {
422 .parent_map = gcc_parent_map_0,
423 .freq_tbl = ftbl_apss_ahb_clk_src,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "apss_ahb_clk_src",
426 .parent_names = gcc_parent_names_ao_0,
428 .flags = CLK_IS_CRITICAL,
429 .ops = &clk_rcg2_ops,
433 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
434 F(19200000, P_XO, 1, 0, 0),
435 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
439 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
443 .parent_map = gcc_parent_map_0,
444 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
445 .clkr.hw.init = &(struct clk_init_data){
446 .name = "blsp1_qup0_i2c_apps_clk_src",
447 .parent_names = gcc_parent_names_0,
449 .ops = &clk_rcg2_ops,
453 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
454 F(960000, P_XO, 10, 1, 2),
455 F(4800000, P_XO, 4, 0, 0),
456 F(9600000, P_XO, 2, 0, 0),
457 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
458 F(19200000, P_XO, 1, 0, 0),
459 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
460 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
464 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
468 .parent_map = gcc_parent_map_0,
469 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "blsp1_qup0_spi_apps_clk_src",
472 .parent_names = gcc_parent_names_0,
474 .ops = &clk_rcg2_ops,
478 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
482 .parent_map = gcc_parent_map_0,
483 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "blsp1_qup1_i2c_apps_clk_src",
486 .parent_names = gcc_parent_names_0,
488 .ops = &clk_rcg2_ops,
492 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
493 F(960000, P_XO, 10, 1, 2),
494 F(4800000, P_XO, 4, 0, 0),
495 F(9600000, P_XO, 2, 0, 0),
496 F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
497 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
498 F(19200000, P_XO, 1, 0, 0),
499 F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
503 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
507 .parent_map = gcc_parent_map_0,
508 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "blsp1_qup1_spi_apps_clk_src",
511 .parent_names = gcc_parent_names_0,
513 .ops = &clk_rcg2_ops,
517 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
521 .parent_map = gcc_parent_map_0,
522 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
523 .clkr.hw.init = &(struct clk_init_data){
524 .name = "blsp1_qup2_i2c_apps_clk_src",
525 .parent_names = gcc_parent_names_0,
527 .ops = &clk_rcg2_ops,
531 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
532 F(960000, P_XO, 10, 1, 2),
533 F(4800000, P_XO, 4, 0, 0),
534 F(9600000, P_XO, 2, 0, 0),
535 F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160),
536 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
537 F(19200000, P_XO, 1, 0, 0),
538 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
539 F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80),
543 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
547 .parent_map = gcc_parent_map_0,
548 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
549 .clkr.hw.init = &(struct clk_init_data){
550 .name = "blsp1_qup2_spi_apps_clk_src",
551 .parent_names = gcc_parent_names_0,
553 .ops = &clk_rcg2_ops,
557 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
561 .parent_map = gcc_parent_map_0,
562 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
563 .clkr.hw.init = &(struct clk_init_data){
564 .name = "blsp1_qup3_i2c_apps_clk_src",
565 .parent_names = gcc_parent_names_0,
567 .ops = &clk_rcg2_ops,
571 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
575 .parent_map = gcc_parent_map_0,
576 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
577 .clkr.hw.init = &(struct clk_init_data){
578 .name = "blsp1_qup3_spi_apps_clk_src",
579 .parent_names = gcc_parent_names_0,
581 .ops = &clk_rcg2_ops,
585 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
589 .parent_map = gcc_parent_map_0,
590 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
591 .clkr.hw.init = &(struct clk_init_data){
592 .name = "blsp1_qup4_i2c_apps_clk_src",
593 .parent_names = gcc_parent_names_0,
595 .ops = &clk_rcg2_ops,
599 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
603 .parent_map = gcc_parent_map_0,
604 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
605 .clkr.hw.init = &(struct clk_init_data){
606 .name = "blsp1_qup4_spi_apps_clk_src",
607 .parent_names = gcc_parent_names_0,
609 .ops = &clk_rcg2_ops,
613 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
614 F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
615 F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
616 F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
617 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
618 F(19200000, P_XO, 1, 0, 0),
619 F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
620 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
621 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
622 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
623 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
624 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
625 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
626 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
627 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
628 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
629 F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
633 static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
637 .parent_map = gcc_parent_map_0,
638 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "blsp1_uart0_apps_clk_src",
641 .parent_names = gcc_parent_names_0,
643 .ops = &clk_rcg2_ops,
647 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
651 .parent_map = gcc_parent_map_0,
652 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
653 .clkr.hw.init = &(struct clk_init_data){
654 .name = "blsp1_uart1_apps_clk_src",
655 .parent_names = gcc_parent_names_0,
657 .ops = &clk_rcg2_ops,
661 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
665 .parent_map = gcc_parent_map_0,
666 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
667 .clkr.hw.init = &(struct clk_init_data){
668 .name = "blsp1_uart2_apps_clk_src",
669 .parent_names = gcc_parent_names_0,
671 .ops = &clk_rcg2_ops,
675 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
680 .parent_map = gcc_parent_map_0,
681 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
682 .clkr.hw.init = &(struct clk_init_data){
683 .name = "blsp1_uart3_apps_clk_src",
684 .parent_names = gcc_parent_names_0,
686 .ops = &clk_rcg2_ops,
690 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
694 .parent_map = gcc_parent_map_0,
695 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "blsp2_qup0_i2c_apps_clk_src",
698 .parent_names = gcc_parent_names_0,
700 .ops = &clk_rcg2_ops,
704 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
708 .parent_map = gcc_parent_map_0,
709 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "blsp2_qup0_spi_apps_clk_src",
712 .parent_names = gcc_parent_names_0,
714 .ops = &clk_rcg2_ops,
718 static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
722 .parent_map = gcc_parent_map_0,
723 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
724 .clkr.hw.init = &(struct clk_init_data){
725 .name = "blsp2_uart0_apps_clk_src",
726 .parent_names = gcc_parent_names_0,
728 .ops = &clk_rcg2_ops,
732 static struct clk_rcg2 byte0_clk_src = {
736 .parent_map = gcc_parent_map_5,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "byte0_clk_src",
739 .parent_names = gcc_parent_names_5,
741 .flags = CLK_SET_RATE_PARENT,
742 .ops = &clk_byte2_ops,
746 static const struct freq_tbl ftbl_emac_clk_src[] = {
747 F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
748 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
749 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
750 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
754 static struct clk_rcg2 emac_clk_src = {
758 .parent_map = gcc_parent_map_4,
759 .freq_tbl = ftbl_emac_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "emac_clk_src",
762 .parent_names = gcc_parent_names_4,
764 .ops = &clk_rcg2_ops,
768 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
769 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
770 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
771 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
775 static struct clk_rcg2 emac_ptp_clk_src = {
779 .parent_map = gcc_parent_map_4,
780 .freq_tbl = ftbl_emac_ptp_clk_src,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "emac_ptp_clk_src",
783 .parent_names = gcc_parent_names_4,
785 .ops = &clk_rcg2_ops,
789 static const struct freq_tbl ftbl_esc0_clk_src[] = {
790 F(19200000, P_XO, 1, 0, 0),
794 static struct clk_rcg2 esc0_clk_src = {
798 .parent_map = gcc_parent_map_6,
799 .freq_tbl = ftbl_esc0_clk_src,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "esc0_clk_src",
802 .parent_names = gcc_parent_names_6,
804 .ops = &clk_rcg2_ops,
808 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
809 F(19200000, P_XO, 1, 0, 0),
810 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
811 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
812 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
813 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
814 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
815 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
816 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
817 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
818 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
819 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
820 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
821 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
822 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
823 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
824 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
828 static struct clk_rcg2 gfx3d_clk_src = {
832 .parent_map = gcc_parent_map_7,
833 .freq_tbl = ftbl_gfx3d_clk_src,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "gfx3d_clk_src",
836 .parent_names = gcc_parent_names_7,
838 .ops = &clk_rcg2_ops,
842 static const struct freq_tbl ftbl_gp1_clk_src[] = {
843 F(19200000, P_XO, 1, 0, 0),
844 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
845 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
849 static struct clk_rcg2 gp1_clk_src = {
853 .parent_map = gcc_parent_map_2,
854 .freq_tbl = ftbl_gp1_clk_src,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "gp1_clk_src",
857 .parent_names = gcc_parent_names_2,
859 .ops = &clk_rcg2_ops,
863 static struct clk_rcg2 gp2_clk_src = {
867 .parent_map = gcc_parent_map_2,
868 .freq_tbl = ftbl_gp1_clk_src,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "gp2_clk_src",
871 .parent_names = gcc_parent_names_2,
873 .ops = &clk_rcg2_ops,
877 static struct clk_rcg2 gp3_clk_src = {
881 .parent_map = gcc_parent_map_2,
882 .freq_tbl = ftbl_gp1_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "gp3_clk_src",
885 .parent_names = gcc_parent_names_2,
887 .ops = &clk_rcg2_ops,
891 static struct clk_rcg2 hdmi_app_clk_src = {
895 .parent_map = gcc_parent_map_1,
896 .freq_tbl = ftbl_esc0_clk_src,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "hdmi_app_clk_src",
899 .parent_names = gcc_parent_names_1,
901 .ops = &clk_rcg2_ops,
905 static struct clk_rcg2 hdmi_pclk_clk_src = {
909 .parent_map = gcc_parent_map_8,
910 .freq_tbl = ftbl_esc0_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "hdmi_pclk_clk_src",
913 .parent_names = gcc_parent_names_8,
915 .ops = &clk_rcg2_ops,
919 static const struct freq_tbl ftbl_mdp_clk_src[] = {
920 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
921 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
922 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
923 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
924 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
925 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
926 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
927 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
928 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
932 static struct clk_rcg2 mdp_clk_src = {
936 .parent_map = gcc_parent_map_9,
937 .freq_tbl = ftbl_mdp_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "mdp_clk_src",
940 .parent_names = gcc_parent_names_9,
942 .ops = &clk_rcg2_ops,
946 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
947 F(1200000, P_XO, 16, 0, 0),
951 static struct clk_rcg2 pcie_0_aux_clk_src = {
955 .parent_map = gcc_parent_map_10,
956 .freq_tbl = ftbl_pcie_0_aux_clk_src,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "pcie_0_aux_clk_src",
959 .parent_names = gcc_parent_names_10,
961 .ops = &clk_rcg2_ops,
965 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
966 F(19200000, P_XO, 1, 0, 0),
967 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
968 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
972 static struct clk_rcg2 pcie_0_pipe_clk_src = {
976 .parent_map = gcc_parent_map_11,
977 .freq_tbl = ftbl_pcie_0_pipe_clk_src,
978 .clkr.hw.init = &(struct clk_init_data){
979 .name = "pcie_0_pipe_clk_src",
980 .parent_names = gcc_parent_names_11,
982 .ops = &clk_rcg2_ops,
986 static struct clk_rcg2 pclk0_clk_src = {
990 .parent_map = gcc_parent_map_12,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "pclk0_clk_src",
993 .parent_names = gcc_parent_names_12,
995 .flags = CLK_SET_RATE_PARENT,
996 .ops = &clk_pixel_ops,
1000 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1001 F(19200000, P_XO, 1, 0, 0),
1002 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1006 static struct clk_rcg2 pdm2_clk_src = {
1007 .cmd_rcgr = 0x44010,
1010 .parent_map = gcc_parent_map_0,
1011 .freq_tbl = ftbl_pdm2_clk_src,
1012 .clkr.hw.init = &(struct clk_init_data){
1013 .name = "pdm2_clk_src",
1014 .parent_names = gcc_parent_names_0,
1016 .ops = &clk_rcg2_ops,
1020 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1021 F(144000, P_XO, 16, 3, 25),
1022 F(400000, P_XO, 12, 1, 4),
1023 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1024 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1025 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1026 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1027 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1028 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1029 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1030 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1034 static struct clk_rcg2 sdcc1_apps_clk_src = {
1035 .cmd_rcgr = 0x42004,
1038 .parent_map = gcc_parent_map_13,
1039 .freq_tbl = ftbl_sdcc1_apps_clk_src,
1040 .clkr.hw.init = &(struct clk_init_data){
1041 .name = "sdcc1_apps_clk_src",
1042 .parent_names = gcc_parent_names_13,
1044 .ops = &clk_rcg2_floor_ops,
1048 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1049 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1050 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1054 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1055 .cmd_rcgr = 0x5d000,
1058 .parent_map = gcc_parent_map_3,
1059 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1060 .clkr.hw.init = &(struct clk_init_data){
1061 .name = "sdcc1_ice_core_clk_src",
1062 .parent_names = gcc_parent_names_3,
1064 .ops = &clk_rcg2_ops,
1068 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1069 F(144000, P_XO, 16, 3, 25),
1070 F(400000, P_XO, 12, 1, 4),
1071 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1072 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1073 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1074 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1075 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1076 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1080 static struct clk_rcg2 sdcc2_apps_clk_src = {
1081 .cmd_rcgr = 0x43004,
1084 .parent_map = gcc_parent_map_14,
1085 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1086 .clkr.hw.init = &(struct clk_init_data){
1087 .name = "sdcc2_apps_clk_src",
1088 .parent_names = gcc_parent_names_14,
1090 .ops = &clk_rcg2_floor_ops,
1094 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1095 .cmd_rcgr = 0x41048,
1098 .parent_map = gcc_parent_map_1,
1099 .freq_tbl = ftbl_esc0_clk_src,
1100 .clkr.hw.init = &(struct clk_init_data){
1101 .name = "usb20_mock_utmi_clk_src",
1102 .parent_names = gcc_parent_names_1,
1104 .ops = &clk_rcg2_ops,
1108 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1109 F(19200000, P_XO, 1, 0, 0),
1110 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1111 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1112 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1116 static struct clk_rcg2 usb30_master_clk_src = {
1117 .cmd_rcgr = 0x39028,
1120 .parent_map = gcc_parent_map_0,
1121 .freq_tbl = ftbl_usb30_master_clk_src,
1122 .clkr.hw.init = &(struct clk_init_data){
1123 .name = "usb30_master_clk_src",
1124 .parent_names = gcc_parent_names_0,
1126 .ops = &clk_rcg2_ops,
1130 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1131 .cmd_rcgr = 0x3901c,
1134 .parent_map = gcc_parent_map_1,
1135 .freq_tbl = ftbl_esc0_clk_src,
1136 .clkr.hw.init = &(struct clk_init_data){
1137 .name = "usb30_mock_utmi_clk_src",
1138 .parent_names = gcc_parent_names_1,
1140 .ops = &clk_rcg2_ops,
1144 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1145 .cmd_rcgr = 0x3903c,
1148 .parent_map = gcc_parent_map_1,
1149 .freq_tbl = ftbl_pcie_0_aux_clk_src,
1150 .clkr.hw.init = &(struct clk_init_data){
1151 .name = "usb3_phy_aux_clk_src",
1152 .parent_names = gcc_parent_names_1,
1154 .ops = &clk_rcg2_ops,
1158 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1159 F(19200000, P_XO, 1, 0, 0),
1160 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1161 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1162 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1163 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1167 static struct clk_rcg2 usb_hs_system_clk_src = {
1168 .cmd_rcgr = 0x41010,
1171 .parent_map = gcc_parent_map_3,
1172 .freq_tbl = ftbl_usb_hs_system_clk_src,
1173 .clkr.hw.init = &(struct clk_init_data){
1174 .name = "usb_hs_system_clk_src",
1175 .parent_names = gcc_parent_names_3,
1177 .ops = &clk_rcg2_ops,
1181 static struct clk_rcg2 vsync_clk_src = {
1182 .cmd_rcgr = 0x4d02c,
1185 .parent_map = gcc_parent_map_15,
1186 .freq_tbl = ftbl_esc0_clk_src,
1187 .clkr.hw.init = &(struct clk_init_data){
1188 .name = "vsync_clk_src",
1189 .parent_names = gcc_parent_names_15,
1191 .ops = &clk_rcg2_ops,
1195 static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
1196 F(19200000, P_XO, 1, 0, 0),
1197 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1198 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1199 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1203 static struct clk_rcg2 cdsp_bimc_clk_src = {
1204 .cmd_rcgr = 0x5e010,
1207 .parent_map = gcc_parent_map_16,
1208 .freq_tbl = ftbl_cdsp_bimc_clk_src,
1209 .clkr.hw.init = &(struct clk_init_data) {
1210 .name = "cdsp_bimc_clk_src",
1211 .parent_names = gcc_parent_names_16,
1213 .ops = &clk_rcg2_ops,
1217 static struct clk_branch gcc_apss_ahb_clk = {
1218 .halt_reg = 0x4601c,
1219 .halt_check = BRANCH_HALT_VOTED,
1221 .enable_reg = 0x45004,
1222 .enable_mask = BIT(14),
1223 .hw.init = &(struct clk_init_data){
1224 .name = "gcc_apss_ahb_clk",
1225 .parent_names = (const char *[]){
1229 .flags = CLK_SET_RATE_PARENT,
1230 .ops = &clk_branch2_ops,
1235 static struct clk_branch gcc_apss_tcu_clk = {
1236 .halt_reg = 0x5b004,
1237 .halt_check = BRANCH_VOTED,
1239 .enable_reg = 0x4500c,
1240 .enable_mask = BIT(1),
1241 .hw.init = &(struct clk_init_data){
1242 .name = "gcc_apss_tcu_clk",
1243 .ops = &clk_branch2_ops,
1248 static struct clk_branch gcc_bimc_gfx_clk = {
1249 .halt_reg = 0x59034,
1250 .halt_check = BRANCH_HALT,
1252 .enable_reg = 0x59034,
1253 .enable_mask = BIT(0),
1254 .hw.init = &(struct clk_init_data){
1255 .name = "gcc_bimc_gfx_clk",
1256 .ops = &clk_branch2_ops,
1257 .parent_names = (const char *[]){
1265 static struct clk_branch gcc_bimc_gpu_clk = {
1266 .halt_reg = 0x59030,
1267 .halt_check = BRANCH_HALT,
1269 .enable_reg = 0x59030,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "gcc_bimc_gpu_clk",
1273 .ops = &clk_branch2_ops,
1278 static struct clk_branch gcc_bimc_cdsp_clk = {
1279 .halt_reg = 0x31030,
1280 .halt_check = BRANCH_HALT,
1282 .enable_reg = 0x31030,
1283 .enable_mask = BIT(0),
1284 .hw.init = &(struct clk_init_data) {
1285 .name = "gcc_bimc_cdsp_clk",
1286 .parent_names = (const char *[]) {
1287 "cdsp_bimc_clk_src",
1290 .flags = CLK_SET_RATE_PARENT,
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch gcc_bimc_mdss_clk = {
1297 .halt_reg = 0x31038,
1298 .halt_check = BRANCH_HALT,
1300 .enable_reg = 0x31038,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_bimc_mdss_clk",
1304 .ops = &clk_branch2_ops,
1309 static struct clk_branch gcc_blsp1_ahb_clk = {
1311 .halt_check = BRANCH_HALT_VOTED,
1313 .enable_reg = 0x45004,
1314 .enable_mask = BIT(10),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gcc_blsp1_ahb_clk",
1317 .ops = &clk_branch2_ops,
1322 static struct clk_branch gcc_dcc_clk = {
1323 .halt_reg = 0x77004,
1324 .halt_check = BRANCH_HALT,
1326 .enable_reg = 0x77004,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_dcc_clk",
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch gcc_dcc_xo_clk = {
1336 .halt_reg = 0x77008,
1337 .halt_check = BRANCH_HALT,
1339 .enable_reg = 0x77008,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_dcc_xo_clk",
1343 .ops = &clk_branch2_ops,
1348 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1350 .halt_check = BRANCH_HALT,
1352 .enable_reg = 0x6028,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gcc_blsp1_qup0_i2c_apps_clk",
1356 .parent_names = (const char *[]){
1357 "blsp1_qup0_i2c_apps_clk_src",
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1366 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1368 .halt_check = BRANCH_HALT,
1370 .enable_reg = 0x6024,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "gcc_blsp1_qup0_spi_apps_clk",
1374 .parent_names = (const char *[]){
1375 "blsp1_qup0_spi_apps_clk_src",
1378 .flags = CLK_SET_RATE_PARENT,
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1386 .halt_check = BRANCH_HALT,
1388 .enable_reg = 0x2008,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1392 .parent_names = (const char *[]){
1393 "blsp1_qup1_i2c_apps_clk_src",
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1404 .halt_check = BRANCH_HALT,
1406 .enable_reg = 0x2004,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_blsp1_qup1_spi_apps_clk",
1410 .parent_names = (const char *[]){
1411 "blsp1_qup1_spi_apps_clk_src",
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1422 .halt_check = BRANCH_HALT,
1424 .enable_reg = 0x3010,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1428 .parent_names = (const char *[]){
1429 "blsp1_qup2_i2c_apps_clk_src",
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1440 .halt_check = BRANCH_HALT,
1442 .enable_reg = 0x300c,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_blsp1_qup2_spi_apps_clk",
1446 .parent_names = (const char *[]){
1447 "blsp1_qup2_spi_apps_clk_src",
1450 .flags = CLK_SET_RATE_PARENT,
1451 .ops = &clk_branch2_ops,
1456 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1458 .halt_check = BRANCH_HALT,
1460 .enable_reg = 0x4020,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1464 .parent_names = (const char *[]){
1465 "blsp1_qup3_i2c_apps_clk_src",
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1476 .halt_check = BRANCH_HALT,
1478 .enable_reg = 0x401c,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_blsp1_qup3_spi_apps_clk",
1482 .parent_names = (const char *[]){
1483 "blsp1_qup3_spi_apps_clk_src",
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1494 .halt_check = BRANCH_HALT,
1496 .enable_reg = 0x5020,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1500 .parent_names = (const char *[]){
1501 "blsp1_qup4_i2c_apps_clk_src",
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1512 .halt_check = BRANCH_HALT,
1514 .enable_reg = 0x501c,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_blsp1_qup4_spi_apps_clk",
1518 .parent_names = (const char *[]){
1519 "blsp1_qup4_spi_apps_clk_src",
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1528 static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1530 .halt_check = BRANCH_HALT,
1532 .enable_reg = 0x6004,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp1_uart0_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp1_uart0_apps_clk_src",
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1546 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1548 .halt_check = BRANCH_HALT,
1550 .enable_reg = 0x203c,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "gcc_blsp1_uart1_apps_clk",
1554 .parent_names = (const char *[]){
1555 "blsp1_uart1_apps_clk_src",
1558 .flags = CLK_SET_RATE_PARENT,
1559 .ops = &clk_branch2_ops,
1564 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1566 .halt_check = BRANCH_HALT,
1568 .enable_reg = 0x302c,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "gcc_blsp1_uart2_apps_clk",
1572 .parent_names = (const char *[]){
1573 "blsp1_uart2_apps_clk_src",
1576 .flags = CLK_SET_RATE_PARENT,
1577 .ops = &clk_branch2_ops,
1582 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1584 .halt_check = BRANCH_HALT,
1586 .enable_reg = 0x400c,
1587 .enable_mask = BIT(0),
1588 .hw.init = &(struct clk_init_data){
1589 .name = "gcc_blsp1_uart3_apps_clk",
1590 .parent_names = (const char *[]){
1591 "blsp1_uart3_apps_clk_src",
1594 .flags = CLK_SET_RATE_PARENT,
1595 .ops = &clk_branch2_ops,
1600 static struct clk_branch gcc_blsp2_ahb_clk = {
1602 .halt_check = BRANCH_HALT_VOTED,
1604 .enable_reg = 0x45004,
1605 .enable_mask = BIT(20),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "gcc_blsp2_ahb_clk",
1608 .ops = &clk_branch2_ops,
1613 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1615 .halt_check = BRANCH_HALT,
1617 .enable_reg = 0xc008,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp2_qup0_i2c_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp2_qup0_i2c_apps_clk_src",
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1631 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1633 .halt_check = BRANCH_HALT,
1635 .enable_reg = 0xc004,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "gcc_blsp2_qup0_spi_apps_clk",
1639 .parent_names = (const char *[]){
1640 "blsp2_qup0_spi_apps_clk_src",
1643 .flags = CLK_SET_RATE_PARENT,
1644 .ops = &clk_branch2_ops,
1649 static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1651 .halt_check = BRANCH_HALT,
1653 .enable_reg = 0xc03c,
1654 .enable_mask = BIT(0),
1655 .hw.init = &(struct clk_init_data){
1656 .name = "gcc_blsp2_uart0_apps_clk",
1657 .parent_names = (const char *[]){
1658 "blsp2_uart0_apps_clk_src",
1661 .flags = CLK_SET_RATE_PARENT,
1662 .ops = &clk_branch2_ops,
1667 static struct clk_branch gcc_boot_rom_ahb_clk = {
1668 .halt_reg = 0x1300c,
1669 .halt_check = BRANCH_HALT_VOTED,
1671 .enable_reg = 0x45004,
1672 .enable_mask = BIT(7),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gcc_boot_rom_ahb_clk",
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_crypto_ahb_clk = {
1681 .halt_reg = 0x16024,
1682 .halt_check = BRANCH_VOTED,
1684 .enable_reg = 0x45004,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_crypto_ahb_clk",
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gcc_crypto_axi_clk = {
1694 .halt_reg = 0x16020,
1695 .halt_check = BRANCH_VOTED,
1697 .enable_reg = 0x45004,
1698 .enable_mask = BIT(1),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_crypto_axi_clk",
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch gcc_crypto_clk = {
1707 .halt_reg = 0x1601c,
1708 .halt_check = BRANCH_VOTED,
1710 .enable_reg = 0x45004,
1711 .enable_mask = BIT(2),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "gcc_crypto_clk",
1714 .ops = &clk_branch2_ops,
1719 static struct clk_branch gcc_eth_axi_clk = {
1720 .halt_reg = 0x4e010,
1721 .halt_check = BRANCH_HALT,
1723 .enable_reg = 0x4e010,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "gcc_eth_axi_clk",
1727 .ops = &clk_branch2_ops,
1732 static struct clk_branch gcc_eth_ptp_clk = {
1733 .halt_reg = 0x4e004,
1734 .halt_check = BRANCH_HALT,
1736 .enable_reg = 0x4e004,
1737 .enable_mask = BIT(0),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "gcc_eth_ptp_clk",
1740 .parent_names = (const char *[]){
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1750 static struct clk_branch gcc_eth_rgmii_clk = {
1751 .halt_reg = 0x4e008,
1752 .halt_check = BRANCH_HALT,
1754 .enable_reg = 0x4e008,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_eth_rgmii_clk",
1758 .parent_names = (const char *[]){
1762 .flags = CLK_SET_RATE_PARENT,
1763 .ops = &clk_branch2_ops,
1768 static struct clk_branch gcc_eth_slave_ahb_clk = {
1769 .halt_reg = 0x4e00c,
1770 .halt_check = BRANCH_HALT,
1772 .enable_reg = 0x4e00c,
1773 .enable_mask = BIT(0),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "gcc_eth_slave_ahb_clk",
1776 .ops = &clk_branch2_ops,
1781 static struct clk_branch gcc_geni_ir_s_clk = {
1783 .halt_check = BRANCH_HALT,
1785 .enable_reg = 0xf008,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_geni_ir_s_clk",
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch gcc_geni_ir_h_clk = {
1796 .halt_check = BRANCH_HALT,
1798 .enable_reg = 0xf004,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_geni_ir_h_clk",
1802 .ops = &clk_branch2_ops,
1807 static struct clk_branch gcc_gfx_tcu_clk = {
1808 .halt_reg = 0x12020,
1809 .halt_check = BRANCH_VOTED,
1811 .enable_reg = 0x4500C,
1812 .enable_mask = BIT(2),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_gfx_tcu_clk",
1815 .ops = &clk_branch2_ops,
1820 static struct clk_branch gcc_gfx_tbu_clk = {
1821 .halt_reg = 0x12010,
1822 .halt_check = BRANCH_VOTED,
1824 .enable_reg = 0x4500C,
1825 .enable_mask = BIT(3),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "gcc_gfx_tbu_clk",
1828 .ops = &clk_branch2_ops,
1833 static struct clk_branch gcc_cdsp_tbu_clk = {
1834 .halt_reg = 0x1203c,
1835 .halt_check = BRANCH_VOTED,
1837 .enable_reg = 0x13020,
1838 .enable_mask = BIT(9),
1839 .hw.init = &(struct clk_init_data) {
1840 .name = "gcc_cdsp_tbu_clk",
1841 .parent_names = (const char *[]) {
1842 "cdsp_bimc_clk_src",
1845 .flags = CLK_SET_RATE_PARENT,
1846 .ops = &clk_branch2_ops,
1851 static struct clk_branch gcc_gp1_clk = {
1853 .halt_check = BRANCH_HALT,
1855 .enable_reg = 0x8000,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_gp1_clk",
1859 .parent_names = (const char *[]){
1863 .flags = CLK_SET_RATE_PARENT,
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch gcc_gp2_clk = {
1871 .halt_check = BRANCH_HALT,
1873 .enable_reg = 0x9000,
1874 .enable_mask = BIT(0),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_gp2_clk",
1877 .parent_names = (const char *[]){
1881 .flags = CLK_SET_RATE_PARENT,
1882 .ops = &clk_branch2_ops,
1887 static struct clk_branch gcc_gp3_clk = {
1889 .halt_check = BRANCH_HALT,
1891 .enable_reg = 0xa000,
1892 .enable_mask = BIT(0),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "gcc_gp3_clk",
1895 .parent_names = (const char *[]){
1899 .flags = CLK_SET_RATE_PARENT,
1900 .ops = &clk_branch2_ops,
1905 static struct clk_branch gcc_gtcu_ahb_clk = {
1906 .halt_reg = 0x12044,
1907 .halt_check = BRANCH_VOTED,
1909 .enable_reg = 0x4500c,
1910 .enable_mask = BIT(13),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "gcc_gtcu_ahb_clk",
1913 .ops = &clk_branch2_ops,
1918 static struct clk_branch gcc_mdp_tbu_clk = {
1919 .halt_reg = 0x1201c,
1920 .halt_check = BRANCH_VOTED,
1922 .enable_reg = 0x4500c,
1923 .enable_mask = BIT(4),
1924 .hw.init = &(struct clk_init_data){
1925 .name = "gcc_mdp_tbu_clk",
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch gcc_mdss_ahb_clk = {
1932 .halt_reg = 0x4d07c,
1933 .halt_check = BRANCH_HALT,
1935 .enable_reg = 0x4d07c,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_mdss_ahb_clk",
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_mdss_axi_clk = {
1945 .halt_reg = 0x4d080,
1946 .halt_check = BRANCH_HALT,
1948 .enable_reg = 0x4d080,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "gcc_mdss_axi_clk",
1952 .ops = &clk_branch2_ops,
1957 static struct clk_branch gcc_mdss_byte0_clk = {
1958 .halt_reg = 0x4d094,
1959 .halt_check = BRANCH_HALT,
1961 .enable_reg = 0x4d094,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "gcc_mdss_byte0_clk",
1965 .parent_names = (const char *[]){
1969 .flags = CLK_SET_RATE_PARENT,
1970 .ops = &clk_branch2_ops,
1975 static struct clk_branch gcc_mdss_esc0_clk = {
1976 .halt_reg = 0x4d098,
1977 .halt_check = BRANCH_HALT,
1979 .enable_reg = 0x4d098,
1980 .enable_mask = BIT(0),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "gcc_mdss_esc0_clk",
1983 .parent_names = (const char *[]){
1987 .flags = CLK_SET_RATE_PARENT,
1988 .ops = &clk_branch2_ops,
1993 static struct clk_branch gcc_mdss_hdmi_app_clk = {
1994 .halt_reg = 0x4d0d8,
1995 .halt_check = BRANCH_HALT,
1997 .enable_reg = 0x4d0d8,
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "gcc_mdss_hdmi_app_clk",
2001 .parent_names = (const char *[]){
2005 .flags = CLK_SET_RATE_PARENT,
2006 .ops = &clk_branch2_ops,
2011 static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
2012 .halt_reg = 0x4d0d4,
2013 .halt_check = BRANCH_HALT,
2015 .enable_reg = 0x4d0d4,
2016 .enable_mask = BIT(0),
2017 .hw.init = &(struct clk_init_data){
2018 .name = "gcc_mdss_hdmi_pclk_clk",
2019 .parent_names = (const char *[]){
2020 "hdmi_pclk_clk_src",
2023 .flags = CLK_SET_RATE_PARENT,
2024 .ops = &clk_branch2_ops,
2029 static struct clk_branch gcc_mdss_mdp_clk = {
2030 .halt_reg = 0x4d088,
2031 .halt_check = BRANCH_HALT,
2033 .enable_reg = 0x4d088,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_mdss_mdp_clk",
2037 .parent_names = (const char *[]){
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2047 static struct clk_branch gcc_mdss_pclk0_clk = {
2048 .halt_reg = 0x4d084,
2049 .halt_check = BRANCH_HALT,
2051 .enable_reg = 0x4d084,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "gcc_mdss_pclk0_clk",
2055 .parent_names = (const char *[]){
2059 .flags = CLK_SET_RATE_PARENT,
2060 .ops = &clk_branch2_ops,
2065 static struct clk_branch gcc_mdss_vsync_clk = {
2066 .halt_reg = 0x4d090,
2067 .halt_check = BRANCH_HALT,
2069 .enable_reg = 0x4d090,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "gcc_mdss_vsync_clk",
2073 .parent_names = (const char *[]){
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2083 static struct clk_branch gcc_oxili_ahb_clk = {
2084 .halt_reg = 0x59028,
2085 .halt_check = BRANCH_HALT,
2087 .enable_reg = 0x59028,
2088 .enable_mask = BIT(0),
2089 .hw.init = &(struct clk_init_data){
2090 .name = "gcc_oxili_ahb_clk",
2091 .ops = &clk_branch2_ops,
2096 static struct clk_branch gcc_oxili_gfx3d_clk = {
2097 .halt_reg = 0x59020,
2098 .halt_check = BRANCH_HALT,
2100 .enable_reg = 0x59020,
2101 .enable_mask = BIT(0),
2102 .hw.init = &(struct clk_init_data){
2103 .name = "gcc_oxili_gfx3d_clk",
2104 .parent_names = (const char *[]){
2108 .flags = CLK_SET_RATE_PARENT,
2109 .ops = &clk_branch2_ops,
2114 static struct clk_branch gcc_pcie_0_aux_clk = {
2115 .halt_reg = 0x3e014,
2116 .halt_check = BRANCH_HALT_VOTED,
2118 .enable_reg = 0x45004,
2119 .enable_mask = BIT(27),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "gcc_pcie_0_aux_clk",
2122 .parent_names = (const char *[]){
2123 "pcie_0_aux_clk_src",
2126 .flags = CLK_SET_RATE_PARENT,
2127 .ops = &clk_branch2_ops,
2132 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2133 .halt_reg = 0x3e008,
2134 .halt_check = BRANCH_HALT_VOTED,
2136 .enable_reg = 0x45004,
2137 .enable_mask = BIT(11),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_pcie_0_cfg_ahb_clk",
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2146 .halt_reg = 0x3e018,
2147 .halt_check = BRANCH_HALT_VOTED,
2149 .enable_reg = 0x45004,
2150 .enable_mask = BIT(18),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_pcie_0_mstr_axi_clk",
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_pcie_0_pipe_clk = {
2159 .halt_reg = 0x3e00c,
2160 .halt_check = BRANCH_HALT_VOTED,
2162 .enable_reg = 0x45004,
2163 .enable_mask = BIT(28),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gcc_pcie_0_pipe_clk",
2166 .parent_names = (const char *[]){
2167 "pcie_0_pipe_clk_src",
2170 .flags = CLK_SET_RATE_PARENT,
2171 .ops = &clk_branch2_ops,
2176 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2177 .halt_reg = 0x3e010,
2178 .halt_check = BRANCH_HALT_VOTED,
2180 .enable_reg = 0x45004,
2181 .enable_mask = BIT(22),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "gcc_pcie_0_slv_axi_clk",
2184 .ops = &clk_branch2_ops,
2189 static struct clk_branch gcc_pcnoc_usb2_clk = {
2190 .halt_reg = 0x27008,
2191 .halt_check = BRANCH_HALT,
2193 .enable_reg = 0x27008,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_pcnoc_usb2_clk",
2197 .flags = CLK_IS_CRITICAL,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_pcnoc_usb3_clk = {
2204 .halt_reg = 0x2700c,
2205 .halt_check = BRANCH_HALT,
2207 .enable_reg = 0x2700c,
2208 .enable_mask = BIT(0),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_pcnoc_usb3_clk",
2211 .flags = CLK_IS_CRITICAL,
2212 .ops = &clk_branch2_ops,
2217 static struct clk_branch gcc_pdm2_clk = {
2218 .halt_reg = 0x4400c,
2219 .halt_check = BRANCH_HALT,
2221 .enable_reg = 0x4400c,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_pdm2_clk",
2225 .parent_names = (const char *[]){
2229 .flags = CLK_SET_RATE_PARENT,
2230 .ops = &clk_branch2_ops,
2235 static struct clk_branch gcc_pdm_ahb_clk = {
2236 .halt_reg = 0x44004,
2237 .halt_check = BRANCH_HALT,
2239 .enable_reg = 0x44004,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "gcc_pdm_ahb_clk",
2243 .ops = &clk_branch2_ops,
2248 static struct clk_branch gcc_prng_ahb_clk = {
2249 .halt_reg = 0x13004,
2250 .halt_check = BRANCH_HALT_VOTED,
2252 .enable_reg = 0x45004,
2253 .enable_mask = BIT(8),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_prng_ahb_clk",
2256 .ops = &clk_branch2_ops,
2261 /* PWM clks do not have XO as parent as src clk is a balance root */
2262 static struct clk_branch gcc_pwm0_xo512_clk = {
2263 .halt_reg = 0x44018,
2264 .halt_check = BRANCH_HALT,
2266 .enable_reg = 0x44018,
2267 .enable_mask = BIT(0),
2268 .hw.init = &(struct clk_init_data){
2269 .name = "gcc_pwm0_xo512_clk",
2270 .ops = &clk_branch2_ops,
2275 static struct clk_branch gcc_pwm1_xo512_clk = {
2276 .halt_reg = 0x49004,
2277 .halt_check = BRANCH_HALT,
2279 .enable_reg = 0x49004,
2280 .enable_mask = BIT(0),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "gcc_pwm1_xo512_clk",
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch gcc_pwm2_xo512_clk = {
2289 .halt_reg = 0x4a004,
2290 .halt_check = BRANCH_HALT,
2292 .enable_reg = 0x4a004,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_pwm2_xo512_clk",
2296 .ops = &clk_branch2_ops,
2301 static struct clk_branch gcc_qdss_dap_clk = {
2302 .halt_reg = 0x29084,
2303 .halt_check = BRANCH_VOTED,
2305 .enable_reg = 0x45004,
2306 .enable_mask = BIT(21),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "gcc_qdss_dap_clk",
2309 .ops = &clk_branch2_ops,
2314 static struct clk_branch gcc_sdcc1_ahb_clk = {
2315 .halt_reg = 0x4201c,
2316 .halt_check = BRANCH_HALT,
2318 .enable_reg = 0x4201c,
2319 .enable_mask = BIT(0),
2320 .hw.init = &(struct clk_init_data){
2321 .name = "gcc_sdcc1_ahb_clk",
2322 .ops = &clk_branch2_ops,
2327 static struct clk_branch gcc_sdcc1_apps_clk = {
2328 .halt_reg = 0x42018,
2329 .halt_check = BRANCH_HALT,
2331 .enable_reg = 0x42018,
2332 .enable_mask = BIT(0),
2333 .hw.init = &(struct clk_init_data){
2334 .name = "gcc_sdcc1_apps_clk",
2335 .parent_names = (const char *[]){
2336 "sdcc1_apps_clk_src",
2339 .flags = CLK_SET_RATE_PARENT,
2340 .ops = &clk_branch2_ops,
2345 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2346 .halt_reg = 0x5d014,
2347 .halt_check = BRANCH_HALT,
2349 .enable_reg = 0x5d014,
2350 .enable_mask = BIT(0),
2351 .hw.init = &(struct clk_init_data){
2352 .name = "gcc_sdcc1_ice_core_clk",
2353 .parent_names = (const char *[]){
2354 "sdcc1_ice_core_clk_src",
2357 .flags = CLK_SET_RATE_PARENT,
2358 .ops = &clk_branch2_ops,
2363 static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
2364 .halt_reg = 0x5e004,
2365 .halt_check = BRANCH_HALT,
2367 .enable_reg = 0x5e004,
2368 .enable_mask = BIT(0),
2369 .hw.init = &(struct clk_init_data) {
2370 .name = "gcc_cdsp_cfg_ahb_cbcr",
2371 .ops = &clk_branch2_ops,
2376 static struct clk_branch gcc_sdcc2_ahb_clk = {
2377 .halt_reg = 0x4301c,
2378 .halt_check = BRANCH_HALT,
2380 .enable_reg = 0x4301c,
2381 .enable_mask = BIT(0),
2382 .hw.init = &(struct clk_init_data){
2383 .name = "gcc_sdcc2_ahb_clk",
2384 .ops = &clk_branch2_ops,
2389 static struct clk_branch gcc_sdcc2_apps_clk = {
2390 .halt_reg = 0x43018,
2391 .halt_check = BRANCH_HALT,
2393 .enable_reg = 0x43018,
2394 .enable_mask = BIT(0),
2395 .hw.init = &(struct clk_init_data){
2396 .name = "gcc_sdcc2_apps_clk",
2397 .parent_names = (const char *[]){
2398 "sdcc2_apps_clk_src",
2401 .flags = CLK_SET_RATE_PARENT,
2402 .ops = &clk_branch2_ops,
2407 static struct clk_branch gcc_smmu_cfg_clk = {
2408 .halt_reg = 0x12038,
2409 .halt_check = BRANCH_VOTED,
2411 .enable_reg = 0x3600C,
2412 .enable_mask = BIT(12),
2413 .hw.init = &(struct clk_init_data){
2414 .name = "gcc_smmu_cfg_clk",
2415 .ops = &clk_branch2_ops,
2420 static struct clk_branch gcc_sys_noc_usb3_clk = {
2421 .halt_reg = 0x26014,
2422 .halt_check = BRANCH_HALT,
2424 .enable_reg = 0x26014,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_sys_noc_usb3_clk",
2428 .parent_names = (const char *[]){
2429 "usb30_master_clk_src",
2432 .ops = &clk_branch2_ops,
2437 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2438 .halt_reg = 0x4100C,
2439 .halt_check = BRANCH_HALT,
2441 .enable_reg = 0x4100C,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "gcc_usb_hs_inactivity_timers_clk",
2445 .ops = &clk_branch2_ops,
2450 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2451 .halt_reg = 0x41044,
2452 .halt_check = BRANCH_HALT,
2454 .enable_reg = 0x41044,
2455 .enable_mask = BIT(0),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "gcc_usb20_mock_utmi_clk",
2458 .parent_names = (const char *[]){
2459 "usb20_mock_utmi_clk_src",
2462 .flags = CLK_SET_RATE_PARENT,
2463 .ops = &clk_branch2_ops,
2468 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2469 .halt_reg = 0x4102c,
2470 .halt_check = BRANCH_HALT,
2472 .enable_reg = 0x4102c,
2473 .enable_mask = BIT(0),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_usb2a_phy_sleep_clk",
2476 .ops = &clk_branch2_ops,
2481 static struct clk_branch gcc_usb30_master_clk = {
2482 .halt_reg = 0x3900c,
2483 .halt_check = BRANCH_HALT,
2485 .enable_reg = 0x3900c,
2486 .enable_mask = BIT(0),
2487 .hw.init = &(struct clk_init_data){
2488 .name = "gcc_usb30_master_clk",
2489 .parent_names = (const char *[]){
2490 "usb30_master_clk_src",
2493 .flags = CLK_SET_RATE_PARENT,
2494 .ops = &clk_branch2_ops,
2499 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2500 .halt_reg = 0x39014,
2501 .halt_check = BRANCH_HALT,
2503 .enable_reg = 0x39014,
2504 .enable_mask = BIT(0),
2505 .hw.init = &(struct clk_init_data){
2506 .name = "gcc_usb30_mock_utmi_clk",
2507 .parent_names = (const char *[]){
2508 "usb30_mock_utmi_clk_src",
2511 .flags = CLK_SET_RATE_PARENT,
2512 .ops = &clk_branch2_ops,
2517 static struct clk_branch gcc_usb30_sleep_clk = {
2518 .halt_reg = 0x39010,
2519 .halt_check = BRANCH_HALT,
2521 .enable_reg = 0x39010,
2522 .enable_mask = BIT(0),
2523 .hw.init = &(struct clk_init_data){
2524 .name = "gcc_usb30_sleep_clk",
2525 .ops = &clk_branch2_ops,
2530 static struct clk_branch gcc_usb3_phy_aux_clk = {
2531 .halt_reg = 0x39044,
2532 .halt_check = BRANCH_HALT,
2534 .enable_reg = 0x39044,
2535 .enable_mask = BIT(0),
2536 .hw.init = &(struct clk_init_data){
2537 .name = "gcc_usb3_phy_aux_clk",
2538 .parent_names = (const char *[]){
2539 "usb3_phy_aux_clk_src",
2542 .flags = CLK_SET_RATE_PARENT,
2543 .ops = &clk_branch2_ops,
2548 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2549 .halt_check = BRANCH_HALT_SKIP,
2551 .enable_reg = 0x39018,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_usb3_phy_pipe_clk",
2555 .ops = &clk_branch2_ops,
2560 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2561 .halt_reg = 0x41030,
2562 .halt_check = BRANCH_HALT,
2564 .enable_reg = 0x41030,
2565 .enable_mask = BIT(0),
2566 .hw.init = &(struct clk_init_data){
2567 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2568 .ops = &clk_branch2_ops,
2573 static struct clk_branch gcc_usb_hs_system_clk = {
2574 .halt_reg = 0x41004,
2575 .halt_check = BRANCH_HALT,
2577 .enable_reg = 0x41004,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "gcc_usb_hs_system_clk",
2581 .parent_names = (const char *[]){
2582 "usb_hs_system_clk_src",
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2591 static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2592 .halt_reg = 0x1e004,
2593 .halt_check = BRANCH_HALT,
2595 .enable_reg = 0x1e004,
2596 .enable_mask = BIT(0),
2597 .hw.init = &(struct clk_init_data){
2598 .name = "gcc_wdsp_q6ss_ahbs_clk",
2599 .ops = &clk_branch2_ops,
2604 static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2605 .halt_reg = 0x1e008,
2606 .halt_check = BRANCH_HALT,
2608 .enable_reg = 0x1e008,
2609 .enable_mask = BIT(0),
2610 .hw.init = &(struct clk_init_data){
2611 .name = "gcc_wdsp_q6ss_axim_clk",
2612 .ops = &clk_branch2_ops,
2617 static struct clk_hw *gcc_qcs404_hws[] = {
2621 static struct clk_regmap *gcc_qcs404_clocks[] = {
2622 [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2623 [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2624 [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2625 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2626 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2627 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2628 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2629 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2630 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2631 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2632 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2633 [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2634 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2635 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2636 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2637 [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2638 [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2639 [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2640 [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2641 [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2642 [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2643 [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2644 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2645 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2646 [GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2647 [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2648 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2649 [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2650 [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2651 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2652 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2653 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2654 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2655 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2656 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2657 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2658 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2659 [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2660 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2661 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2662 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2663 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2664 [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2665 [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2666 [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2667 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2668 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2669 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2670 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2671 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2672 [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2673 [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2674 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2675 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2676 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2677 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2678 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2679 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2680 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2681 [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2682 [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2683 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2684 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2685 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2686 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2687 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2688 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2689 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2690 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2691 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2692 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2693 [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2694 [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2695 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2696 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2697 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2698 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2699 [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2700 [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2701 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2702 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2703 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2704 [GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2705 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2706 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2707 [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2708 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2709 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2710 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2711 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2712 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2713 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2714 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2715 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2716 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2717 [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2718 [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2719 [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2720 [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2721 [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2722 [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2723 [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2724 [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2725 [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2726 [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2727 [GCC_GPLL6] = &gpll6.clkr,
2728 [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2729 [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2730 [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2731 [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2732 [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2733 [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2734 [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2735 [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2736 [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2737 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2738 [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2739 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2740 [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2741 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2742 [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2743 [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2744 [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2745 [GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2746 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2747 &gcc_usb_hs_inactivity_timers_clk.clkr,
2748 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2749 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2750 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2751 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2752 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2753 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2754 [GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2755 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2756 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2757 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2758 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2759 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2760 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2761 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2762 [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2763 [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2767 static const struct qcom_reset_map gcc_qcs404_resets[] = {
2768 [GCC_GENI_IR_BCR] = { 0x0F000 },
2769 [GCC_CDSP_RESTART] = { 0x18000 },
2770 [GCC_USB_HS_BCR] = { 0x41000 },
2771 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2772 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2773 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2774 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2775 [GCC_USB3_PHY_BCR] = { 0x39004 },
2776 [GCC_USB_30_BCR] = { 0x39000 },
2777 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2778 [GCC_PCIE_0_BCR] = { 0x3e000 },
2779 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2780 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2781 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2782 [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2783 [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2784 [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2785 [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2786 [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2787 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2788 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2789 [GCC_EMAC_BCR] = { 0x4e000 },
2790 [GCC_WDSP_RESTART] = {0x19000},
2793 static const struct regmap_config gcc_qcs404_regmap_config = {
2797 .max_register = 0x7f000,
2801 static const struct qcom_cc_desc gcc_qcs404_desc = {
2802 .config = &gcc_qcs404_regmap_config,
2803 .clks = gcc_qcs404_clocks,
2804 .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2805 .resets = gcc_qcs404_resets,
2806 .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2807 .clk_hws = gcc_qcs404_hws,
2808 .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
2811 static const struct of_device_id gcc_qcs404_match_table[] = {
2812 { .compatible = "qcom,gcc-qcs404" },
2815 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2817 static int gcc_qcs404_probe(struct platform_device *pdev)
2819 struct regmap *regmap;
2821 regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2823 return PTR_ERR(regmap);
2825 clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2827 return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
2830 static struct platform_driver gcc_qcs404_driver = {
2831 .probe = gcc_qcs404_probe,
2833 .name = "gcc-qcs404",
2834 .of_match_table = gcc_qcs404_match_table,
2838 static int __init gcc_qcs404_init(void)
2840 return platform_driver_register(&gcc_qcs404_driver);
2842 core_initcall(gcc_qcs404_init);
2844 static void __exit gcc_qcs404_exit(void)
2846 platform_driver_unregister(&gcc_qcs404_driver);
2848 module_exit(gcc_qcs404_exit);
2850 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2851 MODULE_LICENSE("GPL v2");