2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
28 #include "clk-regmap.h"
29 #include "clk-alpha-pll.h"
31 #include "clk-branch.h"
35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
51 static const struct parent_map gcc_sleep_clk_map[] = {
55 static const char * const gcc_sleep_clk[] = {
59 static const struct parent_map gcc_xo_gpll0_map[] = {
64 static const char * const gcc_xo_gpll0[] = {
69 static const struct parent_map gcc_xo_sleep_clk_map[] = {
74 static const char * const gcc_xo_sleep_clk[] = {
79 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
82 { P_GPLL0_EARLY_DIV, 6 }
85 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
91 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
97 static const char * const gcc_xo_gpll0_gpll4[] = {
103 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
109 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
115 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
119 { P_GPLL0_EARLY_DIV, 6 }
122 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
129 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
133 { P_GPLL0_EARLY_DIV, 6 }
136 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
143 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
146 { P_GPLL1_EARLY_DIV, 3 },
149 { P_GPLL0_EARLY_DIV, 6 }
152 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
161 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
167 { P_GPLL2_EARLY, 5 },
168 { P_GPLL0_EARLY_DIV, 6 }
171 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
181 static struct clk_fixed_factor xo = {
184 .hw.init = &(struct clk_init_data){
186 .parent_names = (const char *[]){ "xo_board" },
188 .ops = &clk_fixed_factor_ops,
192 static struct clk_alpha_pll gpll0_early = {
195 .enable_reg = 0x52000,
196 .enable_mask = BIT(0),
197 .hw.init = &(struct clk_init_data){
198 .name = "gpll0_early",
199 .parent_names = (const char *[]){ "xo" },
201 .ops = &clk_alpha_pll_ops,
206 static struct clk_fixed_factor gpll0_early_div = {
209 .hw.init = &(struct clk_init_data){
210 .name = "gpll0_early_div",
211 .parent_names = (const char *[]){ "gpll0_early" },
213 .ops = &clk_fixed_factor_ops,
217 static struct clk_alpha_pll_postdiv gpll0 = {
219 .clkr.hw.init = &(struct clk_init_data){
221 .parent_names = (const char *[]){ "gpll0_early" },
223 .ops = &clk_alpha_pll_postdiv_ops,
227 static struct clk_alpha_pll gpll4_early = {
230 .enable_reg = 0x52000,
231 .enable_mask = BIT(4),
232 .hw.init = &(struct clk_init_data){
233 .name = "gpll4_early",
234 .parent_names = (const char *[]){ "xo" },
236 .ops = &clk_alpha_pll_ops,
241 static struct clk_alpha_pll_postdiv gpll4 = {
243 .clkr.hw.init = &(struct clk_init_data){
245 .parent_names = (const char *[]){ "gpll4_early" },
247 .ops = &clk_alpha_pll_postdiv_ops,
251 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
252 F(19200000, P_XO, 1, 0, 0),
253 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
254 F(100000000, P_GPLL0, 6, 0, 0),
255 F(150000000, P_GPLL0, 4, 0, 0),
256 F(200000000, P_GPLL0, 3, 0, 0),
257 F(240000000, P_GPLL0, 2.5, 0, 0),
261 static struct clk_rcg2 system_noc_clk_src = {
264 .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
265 .freq_tbl = ftbl_system_noc_clk_src,
266 .clkr.hw.init = &(struct clk_init_data){
267 .name = "system_noc_clk_src",
268 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
270 .ops = &clk_rcg2_ops,
274 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
275 F(19200000, P_XO, 1, 0, 0),
276 F(37500000, P_GPLL0, 16, 0, 0),
277 F(75000000, P_GPLL0, 8, 0, 0),
281 static struct clk_rcg2 config_noc_clk_src = {
284 .parent_map = gcc_xo_gpll0_map,
285 .freq_tbl = ftbl_config_noc_clk_src,
286 .clkr.hw.init = &(struct clk_init_data){
287 .name = "config_noc_clk_src",
288 .parent_names = gcc_xo_gpll0,
290 .ops = &clk_rcg2_ops,
294 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
295 F(19200000, P_XO, 1, 0, 0),
296 F(37500000, P_GPLL0, 16, 0, 0),
297 F(50000000, P_GPLL0, 12, 0, 0),
298 F(75000000, P_GPLL0, 8, 0, 0),
299 F(100000000, P_GPLL0, 6, 0, 0),
303 static struct clk_rcg2 periph_noc_clk_src = {
306 .parent_map = gcc_xo_gpll0_map,
307 .freq_tbl = ftbl_periph_noc_clk_src,
308 .clkr.hw.init = &(struct clk_init_data){
309 .name = "periph_noc_clk_src",
310 .parent_names = gcc_xo_gpll0,
312 .ops = &clk_rcg2_ops,
316 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
317 F(19200000, P_XO, 1, 0, 0),
318 F(120000000, P_GPLL0, 5, 0, 0),
319 F(150000000, P_GPLL0, 4, 0, 0),
323 static struct clk_rcg2 usb30_master_clk_src = {
327 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
328 .freq_tbl = ftbl_usb30_master_clk_src,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "usb30_master_clk_src",
331 .parent_names = gcc_xo_gpll0_gpll0_early_div,
333 .ops = &clk_rcg2_ops,
337 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
338 F(19200000, P_XO, 1, 0, 0),
342 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
345 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
346 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "usb30_mock_utmi_clk_src",
349 .parent_names = gcc_xo_gpll0_gpll0_early_div,
351 .ops = &clk_rcg2_ops,
355 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
356 F(1200000, P_XO, 16, 0, 0),
360 static struct clk_rcg2 usb3_phy_aux_clk_src = {
363 .parent_map = gcc_xo_sleep_clk_map,
364 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
365 .clkr.hw.init = &(struct clk_init_data){
366 .name = "usb3_phy_aux_clk_src",
367 .parent_names = gcc_xo_sleep_clk,
369 .ops = &clk_rcg2_ops,
373 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
374 F(120000000, P_GPLL0, 5, 0, 0),
378 static struct clk_rcg2 usb20_master_clk_src = {
382 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
383 .freq_tbl = ftbl_usb20_master_clk_src,
384 .clkr.hw.init = &(struct clk_init_data){
385 .name = "usb20_master_clk_src",
386 .parent_names = gcc_xo_gpll0_gpll0_early_div,
388 .ops = &clk_rcg2_ops,
392 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
395 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
396 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
397 .clkr.hw.init = &(struct clk_init_data){
398 .name = "usb20_mock_utmi_clk_src",
399 .parent_names = gcc_xo_gpll0_gpll0_early_div,
401 .ops = &clk_rcg2_ops,
405 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
406 F(144000, P_XO, 16, 3, 25),
407 F(400000, P_XO, 12, 1, 4),
408 F(20000000, P_GPLL0, 15, 1, 2),
409 F(25000000, P_GPLL0, 12, 1, 2),
410 F(50000000, P_GPLL0, 12, 0, 0),
411 F(96000000, P_GPLL4, 4, 0, 0),
412 F(192000000, P_GPLL4, 2, 0, 0),
413 F(384000000, P_GPLL4, 1, 0, 0),
417 static struct clk_rcg2 sdcc1_apps_clk_src = {
421 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
422 .freq_tbl = ftbl_sdcc1_apps_clk_src,
423 .clkr.hw.init = &(struct clk_init_data){
424 .name = "sdcc1_apps_clk_src",
425 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
427 .ops = &clk_rcg2_floor_ops,
431 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
432 F(19200000, P_XO, 1, 0, 0),
433 F(150000000, P_GPLL0, 4, 0, 0),
434 F(300000000, P_GPLL0, 2, 0, 0),
438 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
441 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
442 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
443 .clkr.hw.init = &(struct clk_init_data){
444 .name = "sdcc1_ice_core_clk_src",
445 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
447 .ops = &clk_rcg2_ops,
451 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
452 F(144000, P_XO, 16, 3, 25),
453 F(400000, P_XO, 12, 1, 4),
454 F(20000000, P_GPLL0, 15, 1, 2),
455 F(25000000, P_GPLL0, 12, 1, 2),
456 F(50000000, P_GPLL0, 12, 0, 0),
457 F(100000000, P_GPLL0, 6, 0, 0),
458 F(200000000, P_GPLL0, 3, 0, 0),
462 static struct clk_rcg2 sdcc2_apps_clk_src = {
466 .parent_map = gcc_xo_gpll0_gpll4_map,
467 .freq_tbl = ftbl_sdcc2_apps_clk_src,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "sdcc2_apps_clk_src",
470 .parent_names = gcc_xo_gpll0_gpll4,
472 .ops = &clk_rcg2_floor_ops,
476 static struct clk_rcg2 sdcc3_apps_clk_src = {
480 .parent_map = gcc_xo_gpll0_gpll4_map,
481 .freq_tbl = ftbl_sdcc2_apps_clk_src,
482 .clkr.hw.init = &(struct clk_init_data){
483 .name = "sdcc3_apps_clk_src",
484 .parent_names = gcc_xo_gpll0_gpll4,
486 .ops = &clk_rcg2_floor_ops,
490 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
491 F(144000, P_XO, 16, 3, 25),
492 F(400000, P_XO, 12, 1, 4),
493 F(20000000, P_GPLL0, 15, 1, 2),
494 F(25000000, P_GPLL0, 12, 1, 2),
495 F(50000000, P_GPLL0, 12, 0, 0),
496 F(100000000, P_GPLL0, 6, 0, 0),
500 static struct clk_rcg2 sdcc4_apps_clk_src = {
504 .parent_map = gcc_xo_gpll0_map,
505 .freq_tbl = ftbl_sdcc4_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "sdcc4_apps_clk_src",
508 .parent_names = gcc_xo_gpll0,
510 .ops = &clk_rcg2_floor_ops,
514 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
515 F(960000, P_XO, 10, 1, 2),
516 F(4800000, P_XO, 4, 0, 0),
517 F(9600000, P_XO, 2, 0, 0),
518 F(15000000, P_GPLL0, 10, 1, 4),
519 F(19200000, P_XO, 1, 0, 0),
520 F(25000000, P_GPLL0, 12, 1, 2),
521 F(50000000, P_GPLL0, 12, 0, 0),
525 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
529 .parent_map = gcc_xo_gpll0_map,
530 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "blsp1_qup1_spi_apps_clk_src",
533 .parent_names = gcc_xo_gpll0,
535 .ops = &clk_rcg2_ops,
539 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
540 F(19200000, P_XO, 1, 0, 0),
541 F(50000000, P_GPLL0, 12, 0, 0),
545 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
548 .parent_map = gcc_xo_gpll0_map,
549 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "blsp1_qup1_i2c_apps_clk_src",
552 .parent_names = gcc_xo_gpll0,
554 .ops = &clk_rcg2_ops,
558 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
559 F(3686400, P_GPLL0, 1, 96, 15625),
560 F(7372800, P_GPLL0, 1, 192, 15625),
561 F(14745600, P_GPLL0, 1, 384, 15625),
562 F(16000000, P_GPLL0, 5, 2, 15),
563 F(19200000, P_XO, 1, 0, 0),
564 F(24000000, P_GPLL0, 5, 1, 5),
565 F(32000000, P_GPLL0, 1, 4, 75),
566 F(40000000, P_GPLL0, 15, 0, 0),
567 F(46400000, P_GPLL0, 1, 29, 375),
568 F(48000000, P_GPLL0, 12.5, 0, 0),
569 F(51200000, P_GPLL0, 1, 32, 375),
570 F(56000000, P_GPLL0, 1, 7, 75),
571 F(58982400, P_GPLL0, 1, 1536, 15625),
572 F(60000000, P_GPLL0, 10, 0, 0),
573 F(63157895, P_GPLL0, 9.5, 0, 0),
577 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
581 .parent_map = gcc_xo_gpll0_map,
582 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "blsp1_uart1_apps_clk_src",
585 .parent_names = gcc_xo_gpll0,
587 .ops = &clk_rcg2_ops,
591 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
595 .parent_map = gcc_xo_gpll0_map,
596 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "blsp1_qup2_spi_apps_clk_src",
599 .parent_names = gcc_xo_gpll0,
601 .ops = &clk_rcg2_ops,
605 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "blsp1_qup2_i2c_apps_clk_src",
612 .parent_names = gcc_xo_gpll0,
614 .ops = &clk_rcg2_ops,
618 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "blsp1_uart2_apps_clk_src",
626 .parent_names = gcc_xo_gpll0,
628 .ops = &clk_rcg2_ops,
632 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
636 .parent_map = gcc_xo_gpll0_map,
637 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "blsp1_qup3_spi_apps_clk_src",
640 .parent_names = gcc_xo_gpll0,
642 .ops = &clk_rcg2_ops,
646 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
649 .parent_map = gcc_xo_gpll0_map,
650 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "blsp1_qup3_i2c_apps_clk_src",
653 .parent_names = gcc_xo_gpll0,
655 .ops = &clk_rcg2_ops,
659 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
663 .parent_map = gcc_xo_gpll0_map,
664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "blsp1_uart3_apps_clk_src",
667 .parent_names = gcc_xo_gpll0,
669 .ops = &clk_rcg2_ops,
673 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
677 .parent_map = gcc_xo_gpll0_map,
678 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "blsp1_qup4_spi_apps_clk_src",
681 .parent_names = gcc_xo_gpll0,
683 .ops = &clk_rcg2_ops,
687 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
690 .parent_map = gcc_xo_gpll0_map,
691 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "blsp1_qup4_i2c_apps_clk_src",
694 .parent_names = gcc_xo_gpll0,
696 .ops = &clk_rcg2_ops,
700 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
704 .parent_map = gcc_xo_gpll0_map,
705 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
706 .clkr.hw.init = &(struct clk_init_data){
707 .name = "blsp1_uart4_apps_clk_src",
708 .parent_names = gcc_xo_gpll0,
710 .ops = &clk_rcg2_ops,
714 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
718 .parent_map = gcc_xo_gpll0_map,
719 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
720 .clkr.hw.init = &(struct clk_init_data){
721 .name = "blsp1_qup5_spi_apps_clk_src",
722 .parent_names = gcc_xo_gpll0,
724 .ops = &clk_rcg2_ops,
728 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
731 .parent_map = gcc_xo_gpll0_map,
732 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "blsp1_qup5_i2c_apps_clk_src",
735 .parent_names = gcc_xo_gpll0,
737 .ops = &clk_rcg2_ops,
741 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "blsp1_uart5_apps_clk_src",
749 .parent_names = gcc_xo_gpll0,
751 .ops = &clk_rcg2_ops,
755 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
759 .parent_map = gcc_xo_gpll0_map,
760 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
761 .clkr.hw.init = &(struct clk_init_data){
762 .name = "blsp1_qup6_spi_apps_clk_src",
763 .parent_names = gcc_xo_gpll0,
765 .ops = &clk_rcg2_ops,
769 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
772 .parent_map = gcc_xo_gpll0_map,
773 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "blsp1_qup6_i2c_apps_clk_src",
776 .parent_names = gcc_xo_gpll0,
778 .ops = &clk_rcg2_ops,
782 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
786 .parent_map = gcc_xo_gpll0_map,
787 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "blsp1_uart6_apps_clk_src",
790 .parent_names = gcc_xo_gpll0,
792 .ops = &clk_rcg2_ops,
796 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
800 .parent_map = gcc_xo_gpll0_map,
801 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
802 .clkr.hw.init = &(struct clk_init_data){
803 .name = "blsp2_qup1_spi_apps_clk_src",
804 .parent_names = gcc_xo_gpll0,
806 .ops = &clk_rcg2_ops,
810 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
813 .parent_map = gcc_xo_gpll0_map,
814 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "blsp2_qup1_i2c_apps_clk_src",
817 .parent_names = gcc_xo_gpll0,
819 .ops = &clk_rcg2_ops,
823 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
827 .parent_map = gcc_xo_gpll0_map,
828 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "blsp2_uart1_apps_clk_src",
831 .parent_names = gcc_xo_gpll0,
833 .ops = &clk_rcg2_ops,
837 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
841 .parent_map = gcc_xo_gpll0_map,
842 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
843 .clkr.hw.init = &(struct clk_init_data){
844 .name = "blsp2_qup2_spi_apps_clk_src",
845 .parent_names = gcc_xo_gpll0,
847 .ops = &clk_rcg2_ops,
851 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
854 .parent_map = gcc_xo_gpll0_map,
855 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "blsp2_qup2_i2c_apps_clk_src",
858 .parent_names = gcc_xo_gpll0,
860 .ops = &clk_rcg2_ops,
864 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
868 .parent_map = gcc_xo_gpll0_map,
869 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "blsp2_uart2_apps_clk_src",
872 .parent_names = gcc_xo_gpll0,
874 .ops = &clk_rcg2_ops,
878 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
882 .parent_map = gcc_xo_gpll0_map,
883 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
884 .clkr.hw.init = &(struct clk_init_data){
885 .name = "blsp2_qup3_spi_apps_clk_src",
886 .parent_names = gcc_xo_gpll0,
888 .ops = &clk_rcg2_ops,
892 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
895 .parent_map = gcc_xo_gpll0_map,
896 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "blsp2_qup3_i2c_apps_clk_src",
899 .parent_names = gcc_xo_gpll0,
901 .ops = &clk_rcg2_ops,
905 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
909 .parent_map = gcc_xo_gpll0_map,
910 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "blsp2_uart3_apps_clk_src",
913 .parent_names = gcc_xo_gpll0,
915 .ops = &clk_rcg2_ops,
919 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
923 .parent_map = gcc_xo_gpll0_map,
924 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "blsp2_qup4_spi_apps_clk_src",
927 .parent_names = gcc_xo_gpll0,
929 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
936 .parent_map = gcc_xo_gpll0_map,
937 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "blsp2_qup4_i2c_apps_clk_src",
940 .parent_names = gcc_xo_gpll0,
942 .ops = &clk_rcg2_ops,
946 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
950 .parent_map = gcc_xo_gpll0_map,
951 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "blsp2_uart4_apps_clk_src",
954 .parent_names = gcc_xo_gpll0,
956 .ops = &clk_rcg2_ops,
960 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
964 .parent_map = gcc_xo_gpll0_map,
965 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
966 .clkr.hw.init = &(struct clk_init_data){
967 .name = "blsp2_qup5_spi_apps_clk_src",
968 .parent_names = gcc_xo_gpll0,
970 .ops = &clk_rcg2_ops,
974 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
977 .parent_map = gcc_xo_gpll0_map,
978 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "blsp2_qup5_i2c_apps_clk_src",
981 .parent_names = gcc_xo_gpll0,
983 .ops = &clk_rcg2_ops,
987 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
991 .parent_map = gcc_xo_gpll0_map,
992 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
993 .clkr.hw.init = &(struct clk_init_data){
994 .name = "blsp2_uart5_apps_clk_src",
995 .parent_names = gcc_xo_gpll0,
997 .ops = &clk_rcg2_ops,
1001 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1002 .cmd_rcgr = 0x3000c,
1005 .parent_map = gcc_xo_gpll0_map,
1006 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1007 .clkr.hw.init = &(struct clk_init_data){
1008 .name = "blsp2_qup6_spi_apps_clk_src",
1009 .parent_names = gcc_xo_gpll0,
1011 .ops = &clk_rcg2_ops,
1015 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1016 .cmd_rcgr = 0x30020,
1018 .parent_map = gcc_xo_gpll0_map,
1019 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "blsp2_qup6_i2c_apps_clk_src",
1022 .parent_names = gcc_xo_gpll0,
1024 .ops = &clk_rcg2_ops,
1028 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1029 .cmd_rcgr = 0x3100c,
1032 .parent_map = gcc_xo_gpll0_map,
1033 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1034 .clkr.hw.init = &(struct clk_init_data){
1035 .name = "blsp2_uart6_apps_clk_src",
1036 .parent_names = gcc_xo_gpll0,
1038 .ops = &clk_rcg2_ops,
1042 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1043 F(60000000, P_GPLL0, 10, 0, 0),
1047 static struct clk_rcg2 pdm2_clk_src = {
1048 .cmd_rcgr = 0x33010,
1050 .parent_map = gcc_xo_gpll0_map,
1051 .freq_tbl = ftbl_pdm2_clk_src,
1052 .clkr.hw.init = &(struct clk_init_data){
1053 .name = "pdm2_clk_src",
1054 .parent_names = gcc_xo_gpll0,
1056 .ops = &clk_rcg2_ops,
1060 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1061 F(105495, P_XO, 1, 1, 182),
1065 static struct clk_rcg2 tsif_ref_clk_src = {
1066 .cmd_rcgr = 0x36010,
1069 .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1070 .freq_tbl = ftbl_tsif_ref_clk_src,
1071 .clkr.hw.init = &(struct clk_init_data){
1072 .name = "tsif_ref_clk_src",
1073 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1075 .ops = &clk_rcg2_ops,
1079 static struct clk_rcg2 gcc_sleep_clk_src = {
1080 .cmd_rcgr = 0x43014,
1082 .parent_map = gcc_sleep_clk_map,
1083 .clkr.hw.init = &(struct clk_init_data){
1084 .name = "gcc_sleep_clk_src",
1085 .parent_names = gcc_sleep_clk,
1087 .ops = &clk_rcg2_ops,
1091 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1092 .cmd_rcgr = 0x48040,
1094 .parent_map = gcc_xo_gpll0_map,
1095 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "hmss_rbcpr_clk_src",
1098 .parent_names = gcc_xo_gpll0,
1100 .ops = &clk_rcg2_ops,
1104 static struct clk_rcg2 hmss_gpll0_clk_src = {
1105 .cmd_rcgr = 0x48058,
1107 .parent_map = gcc_xo_gpll0_map,
1108 .clkr.hw.init = &(struct clk_init_data){
1109 .name = "hmss_gpll0_clk_src",
1110 .parent_names = gcc_xo_gpll0,
1112 .ops = &clk_rcg2_ops,
1116 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1117 F(19200000, P_XO, 1, 0, 0),
1118 F(100000000, P_GPLL0, 6, 0, 0),
1119 F(200000000, P_GPLL0, 3, 0, 0),
1123 static struct clk_rcg2 gp1_clk_src = {
1124 .cmd_rcgr = 0x64004,
1127 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1128 .freq_tbl = ftbl_gp1_clk_src,
1129 .clkr.hw.init = &(struct clk_init_data){
1130 .name = "gp1_clk_src",
1131 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1133 .ops = &clk_rcg2_ops,
1137 static struct clk_rcg2 gp2_clk_src = {
1138 .cmd_rcgr = 0x65004,
1141 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1142 .freq_tbl = ftbl_gp1_clk_src,
1143 .clkr.hw.init = &(struct clk_init_data){
1144 .name = "gp2_clk_src",
1145 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1147 .ops = &clk_rcg2_ops,
1151 static struct clk_rcg2 gp3_clk_src = {
1152 .cmd_rcgr = 0x66004,
1155 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1156 .freq_tbl = ftbl_gp1_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "gp3_clk_src",
1159 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1161 .ops = &clk_rcg2_ops,
1165 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1166 F(1010526, P_XO, 1, 1, 19),
1170 static struct clk_rcg2 pcie_aux_clk_src = {
1171 .cmd_rcgr = 0x6c000,
1174 .parent_map = gcc_xo_sleep_clk_map,
1175 .freq_tbl = ftbl_pcie_aux_clk_src,
1176 .clkr.hw.init = &(struct clk_init_data){
1177 .name = "pcie_aux_clk_src",
1178 .parent_names = gcc_xo_sleep_clk,
1180 .ops = &clk_rcg2_ops,
1184 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1185 F(100000000, P_GPLL0, 6, 0, 0),
1186 F(200000000, P_GPLL0, 3, 0, 0),
1187 F(240000000, P_GPLL0, 2.5, 0, 0),
1191 static struct clk_rcg2 ufs_axi_clk_src = {
1192 .cmd_rcgr = 0x75024,
1195 .parent_map = gcc_xo_gpll0_map,
1196 .freq_tbl = ftbl_ufs_axi_clk_src,
1197 .clkr.hw.init = &(struct clk_init_data){
1198 .name = "ufs_axi_clk_src",
1199 .parent_names = gcc_xo_gpll0,
1201 .ops = &clk_rcg2_ops,
1205 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1206 F(19200000, P_XO, 1, 0, 0),
1207 F(150000000, P_GPLL0, 4, 0, 0),
1208 F(300000000, P_GPLL0, 2, 0, 0),
1212 static struct clk_rcg2 ufs_ice_core_clk_src = {
1213 .cmd_rcgr = 0x76014,
1215 .parent_map = gcc_xo_gpll0_map,
1216 .freq_tbl = ftbl_ufs_ice_core_clk_src,
1217 .clkr.hw.init = &(struct clk_init_data){
1218 .name = "ufs_ice_core_clk_src",
1219 .parent_names = gcc_xo_gpll0,
1221 .ops = &clk_rcg2_ops,
1225 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1226 F(75000000, P_GPLL0, 8, 0, 0),
1227 F(150000000, P_GPLL0, 4, 0, 0),
1228 F(256000000, P_GPLL4, 1.5, 0, 0),
1229 F(300000000, P_GPLL0, 2, 0, 0),
1233 static struct clk_rcg2 qspi_ser_clk_src = {
1234 .cmd_rcgr = 0x8b00c,
1236 .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1237 .freq_tbl = ftbl_qspi_ser_clk_src,
1238 .clkr.hw.init = &(struct clk_init_data){
1239 .name = "qspi_ser_clk_src",
1240 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1242 .ops = &clk_rcg2_ops,
1246 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1247 .halt_reg = 0x0f03c,
1249 .enable_reg = 0x0f03c,
1250 .enable_mask = BIT(0),
1251 .hw.init = &(struct clk_init_data){
1252 .name = "gcc_sys_noc_usb3_axi_clk",
1253 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1255 .flags = CLK_SET_RATE_PARENT,
1256 .ops = &clk_branch2_ops,
1261 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1262 .halt_reg = 0x75038,
1264 .enable_reg = 0x75038,
1265 .enable_mask = BIT(0),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "gcc_sys_noc_ufs_axi_clk",
1268 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1276 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1279 .enable_reg = 0x6010,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "gcc_periph_noc_usb20_ahb_clk",
1283 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1285 .flags = CLK_SET_RATE_PARENT,
1286 .ops = &clk_branch2_ops,
1291 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1294 .enable_reg = 0x9008,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_mmss_noc_cfg_ahb_clk",
1298 .parent_names = (const char *[]){ "config_noc_clk_src" },
1300 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1301 .ops = &clk_branch2_ops,
1306 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1309 .enable_reg = 0x9010,
1310 .enable_mask = BIT(0),
1311 .hw.init = &(struct clk_init_data){
1312 .name = "gcc_mmss_bimc_gfx_clk",
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1319 static struct clk_branch gcc_usb30_master_clk = {
1320 .halt_reg = 0x0f008,
1322 .enable_reg = 0x0f008,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_usb30_master_clk",
1326 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1334 static struct clk_branch gcc_usb30_sleep_clk = {
1335 .halt_reg = 0x0f00c,
1337 .enable_reg = 0x0f00c,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "gcc_usb30_sleep_clk",
1341 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1349 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1350 .halt_reg = 0x0f010,
1352 .enable_reg = 0x0f010,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gcc_usb30_mock_utmi_clk",
1356 .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1358 .flags = CLK_SET_RATE_PARENT,
1359 .ops = &clk_branch2_ops,
1364 static struct clk_branch gcc_usb3_phy_aux_clk = {
1365 .halt_reg = 0x50000,
1367 .enable_reg = 0x50000,
1368 .enable_mask = BIT(0),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "gcc_usb3_phy_aux_clk",
1371 .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1373 .flags = CLK_SET_RATE_PARENT,
1374 .ops = &clk_branch2_ops,
1379 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1380 .halt_reg = 0x50004,
1382 .enable_reg = 0x50004,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "gcc_usb3_phy_pipe_clk",
1386 .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1394 static struct clk_branch gcc_usb20_master_clk = {
1395 .halt_reg = 0x12004,
1397 .enable_reg = 0x12004,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "gcc_usb20_master_clk",
1401 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1403 .flags = CLK_SET_RATE_PARENT,
1404 .ops = &clk_branch2_ops,
1409 static struct clk_branch gcc_usb20_sleep_clk = {
1410 .halt_reg = 0x12008,
1412 .enable_reg = 0x12008,
1413 .enable_mask = BIT(0),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "gcc_usb20_sleep_clk",
1416 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1418 .flags = CLK_SET_RATE_PARENT,
1419 .ops = &clk_branch2_ops,
1424 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1425 .halt_reg = 0x1200c,
1427 .enable_reg = 0x1200c,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "gcc_usb20_mock_utmi_clk",
1431 .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1439 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1440 .halt_reg = 0x6a004,
1442 .enable_reg = 0x6a004,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1446 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1448 .flags = CLK_SET_RATE_PARENT,
1449 .ops = &clk_branch2_ops,
1454 static struct clk_branch gcc_sdcc1_apps_clk = {
1455 .halt_reg = 0x13004,
1457 .enable_reg = 0x13004,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "gcc_sdcc1_apps_clk",
1461 .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1463 .flags = CLK_SET_RATE_PARENT,
1464 .ops = &clk_branch2_ops,
1469 static struct clk_branch gcc_sdcc1_ahb_clk = {
1470 .halt_reg = 0x13008,
1472 .enable_reg = 0x13008,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "gcc_sdcc1_ahb_clk",
1476 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1478 .flags = CLK_SET_RATE_PARENT,
1479 .ops = &clk_branch2_ops,
1484 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1485 .halt_reg = 0x13038,
1487 .enable_reg = 0x13038,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "gcc_sdcc1_ice_core_clk",
1491 .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1493 .flags = CLK_SET_RATE_PARENT,
1494 .ops = &clk_branch2_ops,
1499 static struct clk_branch gcc_sdcc2_apps_clk = {
1500 .halt_reg = 0x14004,
1502 .enable_reg = 0x14004,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "gcc_sdcc2_apps_clk",
1506 .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1508 .flags = CLK_SET_RATE_PARENT,
1509 .ops = &clk_branch2_ops,
1514 static struct clk_branch gcc_sdcc2_ahb_clk = {
1515 .halt_reg = 0x14008,
1517 .enable_reg = 0x14008,
1518 .enable_mask = BIT(0),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "gcc_sdcc2_ahb_clk",
1521 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1529 static struct clk_branch gcc_sdcc3_apps_clk = {
1530 .halt_reg = 0x15004,
1532 .enable_reg = 0x15004,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_sdcc3_apps_clk",
1536 .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1538 .flags = CLK_SET_RATE_PARENT,
1539 .ops = &clk_branch2_ops,
1544 static struct clk_branch gcc_sdcc3_ahb_clk = {
1545 .halt_reg = 0x15008,
1547 .enable_reg = 0x15008,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_sdcc3_ahb_clk",
1551 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1553 .flags = CLK_SET_RATE_PARENT,
1554 .ops = &clk_branch2_ops,
1559 static struct clk_branch gcc_sdcc4_apps_clk = {
1560 .halt_reg = 0x16004,
1562 .enable_reg = 0x16004,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "gcc_sdcc4_apps_clk",
1566 .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch gcc_sdcc4_ahb_clk = {
1575 .halt_reg = 0x16008,
1577 .enable_reg = 0x16008,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "gcc_sdcc4_ahb_clk",
1581 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1583 .flags = CLK_SET_RATE_PARENT,
1584 .ops = &clk_branch2_ops,
1589 static struct clk_branch gcc_blsp1_ahb_clk = {
1590 .halt_reg = 0x17004,
1591 .halt_check = BRANCH_HALT_VOTED,
1593 .enable_reg = 0x52004,
1594 .enable_mask = BIT(17),
1595 .hw.init = &(struct clk_init_data){
1596 .name = "gcc_blsp1_ahb_clk",
1597 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_blsp1_sleep_clk = {
1606 .halt_reg = 0x17008,
1607 .halt_check = BRANCH_HALT_VOTED,
1609 .enable_reg = 0x52004,
1610 .enable_mask = BIT(16),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "gcc_blsp1_sleep_clk",
1613 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1622 .halt_reg = 0x19004,
1624 .enable_reg = 0x19004,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "gcc_blsp1_qup1_spi_apps_clk",
1628 .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1630 .flags = CLK_SET_RATE_PARENT,
1631 .ops = &clk_branch2_ops,
1636 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1637 .halt_reg = 0x19008,
1639 .enable_reg = 0x19008,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1643 .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1645 .flags = CLK_SET_RATE_PARENT,
1646 .ops = &clk_branch2_ops,
1651 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1652 .halt_reg = 0x1a004,
1654 .enable_reg = 0x1a004,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data){
1657 .name = "gcc_blsp1_uart1_apps_clk",
1658 .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_branch2_ops,
1666 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1667 .halt_reg = 0x1b004,
1669 .enable_reg = 0x1b004,
1670 .enable_mask = BIT(0),
1671 .hw.init = &(struct clk_init_data){
1672 .name = "gcc_blsp1_qup2_spi_apps_clk",
1673 .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1675 .flags = CLK_SET_RATE_PARENT,
1676 .ops = &clk_branch2_ops,
1681 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1682 .halt_reg = 0x1b008,
1684 .enable_reg = 0x1b008,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1688 .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1690 .flags = CLK_SET_RATE_PARENT,
1691 .ops = &clk_branch2_ops,
1696 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1697 .halt_reg = 0x1c004,
1699 .enable_reg = 0x1c004,
1700 .enable_mask = BIT(0),
1701 .hw.init = &(struct clk_init_data){
1702 .name = "gcc_blsp1_uart2_apps_clk",
1703 .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1711 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1712 .halt_reg = 0x1d004,
1714 .enable_reg = 0x1d004,
1715 .enable_mask = BIT(0),
1716 .hw.init = &(struct clk_init_data){
1717 .name = "gcc_blsp1_qup3_spi_apps_clk",
1718 .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1720 .flags = CLK_SET_RATE_PARENT,
1721 .ops = &clk_branch2_ops,
1726 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1727 .halt_reg = 0x1d008,
1729 .enable_reg = 0x1d008,
1730 .enable_mask = BIT(0),
1731 .hw.init = &(struct clk_init_data){
1732 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1733 .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1735 .flags = CLK_SET_RATE_PARENT,
1736 .ops = &clk_branch2_ops,
1741 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1742 .halt_reg = 0x1e004,
1744 .enable_reg = 0x1e004,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "gcc_blsp1_uart3_apps_clk",
1748 .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_branch2_ops,
1756 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1757 .halt_reg = 0x1f004,
1759 .enable_reg = 0x1f004,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_blsp1_qup4_spi_apps_clk",
1763 .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1765 .flags = CLK_SET_RATE_PARENT,
1766 .ops = &clk_branch2_ops,
1771 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1772 .halt_reg = 0x1f008,
1774 .enable_reg = 0x1f008,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1778 .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1780 .flags = CLK_SET_RATE_PARENT,
1781 .ops = &clk_branch2_ops,
1786 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1787 .halt_reg = 0x20004,
1789 .enable_reg = 0x20004,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "gcc_blsp1_uart4_apps_clk",
1793 .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1801 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1802 .halt_reg = 0x21004,
1804 .enable_reg = 0x21004,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "gcc_blsp1_qup5_spi_apps_clk",
1808 .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1810 .flags = CLK_SET_RATE_PARENT,
1811 .ops = &clk_branch2_ops,
1816 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1817 .halt_reg = 0x21008,
1819 .enable_reg = 0x21008,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1823 .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1825 .flags = CLK_SET_RATE_PARENT,
1826 .ops = &clk_branch2_ops,
1831 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1832 .halt_reg = 0x22004,
1834 .enable_reg = 0x22004,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_blsp1_uart5_apps_clk",
1838 .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1846 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1847 .halt_reg = 0x23004,
1849 .enable_reg = 0x23004,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_blsp1_qup6_spi_apps_clk",
1853 .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1861 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1862 .halt_reg = 0x23008,
1864 .enable_reg = 0x23008,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1868 .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1870 .flags = CLK_SET_RATE_PARENT,
1871 .ops = &clk_branch2_ops,
1876 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1877 .halt_reg = 0x24004,
1879 .enable_reg = 0x24004,
1880 .enable_mask = BIT(0),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "gcc_blsp1_uart6_apps_clk",
1883 .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1891 static struct clk_branch gcc_blsp2_ahb_clk = {
1892 .halt_reg = 0x25004,
1893 .halt_check = BRANCH_HALT_VOTED,
1895 .enable_reg = 0x52004,
1896 .enable_mask = BIT(15),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "gcc_blsp2_ahb_clk",
1899 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1901 .flags = CLK_SET_RATE_PARENT,
1902 .ops = &clk_branch2_ops,
1907 static struct clk_branch gcc_blsp2_sleep_clk = {
1908 .halt_reg = 0x25008,
1909 .halt_check = BRANCH_HALT_VOTED,
1911 .enable_reg = 0x52004,
1912 .enable_mask = BIT(14),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "gcc_blsp2_sleep_clk",
1915 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1917 .flags = CLK_SET_RATE_PARENT,
1918 .ops = &clk_branch2_ops,
1923 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1924 .halt_reg = 0x26004,
1926 .enable_reg = 0x26004,
1927 .enable_mask = BIT(0),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_blsp2_qup1_spi_apps_clk",
1930 .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_branch2_ops,
1938 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1939 .halt_reg = 0x26008,
1941 .enable_reg = 0x26008,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1945 .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1947 .flags = CLK_SET_RATE_PARENT,
1948 .ops = &clk_branch2_ops,
1953 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1954 .halt_reg = 0x27004,
1956 .enable_reg = 0x27004,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "gcc_blsp2_uart1_apps_clk",
1960 .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1962 .flags = CLK_SET_RATE_PARENT,
1963 .ops = &clk_branch2_ops,
1968 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1969 .halt_reg = 0x28004,
1971 .enable_reg = 0x28004,
1972 .enable_mask = BIT(0),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "gcc_blsp2_qup2_spi_apps_clk",
1975 .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
1977 .flags = CLK_SET_RATE_PARENT,
1978 .ops = &clk_branch2_ops,
1983 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1984 .halt_reg = 0x28008,
1986 .enable_reg = 0x28008,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1990 .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1998 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1999 .halt_reg = 0x29004,
2001 .enable_reg = 0x29004,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_blsp2_uart2_apps_clk",
2005 .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2013 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2014 .halt_reg = 0x2a004,
2016 .enable_reg = 0x2a004,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "gcc_blsp2_qup3_spi_apps_clk",
2020 .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2028 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2029 .halt_reg = 0x2a008,
2031 .enable_reg = 0x2a008,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "gcc_blsp2_qup3_i2c_apps_clk",
2035 .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2043 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2044 .halt_reg = 0x2b004,
2046 .enable_reg = 0x2b004,
2047 .enable_mask = BIT(0),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "gcc_blsp2_uart3_apps_clk",
2050 .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2052 .flags = CLK_SET_RATE_PARENT,
2053 .ops = &clk_branch2_ops,
2058 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2059 .halt_reg = 0x2c004,
2061 .enable_reg = 0x2c004,
2062 .enable_mask = BIT(0),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_blsp2_qup4_spi_apps_clk",
2065 .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2067 .flags = CLK_SET_RATE_PARENT,
2068 .ops = &clk_branch2_ops,
2073 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2074 .halt_reg = 0x2c008,
2076 .enable_reg = 0x2c008,
2077 .enable_mask = BIT(0),
2078 .hw.init = &(struct clk_init_data){
2079 .name = "gcc_blsp2_qup4_i2c_apps_clk",
2080 .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2082 .flags = CLK_SET_RATE_PARENT,
2083 .ops = &clk_branch2_ops,
2088 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2089 .halt_reg = 0x2d004,
2091 .enable_reg = 0x2d004,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "gcc_blsp2_uart4_apps_clk",
2095 .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2097 .flags = CLK_SET_RATE_PARENT,
2098 .ops = &clk_branch2_ops,
2103 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2104 .halt_reg = 0x2e004,
2106 .enable_reg = 0x2e004,
2107 .enable_mask = BIT(0),
2108 .hw.init = &(struct clk_init_data){
2109 .name = "gcc_blsp2_qup5_spi_apps_clk",
2110 .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2118 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2119 .halt_reg = 0x2e008,
2121 .enable_reg = 0x2e008,
2122 .enable_mask = BIT(0),
2123 .hw.init = &(struct clk_init_data){
2124 .name = "gcc_blsp2_qup5_i2c_apps_clk",
2125 .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2127 .flags = CLK_SET_RATE_PARENT,
2128 .ops = &clk_branch2_ops,
2133 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2134 .halt_reg = 0x2f004,
2136 .enable_reg = 0x2f004,
2137 .enable_mask = BIT(0),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_blsp2_uart5_apps_clk",
2140 .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2142 .flags = CLK_SET_RATE_PARENT,
2143 .ops = &clk_branch2_ops,
2148 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2149 .halt_reg = 0x30004,
2151 .enable_reg = 0x30004,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "gcc_blsp2_qup6_spi_apps_clk",
2155 .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2163 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2164 .halt_reg = 0x30008,
2166 .enable_reg = 0x30008,
2167 .enable_mask = BIT(0),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_blsp2_qup6_i2c_apps_clk",
2170 .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2172 .flags = CLK_SET_RATE_PARENT,
2173 .ops = &clk_branch2_ops,
2178 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2179 .halt_reg = 0x31004,
2181 .enable_reg = 0x31004,
2182 .enable_mask = BIT(0),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_blsp2_uart6_apps_clk",
2185 .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2187 .flags = CLK_SET_RATE_PARENT,
2188 .ops = &clk_branch2_ops,
2193 static struct clk_branch gcc_pdm_ahb_clk = {
2194 .halt_reg = 0x33004,
2196 .enable_reg = 0x33004,
2197 .enable_mask = BIT(0),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "gcc_pdm_ahb_clk",
2200 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_branch2_ops,
2208 static struct clk_branch gcc_pdm2_clk = {
2209 .halt_reg = 0x3300c,
2211 .enable_reg = 0x3300c,
2212 .enable_mask = BIT(0),
2213 .hw.init = &(struct clk_init_data){
2214 .name = "gcc_pdm2_clk",
2215 .parent_names = (const char *[]){ "pdm2_clk_src" },
2217 .flags = CLK_SET_RATE_PARENT,
2218 .ops = &clk_branch2_ops,
2223 static struct clk_branch gcc_prng_ahb_clk = {
2224 .halt_reg = 0x34004,
2225 .halt_check = BRANCH_HALT_VOTED,
2227 .enable_reg = 0x52004,
2228 .enable_mask = BIT(13),
2229 .hw.init = &(struct clk_init_data){
2230 .name = "gcc_prng_ahb_clk",
2231 .parent_names = (const char *[]){ "config_noc_clk_src" },
2233 .flags = CLK_SET_RATE_PARENT,
2234 .ops = &clk_branch2_ops,
2239 static struct clk_branch gcc_tsif_ahb_clk = {
2240 .halt_reg = 0x36004,
2242 .enable_reg = 0x36004,
2243 .enable_mask = BIT(0),
2244 .hw.init = &(struct clk_init_data){
2245 .name = "gcc_tsif_ahb_clk",
2246 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2248 .flags = CLK_SET_RATE_PARENT,
2249 .ops = &clk_branch2_ops,
2254 static struct clk_branch gcc_tsif_ref_clk = {
2255 .halt_reg = 0x36008,
2257 .enable_reg = 0x36008,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "gcc_tsif_ref_clk",
2261 .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_branch2_ops,
2269 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2270 .halt_reg = 0x3600c,
2272 .enable_reg = 0x3600c,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(struct clk_init_data){
2275 .name = "gcc_tsif_inactivity_timers_clk",
2276 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2278 .flags = CLK_SET_RATE_PARENT,
2279 .ops = &clk_branch2_ops,
2284 static struct clk_branch gcc_boot_rom_ahb_clk = {
2285 .halt_reg = 0x38004,
2286 .halt_check = BRANCH_HALT_VOTED,
2288 .enable_reg = 0x52004,
2289 .enable_mask = BIT(10),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "gcc_boot_rom_ahb_clk",
2292 .parent_names = (const char *[]){ "config_noc_clk_src" },
2294 .flags = CLK_SET_RATE_PARENT,
2295 .ops = &clk_branch2_ops,
2300 static struct clk_branch gcc_bimc_gfx_clk = {
2301 .halt_reg = 0x46018,
2303 .enable_reg = 0x46018,
2304 .enable_mask = BIT(0),
2305 .hw.init = &(struct clk_init_data){
2306 .name = "gcc_bimc_gfx_clk",
2307 .flags = CLK_SET_RATE_PARENT,
2308 .ops = &clk_branch2_ops,
2313 static struct clk_branch gcc_hmss_rbcpr_clk = {
2314 .halt_reg = 0x4800c,
2316 .enable_reg = 0x4800c,
2317 .enable_mask = BIT(0),
2318 .hw.init = &(struct clk_init_data){
2319 .name = "gcc_hmss_rbcpr_clk",
2320 .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2322 .flags = CLK_SET_RATE_PARENT,
2323 .ops = &clk_branch2_ops,
2328 static struct clk_branch gcc_gp1_clk = {
2329 .halt_reg = 0x64000,
2331 .enable_reg = 0x64000,
2332 .enable_mask = BIT(0),
2333 .hw.init = &(struct clk_init_data){
2334 .name = "gcc_gp1_clk",
2335 .parent_names = (const char *[]){ "gp1_clk_src" },
2337 .flags = CLK_SET_RATE_PARENT,
2338 .ops = &clk_branch2_ops,
2343 static struct clk_branch gcc_gp2_clk = {
2344 .halt_reg = 0x65000,
2346 .enable_reg = 0x65000,
2347 .enable_mask = BIT(0),
2348 .hw.init = &(struct clk_init_data){
2349 .name = "gcc_gp2_clk",
2350 .parent_names = (const char *[]){ "gp2_clk_src" },
2352 .flags = CLK_SET_RATE_PARENT,
2353 .ops = &clk_branch2_ops,
2358 static struct clk_branch gcc_gp3_clk = {
2359 .halt_reg = 0x66000,
2361 .enable_reg = 0x66000,
2362 .enable_mask = BIT(0),
2363 .hw.init = &(struct clk_init_data){
2364 .name = "gcc_gp3_clk",
2365 .parent_names = (const char *[]){ "gp3_clk_src" },
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2373 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2374 .halt_reg = 0x6b008,
2376 .enable_reg = 0x6b008,
2377 .enable_mask = BIT(0),
2378 .hw.init = &(struct clk_init_data){
2379 .name = "gcc_pcie_0_slv_axi_clk",
2380 .parent_names = (const char *[]){ "system_noc_clk_src" },
2382 .flags = CLK_SET_RATE_PARENT,
2383 .ops = &clk_branch2_ops,
2388 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2389 .halt_reg = 0x6b00c,
2391 .enable_reg = 0x6b00c,
2392 .enable_mask = BIT(0),
2393 .hw.init = &(struct clk_init_data){
2394 .name = "gcc_pcie_0_mstr_axi_clk",
2395 .parent_names = (const char *[]){ "system_noc_clk_src" },
2397 .flags = CLK_SET_RATE_PARENT,
2398 .ops = &clk_branch2_ops,
2403 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2404 .halt_reg = 0x6b010,
2406 .enable_reg = 0x6b010,
2407 .enable_mask = BIT(0),
2408 .hw.init = &(struct clk_init_data){
2409 .name = "gcc_pcie_0_cfg_ahb_clk",
2410 .parent_names = (const char *[]){ "config_noc_clk_src" },
2412 .flags = CLK_SET_RATE_PARENT,
2413 .ops = &clk_branch2_ops,
2418 static struct clk_branch gcc_pcie_0_aux_clk = {
2419 .halt_reg = 0x6b014,
2421 .enable_reg = 0x6b014,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_pcie_0_aux_clk",
2425 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2433 static struct clk_branch gcc_pcie_0_pipe_clk = {
2434 .halt_reg = 0x6b018,
2436 .enable_reg = 0x6b018,
2437 .enable_mask = BIT(0),
2438 .hw.init = &(struct clk_init_data){
2439 .name = "gcc_pcie_0_pipe_clk",
2440 .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2442 .flags = CLK_SET_RATE_PARENT,
2443 .ops = &clk_branch2_ops,
2448 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2449 .halt_reg = 0x6d008,
2451 .enable_reg = 0x6d008,
2452 .enable_mask = BIT(0),
2453 .hw.init = &(struct clk_init_data){
2454 .name = "gcc_pcie_1_slv_axi_clk",
2455 .parent_names = (const char *[]){ "system_noc_clk_src" },
2457 .flags = CLK_SET_RATE_PARENT,
2458 .ops = &clk_branch2_ops,
2463 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2464 .halt_reg = 0x6d00c,
2466 .enable_reg = 0x6d00c,
2467 .enable_mask = BIT(0),
2468 .hw.init = &(struct clk_init_data){
2469 .name = "gcc_pcie_1_mstr_axi_clk",
2470 .parent_names = (const char *[]){ "system_noc_clk_src" },
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2478 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2479 .halt_reg = 0x6d010,
2481 .enable_reg = 0x6d010,
2482 .enable_mask = BIT(0),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "gcc_pcie_1_cfg_ahb_clk",
2485 .parent_names = (const char *[]){ "config_noc_clk_src" },
2487 .flags = CLK_SET_RATE_PARENT,
2488 .ops = &clk_branch2_ops,
2493 static struct clk_branch gcc_pcie_1_aux_clk = {
2494 .halt_reg = 0x6d014,
2496 .enable_reg = 0x6d014,
2497 .enable_mask = BIT(0),
2498 .hw.init = &(struct clk_init_data){
2499 .name = "gcc_pcie_1_aux_clk",
2500 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2502 .flags = CLK_SET_RATE_PARENT,
2503 .ops = &clk_branch2_ops,
2508 static struct clk_branch gcc_pcie_1_pipe_clk = {
2509 .halt_reg = 0x6d018,
2511 .enable_reg = 0x6d018,
2512 .enable_mask = BIT(0),
2513 .hw.init = &(struct clk_init_data){
2514 .name = "gcc_pcie_1_pipe_clk",
2515 .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2523 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2524 .halt_reg = 0x6e008,
2526 .enable_reg = 0x6e008,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "gcc_pcie_2_slv_axi_clk",
2530 .parent_names = (const char *[]){ "system_noc_clk_src" },
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2538 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2539 .halt_reg = 0x6e00c,
2541 .enable_reg = 0x6e00c,
2542 .enable_mask = BIT(0),
2543 .hw.init = &(struct clk_init_data){
2544 .name = "gcc_pcie_2_mstr_axi_clk",
2545 .parent_names = (const char *[]){ "system_noc_clk_src" },
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2553 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2554 .halt_reg = 0x6e010,
2556 .enable_reg = 0x6e010,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_pcie_2_cfg_ahb_clk",
2560 .parent_names = (const char *[]){ "config_noc_clk_src" },
2562 .flags = CLK_SET_RATE_PARENT,
2563 .ops = &clk_branch2_ops,
2568 static struct clk_branch gcc_pcie_2_aux_clk = {
2569 .halt_reg = 0x6e014,
2571 .enable_reg = 0x6e014,
2572 .enable_mask = BIT(0),
2573 .hw.init = &(struct clk_init_data){
2574 .name = "gcc_pcie_2_aux_clk",
2575 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2577 .flags = CLK_SET_RATE_PARENT,
2578 .ops = &clk_branch2_ops,
2583 static struct clk_branch gcc_pcie_2_pipe_clk = {
2584 .halt_reg = 0x6e018,
2586 .enable_reg = 0x6e018,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_pcie_2_pipe_clk",
2590 .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2592 .flags = CLK_SET_RATE_PARENT,
2593 .ops = &clk_branch2_ops,
2598 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2599 .halt_reg = 0x6f004,
2601 .enable_reg = 0x6f004,
2602 .enable_mask = BIT(0),
2603 .hw.init = &(struct clk_init_data){
2604 .name = "gcc_pcie_phy_cfg_ahb_clk",
2605 .parent_names = (const char *[]){ "config_noc_clk_src" },
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2613 static struct clk_branch gcc_pcie_phy_aux_clk = {
2614 .halt_reg = 0x6f008,
2616 .enable_reg = 0x6f008,
2617 .enable_mask = BIT(0),
2618 .hw.init = &(struct clk_init_data){
2619 .name = "gcc_pcie_phy_aux_clk",
2620 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2622 .flags = CLK_SET_RATE_PARENT,
2623 .ops = &clk_branch2_ops,
2628 static struct clk_branch gcc_ufs_axi_clk = {
2629 .halt_reg = 0x75008,
2631 .enable_reg = 0x75008,
2632 .enable_mask = BIT(0),
2633 .hw.init = &(struct clk_init_data){
2634 .name = "gcc_ufs_axi_clk",
2635 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2637 .flags = CLK_SET_RATE_PARENT,
2638 .ops = &clk_branch2_ops,
2643 static struct clk_branch gcc_ufs_ahb_clk = {
2644 .halt_reg = 0x7500c,
2646 .enable_reg = 0x7500c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "gcc_ufs_ahb_clk",
2650 .parent_names = (const char *[]){ "config_noc_clk_src" },
2652 .flags = CLK_SET_RATE_PARENT,
2653 .ops = &clk_branch2_ops,
2658 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2661 .hw.init = &(struct clk_init_data){
2662 .name = "ufs_tx_cfg_clk_src",
2663 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2665 .flags = CLK_SET_RATE_PARENT,
2666 .ops = &clk_fixed_factor_ops,
2670 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2671 .halt_reg = 0x75010,
2673 .enable_reg = 0x75010,
2674 .enable_mask = BIT(0),
2675 .hw.init = &(struct clk_init_data){
2676 .name = "gcc_ufs_tx_cfg_clk",
2677 .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2679 .flags = CLK_SET_RATE_PARENT,
2680 .ops = &clk_branch2_ops,
2685 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2688 .hw.init = &(struct clk_init_data){
2689 .name = "ufs_rx_cfg_clk_src",
2690 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2692 .flags = CLK_SET_RATE_PARENT,
2693 .ops = &clk_fixed_factor_ops,
2697 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2698 .halt_reg = 0x7d010,
2699 .halt_check = BRANCH_HALT_VOTED,
2701 .enable_reg = 0x7d010,
2702 .enable_mask = BIT(0),
2703 .hw.init = &(struct clk_init_data){
2704 .name = "hlos1_vote_lpass_core_smmu_clk",
2705 .ops = &clk_branch2_ops,
2710 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2711 .halt_reg = 0x7d014,
2712 .halt_check = BRANCH_HALT_VOTED,
2714 .enable_reg = 0x7d014,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "hlos1_vote_lpass_adsp_smmu_clk",
2718 .ops = &clk_branch2_ops,
2723 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2724 .halt_reg = 0x75014,
2726 .enable_reg = 0x75014,
2727 .enable_mask = BIT(0),
2728 .hw.init = &(struct clk_init_data){
2729 .name = "gcc_ufs_rx_cfg_clk",
2730 .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2732 .flags = CLK_SET_RATE_PARENT,
2733 .ops = &clk_branch2_ops,
2738 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2739 .halt_reg = 0x75018,
2741 .enable_reg = 0x75018,
2742 .enable_mask = BIT(0),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "gcc_ufs_tx_symbol_0_clk",
2745 .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2747 .flags = CLK_SET_RATE_PARENT,
2748 .ops = &clk_branch2_ops,
2753 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2754 .halt_reg = 0x7501c,
2756 .enable_reg = 0x7501c,
2757 .enable_mask = BIT(0),
2758 .hw.init = &(struct clk_init_data){
2759 .name = "gcc_ufs_rx_symbol_0_clk",
2760 .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2762 .flags = CLK_SET_RATE_PARENT,
2763 .ops = &clk_branch2_ops,
2768 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2769 .halt_reg = 0x75020,
2771 .enable_reg = 0x75020,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_ufs_rx_symbol_1_clk",
2775 .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2777 .flags = CLK_SET_RATE_PARENT,
2778 .ops = &clk_branch2_ops,
2783 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2786 .hw.init = &(struct clk_init_data){
2787 .name = "ufs_ice_core_postdiv_clk_src",
2788 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_fixed_factor_ops,
2795 static struct clk_branch gcc_ufs_unipro_core_clk = {
2796 .halt_reg = 0x7600c,
2798 .enable_reg = 0x7600c,
2799 .enable_mask = BIT(0),
2800 .hw.init = &(struct clk_init_data){
2801 .name = "gcc_ufs_unipro_core_clk",
2802 .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2804 .flags = CLK_SET_RATE_PARENT,
2805 .ops = &clk_branch2_ops,
2810 static struct clk_branch gcc_ufs_ice_core_clk = {
2811 .halt_reg = 0x76010,
2813 .enable_reg = 0x76010,
2814 .enable_mask = BIT(0),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "gcc_ufs_ice_core_clk",
2817 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2819 .flags = CLK_SET_RATE_PARENT,
2820 .ops = &clk_branch2_ops,
2825 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2826 .halt_check = BRANCH_HALT_DELAY,
2828 .enable_reg = 0x76030,
2829 .enable_mask = BIT(0),
2830 .hw.init = &(struct clk_init_data){
2831 .name = "gcc_ufs_sys_clk_core_clk",
2832 .ops = &clk_branch2_ops,
2837 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2838 .halt_check = BRANCH_HALT_DELAY,
2840 .enable_reg = 0x76034,
2841 .enable_mask = BIT(0),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_ufs_tx_symbol_clk_core_clk",
2844 .ops = &clk_branch2_ops,
2849 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2850 .halt_reg = 0x81008,
2852 .enable_reg = 0x81008,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(struct clk_init_data){
2855 .name = "gcc_aggre0_snoc_axi_clk",
2856 .parent_names = (const char *[]){ "system_noc_clk_src" },
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2864 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2865 .halt_reg = 0x8100c,
2867 .enable_reg = 0x8100c,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "gcc_aggre0_cnoc_ahb_clk",
2871 .parent_names = (const char *[]){ "config_noc_clk_src" },
2873 .flags = CLK_SET_RATE_PARENT,
2874 .ops = &clk_branch2_ops,
2879 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2880 .halt_reg = 0x81014,
2882 .enable_reg = 0x81014,
2883 .enable_mask = BIT(0),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "gcc_smmu_aggre0_axi_clk",
2886 .parent_names = (const char *[]){ "system_noc_clk_src" },
2888 .flags = CLK_SET_RATE_PARENT,
2889 .ops = &clk_branch2_ops,
2894 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2895 .halt_reg = 0x81018,
2897 .enable_reg = 0x81018,
2898 .enable_mask = BIT(0),
2899 .hw.init = &(struct clk_init_data){
2900 .name = "gcc_smmu_aggre0_ahb_clk",
2901 .parent_names = (const char *[]){ "config_noc_clk_src" },
2903 .flags = CLK_SET_RATE_PARENT,
2904 .ops = &clk_branch2_ops,
2909 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2910 .halt_reg = 0x83014,
2912 .enable_reg = 0x83014,
2913 .enable_mask = BIT(0),
2914 .hw.init = &(struct clk_init_data){
2915 .name = "gcc_aggre2_ufs_axi_clk",
2916 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2918 .flags = CLK_SET_RATE_PARENT,
2919 .ops = &clk_branch2_ops,
2924 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2925 .halt_reg = 0x83018,
2927 .enable_reg = 0x83018,
2928 .enable_mask = BIT(0),
2929 .hw.init = &(struct clk_init_data){
2930 .name = "gcc_aggre2_usb3_axi_clk",
2931 .parent_names = (const char *[]){ "usb30_master_clk_src" },
2933 .flags = CLK_SET_RATE_PARENT,
2934 .ops = &clk_branch2_ops,
2939 static struct clk_branch gcc_qspi_ahb_clk = {
2940 .halt_reg = 0x8b004,
2942 .enable_reg = 0x8b004,
2943 .enable_mask = BIT(0),
2944 .hw.init = &(struct clk_init_data){
2945 .name = "gcc_qspi_ahb_clk",
2946 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2948 .flags = CLK_SET_RATE_PARENT,
2949 .ops = &clk_branch2_ops,
2954 static struct clk_branch gcc_qspi_ser_clk = {
2955 .halt_reg = 0x8b008,
2957 .enable_reg = 0x8b008,
2958 .enable_mask = BIT(0),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "gcc_qspi_ser_clk",
2961 .parent_names = (const char *[]){ "qspi_ser_clk_src" },
2963 .flags = CLK_SET_RATE_PARENT,
2964 .ops = &clk_branch2_ops,
2969 static struct clk_branch gcc_usb3_clkref_clk = {
2970 .halt_reg = 0x8800C,
2972 .enable_reg = 0x8800C,
2973 .enable_mask = BIT(0),
2974 .hw.init = &(struct clk_init_data){
2975 .name = "gcc_usb3_clkref_clk",
2976 .parent_names = (const char *[]){ "xo" },
2978 .ops = &clk_branch2_ops,
2983 static struct clk_branch gcc_hdmi_clkref_clk = {
2984 .halt_reg = 0x88000,
2986 .enable_reg = 0x88000,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "gcc_hdmi_clkref_clk",
2990 .parent_names = (const char *[]){ "xo" },
2992 .ops = &clk_branch2_ops,
2997 static struct clk_branch gcc_ufs_clkref_clk = {
2998 .halt_reg = 0x88008,
3000 .enable_reg = 0x88008,
3001 .enable_mask = BIT(0),
3002 .hw.init = &(struct clk_init_data){
3003 .name = "gcc_ufs_clkref_clk",
3004 .parent_names = (const char *[]){ "xo" },
3006 .ops = &clk_branch2_ops,
3011 static struct clk_branch gcc_pcie_clkref_clk = {
3012 .halt_reg = 0x88010,
3014 .enable_reg = 0x88010,
3015 .enable_mask = BIT(0),
3016 .hw.init = &(struct clk_init_data){
3017 .name = "gcc_pcie_clkref_clk",
3018 .parent_names = (const char *[]){ "xo" },
3020 .ops = &clk_branch2_ops,
3025 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3026 .halt_reg = 0x88014,
3028 .enable_reg = 0x88014,
3029 .enable_mask = BIT(0),
3030 .hw.init = &(struct clk_init_data){
3031 .name = "gcc_rx2_usb2_clkref_clk",
3032 .parent_names = (const char *[]){ "xo" },
3034 .ops = &clk_branch2_ops,
3039 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3040 .halt_reg = 0x88018,
3042 .enable_reg = 0x88018,
3043 .enable_mask = BIT(0),
3044 .hw.init = &(struct clk_init_data){
3045 .name = "gcc_rx1_usb2_clkref_clk",
3046 .parent_names = (const char *[]){ "xo" },
3048 .ops = &clk_branch2_ops,
3053 static struct clk_hw *gcc_msm8996_hws[] = {
3055 &gpll0_early_div.hw,
3056 &ufs_tx_cfg_clk_src.hw,
3057 &ufs_rx_cfg_clk_src.hw,
3058 &ufs_ice_core_postdiv_clk_src.hw,
3061 static struct gdsc aggre0_noc_gdsc = {
3063 .gds_hw_ctrl = 0x81028,
3065 .name = "aggre0_noc",
3067 .pwrsts = PWRSTS_OFF_ON,
3071 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3074 .name = "hlos1_vote_aggre0_noc",
3076 .pwrsts = PWRSTS_OFF_ON,
3080 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3083 .name = "hlos1_vote_lpass_adsp",
3085 .pwrsts = PWRSTS_OFF_ON,
3089 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3092 .name = "hlos1_vote_lpass_core",
3094 .pwrsts = PWRSTS_OFF_ON,
3098 static struct gdsc usb30_gdsc = {
3103 .pwrsts = PWRSTS_OFF_ON,
3106 static struct gdsc pcie0_gdsc = {
3111 .pwrsts = PWRSTS_OFF_ON,
3114 static struct gdsc pcie1_gdsc = {
3119 .pwrsts = PWRSTS_OFF_ON,
3122 static struct gdsc pcie2_gdsc = {
3127 .pwrsts = PWRSTS_OFF_ON,
3130 static struct gdsc ufs_gdsc = {
3135 .pwrsts = PWRSTS_OFF_ON,
3138 static struct clk_regmap *gcc_msm8996_clocks[] = {
3139 [GPLL0_EARLY] = &gpll0_early.clkr,
3140 [GPLL0] = &gpll0.clkr,
3141 [GPLL4_EARLY] = &gpll4_early.clkr,
3142 [GPLL4] = &gpll4.clkr,
3143 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3144 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3145 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3146 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3147 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3148 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3149 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3150 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3151 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3152 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3153 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3154 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3155 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3156 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3157 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3158 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3159 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3160 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3161 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3162 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3163 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3164 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3165 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3166 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3167 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3168 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3169 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3170 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3171 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3172 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3173 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3174 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3175 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3176 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3177 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3178 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3179 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3180 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3181 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3182 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3183 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3184 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3185 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3186 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3187 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3188 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3189 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3190 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3191 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3192 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3193 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3194 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3195 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3196 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3197 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3198 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3199 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3200 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3201 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3202 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3203 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3204 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3205 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3206 [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3207 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3208 [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3209 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3210 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3211 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3212 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3213 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3214 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3215 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3216 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3217 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3218 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3219 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3220 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3221 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3222 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3223 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3224 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3225 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3226 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3227 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3228 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3229 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3230 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3231 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3232 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3233 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3234 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3235 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3236 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3237 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3238 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3239 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3240 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3241 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3242 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3243 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3244 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3245 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3246 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3247 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3248 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3249 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3250 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3251 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3252 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3253 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3254 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3255 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3256 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3257 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3258 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3259 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3260 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3261 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3262 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3263 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3264 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3265 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3266 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3267 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3268 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3269 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3270 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3271 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3272 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3273 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3274 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3275 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3276 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3277 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3278 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3279 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3280 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3281 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3282 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3283 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3284 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3285 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3286 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3287 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3288 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3289 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3290 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3291 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3292 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3293 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3294 [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3295 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3296 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3297 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3298 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3299 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3300 [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3301 [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3302 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3303 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3304 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3305 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3306 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3307 [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3308 [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3309 [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3310 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3311 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3312 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3313 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3314 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3315 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3316 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3317 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3318 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3319 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3320 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3321 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3322 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3325 static struct gdsc *gcc_msm8996_gdscs[] = {
3326 [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3327 [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3328 [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3329 [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3330 [USB30_GDSC] = &usb30_gdsc,
3331 [PCIE0_GDSC] = &pcie0_gdsc,
3332 [PCIE1_GDSC] = &pcie1_gdsc,
3333 [PCIE2_GDSC] = &pcie2_gdsc,
3334 [UFS_GDSC] = &ufs_gdsc,
3337 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3338 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3339 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3340 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3341 [GCC_IMEM_BCR] = { 0x8000 },
3342 [GCC_MMSS_BCR] = { 0x9000 },
3343 [GCC_PIMEM_BCR] = { 0x0a000 },
3344 [GCC_QDSS_BCR] = { 0x0c000 },
3345 [GCC_USB_30_BCR] = { 0x0f000 },
3346 [GCC_USB_20_BCR] = { 0x12000 },
3347 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3348 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3349 [GCC_USB3_PHY_BCR] = { 0x50020 },
3350 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3351 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3352 [GCC_SDCC1_BCR] = { 0x13000 },
3353 [GCC_SDCC2_BCR] = { 0x14000 },
3354 [GCC_SDCC3_BCR] = { 0x15000 },
3355 [GCC_SDCC4_BCR] = { 0x16000 },
3356 [GCC_BLSP1_BCR] = { 0x17000 },
3357 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3358 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3359 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3360 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3361 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3362 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3363 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3364 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3365 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3366 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3367 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3368 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3369 [GCC_BLSP2_BCR] = { 0x25000 },
3370 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3371 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3372 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3373 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3374 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3375 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3376 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3377 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3378 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3379 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3380 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3381 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3382 [GCC_PDM_BCR] = { 0x33000 },
3383 [GCC_PRNG_BCR] = { 0x34000 },
3384 [GCC_TSIF_BCR] = { 0x36000 },
3385 [GCC_TCSR_BCR] = { 0x37000 },
3386 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3387 [GCC_MSG_RAM_BCR] = { 0x39000 },
3388 [GCC_TLMM_BCR] = { 0x3a000 },
3389 [GCC_MPM_BCR] = { 0x3b000 },
3390 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3391 [GCC_SPMI_BCR] = { 0x3f000 },
3392 [GCC_SPDM_BCR] = { 0x40000 },
3393 [GCC_CE1_BCR] = { 0x41000 },
3394 [GCC_BIMC_BCR] = { 0x44000 },
3395 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3396 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3397 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3398 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3399 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3400 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3401 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3402 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3403 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3404 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3405 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3406 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3407 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3408 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3409 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3410 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3411 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3412 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3413 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3414 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3415 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3416 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3417 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3418 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3419 [GCC_PCIE_0_BCR] = { 0x6b000 },
3420 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3421 [GCC_PCIE_1_BCR] = { 0x6d000 },
3422 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3423 [GCC_PCIE_2_BCR] = { 0x6e000 },
3424 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3425 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3426 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3427 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3428 [GCC_DCD_BCR] = { 0x70000 },
3429 [GCC_OBT_ODT_BCR] = { 0x73000 },
3430 [GCC_UFS_BCR] = { 0x75000 },
3431 [GCC_SSC_BCR] = { 0x63000 },
3432 [GCC_VS_BCR] = { 0x7a000 },
3433 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3434 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3435 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3436 [GCC_DCC_BCR] = { 0x84000 },
3437 [GCC_IPA_BCR] = { 0x89000 },
3438 [GCC_QSPI_BCR] = { 0x8b000 },
3439 [GCC_SKL_BCR] = { 0x8c000 },
3440 [GCC_MSMPU_BCR] = { 0x8d000 },
3441 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3442 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3443 [GCC_MSS_RESTART] = { 0x8f008 },
3446 static const struct regmap_config gcc_msm8996_regmap_config = {
3450 .max_register = 0x8f010,
3454 static const struct qcom_cc_desc gcc_msm8996_desc = {
3455 .config = &gcc_msm8996_regmap_config,
3456 .clks = gcc_msm8996_clocks,
3457 .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3458 .resets = gcc_msm8996_resets,
3459 .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3460 .gdscs = gcc_msm8996_gdscs,
3461 .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3464 static const struct of_device_id gcc_msm8996_match_table[] = {
3465 { .compatible = "qcom,gcc-msm8996" },
3468 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3470 static int gcc_msm8996_probe(struct platform_device *pdev)
3472 struct device *dev = &pdev->dev;
3474 struct regmap *regmap;
3476 regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3478 return PTR_ERR(regmap);
3481 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3482 * turned off by hardware during certain apps low power modes.
3484 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3486 for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3487 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3492 return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3495 static struct platform_driver gcc_msm8996_driver = {
3496 .probe = gcc_msm8996_probe,
3498 .name = "gcc-msm8996",
3499 .of_match_table = gcc_msm8996_match_table,
3503 static int __init gcc_msm8996_init(void)
3505 return platform_driver_register(&gcc_msm8996_driver);
3507 core_initcall(gcc_msm8996_init);
3509 static void __exit gcc_msm8996_exit(void)
3511 platform_driver_unregister(&gcc_msm8996_driver);
3513 module_exit(gcc_msm8996_exit);
3515 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3516 MODULE_LICENSE("GPL v2");
3517 MODULE_ALIAS("platform:gcc-msm8996");