1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
23 #include "clk-branch.h"
41 static const struct parent_map gcc_sleep_clk_map[] = {
45 static const char * const gcc_sleep_clk[] = {
49 static const struct parent_map gcc_xo_gpll0_map[] = {
54 static const char * const gcc_xo_gpll0[] = {
59 static const struct parent_map gcc_xo_sleep_clk_map[] = {
64 static const char * const gcc_xo_sleep_clk[] = {
69 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
72 { P_GPLL0_EARLY_DIV, 6 }
75 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
81 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
87 static const char * const gcc_xo_gpll0_gpll4[] = {
93 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
99 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
105 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
109 { P_GPLL0_EARLY_DIV, 6 }
112 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
119 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
123 { P_GPLL0_EARLY_DIV, 6 }
126 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
133 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
136 { P_GPLL1_EARLY_DIV, 3 },
139 { P_GPLL0_EARLY_DIV, 6 }
142 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
151 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
157 { P_GPLL2_EARLY, 5 },
158 { P_GPLL0_EARLY_DIV, 6 }
161 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
171 static struct clk_fixed_factor xo = {
174 .hw.init = &(struct clk_init_data){
176 .parent_names = (const char *[]){ "xo_board" },
178 .ops = &clk_fixed_factor_ops,
182 static struct clk_alpha_pll gpll0_early = {
184 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
186 .enable_reg = 0x52000,
187 .enable_mask = BIT(0),
188 .hw.init = &(struct clk_init_data){
189 .name = "gpll0_early",
190 .parent_names = (const char *[]){ "xo" },
192 .ops = &clk_alpha_pll_ops,
197 static struct clk_fixed_factor gpll0_early_div = {
200 .hw.init = &(struct clk_init_data){
201 .name = "gpll0_early_div",
202 .parent_names = (const char *[]){ "gpll0_early" },
204 .ops = &clk_fixed_factor_ops,
208 static struct clk_alpha_pll_postdiv gpll0 = {
210 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
211 .clkr.hw.init = &(struct clk_init_data){
213 .parent_names = (const char *[]){ "gpll0_early" },
215 .ops = &clk_alpha_pll_postdiv_ops,
219 static struct clk_branch gcc_mmss_gpll0_div_clk = {
220 .halt_check = BRANCH_HALT_DELAY,
222 .enable_reg = 0x5200c,
223 .enable_mask = BIT(0),
224 .hw.init = &(struct clk_init_data){
225 .name = "gcc_mmss_gpll0_div_clk",
226 .parent_names = (const char *[]){ "gpll0" },
228 .flags = CLK_SET_RATE_PARENT,
229 .ops = &clk_branch2_ops,
234 static struct clk_branch gcc_mss_gpll0_div_clk = {
235 .halt_check = BRANCH_HALT_DELAY,
237 .enable_reg = 0x5200c,
238 .enable_mask = BIT(2),
239 .hw.init = &(struct clk_init_data){
240 .name = "gcc_mss_gpll0_div_clk",
241 .parent_names = (const char *[]){ "gpll0" },
243 .flags = CLK_SET_RATE_PARENT,
244 .ops = &clk_branch2_ops
249 static struct clk_alpha_pll gpll4_early = {
251 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
253 .enable_reg = 0x52000,
254 .enable_mask = BIT(4),
255 .hw.init = &(struct clk_init_data){
256 .name = "gpll4_early",
257 .parent_names = (const char *[]){ "xo" },
259 .ops = &clk_alpha_pll_ops,
264 static struct clk_alpha_pll_postdiv gpll4 = {
266 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
267 .clkr.hw.init = &(struct clk_init_data){
269 .parent_names = (const char *[]){ "gpll4_early" },
271 .ops = &clk_alpha_pll_postdiv_ops,
275 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
276 F(19200000, P_XO, 1, 0, 0),
277 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
278 F(100000000, P_GPLL0, 6, 0, 0),
279 F(150000000, P_GPLL0, 4, 0, 0),
280 F(200000000, P_GPLL0, 3, 0, 0),
281 F(240000000, P_GPLL0, 2.5, 0, 0),
285 static struct clk_rcg2 system_noc_clk_src = {
288 .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
289 .freq_tbl = ftbl_system_noc_clk_src,
290 .clkr.hw.init = &(struct clk_init_data){
291 .name = "system_noc_clk_src",
292 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
294 .ops = &clk_rcg2_ops,
298 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
299 F(19200000, P_XO, 1, 0, 0),
300 F(37500000, P_GPLL0, 16, 0, 0),
301 F(75000000, P_GPLL0, 8, 0, 0),
305 static struct clk_rcg2 config_noc_clk_src = {
308 .parent_map = gcc_xo_gpll0_map,
309 .freq_tbl = ftbl_config_noc_clk_src,
310 .clkr.hw.init = &(struct clk_init_data){
311 .name = "config_noc_clk_src",
312 .parent_names = gcc_xo_gpll0,
314 .ops = &clk_rcg2_ops,
318 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
319 F(19200000, P_XO, 1, 0, 0),
320 F(37500000, P_GPLL0, 16, 0, 0),
321 F(50000000, P_GPLL0, 12, 0, 0),
322 F(75000000, P_GPLL0, 8, 0, 0),
323 F(100000000, P_GPLL0, 6, 0, 0),
327 static struct clk_rcg2 periph_noc_clk_src = {
330 .parent_map = gcc_xo_gpll0_map,
331 .freq_tbl = ftbl_periph_noc_clk_src,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "periph_noc_clk_src",
334 .parent_names = gcc_xo_gpll0,
336 .ops = &clk_rcg2_ops,
340 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
341 F(19200000, P_XO, 1, 0, 0),
342 F(120000000, P_GPLL0, 5, 0, 0),
343 F(150000000, P_GPLL0, 4, 0, 0),
347 static struct clk_rcg2 usb30_master_clk_src = {
351 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
352 .freq_tbl = ftbl_usb30_master_clk_src,
353 .clkr.hw.init = &(struct clk_init_data){
354 .name = "usb30_master_clk_src",
355 .parent_names = gcc_xo_gpll0_gpll0_early_div,
357 .ops = &clk_rcg2_ops,
361 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
362 F(19200000, P_XO, 1, 0, 0),
366 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
369 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
370 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
371 .clkr.hw.init = &(struct clk_init_data){
372 .name = "usb30_mock_utmi_clk_src",
373 .parent_names = gcc_xo_gpll0_gpll0_early_div,
375 .ops = &clk_rcg2_ops,
379 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
380 F(1200000, P_XO, 16, 0, 0),
384 static struct clk_rcg2 usb3_phy_aux_clk_src = {
387 .parent_map = gcc_xo_sleep_clk_map,
388 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
389 .clkr.hw.init = &(struct clk_init_data){
390 .name = "usb3_phy_aux_clk_src",
391 .parent_names = gcc_xo_sleep_clk,
393 .ops = &clk_rcg2_ops,
397 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
398 F(120000000, P_GPLL0, 5, 0, 0),
402 static struct clk_rcg2 usb20_master_clk_src = {
406 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
407 .freq_tbl = ftbl_usb20_master_clk_src,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "usb20_master_clk_src",
410 .parent_names = gcc_xo_gpll0_gpll0_early_div,
412 .ops = &clk_rcg2_ops,
416 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
419 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
420 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "usb20_mock_utmi_clk_src",
423 .parent_names = gcc_xo_gpll0_gpll0_early_div,
425 .ops = &clk_rcg2_ops,
429 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
430 F(144000, P_XO, 16, 3, 25),
431 F(400000, P_XO, 12, 1, 4),
432 F(20000000, P_GPLL0, 15, 1, 2),
433 F(25000000, P_GPLL0, 12, 1, 2),
434 F(50000000, P_GPLL0, 12, 0, 0),
435 F(96000000, P_GPLL4, 4, 0, 0),
436 F(192000000, P_GPLL4, 2, 0, 0),
437 F(384000000, P_GPLL4, 1, 0, 0),
441 static struct clk_rcg2 sdcc1_apps_clk_src = {
445 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
446 .freq_tbl = ftbl_sdcc1_apps_clk_src,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "sdcc1_apps_clk_src",
449 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
451 .ops = &clk_rcg2_floor_ops,
455 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
456 F(19200000, P_XO, 1, 0, 0),
457 F(150000000, P_GPLL0, 4, 0, 0),
458 F(300000000, P_GPLL0, 2, 0, 0),
462 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
465 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
466 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
467 .clkr.hw.init = &(struct clk_init_data){
468 .name = "sdcc1_ice_core_clk_src",
469 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
471 .ops = &clk_rcg2_ops,
475 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
476 F(144000, P_XO, 16, 3, 25),
477 F(400000, P_XO, 12, 1, 4),
478 F(20000000, P_GPLL0, 15, 1, 2),
479 F(25000000, P_GPLL0, 12, 1, 2),
480 F(50000000, P_GPLL0, 12, 0, 0),
481 F(100000000, P_GPLL0, 6, 0, 0),
482 F(200000000, P_GPLL0, 3, 0, 0),
486 static struct clk_rcg2 sdcc2_apps_clk_src = {
490 .parent_map = gcc_xo_gpll0_gpll4_map,
491 .freq_tbl = ftbl_sdcc2_apps_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "sdcc2_apps_clk_src",
494 .parent_names = gcc_xo_gpll0_gpll4,
496 .ops = &clk_rcg2_floor_ops,
500 static struct clk_rcg2 sdcc3_apps_clk_src = {
504 .parent_map = gcc_xo_gpll0_gpll4_map,
505 .freq_tbl = ftbl_sdcc2_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "sdcc3_apps_clk_src",
508 .parent_names = gcc_xo_gpll0_gpll4,
510 .ops = &clk_rcg2_floor_ops,
514 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
515 F(144000, P_XO, 16, 3, 25),
516 F(400000, P_XO, 12, 1, 4),
517 F(20000000, P_GPLL0, 15, 1, 2),
518 F(25000000, P_GPLL0, 12, 1, 2),
519 F(50000000, P_GPLL0, 12, 0, 0),
520 F(100000000, P_GPLL0, 6, 0, 0),
524 static struct clk_rcg2 sdcc4_apps_clk_src = {
528 .parent_map = gcc_xo_gpll0_map,
529 .freq_tbl = ftbl_sdcc4_apps_clk_src,
530 .clkr.hw.init = &(struct clk_init_data){
531 .name = "sdcc4_apps_clk_src",
532 .parent_names = gcc_xo_gpll0,
534 .ops = &clk_rcg2_floor_ops,
538 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
539 F(960000, P_XO, 10, 1, 2),
540 F(4800000, P_XO, 4, 0, 0),
541 F(9600000, P_XO, 2, 0, 0),
542 F(15000000, P_GPLL0, 10, 1, 4),
543 F(19200000, P_XO, 1, 0, 0),
544 F(25000000, P_GPLL0, 12, 1, 2),
545 F(50000000, P_GPLL0, 12, 0, 0),
549 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
553 .parent_map = gcc_xo_gpll0_map,
554 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "blsp1_qup1_spi_apps_clk_src",
557 .parent_names = gcc_xo_gpll0,
559 .ops = &clk_rcg2_ops,
563 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
564 F(19200000, P_XO, 1, 0, 0),
565 F(50000000, P_GPLL0, 12, 0, 0),
569 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
572 .parent_map = gcc_xo_gpll0_map,
573 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
574 .clkr.hw.init = &(struct clk_init_data){
575 .name = "blsp1_qup1_i2c_apps_clk_src",
576 .parent_names = gcc_xo_gpll0,
578 .ops = &clk_rcg2_ops,
582 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
583 F(3686400, P_GPLL0, 1, 96, 15625),
584 F(7372800, P_GPLL0, 1, 192, 15625),
585 F(14745600, P_GPLL0, 1, 384, 15625),
586 F(16000000, P_GPLL0, 5, 2, 15),
587 F(19200000, P_XO, 1, 0, 0),
588 F(24000000, P_GPLL0, 5, 1, 5),
589 F(32000000, P_GPLL0, 1, 4, 75),
590 F(40000000, P_GPLL0, 15, 0, 0),
591 F(46400000, P_GPLL0, 1, 29, 375),
592 F(48000000, P_GPLL0, 12.5, 0, 0),
593 F(51200000, P_GPLL0, 1, 32, 375),
594 F(56000000, P_GPLL0, 1, 7, 75),
595 F(58982400, P_GPLL0, 1, 1536, 15625),
596 F(60000000, P_GPLL0, 10, 0, 0),
597 F(63157895, P_GPLL0, 9.5, 0, 0),
601 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
605 .parent_map = gcc_xo_gpll0_map,
606 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "blsp1_uart1_apps_clk_src",
609 .parent_names = gcc_xo_gpll0,
611 .ops = &clk_rcg2_ops,
615 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
619 .parent_map = gcc_xo_gpll0_map,
620 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "blsp1_qup2_spi_apps_clk_src",
623 .parent_names = gcc_xo_gpll0,
625 .ops = &clk_rcg2_ops,
629 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
632 .parent_map = gcc_xo_gpll0_map,
633 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
634 .clkr.hw.init = &(struct clk_init_data){
635 .name = "blsp1_qup2_i2c_apps_clk_src",
636 .parent_names = gcc_xo_gpll0,
638 .ops = &clk_rcg2_ops,
642 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
646 .parent_map = gcc_xo_gpll0_map,
647 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "blsp1_uart2_apps_clk_src",
650 .parent_names = gcc_xo_gpll0,
652 .ops = &clk_rcg2_ops,
656 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
660 .parent_map = gcc_xo_gpll0_map,
661 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
662 .clkr.hw.init = &(struct clk_init_data){
663 .name = "blsp1_qup3_spi_apps_clk_src",
664 .parent_names = gcc_xo_gpll0,
666 .ops = &clk_rcg2_ops,
670 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
673 .parent_map = gcc_xo_gpll0_map,
674 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "blsp1_qup3_i2c_apps_clk_src",
677 .parent_names = gcc_xo_gpll0,
679 .ops = &clk_rcg2_ops,
683 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
687 .parent_map = gcc_xo_gpll0_map,
688 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "blsp1_uart3_apps_clk_src",
691 .parent_names = gcc_xo_gpll0,
693 .ops = &clk_rcg2_ops,
697 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
701 .parent_map = gcc_xo_gpll0_map,
702 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
703 .clkr.hw.init = &(struct clk_init_data){
704 .name = "blsp1_qup4_spi_apps_clk_src",
705 .parent_names = gcc_xo_gpll0,
707 .ops = &clk_rcg2_ops,
711 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
714 .parent_map = gcc_xo_gpll0_map,
715 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
716 .clkr.hw.init = &(struct clk_init_data){
717 .name = "blsp1_qup4_i2c_apps_clk_src",
718 .parent_names = gcc_xo_gpll0,
720 .ops = &clk_rcg2_ops,
724 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
728 .parent_map = gcc_xo_gpll0_map,
729 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "blsp1_uart4_apps_clk_src",
732 .parent_names = gcc_xo_gpll0,
734 .ops = &clk_rcg2_ops,
738 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
742 .parent_map = gcc_xo_gpll0_map,
743 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
744 .clkr.hw.init = &(struct clk_init_data){
745 .name = "blsp1_qup5_spi_apps_clk_src",
746 .parent_names = gcc_xo_gpll0,
748 .ops = &clk_rcg2_ops,
752 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
755 .parent_map = gcc_xo_gpll0_map,
756 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "blsp1_qup5_i2c_apps_clk_src",
759 .parent_names = gcc_xo_gpll0,
761 .ops = &clk_rcg2_ops,
765 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
769 .parent_map = gcc_xo_gpll0_map,
770 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "blsp1_uart5_apps_clk_src",
773 .parent_names = gcc_xo_gpll0,
775 .ops = &clk_rcg2_ops,
779 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
783 .parent_map = gcc_xo_gpll0_map,
784 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
785 .clkr.hw.init = &(struct clk_init_data){
786 .name = "blsp1_qup6_spi_apps_clk_src",
787 .parent_names = gcc_xo_gpll0,
789 .ops = &clk_rcg2_ops,
793 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
796 .parent_map = gcc_xo_gpll0_map,
797 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "blsp1_qup6_i2c_apps_clk_src",
800 .parent_names = gcc_xo_gpll0,
802 .ops = &clk_rcg2_ops,
806 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
810 .parent_map = gcc_xo_gpll0_map,
811 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
812 .clkr.hw.init = &(struct clk_init_data){
813 .name = "blsp1_uart6_apps_clk_src",
814 .parent_names = gcc_xo_gpll0,
816 .ops = &clk_rcg2_ops,
820 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
824 .parent_map = gcc_xo_gpll0_map,
825 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "blsp2_qup1_spi_apps_clk_src",
828 .parent_names = gcc_xo_gpll0,
830 .ops = &clk_rcg2_ops,
834 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
837 .parent_map = gcc_xo_gpll0_map,
838 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "blsp2_qup1_i2c_apps_clk_src",
841 .parent_names = gcc_xo_gpll0,
843 .ops = &clk_rcg2_ops,
847 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
851 .parent_map = gcc_xo_gpll0_map,
852 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
853 .clkr.hw.init = &(struct clk_init_data){
854 .name = "blsp2_uart1_apps_clk_src",
855 .parent_names = gcc_xo_gpll0,
857 .ops = &clk_rcg2_ops,
861 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
865 .parent_map = gcc_xo_gpll0_map,
866 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
867 .clkr.hw.init = &(struct clk_init_data){
868 .name = "blsp2_qup2_spi_apps_clk_src",
869 .parent_names = gcc_xo_gpll0,
871 .ops = &clk_rcg2_ops,
875 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
878 .parent_map = gcc_xo_gpll0_map,
879 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "blsp2_qup2_i2c_apps_clk_src",
882 .parent_names = gcc_xo_gpll0,
884 .ops = &clk_rcg2_ops,
888 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
892 .parent_map = gcc_xo_gpll0_map,
893 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
894 .clkr.hw.init = &(struct clk_init_data){
895 .name = "blsp2_uart2_apps_clk_src",
896 .parent_names = gcc_xo_gpll0,
898 .ops = &clk_rcg2_ops,
902 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
906 .parent_map = gcc_xo_gpll0_map,
907 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
908 .clkr.hw.init = &(struct clk_init_data){
909 .name = "blsp2_qup3_spi_apps_clk_src",
910 .parent_names = gcc_xo_gpll0,
912 .ops = &clk_rcg2_ops,
916 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
919 .parent_map = gcc_xo_gpll0_map,
920 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
921 .clkr.hw.init = &(struct clk_init_data){
922 .name = "blsp2_qup3_i2c_apps_clk_src",
923 .parent_names = gcc_xo_gpll0,
925 .ops = &clk_rcg2_ops,
929 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
933 .parent_map = gcc_xo_gpll0_map,
934 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "blsp2_uart3_apps_clk_src",
937 .parent_names = gcc_xo_gpll0,
939 .ops = &clk_rcg2_ops,
943 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
947 .parent_map = gcc_xo_gpll0_map,
948 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "blsp2_qup4_spi_apps_clk_src",
951 .parent_names = gcc_xo_gpll0,
953 .ops = &clk_rcg2_ops,
957 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
960 .parent_map = gcc_xo_gpll0_map,
961 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
962 .clkr.hw.init = &(struct clk_init_data){
963 .name = "blsp2_qup4_i2c_apps_clk_src",
964 .parent_names = gcc_xo_gpll0,
966 .ops = &clk_rcg2_ops,
970 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
974 .parent_map = gcc_xo_gpll0_map,
975 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "blsp2_uart4_apps_clk_src",
978 .parent_names = gcc_xo_gpll0,
980 .ops = &clk_rcg2_ops,
984 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
988 .parent_map = gcc_xo_gpll0_map,
989 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "blsp2_qup5_spi_apps_clk_src",
992 .parent_names = gcc_xo_gpll0,
994 .ops = &clk_rcg2_ops,
998 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1001 .parent_map = gcc_xo_gpll0_map,
1002 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1003 .clkr.hw.init = &(struct clk_init_data){
1004 .name = "blsp2_qup5_i2c_apps_clk_src",
1005 .parent_names = gcc_xo_gpll0,
1007 .ops = &clk_rcg2_ops,
1011 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1012 .cmd_rcgr = 0x2f00c,
1015 .parent_map = gcc_xo_gpll0_map,
1016 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "blsp2_uart5_apps_clk_src",
1019 .parent_names = gcc_xo_gpll0,
1021 .ops = &clk_rcg2_ops,
1025 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1026 .cmd_rcgr = 0x3000c,
1029 .parent_map = gcc_xo_gpll0_map,
1030 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "blsp2_qup6_spi_apps_clk_src",
1033 .parent_names = gcc_xo_gpll0,
1035 .ops = &clk_rcg2_ops,
1039 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1040 .cmd_rcgr = 0x30020,
1042 .parent_map = gcc_xo_gpll0_map,
1043 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1044 .clkr.hw.init = &(struct clk_init_data){
1045 .name = "blsp2_qup6_i2c_apps_clk_src",
1046 .parent_names = gcc_xo_gpll0,
1048 .ops = &clk_rcg2_ops,
1052 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1053 .cmd_rcgr = 0x3100c,
1056 .parent_map = gcc_xo_gpll0_map,
1057 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1058 .clkr.hw.init = &(struct clk_init_data){
1059 .name = "blsp2_uart6_apps_clk_src",
1060 .parent_names = gcc_xo_gpll0,
1062 .ops = &clk_rcg2_ops,
1066 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1067 F(60000000, P_GPLL0, 10, 0, 0),
1071 static struct clk_rcg2 pdm2_clk_src = {
1072 .cmd_rcgr = 0x33010,
1074 .parent_map = gcc_xo_gpll0_map,
1075 .freq_tbl = ftbl_pdm2_clk_src,
1076 .clkr.hw.init = &(struct clk_init_data){
1077 .name = "pdm2_clk_src",
1078 .parent_names = gcc_xo_gpll0,
1080 .ops = &clk_rcg2_ops,
1084 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1085 F(105495, P_XO, 1, 1, 182),
1089 static struct clk_rcg2 tsif_ref_clk_src = {
1090 .cmd_rcgr = 0x36010,
1093 .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1094 .freq_tbl = ftbl_tsif_ref_clk_src,
1095 .clkr.hw.init = &(struct clk_init_data){
1096 .name = "tsif_ref_clk_src",
1097 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1099 .ops = &clk_rcg2_ops,
1103 static struct clk_rcg2 gcc_sleep_clk_src = {
1104 .cmd_rcgr = 0x43014,
1106 .parent_map = gcc_sleep_clk_map,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "gcc_sleep_clk_src",
1109 .parent_names = gcc_sleep_clk,
1111 .ops = &clk_rcg2_ops,
1115 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1116 .cmd_rcgr = 0x48040,
1118 .parent_map = gcc_xo_gpll0_map,
1119 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1120 .clkr.hw.init = &(struct clk_init_data){
1121 .name = "hmss_rbcpr_clk_src",
1122 .parent_names = gcc_xo_gpll0,
1124 .ops = &clk_rcg2_ops,
1128 static struct clk_rcg2 hmss_gpll0_clk_src = {
1129 .cmd_rcgr = 0x48058,
1131 .parent_map = gcc_xo_gpll0_map,
1132 .clkr.hw.init = &(struct clk_init_data){
1133 .name = "hmss_gpll0_clk_src",
1134 .parent_names = gcc_xo_gpll0,
1136 .ops = &clk_rcg2_ops,
1140 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1141 F(19200000, P_XO, 1, 0, 0),
1142 F(100000000, P_GPLL0, 6, 0, 0),
1143 F(200000000, P_GPLL0, 3, 0, 0),
1147 static struct clk_rcg2 gp1_clk_src = {
1148 .cmd_rcgr = 0x64004,
1151 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1152 .freq_tbl = ftbl_gp1_clk_src,
1153 .clkr.hw.init = &(struct clk_init_data){
1154 .name = "gp1_clk_src",
1155 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1157 .ops = &clk_rcg2_ops,
1161 static struct clk_rcg2 gp2_clk_src = {
1162 .cmd_rcgr = 0x65004,
1165 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1166 .freq_tbl = ftbl_gp1_clk_src,
1167 .clkr.hw.init = &(struct clk_init_data){
1168 .name = "gp2_clk_src",
1169 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1171 .ops = &clk_rcg2_ops,
1175 static struct clk_rcg2 gp3_clk_src = {
1176 .cmd_rcgr = 0x66004,
1179 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1180 .freq_tbl = ftbl_gp1_clk_src,
1181 .clkr.hw.init = &(struct clk_init_data){
1182 .name = "gp3_clk_src",
1183 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1185 .ops = &clk_rcg2_ops,
1189 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1190 F(1010526, P_XO, 1, 1, 19),
1194 static struct clk_rcg2 pcie_aux_clk_src = {
1195 .cmd_rcgr = 0x6c000,
1198 .parent_map = gcc_xo_sleep_clk_map,
1199 .freq_tbl = ftbl_pcie_aux_clk_src,
1200 .clkr.hw.init = &(struct clk_init_data){
1201 .name = "pcie_aux_clk_src",
1202 .parent_names = gcc_xo_sleep_clk,
1204 .ops = &clk_rcg2_ops,
1208 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1209 F(100000000, P_GPLL0, 6, 0, 0),
1210 F(200000000, P_GPLL0, 3, 0, 0),
1211 F(240000000, P_GPLL0, 2.5, 0, 0),
1215 static struct clk_rcg2 ufs_axi_clk_src = {
1216 .cmd_rcgr = 0x75024,
1219 .parent_map = gcc_xo_gpll0_map,
1220 .freq_tbl = ftbl_ufs_axi_clk_src,
1221 .clkr.hw.init = &(struct clk_init_data){
1222 .name = "ufs_axi_clk_src",
1223 .parent_names = gcc_xo_gpll0,
1225 .ops = &clk_rcg2_ops,
1229 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1230 F(19200000, P_XO, 1, 0, 0),
1231 F(150000000, P_GPLL0, 4, 0, 0),
1232 F(300000000, P_GPLL0, 2, 0, 0),
1236 static struct clk_rcg2 ufs_ice_core_clk_src = {
1237 .cmd_rcgr = 0x76014,
1239 .parent_map = gcc_xo_gpll0_map,
1240 .freq_tbl = ftbl_ufs_ice_core_clk_src,
1241 .clkr.hw.init = &(struct clk_init_data){
1242 .name = "ufs_ice_core_clk_src",
1243 .parent_names = gcc_xo_gpll0,
1245 .ops = &clk_rcg2_ops,
1249 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1250 F(75000000, P_GPLL0, 8, 0, 0),
1251 F(150000000, P_GPLL0, 4, 0, 0),
1252 F(256000000, P_GPLL4, 1.5, 0, 0),
1253 F(300000000, P_GPLL0, 2, 0, 0),
1257 static struct clk_rcg2 qspi_ser_clk_src = {
1258 .cmd_rcgr = 0x8b00c,
1260 .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1261 .freq_tbl = ftbl_qspi_ser_clk_src,
1262 .clkr.hw.init = &(struct clk_init_data){
1263 .name = "qspi_ser_clk_src",
1264 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1266 .ops = &clk_rcg2_ops,
1270 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1271 .halt_reg = 0x0f03c,
1273 .enable_reg = 0x0f03c,
1274 .enable_mask = BIT(0),
1275 .hw.init = &(struct clk_init_data){
1276 .name = "gcc_sys_noc_usb3_axi_clk",
1277 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1279 .flags = CLK_SET_RATE_PARENT,
1280 .ops = &clk_branch2_ops,
1285 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1286 .halt_reg = 0x75038,
1288 .enable_reg = 0x75038,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "gcc_sys_noc_ufs_axi_clk",
1292 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1294 .flags = CLK_SET_RATE_PARENT,
1295 .ops = &clk_branch2_ops,
1300 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1303 .enable_reg = 0x6010,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "gcc_periph_noc_usb20_ahb_clk",
1307 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1309 .flags = CLK_SET_RATE_PARENT,
1310 .ops = &clk_branch2_ops,
1315 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1318 .enable_reg = 0x9008,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "gcc_mmss_noc_cfg_ahb_clk",
1322 .parent_names = (const char *[]){ "config_noc_clk_src" },
1324 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1333 .enable_reg = 0x9010,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "gcc_mmss_bimc_gfx_clk",
1337 .flags = CLK_SET_RATE_PARENT,
1338 .ops = &clk_branch2_ops,
1343 static struct clk_branch gcc_usb30_master_clk = {
1344 .halt_reg = 0x0f008,
1346 .enable_reg = 0x0f008,
1347 .enable_mask = BIT(0),
1348 .hw.init = &(struct clk_init_data){
1349 .name = "gcc_usb30_master_clk",
1350 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1352 .flags = CLK_SET_RATE_PARENT,
1353 .ops = &clk_branch2_ops,
1358 static struct clk_branch gcc_usb30_sleep_clk = {
1359 .halt_reg = 0x0f00c,
1361 .enable_reg = 0x0f00c,
1362 .enable_mask = BIT(0),
1363 .hw.init = &(struct clk_init_data){
1364 .name = "gcc_usb30_sleep_clk",
1365 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1367 .flags = CLK_SET_RATE_PARENT,
1368 .ops = &clk_branch2_ops,
1373 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1374 .halt_reg = 0x0f010,
1376 .enable_reg = 0x0f010,
1377 .enable_mask = BIT(0),
1378 .hw.init = &(struct clk_init_data){
1379 .name = "gcc_usb30_mock_utmi_clk",
1380 .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1382 .flags = CLK_SET_RATE_PARENT,
1383 .ops = &clk_branch2_ops,
1388 static struct clk_branch gcc_usb3_phy_aux_clk = {
1389 .halt_reg = 0x50000,
1391 .enable_reg = 0x50000,
1392 .enable_mask = BIT(0),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gcc_usb3_phy_aux_clk",
1395 .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1403 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1404 .halt_reg = 0x50004,
1405 .halt_check = BRANCH_HALT_SKIP,
1407 .enable_reg = 0x50004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_usb3_phy_pipe_clk",
1411 .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1419 static struct clk_branch gcc_usb20_master_clk = {
1420 .halt_reg = 0x12004,
1422 .enable_reg = 0x12004,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_usb20_master_clk",
1426 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1434 static struct clk_branch gcc_usb20_sleep_clk = {
1435 .halt_reg = 0x12008,
1437 .enable_reg = 0x12008,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_usb20_sleep_clk",
1441 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1443 .flags = CLK_SET_RATE_PARENT,
1444 .ops = &clk_branch2_ops,
1449 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1450 .halt_reg = 0x1200c,
1452 .enable_reg = 0x1200c,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_usb20_mock_utmi_clk",
1456 .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1458 .flags = CLK_SET_RATE_PARENT,
1459 .ops = &clk_branch2_ops,
1464 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1465 .halt_reg = 0x6a004,
1467 .enable_reg = 0x6a004,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1471 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1473 .flags = CLK_SET_RATE_PARENT,
1474 .ops = &clk_branch2_ops,
1479 static struct clk_branch gcc_sdcc1_apps_clk = {
1480 .halt_reg = 0x13004,
1482 .enable_reg = 0x13004,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "gcc_sdcc1_apps_clk",
1486 .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1494 static struct clk_branch gcc_sdcc1_ahb_clk = {
1495 .halt_reg = 0x13008,
1497 .enable_reg = 0x13008,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "gcc_sdcc1_ahb_clk",
1501 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1509 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1510 .halt_reg = 0x13038,
1512 .enable_reg = 0x13038,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "gcc_sdcc1_ice_core_clk",
1516 .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1524 static struct clk_branch gcc_sdcc2_apps_clk = {
1525 .halt_reg = 0x14004,
1527 .enable_reg = 0x14004,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_sdcc2_apps_clk",
1531 .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1533 .flags = CLK_SET_RATE_PARENT,
1534 .ops = &clk_branch2_ops,
1539 static struct clk_branch gcc_sdcc2_ahb_clk = {
1540 .halt_reg = 0x14008,
1542 .enable_reg = 0x14008,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_sdcc2_ahb_clk",
1546 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1548 .flags = CLK_SET_RATE_PARENT,
1549 .ops = &clk_branch2_ops,
1554 static struct clk_branch gcc_sdcc3_apps_clk = {
1555 .halt_reg = 0x15004,
1557 .enable_reg = 0x15004,
1558 .enable_mask = BIT(0),
1559 .hw.init = &(struct clk_init_data){
1560 .name = "gcc_sdcc3_apps_clk",
1561 .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch gcc_sdcc3_ahb_clk = {
1570 .halt_reg = 0x15008,
1572 .enable_reg = 0x15008,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_sdcc3_ahb_clk",
1576 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1584 static struct clk_branch gcc_sdcc4_apps_clk = {
1585 .halt_reg = 0x16004,
1587 .enable_reg = 0x16004,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_sdcc4_apps_clk",
1591 .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1593 .flags = CLK_SET_RATE_PARENT,
1594 .ops = &clk_branch2_ops,
1599 static struct clk_branch gcc_sdcc4_ahb_clk = {
1600 .halt_reg = 0x16008,
1602 .enable_reg = 0x16008,
1603 .enable_mask = BIT(0),
1604 .hw.init = &(struct clk_init_data){
1605 .name = "gcc_sdcc4_ahb_clk",
1606 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1614 static struct clk_branch gcc_blsp1_ahb_clk = {
1615 .halt_reg = 0x17004,
1616 .halt_check = BRANCH_HALT_VOTED,
1618 .enable_reg = 0x52004,
1619 .enable_mask = BIT(17),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "gcc_blsp1_ahb_clk",
1622 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1624 .flags = CLK_SET_RATE_PARENT,
1625 .ops = &clk_branch2_ops,
1630 static struct clk_branch gcc_blsp1_sleep_clk = {
1631 .halt_reg = 0x17008,
1632 .halt_check = BRANCH_HALT_VOTED,
1634 .enable_reg = 0x52004,
1635 .enable_mask = BIT(16),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp1_sleep_clk",
1638 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1646 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1647 .halt_reg = 0x19004,
1649 .enable_reg = 0x19004,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_blsp1_qup1_spi_apps_clk",
1653 .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1662 .halt_reg = 0x19008,
1664 .enable_reg = 0x19008,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1668 .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1677 .halt_reg = 0x1a004,
1679 .enable_reg = 0x1a004,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_blsp1_uart1_apps_clk",
1683 .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1692 .halt_reg = 0x1b004,
1694 .enable_reg = 0x1b004,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "gcc_blsp1_qup2_spi_apps_clk",
1698 .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1707 .halt_reg = 0x1b008,
1709 .enable_reg = 0x1b008,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1713 .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1715 .flags = CLK_SET_RATE_PARENT,
1716 .ops = &clk_branch2_ops,
1721 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1722 .halt_reg = 0x1c004,
1724 .enable_reg = 0x1c004,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_blsp1_uart2_apps_clk",
1728 .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1736 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1737 .halt_reg = 0x1d004,
1739 .enable_reg = 0x1d004,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "gcc_blsp1_qup3_spi_apps_clk",
1743 .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1745 .flags = CLK_SET_RATE_PARENT,
1746 .ops = &clk_branch2_ops,
1751 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1752 .halt_reg = 0x1d008,
1754 .enable_reg = 0x1d008,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1758 .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1760 .flags = CLK_SET_RATE_PARENT,
1761 .ops = &clk_branch2_ops,
1766 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1767 .halt_reg = 0x1e004,
1769 .enable_reg = 0x1e004,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_blsp1_uart3_apps_clk",
1773 .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1781 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1782 .halt_reg = 0x1f004,
1784 .enable_reg = 0x1f004,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_blsp1_qup4_spi_apps_clk",
1788 .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1796 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1797 .halt_reg = 0x1f008,
1799 .enable_reg = 0x1f008,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1803 .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1811 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1812 .halt_reg = 0x20004,
1814 .enable_reg = 0x20004,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_blsp1_uart4_apps_clk",
1818 .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1820 .flags = CLK_SET_RATE_PARENT,
1821 .ops = &clk_branch2_ops,
1826 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1827 .halt_reg = 0x21004,
1829 .enable_reg = 0x21004,
1830 .enable_mask = BIT(0),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gcc_blsp1_qup5_spi_apps_clk",
1833 .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1841 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1842 .halt_reg = 0x21008,
1844 .enable_reg = 0x21008,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1848 .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1850 .flags = CLK_SET_RATE_PARENT,
1851 .ops = &clk_branch2_ops,
1856 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1857 .halt_reg = 0x22004,
1859 .enable_reg = 0x22004,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_blsp1_uart5_apps_clk",
1863 .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1871 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1872 .halt_reg = 0x23004,
1874 .enable_reg = 0x23004,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "gcc_blsp1_qup6_spi_apps_clk",
1878 .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1887 .halt_reg = 0x23008,
1889 .enable_reg = 0x23008,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1893 .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1901 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1902 .halt_reg = 0x24004,
1904 .enable_reg = 0x24004,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_blsp1_uart6_apps_clk",
1908 .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1910 .flags = CLK_SET_RATE_PARENT,
1911 .ops = &clk_branch2_ops,
1916 static struct clk_branch gcc_blsp2_ahb_clk = {
1917 .halt_reg = 0x25004,
1918 .halt_check = BRANCH_HALT_VOTED,
1920 .enable_reg = 0x52004,
1921 .enable_mask = BIT(15),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "gcc_blsp2_ahb_clk",
1924 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1926 .flags = CLK_SET_RATE_PARENT,
1927 .ops = &clk_branch2_ops,
1932 static struct clk_branch gcc_blsp2_sleep_clk = {
1933 .halt_reg = 0x25008,
1934 .halt_check = BRANCH_HALT_VOTED,
1936 .enable_reg = 0x52004,
1937 .enable_mask = BIT(14),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_blsp2_sleep_clk",
1940 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1949 .halt_reg = 0x26004,
1951 .enable_reg = 0x26004,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_blsp2_qup1_spi_apps_clk",
1955 .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1963 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1964 .halt_reg = 0x26008,
1966 .enable_reg = 0x26008,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1970 .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1978 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1979 .halt_reg = 0x27004,
1981 .enable_reg = 0x27004,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_blsp2_uart1_apps_clk",
1985 .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1987 .flags = CLK_SET_RATE_PARENT,
1988 .ops = &clk_branch2_ops,
1993 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1994 .halt_reg = 0x28004,
1996 .enable_reg = 0x28004,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_blsp2_qup2_spi_apps_clk",
2000 .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2008 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2009 .halt_reg = 0x28008,
2011 .enable_reg = 0x28008,
2012 .enable_mask = BIT(0),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gcc_blsp2_qup2_i2c_apps_clk",
2015 .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2023 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2024 .halt_reg = 0x29004,
2026 .enable_reg = 0x29004,
2027 .enable_mask = BIT(0),
2028 .hw.init = &(struct clk_init_data){
2029 .name = "gcc_blsp2_uart2_apps_clk",
2030 .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2038 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2039 .halt_reg = 0x2a004,
2041 .enable_reg = 0x2a004,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_blsp2_qup3_spi_apps_clk",
2045 .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2053 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2054 .halt_reg = 0x2a008,
2056 .enable_reg = 0x2a008,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_blsp2_qup3_i2c_apps_clk",
2060 .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2069 .halt_reg = 0x2b004,
2071 .enable_reg = 0x2b004,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_blsp2_uart3_apps_clk",
2075 .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2083 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2084 .halt_reg = 0x2c004,
2086 .enable_reg = 0x2c004,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_blsp2_qup4_spi_apps_clk",
2090 .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2099 .halt_reg = 0x2c008,
2101 .enable_reg = 0x2c008,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_blsp2_qup4_i2c_apps_clk",
2105 .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2113 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2114 .halt_reg = 0x2d004,
2116 .enable_reg = 0x2d004,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_blsp2_uart4_apps_clk",
2120 .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2128 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2129 .halt_reg = 0x2e004,
2131 .enable_reg = 0x2e004,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "gcc_blsp2_qup5_spi_apps_clk",
2135 .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2137 .flags = CLK_SET_RATE_PARENT,
2138 .ops = &clk_branch2_ops,
2143 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2144 .halt_reg = 0x2e008,
2146 .enable_reg = 0x2e008,
2147 .enable_mask = BIT(0),
2148 .hw.init = &(struct clk_init_data){
2149 .name = "gcc_blsp2_qup5_i2c_apps_clk",
2150 .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2159 .halt_reg = 0x2f004,
2161 .enable_reg = 0x2f004,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "gcc_blsp2_uart5_apps_clk",
2165 .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2167 .flags = CLK_SET_RATE_PARENT,
2168 .ops = &clk_branch2_ops,
2173 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2174 .halt_reg = 0x30004,
2176 .enable_reg = 0x30004,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_blsp2_qup6_spi_apps_clk",
2180 .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2182 .flags = CLK_SET_RATE_PARENT,
2183 .ops = &clk_branch2_ops,
2188 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2189 .halt_reg = 0x30008,
2191 .enable_reg = 0x30008,
2192 .enable_mask = BIT(0),
2193 .hw.init = &(struct clk_init_data){
2194 .name = "gcc_blsp2_qup6_i2c_apps_clk",
2195 .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2204 .halt_reg = 0x31004,
2206 .enable_reg = 0x31004,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_blsp2_uart6_apps_clk",
2210 .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2212 .flags = CLK_SET_RATE_PARENT,
2213 .ops = &clk_branch2_ops,
2218 static struct clk_branch gcc_pdm_ahb_clk = {
2219 .halt_reg = 0x33004,
2221 .enable_reg = 0x33004,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_pdm_ahb_clk",
2225 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2227 .flags = CLK_SET_RATE_PARENT,
2228 .ops = &clk_branch2_ops,
2233 static struct clk_branch gcc_pdm2_clk = {
2234 .halt_reg = 0x3300c,
2236 .enable_reg = 0x3300c,
2237 .enable_mask = BIT(0),
2238 .hw.init = &(struct clk_init_data){
2239 .name = "gcc_pdm2_clk",
2240 .parent_names = (const char *[]){ "pdm2_clk_src" },
2242 .flags = CLK_SET_RATE_PARENT,
2243 .ops = &clk_branch2_ops,
2248 static struct clk_branch gcc_prng_ahb_clk = {
2249 .halt_reg = 0x34004,
2250 .halt_check = BRANCH_HALT_VOTED,
2252 .enable_reg = 0x52004,
2253 .enable_mask = BIT(13),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_prng_ahb_clk",
2256 .parent_names = (const char *[]){ "config_noc_clk_src" },
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2264 static struct clk_branch gcc_tsif_ahb_clk = {
2265 .halt_reg = 0x36004,
2267 .enable_reg = 0x36004,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "gcc_tsif_ahb_clk",
2271 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2273 .flags = CLK_SET_RATE_PARENT,
2274 .ops = &clk_branch2_ops,
2279 static struct clk_branch gcc_tsif_ref_clk = {
2280 .halt_reg = 0x36008,
2282 .enable_reg = 0x36008,
2283 .enable_mask = BIT(0),
2284 .hw.init = &(struct clk_init_data){
2285 .name = "gcc_tsif_ref_clk",
2286 .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2288 .flags = CLK_SET_RATE_PARENT,
2289 .ops = &clk_branch2_ops,
2294 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2295 .halt_reg = 0x3600c,
2297 .enable_reg = 0x3600c,
2298 .enable_mask = BIT(0),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_tsif_inactivity_timers_clk",
2301 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2303 .flags = CLK_SET_RATE_PARENT,
2304 .ops = &clk_branch2_ops,
2309 static struct clk_branch gcc_boot_rom_ahb_clk = {
2310 .halt_reg = 0x38004,
2311 .halt_check = BRANCH_HALT_VOTED,
2313 .enable_reg = 0x52004,
2314 .enable_mask = BIT(10),
2315 .hw.init = &(struct clk_init_data){
2316 .name = "gcc_boot_rom_ahb_clk",
2317 .parent_names = (const char *[]){ "config_noc_clk_src" },
2319 .flags = CLK_SET_RATE_PARENT,
2320 .ops = &clk_branch2_ops,
2325 static struct clk_branch gcc_bimc_gfx_clk = {
2326 .halt_reg = 0x46018,
2328 .enable_reg = 0x46018,
2329 .enable_mask = BIT(0),
2330 .hw.init = &(struct clk_init_data){
2331 .name = "gcc_bimc_gfx_clk",
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2338 static struct clk_branch gcc_hmss_rbcpr_clk = {
2339 .halt_reg = 0x4800c,
2341 .enable_reg = 0x4800c,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_hmss_rbcpr_clk",
2345 .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2353 static struct clk_branch gcc_gp1_clk = {
2354 .halt_reg = 0x64000,
2356 .enable_reg = 0x64000,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gcc_gp1_clk",
2360 .parent_names = (const char *[]){ "gp1_clk_src" },
2362 .flags = CLK_SET_RATE_PARENT,
2363 .ops = &clk_branch2_ops,
2368 static struct clk_branch gcc_gp2_clk = {
2369 .halt_reg = 0x65000,
2371 .enable_reg = 0x65000,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_gp2_clk",
2375 .parent_names = (const char *[]){ "gp2_clk_src" },
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2383 static struct clk_branch gcc_gp3_clk = {
2384 .halt_reg = 0x66000,
2386 .enable_reg = 0x66000,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "gcc_gp3_clk",
2390 .parent_names = (const char *[]){ "gp3_clk_src" },
2392 .flags = CLK_SET_RATE_PARENT,
2393 .ops = &clk_branch2_ops,
2398 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2399 .halt_reg = 0x6b008,
2401 .enable_reg = 0x6b008,
2402 .enable_mask = BIT(0),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "gcc_pcie_0_slv_axi_clk",
2405 .parent_names = (const char *[]){ "system_noc_clk_src" },
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2413 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2414 .halt_reg = 0x6b00c,
2416 .enable_reg = 0x6b00c,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "gcc_pcie_0_mstr_axi_clk",
2420 .parent_names = (const char *[]){ "system_noc_clk_src" },
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2429 .halt_reg = 0x6b010,
2431 .enable_reg = 0x6b010,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_pcie_0_cfg_ahb_clk",
2435 .parent_names = (const char *[]){ "config_noc_clk_src" },
2437 .flags = CLK_SET_RATE_PARENT,
2438 .ops = &clk_branch2_ops,
2443 static struct clk_branch gcc_pcie_0_aux_clk = {
2444 .halt_reg = 0x6b014,
2446 .enable_reg = 0x6b014,
2447 .enable_mask = BIT(0),
2448 .hw.init = &(struct clk_init_data){
2449 .name = "gcc_pcie_0_aux_clk",
2450 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2452 .flags = CLK_SET_RATE_PARENT,
2453 .ops = &clk_branch2_ops,
2458 static struct clk_branch gcc_pcie_0_pipe_clk = {
2459 .halt_reg = 0x6b018,
2460 .halt_check = BRANCH_HALT_SKIP,
2462 .enable_reg = 0x6b018,
2463 .enable_mask = BIT(0),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "gcc_pcie_0_pipe_clk",
2466 .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2468 .flags = CLK_SET_RATE_PARENT,
2469 .ops = &clk_branch2_ops,
2474 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2475 .halt_reg = 0x6d008,
2477 .enable_reg = 0x6d008,
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_pcie_1_slv_axi_clk",
2481 .parent_names = (const char *[]){ "system_noc_clk_src" },
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2490 .halt_reg = 0x6d00c,
2492 .enable_reg = 0x6d00c,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_pcie_1_mstr_axi_clk",
2496 .parent_names = (const char *[]){ "system_noc_clk_src" },
2498 .flags = CLK_SET_RATE_PARENT,
2499 .ops = &clk_branch2_ops,
2504 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2505 .halt_reg = 0x6d010,
2507 .enable_reg = 0x6d010,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_pcie_1_cfg_ahb_clk",
2511 .parent_names = (const char *[]){ "config_noc_clk_src" },
2513 .flags = CLK_SET_RATE_PARENT,
2514 .ops = &clk_branch2_ops,
2519 static struct clk_branch gcc_pcie_1_aux_clk = {
2520 .halt_reg = 0x6d014,
2522 .enable_reg = 0x6d014,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "gcc_pcie_1_aux_clk",
2526 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2528 .flags = CLK_SET_RATE_PARENT,
2529 .ops = &clk_branch2_ops,
2534 static struct clk_branch gcc_pcie_1_pipe_clk = {
2535 .halt_reg = 0x6d018,
2536 .halt_check = BRANCH_HALT_SKIP,
2538 .enable_reg = 0x6d018,
2539 .enable_mask = BIT(0),
2540 .hw.init = &(struct clk_init_data){
2541 .name = "gcc_pcie_1_pipe_clk",
2542 .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2544 .flags = CLK_SET_RATE_PARENT,
2545 .ops = &clk_branch2_ops,
2550 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2551 .halt_reg = 0x6e008,
2553 .enable_reg = 0x6e008,
2554 .enable_mask = BIT(0),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "gcc_pcie_2_slv_axi_clk",
2557 .parent_names = (const char *[]){ "system_noc_clk_src" },
2559 .flags = CLK_SET_RATE_PARENT,
2560 .ops = &clk_branch2_ops,
2565 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2566 .halt_reg = 0x6e00c,
2568 .enable_reg = 0x6e00c,
2569 .enable_mask = BIT(0),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gcc_pcie_2_mstr_axi_clk",
2572 .parent_names = (const char *[]){ "system_noc_clk_src" },
2574 .flags = CLK_SET_RATE_PARENT,
2575 .ops = &clk_branch2_ops,
2580 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2581 .halt_reg = 0x6e010,
2583 .enable_reg = 0x6e010,
2584 .enable_mask = BIT(0),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gcc_pcie_2_cfg_ahb_clk",
2587 .parent_names = (const char *[]){ "config_noc_clk_src" },
2589 .flags = CLK_SET_RATE_PARENT,
2590 .ops = &clk_branch2_ops,
2595 static struct clk_branch gcc_pcie_2_aux_clk = {
2596 .halt_reg = 0x6e014,
2598 .enable_reg = 0x6e014,
2599 .enable_mask = BIT(0),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_pcie_2_aux_clk",
2602 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2604 .flags = CLK_SET_RATE_PARENT,
2605 .ops = &clk_branch2_ops,
2610 static struct clk_branch gcc_pcie_2_pipe_clk = {
2611 .halt_reg = 0x6e018,
2612 .halt_check = BRANCH_HALT_SKIP,
2614 .enable_reg = 0x6e018,
2615 .enable_mask = BIT(0),
2616 .hw.init = &(struct clk_init_data){
2617 .name = "gcc_pcie_2_pipe_clk",
2618 .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2620 .flags = CLK_SET_RATE_PARENT,
2621 .ops = &clk_branch2_ops,
2626 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2627 .halt_reg = 0x6f004,
2629 .enable_reg = 0x6f004,
2630 .enable_mask = BIT(0),
2631 .hw.init = &(struct clk_init_data){
2632 .name = "gcc_pcie_phy_cfg_ahb_clk",
2633 .parent_names = (const char *[]){ "config_noc_clk_src" },
2635 .flags = CLK_SET_RATE_PARENT,
2636 .ops = &clk_branch2_ops,
2641 static struct clk_branch gcc_pcie_phy_aux_clk = {
2642 .halt_reg = 0x6f008,
2644 .enable_reg = 0x6f008,
2645 .enable_mask = BIT(0),
2646 .hw.init = &(struct clk_init_data){
2647 .name = "gcc_pcie_phy_aux_clk",
2648 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2650 .flags = CLK_SET_RATE_PARENT,
2651 .ops = &clk_branch2_ops,
2656 static struct clk_branch gcc_ufs_axi_clk = {
2657 .halt_reg = 0x75008,
2659 .enable_reg = 0x75008,
2660 .enable_mask = BIT(0),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "gcc_ufs_axi_clk",
2663 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2665 .flags = CLK_SET_RATE_PARENT,
2666 .ops = &clk_branch2_ops,
2671 static struct clk_branch gcc_ufs_ahb_clk = {
2672 .halt_reg = 0x7500c,
2674 .enable_reg = 0x7500c,
2675 .enable_mask = BIT(0),
2676 .hw.init = &(struct clk_init_data){
2677 .name = "gcc_ufs_ahb_clk",
2678 .parent_names = (const char *[]){ "config_noc_clk_src" },
2680 .flags = CLK_SET_RATE_PARENT,
2681 .ops = &clk_branch2_ops,
2686 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2689 .hw.init = &(struct clk_init_data){
2690 .name = "ufs_tx_cfg_clk_src",
2691 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2693 .flags = CLK_SET_RATE_PARENT,
2694 .ops = &clk_fixed_factor_ops,
2698 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2699 .halt_reg = 0x75010,
2701 .enable_reg = 0x75010,
2702 .enable_mask = BIT(0),
2703 .hw.init = &(struct clk_init_data){
2704 .name = "gcc_ufs_tx_cfg_clk",
2705 .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2707 .flags = CLK_SET_RATE_PARENT,
2708 .ops = &clk_branch2_ops,
2713 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2716 .hw.init = &(struct clk_init_data){
2717 .name = "ufs_rx_cfg_clk_src",
2718 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2720 .flags = CLK_SET_RATE_PARENT,
2721 .ops = &clk_fixed_factor_ops,
2725 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2726 .halt_reg = 0x7d010,
2727 .halt_check = BRANCH_HALT_VOTED,
2729 .enable_reg = 0x7d010,
2730 .enable_mask = BIT(0),
2731 .hw.init = &(struct clk_init_data){
2732 .name = "hlos1_vote_lpass_core_smmu_clk",
2733 .ops = &clk_branch2_ops,
2738 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2739 .halt_reg = 0x7d014,
2740 .halt_check = BRANCH_HALT_VOTED,
2742 .enable_reg = 0x7d014,
2743 .enable_mask = BIT(0),
2744 .hw.init = &(struct clk_init_data){
2745 .name = "hlos1_vote_lpass_adsp_smmu_clk",
2746 .ops = &clk_branch2_ops,
2751 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2752 .halt_reg = 0x75014,
2754 .enable_reg = 0x75014,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "gcc_ufs_rx_cfg_clk",
2758 .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2760 .flags = CLK_SET_RATE_PARENT,
2761 .ops = &clk_branch2_ops,
2766 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2767 .halt_reg = 0x75018,
2768 .halt_check = BRANCH_HALT_SKIP,
2770 .enable_reg = 0x75018,
2771 .enable_mask = BIT(0),
2772 .hw.init = &(struct clk_init_data){
2773 .name = "gcc_ufs_tx_symbol_0_clk",
2774 .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2776 .flags = CLK_SET_RATE_PARENT,
2777 .ops = &clk_branch2_ops,
2782 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2783 .halt_reg = 0x7501c,
2784 .halt_check = BRANCH_HALT_SKIP,
2786 .enable_reg = 0x7501c,
2787 .enable_mask = BIT(0),
2788 .hw.init = &(struct clk_init_data){
2789 .name = "gcc_ufs_rx_symbol_0_clk",
2790 .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2792 .flags = CLK_SET_RATE_PARENT,
2793 .ops = &clk_branch2_ops,
2798 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2799 .halt_reg = 0x75020,
2800 .halt_check = BRANCH_HALT_SKIP,
2802 .enable_reg = 0x75020,
2803 .enable_mask = BIT(0),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "gcc_ufs_rx_symbol_1_clk",
2806 .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2808 .flags = CLK_SET_RATE_PARENT,
2809 .ops = &clk_branch2_ops,
2814 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2817 .hw.init = &(struct clk_init_data){
2818 .name = "ufs_ice_core_postdiv_clk_src",
2819 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2821 .flags = CLK_SET_RATE_PARENT,
2822 .ops = &clk_fixed_factor_ops,
2826 static struct clk_branch gcc_ufs_unipro_core_clk = {
2827 .halt_reg = 0x7600c,
2829 .enable_reg = 0x7600c,
2830 .enable_mask = BIT(0),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "gcc_ufs_unipro_core_clk",
2833 .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2841 static struct clk_branch gcc_ufs_ice_core_clk = {
2842 .halt_reg = 0x76010,
2844 .enable_reg = 0x76010,
2845 .enable_mask = BIT(0),
2846 .hw.init = &(struct clk_init_data){
2847 .name = "gcc_ufs_ice_core_clk",
2848 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2850 .flags = CLK_SET_RATE_PARENT,
2851 .ops = &clk_branch2_ops,
2856 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2857 .halt_check = BRANCH_HALT_DELAY,
2859 .enable_reg = 0x76030,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "gcc_ufs_sys_clk_core_clk",
2863 .ops = &clk_branch2_ops,
2868 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2869 .halt_check = BRANCH_HALT_DELAY,
2871 .enable_reg = 0x76034,
2872 .enable_mask = BIT(0),
2873 .hw.init = &(struct clk_init_data){
2874 .name = "gcc_ufs_tx_symbol_clk_core_clk",
2875 .ops = &clk_branch2_ops,
2880 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2881 .halt_reg = 0x81008,
2883 .enable_reg = 0x81008,
2884 .enable_mask = BIT(0),
2885 .hw.init = &(struct clk_init_data){
2886 .name = "gcc_aggre0_snoc_axi_clk",
2887 .parent_names = (const char *[]){ "system_noc_clk_src" },
2889 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2890 .ops = &clk_branch2_ops,
2895 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2896 .halt_reg = 0x8100c,
2898 .enable_reg = 0x8100c,
2899 .enable_mask = BIT(0),
2900 .hw.init = &(struct clk_init_data){
2901 .name = "gcc_aggre0_cnoc_ahb_clk",
2902 .parent_names = (const char *[]){ "config_noc_clk_src" },
2904 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2905 .ops = &clk_branch2_ops,
2910 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2911 .halt_reg = 0x81014,
2913 .enable_reg = 0x81014,
2914 .enable_mask = BIT(0),
2915 .hw.init = &(struct clk_init_data){
2916 .name = "gcc_smmu_aggre0_axi_clk",
2917 .parent_names = (const char *[]){ "system_noc_clk_src" },
2919 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2920 .ops = &clk_branch2_ops,
2925 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2926 .halt_reg = 0x81018,
2928 .enable_reg = 0x81018,
2929 .enable_mask = BIT(0),
2930 .hw.init = &(struct clk_init_data){
2931 .name = "gcc_smmu_aggre0_ahb_clk",
2932 .parent_names = (const char *[]){ "config_noc_clk_src" },
2934 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2935 .ops = &clk_branch2_ops,
2940 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2941 .halt_reg = 0x83014,
2943 .enable_reg = 0x83014,
2944 .enable_mask = BIT(0),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_aggre2_ufs_axi_clk",
2947 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2949 .flags = CLK_SET_RATE_PARENT,
2950 .ops = &clk_branch2_ops,
2955 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2956 .halt_reg = 0x83018,
2958 .enable_reg = 0x83018,
2959 .enable_mask = BIT(0),
2960 .hw.init = &(struct clk_init_data){
2961 .name = "gcc_aggre2_usb3_axi_clk",
2962 .parent_names = (const char *[]){ "usb30_master_clk_src" },
2964 .flags = CLK_SET_RATE_PARENT,
2965 .ops = &clk_branch2_ops,
2970 static struct clk_branch gcc_dcc_ahb_clk = {
2971 .halt_reg = 0x84004,
2973 .enable_reg = 0x84004,
2974 .enable_mask = BIT(0),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "gcc_dcc_ahb_clk",
2977 .parent_names = (const char *[]){ "config_noc_clk_src" },
2979 .ops = &clk_branch2_ops,
2984 static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
2985 .halt_reg = 0x85000,
2987 .enable_reg = 0x85000,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
2991 .parent_names = (const char *[]){ "config_noc_clk_src" },
2993 .ops = &clk_branch2_ops,
2998 static struct clk_branch gcc_qspi_ahb_clk = {
2999 .halt_reg = 0x8b004,
3001 .enable_reg = 0x8b004,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_qspi_ahb_clk",
3005 .parent_names = (const char *[]){ "periph_noc_clk_src" },
3007 .flags = CLK_SET_RATE_PARENT,
3008 .ops = &clk_branch2_ops,
3013 static struct clk_branch gcc_qspi_ser_clk = {
3014 .halt_reg = 0x8b008,
3016 .enable_reg = 0x8b008,
3017 .enable_mask = BIT(0),
3018 .hw.init = &(struct clk_init_data){
3019 .name = "gcc_qspi_ser_clk",
3020 .parent_names = (const char *[]){ "qspi_ser_clk_src" },
3022 .flags = CLK_SET_RATE_PARENT,
3023 .ops = &clk_branch2_ops,
3028 static struct clk_branch gcc_usb3_clkref_clk = {
3029 .halt_reg = 0x8800C,
3031 .enable_reg = 0x8800C,
3032 .enable_mask = BIT(0),
3033 .hw.init = &(struct clk_init_data){
3034 .name = "gcc_usb3_clkref_clk",
3035 .parent_data = &(const struct clk_parent_data){
3040 .ops = &clk_branch2_ops,
3045 static struct clk_branch gcc_hdmi_clkref_clk = {
3046 .halt_reg = 0x88000,
3048 .enable_reg = 0x88000,
3049 .enable_mask = BIT(0),
3050 .hw.init = &(struct clk_init_data){
3051 .name = "gcc_hdmi_clkref_clk",
3052 .parent_data = &(const struct clk_parent_data){
3057 .ops = &clk_branch2_ops,
3062 static struct clk_branch gcc_edp_clkref_clk = {
3063 .halt_reg = 0x88004,
3065 .enable_reg = 0x88004,
3066 .enable_mask = BIT(0),
3067 .hw.init = &(struct clk_init_data){
3068 .name = "gcc_edp_clkref_clk",
3069 .parent_data = &(const struct clk_parent_data){
3074 .ops = &clk_branch2_ops,
3079 static struct clk_branch gcc_ufs_clkref_clk = {
3080 .halt_reg = 0x88008,
3082 .enable_reg = 0x88008,
3083 .enable_mask = BIT(0),
3084 .hw.init = &(struct clk_init_data){
3085 .name = "gcc_ufs_clkref_clk",
3086 .parent_data = &(const struct clk_parent_data){
3091 .ops = &clk_branch2_ops,
3096 static struct clk_branch gcc_pcie_clkref_clk = {
3097 .halt_reg = 0x88010,
3099 .enable_reg = 0x88010,
3100 .enable_mask = BIT(0),
3101 .hw.init = &(struct clk_init_data){
3102 .name = "gcc_pcie_clkref_clk",
3103 .parent_data = &(const struct clk_parent_data){
3108 .ops = &clk_branch2_ops,
3113 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3114 .halt_reg = 0x88014,
3116 .enable_reg = 0x88014,
3117 .enable_mask = BIT(0),
3118 .hw.init = &(struct clk_init_data){
3119 .name = "gcc_rx2_usb2_clkref_clk",
3120 .parent_data = &(const struct clk_parent_data){
3125 .ops = &clk_branch2_ops,
3130 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3131 .halt_reg = 0x88018,
3133 .enable_reg = 0x88018,
3134 .enable_mask = BIT(0),
3135 .hw.init = &(struct clk_init_data){
3136 .name = "gcc_rx1_usb2_clkref_clk",
3137 .parent_data = &(const struct clk_parent_data){
3142 .ops = &clk_branch2_ops,
3147 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3148 .halt_reg = 0x8a000,
3150 .enable_reg = 0x8a000,
3151 .enable_mask = BIT(0),
3152 .hw.init = &(struct clk_init_data){
3153 .name = "gcc_mss_cfg_ahb_clk",
3154 .parent_names = (const char *[]){ "config_noc_clk_src" },
3156 .ops = &clk_branch2_ops,
3161 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3162 .halt_reg = 0x8a004,
3164 .enable_reg = 0x8a004,
3165 .enable_mask = BIT(0),
3166 .hw.init = &(struct clk_init_data){
3167 .name = "gcc_mss_mnoc_bimc_axi_clk",
3168 .parent_names = (const char *[]){ "system_noc_clk_src" },
3170 .ops = &clk_branch2_ops,
3175 static struct clk_branch gcc_mss_snoc_axi_clk = {
3176 .halt_reg = 0x8a024,
3178 .enable_reg = 0x8a024,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_mss_snoc_axi_clk",
3182 .parent_names = (const char *[]){ "system_noc_clk_src" },
3184 .ops = &clk_branch2_ops,
3189 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3190 .halt_reg = 0x8a028,
3192 .enable_reg = 0x8a028,
3193 .enable_mask = BIT(0),
3194 .hw.init = &(struct clk_init_data){
3195 .name = "gcc_mss_q6_bimc_axi_clk",
3196 .parent_names = (const char *[]){ "system_noc_clk_src" },
3198 .ops = &clk_branch2_ops,
3203 static struct clk_hw *gcc_msm8996_hws[] = {
3205 &gpll0_early_div.hw,
3206 &ufs_tx_cfg_clk_src.hw,
3207 &ufs_rx_cfg_clk_src.hw,
3208 &ufs_ice_core_postdiv_clk_src.hw,
3211 static struct gdsc aggre0_noc_gdsc = {
3213 .gds_hw_ctrl = 0x81028,
3215 .name = "aggre0_noc",
3217 .pwrsts = PWRSTS_OFF_ON,
3218 .flags = VOTABLE | ALWAYS_ON,
3221 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3224 .name = "hlos1_vote_aggre0_noc",
3226 .pwrsts = PWRSTS_OFF_ON,
3230 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3233 .name = "hlos1_vote_lpass_adsp",
3235 .pwrsts = PWRSTS_OFF_ON,
3239 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3242 .name = "hlos1_vote_lpass_core",
3244 .pwrsts = PWRSTS_OFF_ON,
3248 static struct gdsc usb30_gdsc = {
3253 .pwrsts = PWRSTS_OFF_ON,
3256 static struct gdsc pcie0_gdsc = {
3261 .pwrsts = PWRSTS_OFF_ON,
3264 static struct gdsc pcie1_gdsc = {
3269 .pwrsts = PWRSTS_OFF_ON,
3272 static struct gdsc pcie2_gdsc = {
3277 .pwrsts = PWRSTS_OFF_ON,
3280 static struct gdsc ufs_gdsc = {
3285 .pwrsts = PWRSTS_OFF_ON,
3288 static struct clk_regmap *gcc_msm8996_clocks[] = {
3289 [GPLL0_EARLY] = &gpll0_early.clkr,
3290 [GPLL0] = &gpll0.clkr,
3291 [GPLL4_EARLY] = &gpll4_early.clkr,
3292 [GPLL4] = &gpll4.clkr,
3293 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3294 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3295 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3296 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3297 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3298 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3299 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3300 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3301 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3302 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3303 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3304 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3305 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3306 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3307 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3308 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3309 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3310 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3311 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3312 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3313 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3314 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3315 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3316 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3317 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3318 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3319 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3320 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3321 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3322 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3323 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3324 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3325 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3326 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3327 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3328 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3329 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3330 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3331 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3332 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3333 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3334 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3335 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3336 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3337 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3338 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3339 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3340 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3341 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3342 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3343 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3344 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3345 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3346 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3347 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3348 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3349 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3350 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3351 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3352 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3353 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3354 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3355 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3356 [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3357 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3358 [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3359 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3360 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3361 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3362 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3363 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3364 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3365 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3366 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3367 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3368 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3369 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3370 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3371 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3372 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3373 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3374 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3375 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3376 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3377 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3378 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3379 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3380 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3381 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3382 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3383 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3384 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3385 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3386 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3387 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3388 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3389 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3390 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3391 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3392 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3393 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3394 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3395 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3396 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3397 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3398 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3399 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3400 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3401 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3402 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3403 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3404 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3405 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3406 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3407 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3408 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3409 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3410 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3411 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3412 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3413 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3414 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3415 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3416 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3417 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3418 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3419 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3420 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3421 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3422 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3423 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3424 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3425 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3426 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3427 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3428 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3429 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3430 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3431 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3432 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3433 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3434 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3435 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3436 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3437 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3438 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3439 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3440 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3441 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3442 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3443 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3444 [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3445 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3446 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3447 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3448 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3449 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3450 [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3451 [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3452 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3453 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3454 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3455 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3456 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3457 [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3458 [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3459 [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3460 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3461 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3462 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3463 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3464 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3465 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3466 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3467 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3468 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3469 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3470 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3471 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3472 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3473 [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3474 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3475 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3476 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3477 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3478 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3479 [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3480 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3481 [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
3484 static struct gdsc *gcc_msm8996_gdscs[] = {
3485 [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3486 [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3487 [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3488 [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3489 [USB30_GDSC] = &usb30_gdsc,
3490 [PCIE0_GDSC] = &pcie0_gdsc,
3491 [PCIE1_GDSC] = &pcie1_gdsc,
3492 [PCIE2_GDSC] = &pcie2_gdsc,
3493 [UFS_GDSC] = &ufs_gdsc,
3496 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3497 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3498 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3499 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3500 [GCC_IMEM_BCR] = { 0x8000 },
3501 [GCC_MMSS_BCR] = { 0x9000 },
3502 [GCC_PIMEM_BCR] = { 0x0a000 },
3503 [GCC_QDSS_BCR] = { 0x0c000 },
3504 [GCC_USB_30_BCR] = { 0x0f000 },
3505 [GCC_USB_20_BCR] = { 0x12000 },
3506 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3507 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3508 [GCC_USB3_PHY_BCR] = { 0x50020 },
3509 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3510 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3511 [GCC_SDCC1_BCR] = { 0x13000 },
3512 [GCC_SDCC2_BCR] = { 0x14000 },
3513 [GCC_SDCC3_BCR] = { 0x15000 },
3514 [GCC_SDCC4_BCR] = { 0x16000 },
3515 [GCC_BLSP1_BCR] = { 0x17000 },
3516 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3517 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3518 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3519 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3520 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3521 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3522 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3523 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3524 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3525 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3526 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3527 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3528 [GCC_BLSP2_BCR] = { 0x25000 },
3529 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3530 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3531 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3532 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3533 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3534 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3535 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3536 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3537 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3538 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3539 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3540 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3541 [GCC_PDM_BCR] = { 0x33000 },
3542 [GCC_PRNG_BCR] = { 0x34000 },
3543 [GCC_TSIF_BCR] = { 0x36000 },
3544 [GCC_TCSR_BCR] = { 0x37000 },
3545 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3546 [GCC_MSG_RAM_BCR] = { 0x39000 },
3547 [GCC_TLMM_BCR] = { 0x3a000 },
3548 [GCC_MPM_BCR] = { 0x3b000 },
3549 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3550 [GCC_SPMI_BCR] = { 0x3f000 },
3551 [GCC_SPDM_BCR] = { 0x40000 },
3552 [GCC_CE1_BCR] = { 0x41000 },
3553 [GCC_BIMC_BCR] = { 0x44000 },
3554 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3555 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3556 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3557 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3558 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3559 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3560 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3561 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3562 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3563 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3564 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3565 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3566 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3567 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3568 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3569 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3570 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3571 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3572 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3573 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3574 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3575 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3576 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3577 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3578 [GCC_PCIE_0_BCR] = { 0x6b000 },
3579 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3580 [GCC_PCIE_1_BCR] = { 0x6d000 },
3581 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3582 [GCC_PCIE_2_BCR] = { 0x6e000 },
3583 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3584 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3585 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3586 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3587 [GCC_DCD_BCR] = { 0x70000 },
3588 [GCC_OBT_ODT_BCR] = { 0x73000 },
3589 [GCC_UFS_BCR] = { 0x75000 },
3590 [GCC_SSC_BCR] = { 0x63000 },
3591 [GCC_VS_BCR] = { 0x7a000 },
3592 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3593 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3594 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3595 [GCC_DCC_BCR] = { 0x84000 },
3596 [GCC_IPA_BCR] = { 0x89000 },
3597 [GCC_QSPI_BCR] = { 0x8b000 },
3598 [GCC_SKL_BCR] = { 0x8c000 },
3599 [GCC_MSMPU_BCR] = { 0x8d000 },
3600 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3601 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3602 [GCC_MSS_RESTART] = { 0x8f008 },
3605 static const struct regmap_config gcc_msm8996_regmap_config = {
3609 .max_register = 0x8f010,
3613 static const struct qcom_cc_desc gcc_msm8996_desc = {
3614 .config = &gcc_msm8996_regmap_config,
3615 .clks = gcc_msm8996_clocks,
3616 .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3617 .resets = gcc_msm8996_resets,
3618 .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3619 .gdscs = gcc_msm8996_gdscs,
3620 .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3621 .clk_hws = gcc_msm8996_hws,
3622 .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
3625 static const struct of_device_id gcc_msm8996_match_table[] = {
3626 { .compatible = "qcom,gcc-msm8996" },
3629 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3631 static int gcc_msm8996_probe(struct platform_device *pdev)
3633 struct regmap *regmap;
3635 regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3637 return PTR_ERR(regmap);
3640 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3641 * turned off by hardware during certain apps low power modes.
3643 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3645 return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3648 static struct platform_driver gcc_msm8996_driver = {
3649 .probe = gcc_msm8996_probe,
3651 .name = "gcc-msm8996",
3652 .of_match_table = gcc_msm8996_match_table,
3656 static int __init gcc_msm8996_init(void)
3658 return platform_driver_register(&gcc_msm8996_driver);
3660 core_initcall(gcc_msm8996_init);
3662 static void __exit gcc_msm8996_exit(void)
3664 platform_driver_unregister(&gcc_msm8996_driver);
3666 module_exit(gcc_msm8996_exit);
3668 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3669 MODULE_LICENSE("GPL v2");
3670 MODULE_ALIAS("platform:gcc-msm8996");