1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <linux/kernel.h>
6 #include <linux/init.h>
8 #include <linux/ctype.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
18 #include "clk-regmap.h"
19 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
31 static const struct parent_map gcc_xo_gpll0_map[] = {
36 static const char * const gcc_xo_gpll0[] = {
41 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
47 static const char * const gcc_xo_gpll0_gpll4[] = {
53 static struct clk_fixed_factor xo = {
56 .hw.init = &(struct clk_init_data)
59 .parent_names = (const char *[]) { "xo_board" },
61 .ops = &clk_fixed_factor_ops,
65 static struct clk_alpha_pll gpll0_early = {
67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
70 .enable_mask = BIT(0),
71 .hw.init = &(struct clk_init_data)
73 .name = "gpll0_early",
74 .parent_names = (const char *[]) { "xo" },
76 .ops = &clk_alpha_pll_ops,
81 static struct clk_alpha_pll_postdiv gpll0 = {
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
84 .clkr.hw.init = &(struct clk_init_data)
87 .parent_names = (const char *[]) { "gpll0_early" },
89 .ops = &clk_alpha_pll_postdiv_ops,
93 static struct clk_alpha_pll gpll4_early = {
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
98 .enable_mask = BIT(4),
99 .hw.init = &(struct clk_init_data)
101 .name = "gpll4_early",
102 .parent_names = (const char *[]) { "xo" },
104 .ops = &clk_alpha_pll_ops,
109 static struct clk_alpha_pll_postdiv gpll4 = {
112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
113 .clkr.hw.init = &(struct clk_init_data)
116 .parent_names = (const char *[]) { "gpll4_early" },
118 .ops = &clk_alpha_pll_postdiv_ops,
122 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
123 F(50000000, P_GPLL0, 12, 0, 0),
124 F(100000000, P_GPLL0, 6, 0, 0),
125 F(150000000, P_GPLL0, 4, 0, 0),
126 F(171430000, P_GPLL0, 3.5, 0, 0),
127 F(200000000, P_GPLL0, 3, 0, 0),
128 F(240000000, P_GPLL0, 2.5, 0, 0),
132 static struct clk_rcg2 ufs_axi_clk_src = {
136 .parent_map = gcc_xo_gpll0_map,
137 .freq_tbl = ftbl_ufs_axi_clk_src,
138 .clkr.hw.init = &(struct clk_init_data)
140 .name = "ufs_axi_clk_src",
141 .parent_names = gcc_xo_gpll0,
143 .ops = &clk_rcg2_ops,
147 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
148 F(19200000, P_XO, 1, 0, 0),
149 F(125000000, P_GPLL0, 1, 5, 24),
153 static struct clk_rcg2 usb30_master_clk_src = {
157 .parent_map = gcc_xo_gpll0_map,
158 .freq_tbl = ftbl_usb30_master_clk_src,
159 .clkr.hw.init = &(struct clk_init_data)
161 .name = "usb30_master_clk_src",
162 .parent_names = gcc_xo_gpll0,
164 .ops = &clk_rcg2_ops,
168 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
169 F(19200000, P_XO, 1, 0, 0),
170 F(50000000, P_GPLL0, 12, 0, 0),
174 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
177 .parent_map = gcc_xo_gpll0_map,
178 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
179 .clkr.hw.init = &(struct clk_init_data)
181 .name = "blsp1_qup1_i2c_apps_clk_src",
182 .parent_names = gcc_xo_gpll0,
184 .ops = &clk_rcg2_ops,
188 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
189 F(960000, P_XO, 10, 1, 2),
190 F(4800000, P_XO, 4, 0, 0),
191 F(9600000, P_XO, 2, 0, 0),
192 F(15000000, P_GPLL0, 10, 1, 4),
193 F(19200000, P_XO, 1, 0, 0),
194 F(24000000, P_GPLL0, 12.5, 1, 2),
195 F(25000000, P_GPLL0, 12, 1, 2),
196 F(48000000, P_GPLL0, 12.5, 0, 0),
197 F(50000000, P_GPLL0, 12, 0, 0),
201 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
205 .parent_map = gcc_xo_gpll0_map,
206 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
207 .clkr.hw.init = &(struct clk_init_data)
209 .name = "blsp1_qup1_spi_apps_clk_src",
210 .parent_names = gcc_xo_gpll0,
212 .ops = &clk_rcg2_ops,
216 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
219 .parent_map = gcc_xo_gpll0_map,
220 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
221 .clkr.hw.init = &(struct clk_init_data)
223 .name = "blsp1_qup2_i2c_apps_clk_src",
224 .parent_names = gcc_xo_gpll0,
226 .ops = &clk_rcg2_ops,
230 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
234 .parent_map = gcc_xo_gpll0_map,
235 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
236 .clkr.hw.init = &(struct clk_init_data)
238 .name = "blsp1_qup2_spi_apps_clk_src",
239 .parent_names = gcc_xo_gpll0,
241 .ops = &clk_rcg2_ops,
245 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
248 .parent_map = gcc_xo_gpll0_map,
249 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
250 .clkr.hw.init = &(struct clk_init_data)
252 .name = "blsp1_qup3_i2c_apps_clk_src",
253 .parent_names = gcc_xo_gpll0,
255 .ops = &clk_rcg2_ops,
259 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
263 .parent_map = gcc_xo_gpll0_map,
264 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
265 .clkr.hw.init = &(struct clk_init_data)
267 .name = "blsp1_qup3_spi_apps_clk_src",
268 .parent_names = gcc_xo_gpll0,
270 .ops = &clk_rcg2_ops,
274 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
277 .parent_map = gcc_xo_gpll0_map,
278 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
279 .clkr.hw.init = &(struct clk_init_data)
281 .name = "blsp1_qup4_i2c_apps_clk_src",
282 .parent_names = gcc_xo_gpll0,
284 .ops = &clk_rcg2_ops,
288 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
292 .parent_map = gcc_xo_gpll0_map,
293 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
294 .clkr.hw.init = &(struct clk_init_data)
296 .name = "blsp1_qup4_spi_apps_clk_src",
297 .parent_names = gcc_xo_gpll0,
299 .ops = &clk_rcg2_ops,
303 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
306 .parent_map = gcc_xo_gpll0_map,
307 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
308 .clkr.hw.init = &(struct clk_init_data)
310 .name = "blsp1_qup5_i2c_apps_clk_src",
311 .parent_names = gcc_xo_gpll0,
313 .ops = &clk_rcg2_ops,
317 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
321 .parent_map = gcc_xo_gpll0_map,
322 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
323 .clkr.hw.init = &(struct clk_init_data)
325 .name = "blsp1_qup5_spi_apps_clk_src",
326 .parent_names = gcc_xo_gpll0,
328 .ops = &clk_rcg2_ops,
332 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
335 .parent_map = gcc_xo_gpll0_map,
336 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
337 .clkr.hw.init = &(struct clk_init_data)
339 .name = "blsp1_qup6_i2c_apps_clk_src",
340 .parent_names = gcc_xo_gpll0,
342 .ops = &clk_rcg2_ops,
346 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
350 .parent_map = gcc_xo_gpll0_map,
351 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
352 .clkr.hw.init = &(struct clk_init_data)
354 .name = "blsp1_qup6_spi_apps_clk_src",
355 .parent_names = gcc_xo_gpll0,
357 .ops = &clk_rcg2_ops,
361 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
362 F(3686400, P_GPLL0, 1, 96, 15625),
363 F(7372800, P_GPLL0, 1, 192, 15625),
364 F(14745600, P_GPLL0, 1, 384, 15625),
365 F(16000000, P_GPLL0, 5, 2, 15),
366 F(19200000, P_XO, 1, 0, 0),
367 F(24000000, P_GPLL0, 5, 1, 5),
368 F(32000000, P_GPLL0, 1, 4, 75),
369 F(40000000, P_GPLL0, 15, 0, 0),
370 F(46400000, P_GPLL0, 1, 29, 375),
371 F(48000000, P_GPLL0, 12.5, 0, 0),
372 F(51200000, P_GPLL0, 1, 32, 375),
373 F(56000000, P_GPLL0, 1, 7, 75),
374 F(58982400, P_GPLL0, 1, 1536, 15625),
375 F(60000000, P_GPLL0, 10, 0, 0),
376 F(63160000, P_GPLL0, 9.5, 0, 0),
380 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
384 .parent_map = gcc_xo_gpll0_map,
385 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
386 .clkr.hw.init = &(struct clk_init_data)
388 .name = "blsp1_uart1_apps_clk_src",
389 .parent_names = gcc_xo_gpll0,
391 .ops = &clk_rcg2_ops,
395 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
399 .parent_map = gcc_xo_gpll0_map,
400 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
401 .clkr.hw.init = &(struct clk_init_data)
403 .name = "blsp1_uart2_apps_clk_src",
404 .parent_names = gcc_xo_gpll0,
406 .ops = &clk_rcg2_ops,
410 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
414 .parent_map = gcc_xo_gpll0_map,
415 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
416 .clkr.hw.init = &(struct clk_init_data)
418 .name = "blsp1_uart3_apps_clk_src",
419 .parent_names = gcc_xo_gpll0,
421 .ops = &clk_rcg2_ops,
425 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
429 .parent_map = gcc_xo_gpll0_map,
430 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
431 .clkr.hw.init = &(struct clk_init_data)
433 .name = "blsp1_uart4_apps_clk_src",
434 .parent_names = gcc_xo_gpll0,
436 .ops = &clk_rcg2_ops,
440 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
444 .parent_map = gcc_xo_gpll0_map,
445 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
446 .clkr.hw.init = &(struct clk_init_data)
448 .name = "blsp1_uart5_apps_clk_src",
449 .parent_names = gcc_xo_gpll0,
451 .ops = &clk_rcg2_ops,
455 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
459 .parent_map = gcc_xo_gpll0_map,
460 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
461 .clkr.hw.init = &(struct clk_init_data)
463 .name = "blsp1_uart6_apps_clk_src",
464 .parent_names = gcc_xo_gpll0,
466 .ops = &clk_rcg2_ops,
470 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
473 .parent_map = gcc_xo_gpll0_map,
474 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
475 .clkr.hw.init = &(struct clk_init_data)
477 .name = "blsp2_qup1_i2c_apps_clk_src",
478 .parent_names = gcc_xo_gpll0,
480 .ops = &clk_rcg2_ops,
484 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
488 .parent_map = gcc_xo_gpll0_map,
489 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
490 .clkr.hw.init = &(struct clk_init_data)
492 .name = "blsp2_qup1_spi_apps_clk_src",
493 .parent_names = gcc_xo_gpll0,
495 .ops = &clk_rcg2_ops,
499 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
502 .parent_map = gcc_xo_gpll0_map,
503 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
504 .clkr.hw.init = &(struct clk_init_data)
506 .name = "blsp2_qup2_i2c_apps_clk_src",
507 .parent_names = gcc_xo_gpll0,
509 .ops = &clk_rcg2_ops,
513 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
517 .parent_map = gcc_xo_gpll0_map,
518 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
519 .clkr.hw.init = &(struct clk_init_data)
521 .name = "blsp2_qup2_spi_apps_clk_src",
522 .parent_names = gcc_xo_gpll0,
524 .ops = &clk_rcg2_ops,
528 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
531 .parent_map = gcc_xo_gpll0_map,
532 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
533 .clkr.hw.init = &(struct clk_init_data)
535 .name = "blsp2_qup3_i2c_apps_clk_src",
536 .parent_names = gcc_xo_gpll0,
538 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
546 .parent_map = gcc_xo_gpll0_map,
547 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
548 .clkr.hw.init = &(struct clk_init_data)
550 .name = "blsp2_qup3_spi_apps_clk_src",
551 .parent_names = gcc_xo_gpll0,
553 .ops = &clk_rcg2_ops,
557 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
560 .parent_map = gcc_xo_gpll0_map,
561 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
562 .clkr.hw.init = &(struct clk_init_data)
564 .name = "blsp2_qup4_i2c_apps_clk_src",
565 .parent_names = gcc_xo_gpll0,
567 .ops = &clk_rcg2_ops,
571 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
575 .parent_map = gcc_xo_gpll0_map,
576 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
577 .clkr.hw.init = &(struct clk_init_data)
579 .name = "blsp2_qup4_spi_apps_clk_src",
580 .parent_names = gcc_xo_gpll0,
582 .ops = &clk_rcg2_ops,
586 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
589 .parent_map = gcc_xo_gpll0_map,
590 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
591 .clkr.hw.init = &(struct clk_init_data)
593 .name = "blsp2_qup5_i2c_apps_clk_src",
594 .parent_names = gcc_xo_gpll0,
596 .ops = &clk_rcg2_ops,
600 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
604 .parent_map = gcc_xo_gpll0_map,
605 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
606 .clkr.hw.init = &(struct clk_init_data)
608 .name = "blsp2_qup5_spi_apps_clk_src",
609 .parent_names = gcc_xo_gpll0,
611 .ops = &clk_rcg2_ops,
615 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
618 .parent_map = gcc_xo_gpll0_map,
619 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
620 .clkr.hw.init = &(struct clk_init_data)
622 .name = "blsp2_qup6_i2c_apps_clk_src",
623 .parent_names = gcc_xo_gpll0,
625 .ops = &clk_rcg2_ops,
629 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
633 .parent_map = gcc_xo_gpll0_map,
634 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
635 .clkr.hw.init = &(struct clk_init_data)
637 .name = "blsp2_qup6_spi_apps_clk_src",
638 .parent_names = gcc_xo_gpll0,
640 .ops = &clk_rcg2_ops,
644 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
648 .parent_map = gcc_xo_gpll0_map,
649 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
650 .clkr.hw.init = &(struct clk_init_data)
652 .name = "blsp2_uart1_apps_clk_src",
653 .parent_names = gcc_xo_gpll0,
655 .ops = &clk_rcg2_ops,
659 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
663 .parent_map = gcc_xo_gpll0_map,
664 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data)
667 .name = "blsp2_uart2_apps_clk_src",
668 .parent_names = gcc_xo_gpll0,
670 .ops = &clk_rcg2_ops,
674 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
678 .parent_map = gcc_xo_gpll0_map,
679 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
680 .clkr.hw.init = &(struct clk_init_data)
682 .name = "blsp2_uart3_apps_clk_src",
683 .parent_names = gcc_xo_gpll0,
685 .ops = &clk_rcg2_ops,
689 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
693 .parent_map = gcc_xo_gpll0_map,
694 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
695 .clkr.hw.init = &(struct clk_init_data)
697 .name = "blsp2_uart4_apps_clk_src",
698 .parent_names = gcc_xo_gpll0,
700 .ops = &clk_rcg2_ops,
704 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
708 .parent_map = gcc_xo_gpll0_map,
709 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
710 .clkr.hw.init = &(struct clk_init_data)
712 .name = "blsp2_uart5_apps_clk_src",
713 .parent_names = gcc_xo_gpll0,
715 .ops = &clk_rcg2_ops,
719 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
723 .parent_map = gcc_xo_gpll0_map,
724 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
725 .clkr.hw.init = &(struct clk_init_data)
727 .name = "blsp2_uart6_apps_clk_src",
728 .parent_names = gcc_xo_gpll0,
730 .ops = &clk_rcg2_ops,
734 static struct freq_tbl ftbl_gp1_clk_src[] = {
735 F(19200000, P_XO, 1, 0, 0),
736 F(100000000, P_GPLL0, 6, 0, 0),
737 F(200000000, P_GPLL0, 3, 0, 0),
741 static struct clk_rcg2 gp1_clk_src = {
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_gp1_clk_src,
747 .clkr.hw.init = &(struct clk_init_data)
749 .name = "gp1_clk_src",
750 .parent_names = gcc_xo_gpll0,
752 .ops = &clk_rcg2_ops,
756 static struct freq_tbl ftbl_gp2_clk_src[] = {
757 F(19200000, P_XO, 1, 0, 0),
758 F(100000000, P_GPLL0, 6, 0, 0),
759 F(200000000, P_GPLL0, 3, 0, 0),
763 static struct clk_rcg2 gp2_clk_src = {
767 .parent_map = gcc_xo_gpll0_map,
768 .freq_tbl = ftbl_gp2_clk_src,
769 .clkr.hw.init = &(struct clk_init_data)
771 .name = "gp2_clk_src",
772 .parent_names = gcc_xo_gpll0,
774 .ops = &clk_rcg2_ops,
778 static struct freq_tbl ftbl_gp3_clk_src[] = {
779 F(19200000, P_XO, 1, 0, 0),
780 F(100000000, P_GPLL0, 6, 0, 0),
781 F(200000000, P_GPLL0, 3, 0, 0),
785 static struct clk_rcg2 gp3_clk_src = {
789 .parent_map = gcc_xo_gpll0_map,
790 .freq_tbl = ftbl_gp3_clk_src,
791 .clkr.hw.init = &(struct clk_init_data)
793 .name = "gp3_clk_src",
794 .parent_names = gcc_xo_gpll0,
796 .ops = &clk_rcg2_ops,
800 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
801 F(1011000, P_XO, 1, 1, 19),
805 static struct clk_rcg2 pcie_0_aux_clk_src = {
809 .freq_tbl = ftbl_pcie_0_aux_clk_src,
810 .clkr.hw.init = &(struct clk_init_data)
812 .name = "pcie_0_aux_clk_src",
813 .parent_names = (const char *[]) { "xo" },
815 .ops = &clk_rcg2_ops,
819 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
820 F(125000000, P_XO, 1, 0, 0),
824 static struct clk_rcg2 pcie_0_pipe_clk_src = {
827 .freq_tbl = ftbl_pcie_pipe_clk_src,
828 .clkr.hw.init = &(struct clk_init_data)
830 .name = "pcie_0_pipe_clk_src",
831 .parent_names = (const char *[]) { "xo" },
833 .ops = &clk_rcg2_ops,
837 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
838 F(1011000, P_XO, 1, 1, 19),
842 static struct clk_rcg2 pcie_1_aux_clk_src = {
846 .freq_tbl = ftbl_pcie_1_aux_clk_src,
847 .clkr.hw.init = &(struct clk_init_data)
849 .name = "pcie_1_aux_clk_src",
850 .parent_names = (const char *[]) { "xo" },
852 .ops = &clk_rcg2_ops,
856 static struct clk_rcg2 pcie_1_pipe_clk_src = {
859 .freq_tbl = ftbl_pcie_pipe_clk_src,
860 .clkr.hw.init = &(struct clk_init_data)
862 .name = "pcie_1_pipe_clk_src",
863 .parent_names = (const char *[]) { "xo" },
865 .ops = &clk_rcg2_ops,
869 static struct freq_tbl ftbl_pdm2_clk_src[] = {
870 F(60000000, P_GPLL0, 10, 0, 0),
874 static struct clk_rcg2 pdm2_clk_src = {
877 .parent_map = gcc_xo_gpll0_map,
878 .freq_tbl = ftbl_pdm2_clk_src,
879 .clkr.hw.init = &(struct clk_init_data)
881 .name = "pdm2_clk_src",
882 .parent_names = gcc_xo_gpll0,
884 .ops = &clk_rcg2_ops,
888 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
889 F(144000, P_XO, 16, 3, 25),
890 F(400000, P_XO, 12, 1, 4),
891 F(20000000, P_GPLL0, 15, 1, 2),
892 F(25000000, P_GPLL0, 12, 1, 2),
893 F(50000000, P_GPLL0, 12, 0, 0),
894 F(100000000, P_GPLL0, 6, 0, 0),
895 F(192000000, P_GPLL4, 2, 0, 0),
896 F(384000000, P_GPLL4, 1, 0, 0),
900 static struct clk_rcg2 sdcc1_apps_clk_src = {
904 .parent_map = gcc_xo_gpll0_gpll4_map,
905 .freq_tbl = ftbl_sdcc1_apps_clk_src,
906 .clkr.hw.init = &(struct clk_init_data)
908 .name = "sdcc1_apps_clk_src",
909 .parent_names = gcc_xo_gpll0_gpll4,
911 .ops = &clk_rcg2_floor_ops,
915 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
916 F(144000, P_XO, 16, 3, 25),
917 F(400000, P_XO, 12, 1, 4),
918 F(20000000, P_GPLL0, 15, 1, 2),
919 F(25000000, P_GPLL0, 12, 1, 2),
920 F(50000000, P_GPLL0, 12, 0, 0),
921 F(100000000, P_GPLL0, 6, 0, 0),
922 F(200000000, P_GPLL0, 3, 0, 0),
926 static struct clk_rcg2 sdcc2_apps_clk_src = {
930 .parent_map = gcc_xo_gpll0_map,
931 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
932 .clkr.hw.init = &(struct clk_init_data)
934 .name = "sdcc2_apps_clk_src",
935 .parent_names = gcc_xo_gpll0,
937 .ops = &clk_rcg2_floor_ops,
941 static struct clk_rcg2 sdcc3_apps_clk_src = {
945 .parent_map = gcc_xo_gpll0_map,
946 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
947 .clkr.hw.init = &(struct clk_init_data)
949 .name = "sdcc3_apps_clk_src",
950 .parent_names = gcc_xo_gpll0,
952 .ops = &clk_rcg2_floor_ops,
956 static struct clk_rcg2 sdcc4_apps_clk_src = {
960 .parent_map = gcc_xo_gpll0_map,
961 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
962 .clkr.hw.init = &(struct clk_init_data)
964 .name = "sdcc4_apps_clk_src",
965 .parent_names = gcc_xo_gpll0,
967 .ops = &clk_rcg2_floor_ops,
971 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
972 F(105500, P_XO, 1, 1, 182),
976 static struct clk_rcg2 tsif_ref_clk_src = {
980 .freq_tbl = ftbl_tsif_ref_clk_src,
981 .clkr.hw.init = &(struct clk_init_data)
983 .name = "tsif_ref_clk_src",
984 .parent_names = (const char *[]) { "xo" },
986 .ops = &clk_rcg2_ops,
990 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
991 F(19200000, P_XO, 1, 0, 0),
992 F(60000000, P_GPLL0, 10, 0, 0),
996 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
999 .parent_map = gcc_xo_gpll0_map,
1000 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1001 .clkr.hw.init = &(struct clk_init_data)
1003 .name = "usb30_mock_utmi_clk_src",
1004 .parent_names = gcc_xo_gpll0,
1006 .ops = &clk_rcg2_ops,
1010 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1011 F(1200000, P_XO, 16, 0, 0),
1015 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1018 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1019 .clkr.hw.init = &(struct clk_init_data)
1021 .name = "usb3_phy_aux_clk_src",
1022 .parent_names = (const char *[]) { "xo" },
1024 .ops = &clk_rcg2_ops,
1028 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1029 F(75000000, P_GPLL0, 8, 0, 0),
1033 static struct clk_rcg2 usb_hs_system_clk_src = {
1036 .parent_map = gcc_xo_gpll0_map,
1037 .freq_tbl = ftbl_usb_hs_system_clk_src,
1038 .clkr.hw.init = &(struct clk_init_data)
1040 .name = "usb_hs_system_clk_src",
1041 .parent_names = gcc_xo_gpll0,
1043 .ops = &clk_rcg2_ops,
1047 static struct clk_branch gcc_blsp1_ahb_clk = {
1049 .halt_check = BRANCH_HALT_VOTED,
1051 .enable_reg = 0x1484,
1052 .enable_mask = BIT(17),
1053 .hw.init = &(struct clk_init_data)
1055 .name = "gcc_blsp1_ahb_clk",
1056 .ops = &clk_branch2_ops,
1061 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1064 .enable_reg = 0x0648,
1065 .enable_mask = BIT(0),
1066 .hw.init = &(struct clk_init_data)
1068 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1069 .parent_names = (const char *[]) {
1070 "blsp1_qup1_i2c_apps_clk_src",
1073 .flags = CLK_SET_RATE_PARENT,
1074 .ops = &clk_branch2_ops,
1079 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1082 .enable_reg = 0x0644,
1083 .enable_mask = BIT(0),
1084 .hw.init = &(struct clk_init_data)
1086 .name = "gcc_blsp1_qup1_spi_apps_clk",
1087 .parent_names = (const char *[]) {
1088 "blsp1_qup1_spi_apps_clk_src",
1091 .flags = CLK_SET_RATE_PARENT,
1092 .ops = &clk_branch2_ops,
1097 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1100 .enable_reg = 0x06c8,
1101 .enable_mask = BIT(0),
1102 .hw.init = &(struct clk_init_data)
1104 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1105 .parent_names = (const char *[]) {
1106 "blsp1_qup2_i2c_apps_clk_src",
1109 .flags = CLK_SET_RATE_PARENT,
1110 .ops = &clk_branch2_ops,
1115 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1118 .enable_reg = 0x06c4,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data)
1122 .name = "gcc_blsp1_qup2_spi_apps_clk",
1123 .parent_names = (const char *[]) {
1124 "blsp1_qup2_spi_apps_clk_src",
1127 .flags = CLK_SET_RATE_PARENT,
1128 .ops = &clk_branch2_ops,
1133 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1136 .enable_reg = 0x0748,
1137 .enable_mask = BIT(0),
1138 .hw.init = &(struct clk_init_data)
1140 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1141 .parent_names = (const char *[]) {
1142 "blsp1_qup3_i2c_apps_clk_src",
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1151 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1154 .enable_reg = 0x0744,
1155 .enable_mask = BIT(0),
1156 .hw.init = &(struct clk_init_data)
1158 .name = "gcc_blsp1_qup3_spi_apps_clk",
1159 .parent_names = (const char *[]) {
1160 "blsp1_qup3_spi_apps_clk_src",
1163 .flags = CLK_SET_RATE_PARENT,
1164 .ops = &clk_branch2_ops,
1169 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1172 .enable_reg = 0x07c8,
1173 .enable_mask = BIT(0),
1174 .hw.init = &(struct clk_init_data)
1176 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1177 .parent_names = (const char *[]) {
1178 "blsp1_qup4_i2c_apps_clk_src",
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1187 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1190 .enable_reg = 0x07c4,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data)
1194 .name = "gcc_blsp1_qup4_spi_apps_clk",
1195 .parent_names = (const char *[]) {
1196 "blsp1_qup4_spi_apps_clk_src",
1199 .flags = CLK_SET_RATE_PARENT,
1200 .ops = &clk_branch2_ops,
1205 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1208 .enable_reg = 0x0848,
1209 .enable_mask = BIT(0),
1210 .hw.init = &(struct clk_init_data)
1212 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1213 .parent_names = (const char *[]) {
1214 "blsp1_qup5_i2c_apps_clk_src",
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1223 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1226 .enable_reg = 0x0844,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data)
1230 .name = "gcc_blsp1_qup5_spi_apps_clk",
1231 .parent_names = (const char *[]) {
1232 "blsp1_qup5_spi_apps_clk_src",
1235 .flags = CLK_SET_RATE_PARENT,
1236 .ops = &clk_branch2_ops,
1241 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1244 .enable_reg = 0x08c8,
1245 .enable_mask = BIT(0),
1246 .hw.init = &(struct clk_init_data)
1248 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1249 .parent_names = (const char *[]) {
1250 "blsp1_qup6_i2c_apps_clk_src",
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1259 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1262 .enable_reg = 0x08c4,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data)
1266 .name = "gcc_blsp1_qup6_spi_apps_clk",
1267 .parent_names = (const char *[]) {
1268 "blsp1_qup6_spi_apps_clk_src",
1271 .flags = CLK_SET_RATE_PARENT,
1272 .ops = &clk_branch2_ops,
1277 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1280 .enable_reg = 0x0684,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data)
1284 .name = "gcc_blsp1_uart1_apps_clk",
1285 .parent_names = (const char *[]) {
1286 "blsp1_uart1_apps_clk_src",
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1295 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1298 .enable_reg = 0x0704,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data)
1302 .name = "gcc_blsp1_uart2_apps_clk",
1303 .parent_names = (const char *[]) {
1304 "blsp1_uart2_apps_clk_src",
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1313 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1316 .enable_reg = 0x0784,
1317 .enable_mask = BIT(0),
1318 .hw.init = &(struct clk_init_data)
1320 .name = "gcc_blsp1_uart3_apps_clk",
1321 .parent_names = (const char *[]) {
1322 "blsp1_uart3_apps_clk_src",
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1331 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1334 .enable_reg = 0x0804,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data)
1338 .name = "gcc_blsp1_uart4_apps_clk",
1339 .parent_names = (const char *[]) {
1340 "blsp1_uart4_apps_clk_src",
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1349 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1352 .enable_reg = 0x0884,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data)
1356 .name = "gcc_blsp1_uart5_apps_clk",
1357 .parent_names = (const char *[]) {
1358 "blsp1_uart5_apps_clk_src",
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1367 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1370 .enable_reg = 0x0904,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data)
1374 .name = "gcc_blsp1_uart6_apps_clk",
1375 .parent_names = (const char *[]) {
1376 "blsp1_uart6_apps_clk_src",
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch gcc_blsp2_ahb_clk = {
1387 .halt_check = BRANCH_HALT_VOTED,
1389 .enable_reg = 0x1484,
1390 .enable_mask = BIT(15),
1391 .hw.init = &(struct clk_init_data)
1393 .name = "gcc_blsp2_ahb_clk",
1394 .ops = &clk_branch2_ops,
1399 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1402 .enable_reg = 0x0988,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data)
1406 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1407 .parent_names = (const char *[]) {
1408 "blsp2_qup1_i2c_apps_clk_src",
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1420 .enable_reg = 0x0984,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data)
1424 .name = "gcc_blsp2_qup1_spi_apps_clk",
1425 .parent_names = (const char *[]) {
1426 "blsp2_qup1_spi_apps_clk_src",
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1435 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1438 .enable_reg = 0x0a08,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data)
1442 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1443 .parent_names = (const char *[]) {
1444 "blsp2_qup2_i2c_apps_clk_src",
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1453 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1456 .enable_reg = 0x0a04,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data)
1460 .name = "gcc_blsp2_qup2_spi_apps_clk",
1461 .parent_names = (const char *[]) {
1462 "blsp2_qup2_spi_apps_clk_src",
1465 .flags = CLK_SET_RATE_PARENT,
1466 .ops = &clk_branch2_ops,
1471 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1474 .enable_reg = 0x0a88,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data)
1478 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1479 .parent_names = (const char *[]) {
1480 "blsp2_qup3_i2c_apps_clk_src",
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1492 .enable_reg = 0x0a84,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data)
1496 .name = "gcc_blsp2_qup3_spi_apps_clk",
1497 .parent_names = (const char *[]) {
1498 "blsp2_qup3_spi_apps_clk_src",
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1510 .enable_reg = 0x0b08,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data)
1514 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1515 .parent_names = (const char *[]) {
1516 "blsp2_qup4_i2c_apps_clk_src",
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1525 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1528 .enable_reg = 0x0b04,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data)
1532 .name = "gcc_blsp2_qup4_spi_apps_clk",
1533 .parent_names = (const char *[]) {
1534 "blsp2_qup4_spi_apps_clk_src",
1537 .flags = CLK_SET_RATE_PARENT,
1538 .ops = &clk_branch2_ops,
1543 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1546 .enable_reg = 0x0b88,
1547 .enable_mask = BIT(0),
1548 .hw.init = &(struct clk_init_data)
1550 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1551 .parent_names = (const char *[]) {
1552 "blsp2_qup5_i2c_apps_clk_src",
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1561 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1564 .enable_reg = 0x0b84,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data)
1568 .name = "gcc_blsp2_qup5_spi_apps_clk",
1569 .parent_names = (const char *[]) {
1570 "blsp2_qup5_spi_apps_clk_src",
1573 .flags = CLK_SET_RATE_PARENT,
1574 .ops = &clk_branch2_ops,
1579 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1582 .enable_reg = 0x0c08,
1583 .enable_mask = BIT(0),
1584 .hw.init = &(struct clk_init_data)
1586 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1587 .parent_names = (const char *[]) {
1588 "blsp2_qup6_i2c_apps_clk_src",
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1597 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1600 .enable_reg = 0x0c04,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data)
1604 .name = "gcc_blsp2_qup6_spi_apps_clk",
1605 .parent_names = (const char *[]) {
1606 "blsp2_qup6_spi_apps_clk_src",
1609 .flags = CLK_SET_RATE_PARENT,
1610 .ops = &clk_branch2_ops,
1615 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1618 .enable_reg = 0x09c4,
1619 .enable_mask = BIT(0),
1620 .hw.init = &(struct clk_init_data)
1622 .name = "gcc_blsp2_uart1_apps_clk",
1623 .parent_names = (const char *[]) {
1624 "blsp2_uart1_apps_clk_src",
1627 .flags = CLK_SET_RATE_PARENT,
1628 .ops = &clk_branch2_ops,
1633 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1636 .enable_reg = 0x0a44,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data)
1640 .name = "gcc_blsp2_uart2_apps_clk",
1641 .parent_names = (const char *[]) {
1642 "blsp2_uart2_apps_clk_src",
1645 .flags = CLK_SET_RATE_PARENT,
1646 .ops = &clk_branch2_ops,
1651 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1654 .enable_reg = 0x0ac4,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data)
1658 .name = "gcc_blsp2_uart3_apps_clk",
1659 .parent_names = (const char *[]) {
1660 "blsp2_uart3_apps_clk_src",
1663 .flags = CLK_SET_RATE_PARENT,
1664 .ops = &clk_branch2_ops,
1669 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1672 .enable_reg = 0x0b44,
1673 .enable_mask = BIT(0),
1674 .hw.init = &(struct clk_init_data)
1676 .name = "gcc_blsp2_uart4_apps_clk",
1677 .parent_names = (const char *[]) {
1678 "blsp2_uart4_apps_clk_src",
1681 .flags = CLK_SET_RATE_PARENT,
1682 .ops = &clk_branch2_ops,
1687 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1690 .enable_reg = 0x0bc4,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data)
1694 .name = "gcc_blsp2_uart5_apps_clk",
1695 .parent_names = (const char *[]) {
1696 "blsp2_uart5_apps_clk_src",
1699 .flags = CLK_SET_RATE_PARENT,
1700 .ops = &clk_branch2_ops,
1705 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1708 .enable_reg = 0x0c44,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data)
1712 .name = "gcc_blsp2_uart6_apps_clk",
1713 .parent_names = (const char *[]) {
1714 "blsp2_uart6_apps_clk_src",
1717 .flags = CLK_SET_RATE_PARENT,
1718 .ops = &clk_branch2_ops,
1723 static struct clk_branch gcc_gp1_clk = {
1726 .enable_reg = 0x1900,
1727 .enable_mask = BIT(0),
1728 .hw.init = &(struct clk_init_data)
1730 .name = "gcc_gp1_clk",
1731 .parent_names = (const char *[]) {
1735 .flags = CLK_SET_RATE_PARENT,
1736 .ops = &clk_branch2_ops,
1741 static struct clk_branch gcc_gp2_clk = {
1744 .enable_reg = 0x1940,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data)
1748 .name = "gcc_gp2_clk",
1749 .parent_names = (const char *[]) {
1753 .flags = CLK_SET_RATE_PARENT,
1754 .ops = &clk_branch2_ops,
1759 static struct clk_branch gcc_gp3_clk = {
1762 .enable_reg = 0x1980,
1763 .enable_mask = BIT(0),
1764 .hw.init = &(struct clk_init_data)
1766 .name = "gcc_gp3_clk",
1767 .parent_names = (const char *[]) {
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch gcc_lpass_q6_axi_clk = {
1780 .enable_reg = 0x0280,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data)
1784 .name = "gcc_lpass_q6_axi_clk",
1785 .ops = &clk_branch2_ops,
1790 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1793 .enable_reg = 0x0284,
1794 .enable_mask = BIT(0),
1795 .hw.init = &(struct clk_init_data)
1797 .name = "gcc_mss_q6_bimc_axi_clk",
1798 .ops = &clk_branch2_ops,
1803 static struct clk_branch gcc_pcie_0_aux_clk = {
1806 .enable_reg = 0x1ad4,
1807 .enable_mask = BIT(0),
1808 .hw.init = &(struct clk_init_data)
1810 .name = "gcc_pcie_0_aux_clk",
1811 .parent_names = (const char *[]) {
1812 "pcie_0_aux_clk_src",
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1821 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1824 .enable_reg = 0x1ad0,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data)
1828 .name = "gcc_pcie_0_cfg_ahb_clk",
1829 .ops = &clk_branch2_ops,
1834 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1837 .enable_reg = 0x1acc,
1838 .enable_mask = BIT(0),
1839 .hw.init = &(struct clk_init_data)
1841 .name = "gcc_pcie_0_mstr_axi_clk",
1842 .ops = &clk_branch2_ops,
1847 static struct clk_branch gcc_pcie_0_pipe_clk = {
1849 .halt_check = BRANCH_HALT_DELAY,
1851 .enable_reg = 0x1ad8,
1852 .enable_mask = BIT(0),
1853 .hw.init = &(struct clk_init_data)
1855 .name = "gcc_pcie_0_pipe_clk",
1856 .parent_names = (const char *[]) {
1857 "pcie_0_pipe_clk_src",
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1868 .halt_check = BRANCH_HALT_DELAY,
1870 .enable_reg = 0x1ac8,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data)
1874 .name = "gcc_pcie_0_slv_axi_clk",
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch gcc_pcie_1_aux_clk = {
1883 .enable_reg = 0x1b54,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data)
1887 .name = "gcc_pcie_1_aux_clk",
1888 .parent_names = (const char *[]) {
1889 "pcie_1_aux_clk_src",
1892 .flags = CLK_SET_RATE_PARENT,
1893 .ops = &clk_branch2_ops,
1898 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1901 .enable_reg = 0x1b54,
1902 .enable_mask = BIT(0),
1903 .hw.init = &(struct clk_init_data)
1905 .name = "gcc_pcie_1_cfg_ahb_clk",
1906 .ops = &clk_branch2_ops,
1911 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1914 .enable_reg = 0x1b50,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data)
1918 .name = "gcc_pcie_1_mstr_axi_clk",
1919 .ops = &clk_branch2_ops,
1924 static struct clk_branch gcc_pcie_1_pipe_clk = {
1926 .halt_check = BRANCH_HALT_DELAY,
1928 .enable_reg = 0x1b58,
1929 .enable_mask = BIT(0),
1930 .hw.init = &(struct clk_init_data)
1932 .name = "gcc_pcie_1_pipe_clk",
1933 .parent_names = (const char *[]) {
1934 "pcie_1_pipe_clk_src",
1937 .flags = CLK_SET_RATE_PARENT,
1938 .ops = &clk_branch2_ops,
1943 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1946 .enable_reg = 0x1b48,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data)
1950 .name = "gcc_pcie_1_slv_axi_clk",
1951 .ops = &clk_branch2_ops,
1956 static struct clk_branch gcc_pdm2_clk = {
1959 .enable_reg = 0x0ccc,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data)
1963 .name = "gcc_pdm2_clk",
1964 .parent_names = (const char *[]) {
1968 .flags = CLK_SET_RATE_PARENT,
1969 .ops = &clk_branch2_ops,
1974 static struct clk_branch gcc_pdm_ahb_clk = {
1977 .enable_reg = 0x0cc4,
1978 .enable_mask = BIT(0),
1979 .hw.init = &(struct clk_init_data)
1981 .name = "gcc_pdm_ahb_clk",
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch gcc_sdcc1_apps_clk = {
1990 .enable_reg = 0x04c4,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data)
1994 .name = "gcc_sdcc1_apps_clk",
1995 .parent_names = (const char *[]) {
1996 "sdcc1_apps_clk_src",
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_sdcc1_ahb_clk = {
2008 .enable_reg = 0x04c8,
2009 .enable_mask = BIT(0),
2010 .hw.init = &(struct clk_init_data)
2012 .name = "gcc_sdcc1_ahb_clk",
2013 .parent_names = (const char *[]){
2014 "periph_noc_clk_src",
2017 .ops = &clk_branch2_ops,
2022 static struct clk_branch gcc_sdcc2_ahb_clk = {
2025 .enable_reg = 0x0508,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data)
2029 .name = "gcc_sdcc2_ahb_clk",
2030 .parent_names = (const char *[]){
2031 "periph_noc_clk_src",
2034 .ops = &clk_branch2_ops,
2039 static struct clk_branch gcc_sdcc2_apps_clk = {
2042 .enable_reg = 0x0504,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data)
2046 .name = "gcc_sdcc2_apps_clk",
2047 .parent_names = (const char *[]) {
2048 "sdcc2_apps_clk_src",
2051 .flags = CLK_SET_RATE_PARENT,
2052 .ops = &clk_branch2_ops,
2057 static struct clk_branch gcc_sdcc3_ahb_clk = {
2060 .enable_reg = 0x0548,
2061 .enable_mask = BIT(0),
2062 .hw.init = &(struct clk_init_data)
2064 .name = "gcc_sdcc3_ahb_clk",
2065 .parent_names = (const char *[]){
2066 "periph_noc_clk_src",
2069 .ops = &clk_branch2_ops,
2074 static struct clk_branch gcc_sdcc3_apps_clk = {
2077 .enable_reg = 0x0544,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(struct clk_init_data)
2081 .name = "gcc_sdcc3_apps_clk",
2082 .parent_names = (const char *[]) {
2083 "sdcc3_apps_clk_src",
2086 .flags = CLK_SET_RATE_PARENT,
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch gcc_sdcc4_ahb_clk = {
2095 .enable_reg = 0x0588,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data)
2099 .name = "gcc_sdcc4_ahb_clk",
2100 .parent_names = (const char *[]){
2101 "periph_noc_clk_src",
2104 .ops = &clk_branch2_ops,
2109 static struct clk_branch gcc_sdcc4_apps_clk = {
2112 .enable_reg = 0x0584,
2113 .enable_mask = BIT(0),
2114 .hw.init = &(struct clk_init_data)
2116 .name = "gcc_sdcc4_apps_clk",
2117 .parent_names = (const char *[]) {
2118 "sdcc4_apps_clk_src",
2121 .flags = CLK_SET_RATE_PARENT,
2122 .ops = &clk_branch2_ops,
2127 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2130 .enable_reg = 0x1d7c,
2131 .enable_mask = BIT(0),
2132 .hw.init = &(struct clk_init_data)
2134 .name = "gcc_sys_noc_ufs_axi_clk",
2135 .parent_names = (const char *[]) {
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2148 .enable_reg = 0x03fc,
2149 .enable_mask = BIT(0),
2150 .hw.init = &(struct clk_init_data)
2152 .name = "gcc_sys_noc_usb3_axi_clk",
2153 .parent_names = (const char *[]) {
2154 "usb30_master_clk_src",
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2163 static struct clk_branch gcc_tsif_ahb_clk = {
2166 .enable_reg = 0x0d84,
2167 .enable_mask = BIT(0),
2168 .hw.init = &(struct clk_init_data)
2170 .name = "gcc_tsif_ahb_clk",
2171 .ops = &clk_branch2_ops,
2176 static struct clk_branch gcc_tsif_ref_clk = {
2179 .enable_reg = 0x0d88,
2180 .enable_mask = BIT(0),
2181 .hw.init = &(struct clk_init_data)
2183 .name = "gcc_tsif_ref_clk",
2184 .parent_names = (const char *[]) {
2188 .flags = CLK_SET_RATE_PARENT,
2189 .ops = &clk_branch2_ops,
2194 static struct clk_branch gcc_ufs_ahb_clk = {
2197 .enable_reg = 0x1d4c,
2198 .enable_mask = BIT(0),
2199 .hw.init = &(struct clk_init_data)
2201 .name = "gcc_ufs_ahb_clk",
2202 .ops = &clk_branch2_ops,
2207 static struct clk_branch gcc_ufs_axi_clk = {
2210 .enable_reg = 0x1d48,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(struct clk_init_data)
2214 .name = "gcc_ufs_axi_clk",
2215 .parent_names = (const char *[]) {
2219 .flags = CLK_SET_RATE_PARENT,
2220 .ops = &clk_branch2_ops,
2225 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2228 .enable_reg = 0x1d54,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data)
2232 .name = "gcc_ufs_rx_cfg_clk",
2233 .parent_names = (const char *[]) {
2237 .flags = CLK_SET_RATE_PARENT,
2238 .ops = &clk_branch2_ops,
2243 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2245 .halt_check = BRANCH_HALT_DELAY,
2247 .enable_reg = 0x1d60,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data)
2251 .name = "gcc_ufs_rx_symbol_0_clk",
2252 .ops = &clk_branch2_ops,
2257 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2259 .halt_check = BRANCH_HALT_DELAY,
2261 .enable_reg = 0x1d64,
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data)
2265 .name = "gcc_ufs_rx_symbol_1_clk",
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2274 .enable_reg = 0x1d50,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data)
2278 .name = "gcc_ufs_tx_cfg_clk",
2279 .parent_names = (const char *[]) {
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2289 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2291 .halt_check = BRANCH_HALT_DELAY,
2293 .enable_reg = 0x1d58,
2294 .enable_mask = BIT(0),
2295 .hw.init = &(struct clk_init_data)
2297 .name = "gcc_ufs_tx_symbol_0_clk",
2298 .ops = &clk_branch2_ops,
2303 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2305 .halt_check = BRANCH_HALT_DELAY,
2307 .enable_reg = 0x1d5c,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data)
2311 .name = "gcc_ufs_tx_symbol_1_clk",
2312 .ops = &clk_branch2_ops,
2317 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2320 .enable_reg = 0x04ac,
2321 .enable_mask = BIT(0),
2322 .hw.init = &(struct clk_init_data)
2324 .name = "gcc_usb2_hs_phy_sleep_clk",
2325 .ops = &clk_branch2_ops,
2330 static struct clk_branch gcc_usb30_master_clk = {
2333 .enable_reg = 0x03c8,
2334 .enable_mask = BIT(0),
2335 .hw.init = &(struct clk_init_data)
2337 .name = "gcc_usb30_master_clk",
2338 .parent_names = (const char *[]) {
2339 "usb30_master_clk_src",
2342 .flags = CLK_SET_RATE_PARENT,
2343 .ops = &clk_branch2_ops,
2348 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2351 .enable_reg = 0x03d0,
2352 .enable_mask = BIT(0),
2353 .hw.init = &(struct clk_init_data)
2355 .name = "gcc_usb30_mock_utmi_clk",
2356 .parent_names = (const char *[]) {
2357 "usb30_mock_utmi_clk_src",
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2366 static struct clk_branch gcc_usb30_sleep_clk = {
2369 .enable_reg = 0x03cc,
2370 .enable_mask = BIT(0),
2371 .hw.init = &(struct clk_init_data)
2373 .name = "gcc_usb30_sleep_clk",
2374 .ops = &clk_branch2_ops,
2379 static struct clk_branch gcc_usb3_phy_aux_clk = {
2382 .enable_reg = 0x1408,
2383 .enable_mask = BIT(0),
2384 .hw.init = &(struct clk_init_data)
2386 .name = "gcc_usb3_phy_aux_clk",
2387 .parent_names = (const char *[]) {
2388 "usb3_phy_aux_clk_src",
2391 .flags = CLK_SET_RATE_PARENT,
2392 .ops = &clk_branch2_ops,
2397 static struct clk_branch gcc_usb_hs_ahb_clk = {
2400 .enable_reg = 0x0488,
2401 .enable_mask = BIT(0),
2402 .hw.init = &(struct clk_init_data)
2404 .name = "gcc_usb_hs_ahb_clk",
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_usb_hs_system_clk = {
2413 .enable_reg = 0x0484,
2414 .enable_mask = BIT(0),
2415 .hw.init = &(struct clk_init_data)
2417 .name = "gcc_usb_hs_system_clk",
2418 .parent_names = (const char *[]) {
2419 "usb_hs_system_clk_src",
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2431 .enable_reg = 0x1a84,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data)
2435 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2436 .ops = &clk_branch2_ops,
2441 static struct gdsc pcie_gdsc = {
2446 .pwrsts = PWRSTS_OFF_ON,
2449 static struct gdsc pcie_0_gdsc = {
2454 .pwrsts = PWRSTS_OFF_ON,
2457 static struct gdsc pcie_1_gdsc = {
2462 .pwrsts = PWRSTS_OFF_ON,
2465 static struct gdsc usb30_gdsc = {
2470 .pwrsts = PWRSTS_OFF_ON,
2473 static struct gdsc ufs_gdsc = {
2478 .pwrsts = PWRSTS_OFF_ON,
2481 static struct clk_regmap *gcc_msm8994_clocks[] = {
2482 [GPLL0_EARLY] = &gpll0_early.clkr,
2483 [GPLL0] = &gpll0.clkr,
2484 [GPLL4_EARLY] = &gpll4_early.clkr,
2485 [GPLL4] = &gpll4.clkr,
2486 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2487 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2488 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2489 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2490 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2491 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2492 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2493 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2494 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2495 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2496 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2497 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2498 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2499 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2500 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2501 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2502 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2503 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2504 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2505 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2506 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2507 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2508 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2509 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2510 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2511 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2512 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2513 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2514 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2515 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2516 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2517 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2518 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2519 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2520 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2521 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2522 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2523 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2524 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2525 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2526 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2527 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2528 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2529 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2530 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2531 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2532 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2533 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2534 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2535 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2536 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2537 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2538 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2539 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2540 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2541 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2542 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2543 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2544 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2545 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2546 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2547 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2548 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2549 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2550 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2551 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2552 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2553 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2554 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2555 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2556 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2557 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2558 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2559 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2560 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2561 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2562 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2563 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2564 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2565 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2566 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2567 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2568 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2569 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2570 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2571 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2572 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2573 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2574 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2575 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2576 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2577 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2578 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2579 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2580 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2581 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2582 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2583 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2584 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2585 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2586 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2587 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2588 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2589 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2590 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2591 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2592 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2593 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2594 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2595 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2596 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2597 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2598 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2599 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2600 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2601 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2602 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2603 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2604 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2605 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2606 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2607 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2608 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2609 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2610 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2611 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2612 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2613 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2614 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2615 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2616 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2617 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2618 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2619 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2620 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2621 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2622 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2625 static struct gdsc *gcc_msm8994_gdscs[] = {
2626 [PCIE_GDSC] = &pcie_gdsc,
2627 [PCIE_0_GDSC] = &pcie_0_gdsc,
2628 [PCIE_1_GDSC] = &pcie_1_gdsc,
2629 [USB30_GDSC] = &usb30_gdsc,
2630 [UFS_GDSC] = &ufs_gdsc,
2633 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2634 [USB3_PHY_RESET] = { 0x1400 },
2635 [USB3PHY_PHY_RESET] = { 0x1404 },
2636 [PCIE_PHY_0_RESET] = { 0x1b18 },
2637 [PCIE_PHY_1_RESET] = { 0x1b98 },
2638 [QUSB2_PHY_RESET] = { 0x04b8 },
2641 static const struct regmap_config gcc_msm8994_regmap_config = {
2645 .max_register = 0x2000,
2649 static const struct qcom_cc_desc gcc_msm8994_desc = {
2650 .config = &gcc_msm8994_regmap_config,
2651 .clks = gcc_msm8994_clocks,
2652 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2653 .resets = gcc_msm8994_resets,
2654 .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2655 .gdscs = gcc_msm8994_gdscs,
2656 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2659 static const struct of_device_id gcc_msm8994_match_table[] = {
2660 { .compatible = "qcom,gcc-msm8994" },
2663 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2665 static int gcc_msm8994_probe(struct platform_device *pdev)
2667 struct device *dev = &pdev->dev;
2670 clk = devm_clk_register(dev, &xo.hw);
2672 return PTR_ERR(clk);
2674 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2677 static struct platform_driver gcc_msm8994_driver = {
2678 .probe = gcc_msm8994_probe,
2680 .name = "gcc-msm8994",
2681 .of_match_table = gcc_msm8994_match_table,
2685 static int __init gcc_msm8994_init(void)
2687 return platform_driver_register(&gcc_msm8994_driver);
2689 core_initcall(gcc_msm8994_init);
2691 static void __exit gcc_msm8994_exit(void)
2693 platform_driver_unregister(&gcc_msm8994_driver);
2695 module_exit(gcc_msm8994_exit);
2697 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2698 MODULE_LICENSE("GPL v2");
2699 MODULE_ALIAS("platform:gcc-msm8994");