1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/ctype.h>
19 #include <linux/platform_device.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
23 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
26 #include "clk-regmap.h"
27 #include "clk-alpha-pll.h"
29 #include "clk-branch.h"
38 static const struct parent_map gcc_xo_gpll0_map[] = {
43 static const char * const gcc_xo_gpll0[] = {
48 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
54 static const char * const gcc_xo_gpll0_gpll4[] = {
60 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
62 static struct clk_fixed_factor xo = {
65 .hw.init = &(struct clk_init_data)
68 .parent_names = (const char *[]) { "xo_board" },
70 .ops = &clk_fixed_factor_ops,
74 static struct clk_alpha_pll gpll0_early = {
78 .enable_mask = BIT(0),
79 .hw.init = &(struct clk_init_data)
81 .name = "gpll0_early",
82 .parent_names = (const char *[]) { "xo" },
84 .ops = &clk_alpha_pll_ops,
89 static struct clk_alpha_pll_postdiv gpll0 = {
91 .clkr.hw.init = &(struct clk_init_data)
94 .parent_names = (const char *[]) { "gpll0_early" },
96 .ops = &clk_alpha_pll_postdiv_ops,
100 static struct clk_alpha_pll gpll4_early = {
103 .enable_reg = 0x1480,
104 .enable_mask = BIT(4),
105 .hw.init = &(struct clk_init_data)
107 .name = "gpll4_early",
108 .parent_names = (const char *[]) { "xo" },
110 .ops = &clk_alpha_pll_ops,
115 static struct clk_alpha_pll_postdiv gpll4 = {
117 .clkr.hw.init = &(struct clk_init_data)
120 .parent_names = (const char *[]) { "gpll4_early" },
122 .ops = &clk_alpha_pll_postdiv_ops,
126 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
127 F(50000000, P_GPLL0, 12, 0, 0),
128 F(100000000, P_GPLL0, 6, 0, 0),
129 F(150000000, P_GPLL0, 4, 0, 0),
130 F(171430000, P_GPLL0, 3.5, 0, 0),
131 F(200000000, P_GPLL0, 3, 0, 0),
132 F(240000000, P_GPLL0, 2.5, 0, 0),
136 static struct clk_rcg2 ufs_axi_clk_src = {
140 .parent_map = gcc_xo_gpll0_map,
141 .freq_tbl = ftbl_ufs_axi_clk_src,
142 .clkr.hw.init = &(struct clk_init_data)
144 .name = "ufs_axi_clk_src",
145 .parent_names = gcc_xo_gpll0,
147 .ops = &clk_rcg2_ops,
151 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
152 F(19200000, P_XO, 1, 0, 0),
153 F(125000000, P_GPLL0, 1, 5, 24),
157 static struct clk_rcg2 usb30_master_clk_src = {
161 .parent_map = gcc_xo_gpll0_map,
162 .freq_tbl = ftbl_usb30_master_clk_src,
163 .clkr.hw.init = &(struct clk_init_data)
165 .name = "usb30_master_clk_src",
166 .parent_names = gcc_xo_gpll0,
168 .ops = &clk_rcg2_ops,
172 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
173 F(19200000, P_XO, 1, 0, 0),
174 F(50000000, P_GPLL0, 12, 0, 0),
178 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
181 .parent_map = gcc_xo_gpll0_map,
182 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
183 .clkr.hw.init = &(struct clk_init_data)
185 .name = "blsp1_qup1_i2c_apps_clk_src",
186 .parent_names = gcc_xo_gpll0,
188 .ops = &clk_rcg2_ops,
192 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
193 F(960000, P_XO, 10, 1, 2),
194 F(4800000, P_XO, 4, 0, 0),
195 F(9600000, P_XO, 2, 0, 0),
196 F(15000000, P_GPLL0, 10, 1, 4),
197 F(19200000, P_XO, 1, 0, 0),
198 F(24000000, P_GPLL0, 12.5, 1, 2),
199 F(25000000, P_GPLL0, 12, 1, 2),
200 F(48000000, P_GPLL0, 12.5, 0, 0),
201 F(50000000, P_GPLL0, 12, 0, 0),
205 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
209 .parent_map = gcc_xo_gpll0_map,
210 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
211 .clkr.hw.init = &(struct clk_init_data)
213 .name = "blsp1_qup1_spi_apps_clk_src",
214 .parent_names = gcc_xo_gpll0,
216 .ops = &clk_rcg2_ops,
220 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
223 .parent_map = gcc_xo_gpll0_map,
224 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
225 .clkr.hw.init = &(struct clk_init_data)
227 .name = "blsp1_qup2_i2c_apps_clk_src",
228 .parent_names = gcc_xo_gpll0,
230 .ops = &clk_rcg2_ops,
234 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
238 .parent_map = gcc_xo_gpll0_map,
239 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
240 .clkr.hw.init = &(struct clk_init_data)
242 .name = "blsp1_qup2_spi_apps_clk_src",
243 .parent_names = gcc_xo_gpll0,
245 .ops = &clk_rcg2_ops,
249 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
252 .parent_map = gcc_xo_gpll0_map,
253 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
254 .clkr.hw.init = &(struct clk_init_data)
256 .name = "blsp1_qup3_i2c_apps_clk_src",
257 .parent_names = gcc_xo_gpll0,
259 .ops = &clk_rcg2_ops,
263 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
267 .parent_map = gcc_xo_gpll0_map,
268 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
269 .clkr.hw.init = &(struct clk_init_data)
271 .name = "blsp1_qup3_spi_apps_clk_src",
272 .parent_names = gcc_xo_gpll0,
274 .ops = &clk_rcg2_ops,
278 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
281 .parent_map = gcc_xo_gpll0_map,
282 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
283 .clkr.hw.init = &(struct clk_init_data)
285 .name = "blsp1_qup4_i2c_apps_clk_src",
286 .parent_names = gcc_xo_gpll0,
288 .ops = &clk_rcg2_ops,
292 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
296 .parent_map = gcc_xo_gpll0_map,
297 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
298 .clkr.hw.init = &(struct clk_init_data)
300 .name = "blsp1_qup4_spi_apps_clk_src",
301 .parent_names = gcc_xo_gpll0,
303 .ops = &clk_rcg2_ops,
307 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
310 .parent_map = gcc_xo_gpll0_map,
311 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
312 .clkr.hw.init = &(struct clk_init_data)
314 .name = "blsp1_qup5_i2c_apps_clk_src",
315 .parent_names = gcc_xo_gpll0,
317 .ops = &clk_rcg2_ops,
321 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
325 .parent_map = gcc_xo_gpll0_map,
326 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
327 .clkr.hw.init = &(struct clk_init_data)
329 .name = "blsp1_qup5_spi_apps_clk_src",
330 .parent_names = gcc_xo_gpll0,
332 .ops = &clk_rcg2_ops,
336 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
339 .parent_map = gcc_xo_gpll0_map,
340 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
341 .clkr.hw.init = &(struct clk_init_data)
343 .name = "blsp1_qup6_i2c_apps_clk_src",
344 .parent_names = gcc_xo_gpll0,
346 .ops = &clk_rcg2_ops,
350 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
356 .clkr.hw.init = &(struct clk_init_data)
358 .name = "blsp1_qup6_spi_apps_clk_src",
359 .parent_names = gcc_xo_gpll0,
361 .ops = &clk_rcg2_ops,
365 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
366 F(3686400, P_GPLL0, 1, 96, 15625),
367 F(7372800, P_GPLL0, 1, 192, 15625),
368 F(14745600, P_GPLL0, 1, 384, 15625),
369 F(16000000, P_GPLL0, 5, 2, 15),
370 F(19200000, P_XO, 1, 0, 0),
371 F(24000000, P_GPLL0, 5, 1, 5),
372 F(32000000, P_GPLL0, 1, 4, 75),
373 F(40000000, P_GPLL0, 15, 0, 0),
374 F(46400000, P_GPLL0, 1, 29, 375),
375 F(48000000, P_GPLL0, 12.5, 0, 0),
376 F(51200000, P_GPLL0, 1, 32, 375),
377 F(56000000, P_GPLL0, 1, 7, 75),
378 F(58982400, P_GPLL0, 1, 1536, 15625),
379 F(60000000, P_GPLL0, 10, 0, 0),
380 F(63160000, P_GPLL0, 9.5, 0, 0),
384 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
388 .parent_map = gcc_xo_gpll0_map,
389 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
390 .clkr.hw.init = &(struct clk_init_data)
392 .name = "blsp1_uart1_apps_clk_src",
393 .parent_names = gcc_xo_gpll0,
395 .ops = &clk_rcg2_ops,
399 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
403 .parent_map = gcc_xo_gpll0_map,
404 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
405 .clkr.hw.init = &(struct clk_init_data)
407 .name = "blsp1_uart2_apps_clk_src",
408 .parent_names = gcc_xo_gpll0,
410 .ops = &clk_rcg2_ops,
414 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
418 .parent_map = gcc_xo_gpll0_map,
419 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
420 .clkr.hw.init = &(struct clk_init_data)
422 .name = "blsp1_uart3_apps_clk_src",
423 .parent_names = gcc_xo_gpll0,
425 .ops = &clk_rcg2_ops,
429 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
433 .parent_map = gcc_xo_gpll0_map,
434 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
435 .clkr.hw.init = &(struct clk_init_data)
437 .name = "blsp1_uart4_apps_clk_src",
438 .parent_names = gcc_xo_gpll0,
440 .ops = &clk_rcg2_ops,
444 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
448 .parent_map = gcc_xo_gpll0_map,
449 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
450 .clkr.hw.init = &(struct clk_init_data)
452 .name = "blsp1_uart5_apps_clk_src",
453 .parent_names = gcc_xo_gpll0,
455 .ops = &clk_rcg2_ops,
459 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
463 .parent_map = gcc_xo_gpll0_map,
464 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
465 .clkr.hw.init = &(struct clk_init_data)
467 .name = "blsp1_uart6_apps_clk_src",
468 .parent_names = gcc_xo_gpll0,
470 .ops = &clk_rcg2_ops,
474 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
477 .parent_map = gcc_xo_gpll0_map,
478 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
479 .clkr.hw.init = &(struct clk_init_data)
481 .name = "blsp2_qup1_i2c_apps_clk_src",
482 .parent_names = gcc_xo_gpll0,
484 .ops = &clk_rcg2_ops,
488 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
492 .parent_map = gcc_xo_gpll0_map,
493 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
494 .clkr.hw.init = &(struct clk_init_data)
496 .name = "blsp2_qup1_spi_apps_clk_src",
497 .parent_names = gcc_xo_gpll0,
499 .ops = &clk_rcg2_ops,
503 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
506 .parent_map = gcc_xo_gpll0_map,
507 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
508 .clkr.hw.init = &(struct clk_init_data)
510 .name = "blsp2_qup2_i2c_apps_clk_src",
511 .parent_names = gcc_xo_gpll0,
513 .ops = &clk_rcg2_ops,
517 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
521 .parent_map = gcc_xo_gpll0_map,
522 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
523 .clkr.hw.init = &(struct clk_init_data)
525 .name = "blsp2_qup2_spi_apps_clk_src",
526 .parent_names = gcc_xo_gpll0,
528 .ops = &clk_rcg2_ops,
532 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
535 .parent_map = gcc_xo_gpll0_map,
536 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
537 .clkr.hw.init = &(struct clk_init_data)
539 .name = "blsp2_qup3_i2c_apps_clk_src",
540 .parent_names = gcc_xo_gpll0,
542 .ops = &clk_rcg2_ops,
546 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
550 .parent_map = gcc_xo_gpll0_map,
551 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
552 .clkr.hw.init = &(struct clk_init_data)
554 .name = "blsp2_qup3_spi_apps_clk_src",
555 .parent_names = gcc_xo_gpll0,
557 .ops = &clk_rcg2_ops,
561 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
564 .parent_map = gcc_xo_gpll0_map,
565 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data)
568 .name = "blsp2_qup4_i2c_apps_clk_src",
569 .parent_names = gcc_xo_gpll0,
571 .ops = &clk_rcg2_ops,
575 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
579 .parent_map = gcc_xo_gpll0_map,
580 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
581 .clkr.hw.init = &(struct clk_init_data)
583 .name = "blsp2_qup4_spi_apps_clk_src",
584 .parent_names = gcc_xo_gpll0,
586 .ops = &clk_rcg2_ops,
590 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
593 .parent_map = gcc_xo_gpll0_map,
594 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
595 .clkr.hw.init = &(struct clk_init_data)
597 .name = "blsp2_qup5_i2c_apps_clk_src",
598 .parent_names = gcc_xo_gpll0,
600 .ops = &clk_rcg2_ops,
604 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
610 .clkr.hw.init = &(struct clk_init_data)
612 .name = "blsp2_qup5_spi_apps_clk_src",
613 .parent_names = gcc_xo_gpll0,
615 .ops = &clk_rcg2_ops,
619 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
624 .clkr.hw.init = &(struct clk_init_data)
626 .name = "blsp2_qup6_i2c_apps_clk_src",
627 .parent_names = gcc_xo_gpll0,
629 .ops = &clk_rcg2_ops,
633 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
637 .parent_map = gcc_xo_gpll0_map,
638 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
639 .clkr.hw.init = &(struct clk_init_data)
641 .name = "blsp2_qup6_spi_apps_clk_src",
642 .parent_names = gcc_xo_gpll0,
644 .ops = &clk_rcg2_ops,
648 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
652 .parent_map = gcc_xo_gpll0_map,
653 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
654 .clkr.hw.init = &(struct clk_init_data)
656 .name = "blsp2_uart1_apps_clk_src",
657 .parent_names = gcc_xo_gpll0,
659 .ops = &clk_rcg2_ops,
663 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
667 .parent_map = gcc_xo_gpll0_map,
668 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
669 .clkr.hw.init = &(struct clk_init_data)
671 .name = "blsp2_uart2_apps_clk_src",
672 .parent_names = gcc_xo_gpll0,
674 .ops = &clk_rcg2_ops,
678 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
682 .parent_map = gcc_xo_gpll0_map,
683 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
684 .clkr.hw.init = &(struct clk_init_data)
686 .name = "blsp2_uart3_apps_clk_src",
687 .parent_names = gcc_xo_gpll0,
689 .ops = &clk_rcg2_ops,
693 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
697 .parent_map = gcc_xo_gpll0_map,
698 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
699 .clkr.hw.init = &(struct clk_init_data)
701 .name = "blsp2_uart4_apps_clk_src",
702 .parent_names = gcc_xo_gpll0,
704 .ops = &clk_rcg2_ops,
708 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
712 .parent_map = gcc_xo_gpll0_map,
713 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
714 .clkr.hw.init = &(struct clk_init_data)
716 .name = "blsp2_uart5_apps_clk_src",
717 .parent_names = gcc_xo_gpll0,
719 .ops = &clk_rcg2_ops,
723 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
727 .parent_map = gcc_xo_gpll0_map,
728 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
729 .clkr.hw.init = &(struct clk_init_data)
731 .name = "blsp2_uart6_apps_clk_src",
732 .parent_names = gcc_xo_gpll0,
734 .ops = &clk_rcg2_ops,
738 static struct freq_tbl ftbl_gp1_clk_src[] = {
739 F(19200000, P_XO, 1, 0, 0),
740 F(100000000, P_GPLL0, 6, 0, 0),
741 F(200000000, P_GPLL0, 3, 0, 0),
745 static struct clk_rcg2 gp1_clk_src = {
749 .parent_map = gcc_xo_gpll0_map,
750 .freq_tbl = ftbl_gp1_clk_src,
751 .clkr.hw.init = &(struct clk_init_data)
753 .name = "gp1_clk_src",
754 .parent_names = gcc_xo_gpll0,
756 .ops = &clk_rcg2_ops,
760 static struct freq_tbl ftbl_gp2_clk_src[] = {
761 F(19200000, P_XO, 1, 0, 0),
762 F(100000000, P_GPLL0, 6, 0, 0),
763 F(200000000, P_GPLL0, 3, 0, 0),
767 static struct clk_rcg2 gp2_clk_src = {
771 .parent_map = gcc_xo_gpll0_map,
772 .freq_tbl = ftbl_gp2_clk_src,
773 .clkr.hw.init = &(struct clk_init_data)
775 .name = "gp2_clk_src",
776 .parent_names = gcc_xo_gpll0,
778 .ops = &clk_rcg2_ops,
782 static struct freq_tbl ftbl_gp3_clk_src[] = {
783 F(19200000, P_XO, 1, 0, 0),
784 F(100000000, P_GPLL0, 6, 0, 0),
785 F(200000000, P_GPLL0, 3, 0, 0),
789 static struct clk_rcg2 gp3_clk_src = {
793 .parent_map = gcc_xo_gpll0_map,
794 .freq_tbl = ftbl_gp3_clk_src,
795 .clkr.hw.init = &(struct clk_init_data)
797 .name = "gp3_clk_src",
798 .parent_names = gcc_xo_gpll0,
800 .ops = &clk_rcg2_ops,
804 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
805 F(1011000, P_XO, 1, 1, 19),
809 static struct clk_rcg2 pcie_0_aux_clk_src = {
813 .freq_tbl = ftbl_pcie_0_aux_clk_src,
814 .clkr.hw.init = &(struct clk_init_data)
816 .name = "pcie_0_aux_clk_src",
817 .parent_names = (const char *[]) { "xo" },
819 .ops = &clk_rcg2_ops,
823 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
824 F(125000000, P_XO, 1, 0, 0),
828 static struct clk_rcg2 pcie_0_pipe_clk_src = {
831 .freq_tbl = ftbl_pcie_pipe_clk_src,
832 .clkr.hw.init = &(struct clk_init_data)
834 .name = "pcie_0_pipe_clk_src",
835 .parent_names = (const char *[]) { "xo" },
837 .ops = &clk_rcg2_ops,
841 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
842 F(1011000, P_XO, 1, 1, 19),
846 static struct clk_rcg2 pcie_1_aux_clk_src = {
850 .freq_tbl = ftbl_pcie_1_aux_clk_src,
851 .clkr.hw.init = &(struct clk_init_data)
853 .name = "pcie_1_aux_clk_src",
854 .parent_names = (const char *[]) { "xo" },
856 .ops = &clk_rcg2_ops,
860 static struct clk_rcg2 pcie_1_pipe_clk_src = {
863 .freq_tbl = ftbl_pcie_pipe_clk_src,
864 .clkr.hw.init = &(struct clk_init_data)
866 .name = "pcie_1_pipe_clk_src",
867 .parent_names = (const char *[]) { "xo" },
869 .ops = &clk_rcg2_ops,
873 static struct freq_tbl ftbl_pdm2_clk_src[] = {
874 F(60000000, P_GPLL0, 10, 0, 0),
878 static struct clk_rcg2 pdm2_clk_src = {
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_pdm2_clk_src,
883 .clkr.hw.init = &(struct clk_init_data)
885 .name = "pdm2_clk_src",
886 .parent_names = gcc_xo_gpll0,
888 .ops = &clk_rcg2_ops,
892 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
893 F(144000, P_XO, 16, 3, 25),
894 F(400000, P_XO, 12, 1, 4),
895 F(20000000, P_GPLL0, 15, 1, 2),
896 F(25000000, P_GPLL0, 12, 1, 2),
897 F(50000000, P_GPLL0, 12, 0, 0),
898 F(100000000, P_GPLL0, 6, 0, 0),
899 F(192000000, P_GPLL4, 2, 0, 0),
900 F(384000000, P_GPLL4, 1, 0, 0),
904 static struct clk_rcg2 sdcc1_apps_clk_src = {
908 .parent_map = gcc_xo_gpll0_gpll4_map,
909 .freq_tbl = ftbl_sdcc1_apps_clk_src,
910 .clkr.hw.init = &(struct clk_init_data)
912 .name = "sdcc1_apps_clk_src",
913 .parent_names = gcc_xo_gpll0_gpll4,
915 .ops = &clk_rcg2_floor_ops,
919 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
920 F(144000, P_XO, 16, 3, 25),
921 F(400000, P_XO, 12, 1, 4),
922 F(20000000, P_GPLL0, 15, 1, 2),
923 F(25000000, P_GPLL0, 12, 1, 2),
924 F(50000000, P_GPLL0, 12, 0, 0),
925 F(100000000, P_GPLL0, 6, 0, 0),
926 F(200000000, P_GPLL0, 3, 0, 0),
930 static struct clk_rcg2 sdcc2_apps_clk_src = {
934 .parent_map = gcc_xo_gpll0_map,
935 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
936 .clkr.hw.init = &(struct clk_init_data)
938 .name = "sdcc2_apps_clk_src",
939 .parent_names = gcc_xo_gpll0,
941 .ops = &clk_rcg2_floor_ops,
945 static struct clk_rcg2 sdcc3_apps_clk_src = {
949 .parent_map = gcc_xo_gpll0_map,
950 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
951 .clkr.hw.init = &(struct clk_init_data)
953 .name = "sdcc3_apps_clk_src",
954 .parent_names = gcc_xo_gpll0,
956 .ops = &clk_rcg2_floor_ops,
960 static struct clk_rcg2 sdcc4_apps_clk_src = {
964 .parent_map = gcc_xo_gpll0_map,
965 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
966 .clkr.hw.init = &(struct clk_init_data)
968 .name = "sdcc4_apps_clk_src",
969 .parent_names = gcc_xo_gpll0,
971 .ops = &clk_rcg2_floor_ops,
975 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
976 F(105500, P_XO, 1, 1, 182),
980 static struct clk_rcg2 tsif_ref_clk_src = {
984 .freq_tbl = ftbl_tsif_ref_clk_src,
985 .clkr.hw.init = &(struct clk_init_data)
987 .name = "tsif_ref_clk_src",
988 .parent_names = (const char *[]) { "xo" },
990 .ops = &clk_rcg2_ops,
994 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
995 F(19200000, P_XO, 1, 0, 0),
996 F(60000000, P_GPLL0, 10, 0, 0),
1000 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1003 .parent_map = gcc_xo_gpll0_map,
1004 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data)
1007 .name = "usb30_mock_utmi_clk_src",
1008 .parent_names = gcc_xo_gpll0,
1010 .ops = &clk_rcg2_ops,
1014 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1015 F(1200000, P_XO, 16, 0, 0),
1019 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1022 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1023 .clkr.hw.init = &(struct clk_init_data)
1025 .name = "usb3_phy_aux_clk_src",
1026 .parent_names = (const char *[]) { "xo" },
1028 .ops = &clk_rcg2_ops,
1032 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1033 F(75000000, P_GPLL0, 8, 0, 0),
1037 static struct clk_rcg2 usb_hs_system_clk_src = {
1040 .parent_map = gcc_xo_gpll0_map,
1041 .freq_tbl = ftbl_usb_hs_system_clk_src,
1042 .clkr.hw.init = &(struct clk_init_data)
1044 .name = "usb_hs_system_clk_src",
1045 .parent_names = gcc_xo_gpll0,
1047 .ops = &clk_rcg2_ops,
1051 static struct clk_branch gcc_blsp1_ahb_clk = {
1053 .halt_check = BRANCH_HALT_VOTED,
1055 .enable_reg = 0x1484,
1056 .enable_mask = BIT(17),
1057 .hw.init = &(struct clk_init_data)
1059 .name = "gcc_blsp1_ahb_clk",
1060 .ops = &clk_branch2_ops,
1065 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1068 .enable_reg = 0x0648,
1069 .enable_mask = BIT(0),
1070 .hw.init = &(struct clk_init_data)
1072 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1073 .parent_names = (const char *[]) {
1074 "blsp1_qup1_i2c_apps_clk_src",
1077 .flags = CLK_SET_RATE_PARENT,
1078 .ops = &clk_branch2_ops,
1083 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1086 .enable_reg = 0x0644,
1087 .enable_mask = BIT(0),
1088 .hw.init = &(struct clk_init_data)
1090 .name = "gcc_blsp1_qup1_spi_apps_clk",
1091 .parent_names = (const char *[]) {
1092 "blsp1_qup1_spi_apps_clk_src",
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1101 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1104 .enable_reg = 0x06c8,
1105 .enable_mask = BIT(0),
1106 .hw.init = &(struct clk_init_data)
1108 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1109 .parent_names = (const char *[]) {
1110 "blsp1_qup2_i2c_apps_clk_src",
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_branch2_ops,
1119 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1122 .enable_reg = 0x06c4,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data)
1126 .name = "gcc_blsp1_qup2_spi_apps_clk",
1127 .parent_names = (const char *[]) {
1128 "blsp1_qup2_spi_apps_clk_src",
1131 .flags = CLK_SET_RATE_PARENT,
1132 .ops = &clk_branch2_ops,
1137 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1140 .enable_reg = 0x0748,
1141 .enable_mask = BIT(0),
1142 .hw.init = &(struct clk_init_data)
1144 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1145 .parent_names = (const char *[]) {
1146 "blsp1_qup3_i2c_apps_clk_src",
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1155 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1158 .enable_reg = 0x0744,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data)
1162 .name = "gcc_blsp1_qup3_spi_apps_clk",
1163 .parent_names = (const char *[]) {
1164 "blsp1_qup3_spi_apps_clk_src",
1167 .flags = CLK_SET_RATE_PARENT,
1168 .ops = &clk_branch2_ops,
1173 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1176 .enable_reg = 0x07c8,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data)
1180 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1181 .parent_names = (const char *[]) {
1182 "blsp1_qup4_i2c_apps_clk_src",
1185 .flags = CLK_SET_RATE_PARENT,
1186 .ops = &clk_branch2_ops,
1191 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1194 .enable_reg = 0x07c4,
1195 .enable_mask = BIT(0),
1196 .hw.init = &(struct clk_init_data)
1198 .name = "gcc_blsp1_qup4_spi_apps_clk",
1199 .parent_names = (const char *[]) {
1200 "blsp1_qup4_spi_apps_clk_src",
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1209 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1212 .enable_reg = 0x0848,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data)
1216 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1217 .parent_names = (const char *[]) {
1218 "blsp1_qup5_i2c_apps_clk_src",
1221 .flags = CLK_SET_RATE_PARENT,
1222 .ops = &clk_branch2_ops,
1227 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1230 .enable_reg = 0x0844,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data)
1234 .name = "gcc_blsp1_qup5_spi_apps_clk",
1235 .parent_names = (const char *[]) {
1236 "blsp1_qup5_spi_apps_clk_src",
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_branch2_ops,
1245 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1248 .enable_reg = 0x08c8,
1249 .enable_mask = BIT(0),
1250 .hw.init = &(struct clk_init_data)
1252 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1253 .parent_names = (const char *[]) {
1254 "blsp1_qup6_i2c_apps_clk_src",
1257 .flags = CLK_SET_RATE_PARENT,
1258 .ops = &clk_branch2_ops,
1263 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1266 .enable_reg = 0x08c4,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data)
1270 .name = "gcc_blsp1_qup6_spi_apps_clk",
1271 .parent_names = (const char *[]) {
1272 "blsp1_qup6_spi_apps_clk_src",
1275 .flags = CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1281 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1284 .enable_reg = 0x0684,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data)
1288 .name = "gcc_blsp1_uart1_apps_clk",
1289 .parent_names = (const char *[]) {
1290 "blsp1_uart1_apps_clk_src",
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1299 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1302 .enable_reg = 0x0704,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data)
1306 .name = "gcc_blsp1_uart2_apps_clk",
1307 .parent_names = (const char *[]) {
1308 "blsp1_uart2_apps_clk_src",
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1320 .enable_reg = 0x0784,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data)
1324 .name = "gcc_blsp1_uart3_apps_clk",
1325 .parent_names = (const char *[]) {
1326 "blsp1_uart3_apps_clk_src",
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1338 .enable_reg = 0x0804,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data)
1342 .name = "gcc_blsp1_uart4_apps_clk",
1343 .parent_names = (const char *[]) {
1344 "blsp1_uart4_apps_clk_src",
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1353 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1356 .enable_reg = 0x0884,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data)
1360 .name = "gcc_blsp1_uart5_apps_clk",
1361 .parent_names = (const char *[]) {
1362 "blsp1_uart5_apps_clk_src",
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1371 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1374 .enable_reg = 0x0904,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data)
1378 .name = "gcc_blsp1_uart6_apps_clk",
1379 .parent_names = (const char *[]) {
1380 "blsp1_uart6_apps_clk_src",
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1389 static struct clk_branch gcc_blsp2_ahb_clk = {
1391 .halt_check = BRANCH_HALT_VOTED,
1393 .enable_reg = 0x1484,
1394 .enable_mask = BIT(15),
1395 .hw.init = &(struct clk_init_data)
1397 .name = "gcc_blsp2_ahb_clk",
1398 .ops = &clk_branch2_ops,
1403 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1406 .enable_reg = 0x0988,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data)
1410 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1411 .parent_names = (const char *[]) {
1412 "blsp2_qup1_i2c_apps_clk_src",
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1424 .enable_reg = 0x0984,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data)
1428 .name = "gcc_blsp2_qup1_spi_apps_clk",
1429 .parent_names = (const char *[]) {
1430 "blsp2_qup1_spi_apps_clk_src",
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1439 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1442 .enable_reg = 0x0a08,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data)
1446 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1447 .parent_names = (const char *[]) {
1448 "blsp2_qup2_i2c_apps_clk_src",
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1457 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1460 .enable_reg = 0x0a04,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data)
1464 .name = "gcc_blsp2_qup2_spi_apps_clk",
1465 .parent_names = (const char *[]) {
1466 "blsp2_qup2_spi_apps_clk_src",
1469 .flags = CLK_SET_RATE_PARENT,
1470 .ops = &clk_branch2_ops,
1475 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1478 .enable_reg = 0x0a88,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data)
1482 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1483 .parent_names = (const char *[]) {
1484 "blsp2_qup3_i2c_apps_clk_src",
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1493 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1496 .enable_reg = 0x0a84,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data)
1500 .name = "gcc_blsp2_qup3_spi_apps_clk",
1501 .parent_names = (const char *[]) {
1502 "blsp2_qup3_spi_apps_clk_src",
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1511 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1514 .enable_reg = 0x0b08,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data)
1518 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1519 .parent_names = (const char *[]) {
1520 "blsp2_qup4_i2c_apps_clk_src",
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1529 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1532 .enable_reg = 0x0b04,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data)
1536 .name = "gcc_blsp2_qup4_spi_apps_clk",
1537 .parent_names = (const char *[]) {
1538 "blsp2_qup4_spi_apps_clk_src",
1541 .flags = CLK_SET_RATE_PARENT,
1542 .ops = &clk_branch2_ops,
1547 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1550 .enable_reg = 0x0b88,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data)
1554 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1555 .parent_names = (const char *[]) {
1556 "blsp2_qup5_i2c_apps_clk_src",
1559 .flags = CLK_SET_RATE_PARENT,
1560 .ops = &clk_branch2_ops,
1565 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1568 .enable_reg = 0x0b84,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data)
1572 .name = "gcc_blsp2_qup5_spi_apps_clk",
1573 .parent_names = (const char *[]) {
1574 "blsp2_qup5_spi_apps_clk_src",
1577 .flags = CLK_SET_RATE_PARENT,
1578 .ops = &clk_branch2_ops,
1583 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1586 .enable_reg = 0x0c08,
1587 .enable_mask = BIT(0),
1588 .hw.init = &(struct clk_init_data)
1590 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1591 .parent_names = (const char *[]) {
1592 "blsp2_qup6_i2c_apps_clk_src",
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1601 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1604 .enable_reg = 0x0c04,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data)
1608 .name = "gcc_blsp2_qup6_spi_apps_clk",
1609 .parent_names = (const char *[]) {
1610 "blsp2_qup6_spi_apps_clk_src",
1613 .flags = CLK_SET_RATE_PARENT,
1614 .ops = &clk_branch2_ops,
1619 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1622 .enable_reg = 0x09c4,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data)
1626 .name = "gcc_blsp2_uart1_apps_clk",
1627 .parent_names = (const char *[]) {
1628 "blsp2_uart1_apps_clk_src",
1631 .flags = CLK_SET_RATE_PARENT,
1632 .ops = &clk_branch2_ops,
1637 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1640 .enable_reg = 0x0a44,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data)
1644 .name = "gcc_blsp2_uart2_apps_clk",
1645 .parent_names = (const char *[]) {
1646 "blsp2_uart2_apps_clk_src",
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1655 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1658 .enable_reg = 0x0ac4,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data)
1662 .name = "gcc_blsp2_uart3_apps_clk",
1663 .parent_names = (const char *[]) {
1664 "blsp2_uart3_apps_clk_src",
1667 .flags = CLK_SET_RATE_PARENT,
1668 .ops = &clk_branch2_ops,
1673 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1676 .enable_reg = 0x0b44,
1677 .enable_mask = BIT(0),
1678 .hw.init = &(struct clk_init_data)
1680 .name = "gcc_blsp2_uart4_apps_clk",
1681 .parent_names = (const char *[]) {
1682 "blsp2_uart4_apps_clk_src",
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1694 .enable_reg = 0x0bc4,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data)
1698 .name = "gcc_blsp2_uart5_apps_clk",
1699 .parent_names = (const char *[]) {
1700 "blsp2_uart5_apps_clk_src",
1703 .flags = CLK_SET_RATE_PARENT,
1704 .ops = &clk_branch2_ops,
1709 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1712 .enable_reg = 0x0c44,
1713 .enable_mask = BIT(0),
1714 .hw.init = &(struct clk_init_data)
1716 .name = "gcc_blsp2_uart6_apps_clk",
1717 .parent_names = (const char *[]) {
1718 "blsp2_uart6_apps_clk_src",
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch gcc_gp1_clk = {
1730 .enable_reg = 0x1900,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data)
1734 .name = "gcc_gp1_clk",
1735 .parent_names = (const char *[]) {
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1745 static struct clk_branch gcc_gp2_clk = {
1748 .enable_reg = 0x1940,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data)
1752 .name = "gcc_gp2_clk",
1753 .parent_names = (const char *[]) {
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1763 static struct clk_branch gcc_gp3_clk = {
1766 .enable_reg = 0x1980,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data)
1770 .name = "gcc_gp3_clk",
1771 .parent_names = (const char *[]) {
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1781 static struct clk_branch gcc_pcie_0_aux_clk = {
1784 .enable_reg = 0x1ad4,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data)
1788 .name = "gcc_pcie_0_aux_clk",
1789 .parent_names = (const char *[]) {
1790 "pcie_0_aux_clk_src",
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1799 static struct clk_branch gcc_pcie_0_pipe_clk = {
1801 .halt_check = BRANCH_HALT_DELAY,
1803 .enable_reg = 0x1ad8,
1804 .enable_mask = BIT(0),
1805 .hw.init = &(struct clk_init_data)
1807 .name = "gcc_pcie_0_pipe_clk",
1808 .parent_names = (const char *[]) {
1809 "pcie_0_pipe_clk_src",
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1818 static struct clk_branch gcc_pcie_1_aux_clk = {
1821 .enable_reg = 0x1b54,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data)
1825 .name = "gcc_pcie_1_aux_clk",
1826 .parent_names = (const char *[]) {
1827 "pcie_1_aux_clk_src",
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch gcc_pcie_1_pipe_clk = {
1838 .halt_check = BRANCH_HALT_DELAY,
1840 .enable_reg = 0x1b58,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data)
1844 .name = "gcc_pcie_1_pipe_clk",
1845 .parent_names = (const char *[]) {
1846 "pcie_1_pipe_clk_src",
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1855 static struct clk_branch gcc_pdm2_clk = {
1858 .enable_reg = 0x0ccc,
1859 .enable_mask = BIT(0),
1860 .hw.init = &(struct clk_init_data)
1862 .name = "gcc_pdm2_clk",
1863 .parent_names = (const char *[]) {
1867 .flags = CLK_SET_RATE_PARENT,
1868 .ops = &clk_branch2_ops,
1873 static struct clk_branch gcc_sdcc1_apps_clk = {
1876 .enable_reg = 0x04c4,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data)
1880 .name = "gcc_sdcc1_apps_clk",
1881 .parent_names = (const char *[]) {
1882 "sdcc1_apps_clk_src",
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1891 static struct clk_branch gcc_sdcc1_ahb_clk = {
1894 .enable_reg = 0x04c8,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data)
1898 .name = "gcc_sdcc1_ahb_clk",
1899 .parent_names = (const char *[]){
1900 "periph_noc_clk_src",
1903 .ops = &clk_branch2_ops,
1908 static struct clk_branch gcc_sdcc2_apps_clk = {
1911 .enable_reg = 0x0504,
1912 .enable_mask = BIT(0),
1913 .hw.init = &(struct clk_init_data)
1915 .name = "gcc_sdcc2_apps_clk",
1916 .parent_names = (const char *[]) {
1917 "sdcc2_apps_clk_src",
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1926 static struct clk_branch gcc_sdcc3_apps_clk = {
1929 .enable_reg = 0x0544,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data)
1933 .name = "gcc_sdcc3_apps_clk",
1934 .parent_names = (const char *[]) {
1935 "sdcc3_apps_clk_src",
1938 .flags = CLK_SET_RATE_PARENT,
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_sdcc4_apps_clk = {
1947 .enable_reg = 0x0584,
1948 .enable_mask = BIT(0),
1949 .hw.init = &(struct clk_init_data)
1951 .name = "gcc_sdcc4_apps_clk",
1952 .parent_names = (const char *[]) {
1953 "sdcc4_apps_clk_src",
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1962 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1965 .enable_reg = 0x1d7c,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data)
1969 .name = "gcc_sys_noc_ufs_axi_clk",
1970 .parent_names = (const char *[]) {
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1980 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1983 .enable_reg = 0x03fc,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data)
1987 .name = "gcc_sys_noc_usb3_axi_clk",
1988 .parent_names = (const char *[]) {
1989 "usb30_master_clk_src",
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1998 static struct clk_branch gcc_tsif_ref_clk = {
2001 .enable_reg = 0x0d88,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data)
2005 .name = "gcc_tsif_ref_clk",
2006 .parent_names = (const char *[]) {
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2016 static struct clk_branch gcc_ufs_axi_clk = {
2019 .enable_reg = 0x1d48,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data)
2023 .name = "gcc_ufs_axi_clk",
2024 .parent_names = (const char *[]) {
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2034 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2037 .enable_reg = 0x1d54,
2038 .enable_mask = BIT(0),
2039 .hw.init = &(struct clk_init_data)
2041 .name = "gcc_ufs_rx_cfg_clk",
2042 .parent_names = (const char *[]) {
2046 .flags = CLK_SET_RATE_PARENT,
2047 .ops = &clk_branch2_ops,
2052 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2055 .enable_reg = 0x1d50,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data)
2059 .name = "gcc_ufs_tx_cfg_clk",
2060 .parent_names = (const char *[]) {
2064 .flags = CLK_SET_RATE_PARENT,
2065 .ops = &clk_branch2_ops,
2070 static struct clk_branch gcc_usb30_master_clk = {
2073 .enable_reg = 0x03c8,
2074 .enable_mask = BIT(0),
2075 .hw.init = &(struct clk_init_data)
2077 .name = "gcc_usb30_master_clk",
2078 .parent_names = (const char *[]) {
2079 "usb30_master_clk_src",
2082 .flags = CLK_SET_RATE_PARENT,
2083 .ops = &clk_branch2_ops,
2088 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2091 .enable_reg = 0x03d0,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data)
2095 .name = "gcc_usb30_mock_utmi_clk",
2096 .parent_names = (const char *[]) {
2097 "usb30_mock_utmi_clk_src",
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2106 static struct clk_branch gcc_usb3_phy_aux_clk = {
2109 .enable_reg = 0x1408,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data)
2113 .name = "gcc_usb3_phy_aux_clk",
2114 .parent_names = (const char *[]) {
2115 "usb3_phy_aux_clk_src",
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2124 static struct clk_branch gcc_usb_hs_system_clk = {
2127 .enable_reg = 0x0484,
2128 .enable_mask = BIT(0),
2129 .hw.init = &(struct clk_init_data)
2131 .name = "gcc_usb_hs_system_clk",
2132 .parent_names = (const char *[]) {
2133 "usb_hs_system_clk_src",
2136 .flags = CLK_SET_RATE_PARENT,
2137 .ops = &clk_branch2_ops,
2142 static struct clk_regmap *gcc_msm8994_clocks[] = {
2143 [GPLL0_EARLY] = &gpll0_early.clkr,
2144 [GPLL0] = &gpll0.clkr,
2145 [GPLL4_EARLY] = &gpll4_early.clkr,
2146 [GPLL4] = &gpll4.clkr,
2147 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2148 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2149 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2150 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2151 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2152 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2153 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2154 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2155 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2156 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2157 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2158 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2159 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2160 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2161 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2162 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2163 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2164 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2165 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2166 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2167 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2168 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2169 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2170 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2171 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2172 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2173 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2174 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2175 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2176 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2177 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2178 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2179 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2180 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2181 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2182 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2183 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2184 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2185 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2186 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2187 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2188 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2189 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2190 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2191 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2192 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2193 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2194 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2195 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2196 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2197 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2198 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2199 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2200 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2201 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2202 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2203 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2204 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2205 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2206 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2207 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2208 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2209 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2210 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2211 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2212 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2213 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2214 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2215 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2216 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2217 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2218 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2219 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2220 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2221 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2222 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2223 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2224 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2225 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2226 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2227 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2228 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2229 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2230 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2231 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2232 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2233 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2234 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2235 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2236 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2237 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2238 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2239 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2240 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2241 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2242 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2243 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2244 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2245 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2246 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2247 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2248 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2249 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2250 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2251 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2252 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2253 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2254 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2255 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2256 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2257 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2258 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2259 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2260 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2261 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2264 static const struct regmap_config gcc_msm8994_regmap_config = {
2268 .max_register = 0x2000,
2272 static const struct qcom_cc_desc gcc_msm8994_desc = {
2273 .config = &gcc_msm8994_regmap_config,
2274 .clks = gcc_msm8994_clocks,
2275 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2278 static const struct of_device_id gcc_msm8994_match_table[] = {
2279 { .compatible = "qcom,gcc-msm8994" },
2282 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2284 static int gcc_msm8994_probe(struct platform_device *pdev)
2286 struct device *dev = &pdev->dev;
2289 clk = devm_clk_register(dev, &xo.hw);
2291 return PTR_ERR(clk);
2293 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2296 static struct platform_driver gcc_msm8994_driver = {
2297 .probe = gcc_msm8994_probe,
2299 .name = "gcc-msm8994",
2300 .of_match_table = gcc_msm8994_match_table,
2304 static int __init gcc_msm8994_init(void)
2306 return platform_driver_register(&gcc_msm8994_driver);
2308 core_initcall(gcc_msm8994_init);
2310 static void __exit gcc_msm8994_exit(void)
2312 platform_driver_unregister(&gcc_msm8994_driver);
2314 module_exit(gcc_msm8994_exit);
2316 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2317 MODULE_LICENSE("GPL v2");
2318 MODULE_ALIAS("platform:gcc-msm8994");