drivers/clk/qcom/gcc-msm8994.c

   1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/ctype.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-alpha-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "reset.h"
  31
  32 enum {
  33         P_XO,
  34         P_GPLL0,
  35         P_GPLL4,
  36 };
  37
  38 static const struct parent_map gcc_xo_gpll0_map[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0, 1 },
  41 };
  42
  43 static const char * const gcc_xo_gpll0[] = {
  44         "xo",
  45         "gpll0",
  46 };
  47
  48 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  49         { P_XO, 0 },
  50         { P_GPLL0, 1 },
  51         { P_GPLL4, 5 },
  52 };
  53
  54 static const char * const gcc_xo_gpll0_gpll4[] = {
  55         "xo",
  56         "gpll0",
  57         "gpll4",
  58 };
  59
  60 static struct clk_fixed_factor xo = {
  61         .mult = 1,
  62         .div = 1,
  63         .hw.init = &(struct clk_init_data)
  64         {
  65                 .name = "xo",
  66                 .parent_names = (const char *[]) { "xo_board" },
  67                 .num_parents = 1,
  68                 .ops = &clk_fixed_factor_ops,
  69         },
  70 };
  71
  72 static struct clk_alpha_pll gpll0_early = {
  73         .offset = 0x00000,
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  75         .clkr = {
  76                 .enable_reg = 0x1480,
  77                 .enable_mask = BIT(0),
  78                 .hw.init = &(struct clk_init_data)
  79                 {
  80                         .name = "gpll0_early",
  81                         .parent_names = (const char *[]) { "xo" },
  82                         .num_parents = 1,
  83                         .ops = &clk_alpha_pll_ops,
  84                 },
  85         },
  86 };
  87
  88 static struct clk_alpha_pll_postdiv gpll0 = {
  89         .offset = 0x00000,
  90         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  91         .clkr.hw.init = &(struct clk_init_data)
  92         {
  93                 .name = "gpll0",
  94                 .parent_names = (const char *[]) { "gpll0_early" },
  95                 .num_parents = 1,
  96                 .ops = &clk_alpha_pll_postdiv_ops,
  97         },
  98 };
  99
 100 static struct clk_alpha_pll gpll4_early = {
 101         .offset = 0x1dc0,
 102         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 103         .clkr = {
 104                 .enable_reg = 0x1480,
 105                 .enable_mask = BIT(4),
 106                 .hw.init = &(struct clk_init_data)
 107                 {
 108                         .name = "gpll4_early",
 109                         .parent_names = (const char *[]) { "xo" },
 110                         .num_parents = 1,
 111                         .ops = &clk_alpha_pll_ops,
 112                 },
 113         },
 114 };
 115
 116 static struct clk_alpha_pll_postdiv gpll4 = {
 117         .offset = 0x1dc0,
 118         .width = 4,
 119         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 120         .clkr.hw.init = &(struct clk_init_data)
 121         {
 122                 .name = "gpll4",
 123                 .parent_names = (const char *[]) { "gpll4_early" },
 124                 .num_parents = 1,
 125                 .ops = &clk_alpha_pll_postdiv_ops,
 126         },
 127 };
 128
 129 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
 130         F(50000000, P_GPLL0, 12, 0, 0),
 131         F(100000000, P_GPLL0, 6, 0, 0),
 132         F(150000000, P_GPLL0, 4, 0, 0),
 133         F(171430000, P_GPLL0, 3.5, 0, 0),
 134         F(200000000, P_GPLL0, 3, 0, 0),
 135         F(240000000, P_GPLL0, 2.5, 0, 0),
 136         { }
 137 };
 138
 139 static struct clk_rcg2 ufs_axi_clk_src = {
 140         .cmd_rcgr = 0x1d68,
 141         .mnd_width = 8,
 142         .hid_width = 5,
 143         .parent_map = gcc_xo_gpll0_map,
 144         .freq_tbl = ftbl_ufs_axi_clk_src,
 145         .clkr.hw.init = &(struct clk_init_data)
 146         {
 147                 .name = "ufs_axi_clk_src",
 148                 .parent_names = gcc_xo_gpll0,
 149                 .num_parents = 2,
 150                 .ops = &clk_rcg2_ops,
 151         },
 152 };
 153
 154 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
 155         F(19200000, P_XO, 1, 0, 0),
 156         F(125000000, P_GPLL0, 1, 5, 24),
 157         { }
 158 };
 159
 160 static struct clk_rcg2 usb30_master_clk_src = {
 161         .cmd_rcgr = 0x03d4,
 162         .mnd_width = 8,
 163         .hid_width = 5,
 164         .parent_map = gcc_xo_gpll0_map,
 165         .freq_tbl = ftbl_usb30_master_clk_src,
 166         .clkr.hw.init = &(struct clk_init_data)
 167         {
 168                 .name = "usb30_master_clk_src",
 169                 .parent_names = gcc_xo_gpll0,
 170                 .num_parents = 2,
 171                 .ops = &clk_rcg2_ops,
 172         },
 173 };
 174
 175 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 176         F(19200000, P_XO, 1, 0, 0),
 177         F(50000000, P_GPLL0, 12, 0, 0),
 178         { }
 179 };
 180
 181 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 182         .cmd_rcgr = 0x0660,
 183         .hid_width = 5,
 184         .parent_map = gcc_xo_gpll0_map,
 185         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 186         .clkr.hw.init = &(struct clk_init_data)
 187         {
 188                 .name = "blsp1_qup1_i2c_apps_clk_src",
 189                 .parent_names = gcc_xo_gpll0,
 190                 .num_parents = 2,
 191                 .ops = &clk_rcg2_ops,
 192         },
 193 };
 194
 195 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
 196         F(960000, P_XO, 10, 1, 2),
 197         F(4800000, P_XO, 4, 0, 0),
 198         F(9600000, P_XO, 2, 0, 0),
 199         F(15000000, P_GPLL0, 10, 1, 4),
 200         F(19200000, P_XO, 1, 0, 0),
 201         F(24000000, P_GPLL0, 12.5, 1, 2),
 202         F(25000000, P_GPLL0, 12, 1, 2),
 203         F(48000000, P_GPLL0, 12.5, 0, 0),
 204         F(50000000, P_GPLL0, 12, 0, 0),
 205         { }
 206 };
 207
 208 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 209         .cmd_rcgr = 0x064c,
 210         .mnd_width = 8,
 211         .hid_width = 5,
 212         .parent_map = gcc_xo_gpll0_map,
 213         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 214         .clkr.hw.init = &(struct clk_init_data)
 215         {
 216                 .name = "blsp1_qup1_spi_apps_clk_src",
 217                 .parent_names = gcc_xo_gpll0,
 218                 .num_parents = 2,
 219                 .ops = &clk_rcg2_ops,
 220         },
 221 };
 222
 223 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 224         .cmd_rcgr = 0x06e0,
 225         .hid_width = 5,
 226         .parent_map = gcc_xo_gpll0_map,
 227         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 228         .clkr.hw.init = &(struct clk_init_data)
 229         {
 230                 .name = "blsp1_qup2_i2c_apps_clk_src",
 231                 .parent_names = gcc_xo_gpll0,
 232                 .num_parents = 2,
 233                 .ops = &clk_rcg2_ops,
 234         },
 235 };
 236
 237 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 238         .cmd_rcgr = 0x06cc,
 239         .mnd_width = 8,
 240         .hid_width = 5,
 241         .parent_map = gcc_xo_gpll0_map,
 242         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 243         .clkr.hw.init = &(struct clk_init_data)
 244         {
 245                 .name = "blsp1_qup2_spi_apps_clk_src",
 246                 .parent_names = gcc_xo_gpll0,
 247                 .num_parents = 2,
 248                 .ops = &clk_rcg2_ops,
 249         },
 250 };
 251
 252 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 253         .cmd_rcgr = 0x0760,
 254         .hid_width = 5,
 255         .parent_map = gcc_xo_gpll0_map,
 256         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 257         .clkr.hw.init = &(struct clk_init_data)
 258         {
 259                 .name = "blsp1_qup3_i2c_apps_clk_src",
 260                 .parent_names = gcc_xo_gpll0,
 261                 .num_parents = 2,
 262                 .ops = &clk_rcg2_ops,
 263         },
 264 };
 265
 266 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 267         .cmd_rcgr = 0x074c,
 268         .mnd_width = 8,
 269         .hid_width = 5,
 270         .parent_map = gcc_xo_gpll0_map,
 271         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 272         .clkr.hw.init = &(struct clk_init_data)
 273         {
 274                 .name = "blsp1_qup3_spi_apps_clk_src",
 275                 .parent_names = gcc_xo_gpll0,
 276                 .num_parents = 2,
 277                 .ops = &clk_rcg2_ops,
 278         },
 279 };
 280
 281 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 282         .cmd_rcgr = 0x07e0,
 283         .hid_width = 5,
 284         .parent_map = gcc_xo_gpll0_map,
 285         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 286         .clkr.hw.init = &(struct clk_init_data)
 287         {
 288                 .name = "blsp1_qup4_i2c_apps_clk_src",
 289                 .parent_names = gcc_xo_gpll0,
 290                 .num_parents = 2,
 291                 .ops = &clk_rcg2_ops,
 292         },
 293 };
 294
 295 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 296         .cmd_rcgr = 0x07cc,
 297         .mnd_width = 8,
 298         .hid_width = 5,
 299         .parent_map = gcc_xo_gpll0_map,
 300         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 301         .clkr.hw.init = &(struct clk_init_data)
 302         {
 303                 .name = "blsp1_qup4_spi_apps_clk_src",
 304                 .parent_names = gcc_xo_gpll0,
 305                 .num_parents = 2,
 306                 .ops = &clk_rcg2_ops,
 307         },
 308 };
 309
 310 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 311         .cmd_rcgr = 0x0860,
 312         .hid_width = 5,
 313         .parent_map = gcc_xo_gpll0_map,
 314         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 315         .clkr.hw.init = &(struct clk_init_data)
 316         {
 317                 .name = "blsp1_qup5_i2c_apps_clk_src",
 318                 .parent_names = gcc_xo_gpll0,
 319                 .num_parents = 2,
 320                 .ops = &clk_rcg2_ops,
 321         },
 322 };
 323
 324 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 325         .cmd_rcgr = 0x084c,
 326         .mnd_width = 8,
 327         .hid_width = 5,
 328         .parent_map = gcc_xo_gpll0_map,
 329         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 330         .clkr.hw.init = &(struct clk_init_data)
 331         {
 332                 .name = "blsp1_qup5_spi_apps_clk_src",
 333                 .parent_names = gcc_xo_gpll0,
 334                 .num_parents = 2,
 335                 .ops = &clk_rcg2_ops,
 336         },
 337 };
 338
 339 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 340         .cmd_rcgr = 0x08e0,
 341         .hid_width = 5,
 342         .parent_map = gcc_xo_gpll0_map,
 343         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 344         .clkr.hw.init = &(struct clk_init_data)
 345         {
 346                 .name = "blsp1_qup6_i2c_apps_clk_src",
 347                 .parent_names = gcc_xo_gpll0,
 348                 .num_parents = 2,
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 354         .cmd_rcgr = 0x08cc,
 355         .mnd_width = 8,
 356         .hid_width = 5,
 357         .parent_map = gcc_xo_gpll0_map,
 358         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 359         .clkr.hw.init = &(struct clk_init_data)
 360         {
 361                 .name = "blsp1_qup6_spi_apps_clk_src",
 362                 .parent_names = gcc_xo_gpll0,
 363                 .num_parents = 2,
 364                 .ops = &clk_rcg2_ops,
 365         },
 366 };
 367
 368 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 369         F(3686400, P_GPLL0, 1, 96, 15625),
 370         F(7372800, P_GPLL0, 1, 192, 15625),
 371         F(14745600, P_GPLL0, 1, 384, 15625),
 372         F(16000000, P_GPLL0, 5, 2, 15),
 373         F(19200000, P_XO, 1, 0, 0),
 374         F(24000000, P_GPLL0, 5, 1, 5),
 375         F(32000000, P_GPLL0, 1, 4, 75),
 376         F(40000000, P_GPLL0, 15, 0, 0),
 377         F(46400000, P_GPLL0, 1, 29, 375),
 378         F(48000000, P_GPLL0, 12.5, 0, 0),
 379         F(51200000, P_GPLL0, 1, 32, 375),
 380         F(56000000, P_GPLL0, 1, 7, 75),
 381         F(58982400, P_GPLL0, 1, 1536, 15625),
 382         F(60000000, P_GPLL0, 10, 0, 0),
 383         F(63160000, P_GPLL0, 9.5, 0, 0),
 384         { }
 385 };
 386
 387 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 388         .cmd_rcgr = 0x068c,
 389         .mnd_width = 16,
 390         .hid_width = 5,
 391         .parent_map = gcc_xo_gpll0_map,
 392         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 393         .clkr.hw.init = &(struct clk_init_data)
 394         {
 395                 .name = "blsp1_uart1_apps_clk_src",
 396                 .parent_names = gcc_xo_gpll0,
 397                 .num_parents = 2,
 398                 .ops = &clk_rcg2_ops,
 399         },
 400 };
 401
 402 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 403         .cmd_rcgr = 0x070c,
 404         .mnd_width = 16,
 405         .hid_width = 5,
 406         .parent_map = gcc_xo_gpll0_map,
 407         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 408         .clkr.hw.init = &(struct clk_init_data)
 409         {
 410                 .name = "blsp1_uart2_apps_clk_src",
 411                 .parent_names = gcc_xo_gpll0,
 412                 .num_parents = 2,
 413                 .ops = &clk_rcg2_ops,
 414         },
 415 };
 416
 417 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 418         .cmd_rcgr = 0x078c,
 419         .mnd_width = 16,
 420         .hid_width = 5,
 421         .parent_map = gcc_xo_gpll0_map,
 422         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 423         .clkr.hw.init = &(struct clk_init_data)
 424         {
 425                 .name = "blsp1_uart3_apps_clk_src",
 426                 .parent_names = gcc_xo_gpll0,
 427                 .num_parents = 2,
 428                 .ops = &clk_rcg2_ops,
 429         },
 430 };
 431
 432 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 433         .cmd_rcgr = 0x080c,
 434         .mnd_width = 16,
 435         .hid_width = 5,
 436         .parent_map = gcc_xo_gpll0_map,
 437         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 438         .clkr.hw.init = &(struct clk_init_data)
 439         {
 440                 .name = "blsp1_uart4_apps_clk_src",
 441                 .parent_names = gcc_xo_gpll0,
 442                 .num_parents = 2,
 443                 .ops = &clk_rcg2_ops,
 444         },
 445 };
 446
 447 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 448         .cmd_rcgr = 0x088c,
 449         .mnd_width = 16,
 450         .hid_width = 5,
 451         .parent_map = gcc_xo_gpll0_map,
 452         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 453         .clkr.hw.init = &(struct clk_init_data)
 454         {
 455                 .name = "blsp1_uart5_apps_clk_src",
 456                 .parent_names = gcc_xo_gpll0,
 457                 .num_parents = 2,
 458                 .ops = &clk_rcg2_ops,
 459         },
 460 };
 461
 462 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 463         .cmd_rcgr = 0x090c,
 464         .mnd_width = 16,
 465         .hid_width = 5,
 466         .parent_map = gcc_xo_gpll0_map,
 467         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 468         .clkr.hw.init = &(struct clk_init_data)
 469         {
 470                 .name = "blsp1_uart6_apps_clk_src",
 471                 .parent_names = gcc_xo_gpll0,
 472                 .num_parents = 2,
 473                 .ops = &clk_rcg2_ops,
 474         },
 475 };
 476
 477 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 478         .cmd_rcgr = 0x09a0,
 479         .hid_width = 5,
 480         .parent_map = gcc_xo_gpll0_map,
 481         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 482         .clkr.hw.init = &(struct clk_init_data)
 483         {
 484                 .name = "blsp2_qup1_i2c_apps_clk_src",
 485                 .parent_names = gcc_xo_gpll0,
 486                 .num_parents = 2,
 487                 .ops = &clk_rcg2_ops,
 488         },
 489 };
 490
 491 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 492         .cmd_rcgr = 0x098c,
 493         .mnd_width = 8,
 494         .hid_width = 5,
 495         .parent_map = gcc_xo_gpll0_map,
 496         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 497         .clkr.hw.init = &(struct clk_init_data)
 498         {
 499                 .name = "blsp2_qup1_spi_apps_clk_src",
 500                 .parent_names = gcc_xo_gpll0,
 501                 .num_parents = 2,
 502                 .ops = &clk_rcg2_ops,
 503         },
 504 };
 505
 506 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 507         .cmd_rcgr = 0x0a20,
 508         .hid_width = 5,
 509         .parent_map = gcc_xo_gpll0_map,
 510         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 511         .clkr.hw.init = &(struct clk_init_data)
 512         {
 513                 .name = "blsp2_qup2_i2c_apps_clk_src",
 514                 .parent_names = gcc_xo_gpll0,
 515                 .num_parents = 2,
 516                 .ops = &clk_rcg2_ops,
 517         },
 518 };
 519
 520 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 521         .cmd_rcgr = 0x0a0c,
 522         .mnd_width = 8,
 523         .hid_width = 5,
 524         .parent_map = gcc_xo_gpll0_map,
 525         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 526         .clkr.hw.init = &(struct clk_init_data)
 527         {
 528                 .name = "blsp2_qup2_spi_apps_clk_src",
 529                 .parent_names = gcc_xo_gpll0,
 530                 .num_parents = 2,
 531                 .ops = &clk_rcg2_ops,
 532         },
 533 };
 534
 535 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 536         .cmd_rcgr = 0x0aa0,
 537         .hid_width = 5,
 538         .parent_map = gcc_xo_gpll0_map,
 539         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 540         .clkr.hw.init = &(struct clk_init_data)
 541         {
 542                 .name = "blsp2_qup3_i2c_apps_clk_src",
 543                 .parent_names = gcc_xo_gpll0,
 544                 .num_parents = 2,
 545                 .ops = &clk_rcg2_ops,
 546         },
 547 };
 548
 549 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 550         .cmd_rcgr = 0x0a8c,
 551         .mnd_width = 8,
 552         .hid_width = 5,
 553         .parent_map = gcc_xo_gpll0_map,
 554         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 555         .clkr.hw.init = &(struct clk_init_data)
 556         {
 557                 .name = "blsp2_qup3_spi_apps_clk_src",
 558                 .parent_names = gcc_xo_gpll0,
 559                 .num_parents = 2,
 560                 .ops = &clk_rcg2_ops,
 561         },
 562 };
 563
 564 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 565         .cmd_rcgr = 0x0b20,
 566         .hid_width = 5,
 567         .parent_map = gcc_xo_gpll0_map,
 568         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 569         .clkr.hw.init = &(struct clk_init_data)
 570         {
 571                 .name = "blsp2_qup4_i2c_apps_clk_src",
 572                 .parent_names = gcc_xo_gpll0,
 573                 .num_parents = 2,
 574                 .ops = &clk_rcg2_ops,
 575         },
 576 };
 577
 578 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 579         .cmd_rcgr = 0x0b0c,
 580         .mnd_width = 8,
 581         .hid_width = 5,
 582         .parent_map = gcc_xo_gpll0_map,
 583         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 584         .clkr.hw.init = &(struct clk_init_data)
 585         {
 586                 .name = "blsp2_qup4_spi_apps_clk_src",
 587                 .parent_names = gcc_xo_gpll0,
 588                 .num_parents = 2,
 589                 .ops = &clk_rcg2_ops,
 590         },
 591 };
 592
 593 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 594         .cmd_rcgr = 0x0ba0,
 595         .hid_width = 5,
 596         .parent_map = gcc_xo_gpll0_map,
 597         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 598         .clkr.hw.init = &(struct clk_init_data)
 599         {
 600                 .name = "blsp2_qup5_i2c_apps_clk_src",
 601                 .parent_names = gcc_xo_gpll0,
 602                 .num_parents = 2,
 603                 .ops = &clk_rcg2_ops,
 604         },
 605 };
 606
 607 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 608         .cmd_rcgr = 0x0b8c,
 609         .mnd_width = 8,
 610         .hid_width = 5,
 611         .parent_map = gcc_xo_gpll0_map,
 612         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 613         .clkr.hw.init = &(struct clk_init_data)
 614         {
 615                 .name = "blsp2_qup5_spi_apps_clk_src",
 616                 .parent_names = gcc_xo_gpll0,
 617                 .num_parents = 2,
 618                 .ops = &clk_rcg2_ops,
 619         },
 620 };
 621
 622 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 623         .cmd_rcgr = 0x0c20,
 624         .hid_width = 5,
 625         .parent_map = gcc_xo_gpll0_map,
 626         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 627         .clkr.hw.init = &(struct clk_init_data)
 628         {
 629                 .name = "blsp2_qup6_i2c_apps_clk_src",
 630                 .parent_names = gcc_xo_gpll0,
 631                 .num_parents = 2,
 632                 .ops = &clk_rcg2_ops,
 633         },
 634 };
 635
 636 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 637         .cmd_rcgr = 0x0c0c,
 638         .mnd_width = 8,
 639         .hid_width = 5,
 640         .parent_map = gcc_xo_gpll0_map,
 641         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 642         .clkr.hw.init = &(struct clk_init_data)
 643         {
 644                 .name = "blsp2_qup6_spi_apps_clk_src",
 645                 .parent_names = gcc_xo_gpll0,
 646                 .num_parents = 2,
 647                 .ops = &clk_rcg2_ops,
 648         },
 649 };
 650
 651 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 652         .cmd_rcgr = 0x09cc,
 653         .mnd_width = 16,
 654         .hid_width = 5,
 655         .parent_map = gcc_xo_gpll0_map,
 656         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 657         .clkr.hw.init = &(struct clk_init_data)
 658         {
 659                 .name = "blsp2_uart1_apps_clk_src",
 660                 .parent_names = gcc_xo_gpll0,
 661                 .num_parents = 2,
 662                 .ops = &clk_rcg2_ops,
 663         },
 664 };
 665
 666 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 667         .cmd_rcgr = 0x0a4c,
 668         .mnd_width = 16,
 669         .hid_width = 5,
 670         .parent_map = gcc_xo_gpll0_map,
 671         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 672         .clkr.hw.init = &(struct clk_init_data)
 673         {
 674                 .name = "blsp2_uart2_apps_clk_src",
 675                 .parent_names = gcc_xo_gpll0,
 676                 .num_parents = 2,
 677                 .ops = &clk_rcg2_ops,
 678         },
 679 };
 680
 681 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 682         .cmd_rcgr = 0x0acc,
 683         .mnd_width = 16,
 684         .hid_width = 5,
 685         .parent_map = gcc_xo_gpll0_map,
 686         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 687         .clkr.hw.init = &(struct clk_init_data)
 688         {
 689                 .name = "blsp2_uart3_apps_clk_src",
 690                 .parent_names = gcc_xo_gpll0,
 691                 .num_parents = 2,
 692                 .ops = &clk_rcg2_ops,
 693         },
 694 };
 695
 696 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 697         .cmd_rcgr = 0x0b4c,
 698         .mnd_width = 16,
 699         .hid_width = 5,
 700         .parent_map = gcc_xo_gpll0_map,
 701         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 702         .clkr.hw.init = &(struct clk_init_data)
 703         {
 704                 .name = "blsp2_uart4_apps_clk_src",
 705                 .parent_names = gcc_xo_gpll0,
 706                 .num_parents = 2,
 707                 .ops = &clk_rcg2_ops,
 708         },
 709 };
 710
 711 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 712         .cmd_rcgr = 0x0bcc,
 713         .mnd_width = 16,
 714         .hid_width = 5,
 715         .parent_map = gcc_xo_gpll0_map,
 716         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 717         .clkr.hw.init = &(struct clk_init_data)
 718         {
 719                 .name = "blsp2_uart5_apps_clk_src",
 720                 .parent_names = gcc_xo_gpll0,
 721                 .num_parents = 2,
 722                 .ops = &clk_rcg2_ops,
 723         },
 724 };
 725
 726 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 727         .cmd_rcgr = 0x0c4c,
 728         .mnd_width = 16,
 729         .hid_width = 5,
 730         .parent_map = gcc_xo_gpll0_map,
 731         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data)
 733         {
 734                 .name = "blsp2_uart6_apps_clk_src",
 735                 .parent_names = gcc_xo_gpll0,
 736                 .num_parents = 2,
 737                 .ops = &clk_rcg2_ops,
 738         },
 739 };
 740
 741 static struct freq_tbl ftbl_gp1_clk_src[] = {
 742         F(19200000, P_XO, 1, 0, 0),
 743         F(100000000, P_GPLL0, 6, 0, 0),
 744         F(200000000, P_GPLL0, 3, 0, 0),
 745         { }
 746 };
 747
 748 static struct clk_rcg2 gp1_clk_src = {
 749         .cmd_rcgr = 0x1904,
 750         .mnd_width = 8,
 751         .hid_width = 5,
 752         .parent_map = gcc_xo_gpll0_map,
 753         .freq_tbl = ftbl_gp1_clk_src,
 754         .clkr.hw.init = &(struct clk_init_data)
 755         {
 756                 .name = "gp1_clk_src",
 757                 .parent_names = gcc_xo_gpll0,
 758                 .num_parents = 2,
 759                 .ops = &clk_rcg2_ops,
 760         },
 761 };
 762
 763 static struct freq_tbl ftbl_gp2_clk_src[] = {
 764         F(19200000, P_XO, 1, 0, 0),
 765         F(100000000, P_GPLL0, 6, 0, 0),
 766         F(200000000, P_GPLL0, 3, 0, 0),
 767         { }
 768 };
 769
 770 static struct clk_rcg2 gp2_clk_src = {
 771         .cmd_rcgr = 0x1944,
 772         .mnd_width = 8,
 773         .hid_width = 5,
 774         .parent_map = gcc_xo_gpll0_map,
 775         .freq_tbl = ftbl_gp2_clk_src,
 776         .clkr.hw.init = &(struct clk_init_data)
 777         {
 778                 .name = "gp2_clk_src",
 779                 .parent_names = gcc_xo_gpll0,
 780                 .num_parents = 2,
 781                 .ops = &clk_rcg2_ops,
 782         },
 783 };
 784
 785 static struct freq_tbl ftbl_gp3_clk_src[] = {
 786         F(19200000, P_XO, 1, 0, 0),
 787         F(100000000, P_GPLL0, 6, 0, 0),
 788         F(200000000, P_GPLL0, 3, 0, 0),
 789         { }
 790 };
 791
 792 static struct clk_rcg2 gp3_clk_src = {
 793         .cmd_rcgr = 0x1984,
 794         .mnd_width = 8,
 795         .hid_width = 5,
 796         .parent_map = gcc_xo_gpll0_map,
 797         .freq_tbl = ftbl_gp3_clk_src,
 798         .clkr.hw.init = &(struct clk_init_data)
 799         {
 800                 .name = "gp3_clk_src",
 801                 .parent_names = gcc_xo_gpll0,
 802                 .num_parents = 2,
 803                 .ops = &clk_rcg2_ops,
 804         },
 805 };
 806
 807 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 808         F(1011000, P_XO, 1, 1, 19),
 809         { }
 810 };
 811
 812 static struct clk_rcg2 pcie_0_aux_clk_src = {
 813         .cmd_rcgr = 0x1b00,
 814         .mnd_width = 8,
 815         .hid_width = 5,
 816         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 817         .clkr.hw.init = &(struct clk_init_data)
 818         {
 819                 .name = "pcie_0_aux_clk_src",
 820                 .parent_names = (const char *[]) { "xo" },
 821                 .num_parents = 1,
 822                 .ops = &clk_rcg2_ops,
 823         },
 824 };
 825
 826 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
 827         F(125000000, P_XO, 1, 0, 0),
 828         { }
 829 };
 830
 831 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 832         .cmd_rcgr = 0x1adc,
 833         .hid_width = 5,
 834         .freq_tbl = ftbl_pcie_pipe_clk_src,
 835         .clkr.hw.init = &(struct clk_init_data)
 836         {
 837                 .name = "pcie_0_pipe_clk_src",
 838                 .parent_names = (const char *[]) { "xo" },
 839                 .num_parents = 1,
 840                 .ops = &clk_rcg2_ops,
 841         },
 842 };
 843
 844 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
 845         F(1011000, P_XO, 1, 1, 19),
 846         { }
 847 };
 848
 849 static struct clk_rcg2 pcie_1_aux_clk_src = {
 850         .cmd_rcgr = 0x1b80,
 851         .mnd_width = 8,
 852         .hid_width = 5,
 853         .freq_tbl = ftbl_pcie_1_aux_clk_src,
 854         .clkr.hw.init = &(struct clk_init_data)
 855         {
 856                 .name = "pcie_1_aux_clk_src",
 857                 .parent_names = (const char *[]) { "xo" },
 858                 .num_parents = 1,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static struct clk_rcg2 pcie_1_pipe_clk_src = {
 864         .cmd_rcgr = 0x1b5c,
 865         .hid_width = 5,
 866         .freq_tbl = ftbl_pcie_pipe_clk_src,
 867         .clkr.hw.init = &(struct clk_init_data)
 868         {
 869                 .name = "pcie_1_pipe_clk_src",
 870                 .parent_names = (const char *[]) { "xo" },
 871                 .num_parents = 1,
 872                 .ops = &clk_rcg2_ops,
 873         },
 874 };
 875
 876 static struct freq_tbl ftbl_pdm2_clk_src[] = {
 877         F(60000000, P_GPLL0, 10, 0, 0),
 878         { }
 879 };
 880
 881 static struct clk_rcg2 pdm2_clk_src = {
 882         .cmd_rcgr = 0x0cd0,
 883         .hid_width = 5,
 884         .parent_map = gcc_xo_gpll0_map,
 885         .freq_tbl = ftbl_pdm2_clk_src,
 886         .clkr.hw.init = &(struct clk_init_data)
 887         {
 888                 .name = "pdm2_clk_src",
 889                 .parent_names = gcc_xo_gpll0,
 890                 .num_parents = 2,
 891                 .ops = &clk_rcg2_ops,
 892         },
 893 };
 894
 895 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 896         F(144000, P_XO, 16, 3, 25),
 897         F(400000, P_XO, 12, 1, 4),
 898         F(20000000, P_GPLL0, 15, 1, 2),
 899         F(25000000, P_GPLL0, 12, 1, 2),
 900         F(50000000, P_GPLL0, 12, 0, 0),
 901         F(100000000, P_GPLL0, 6, 0, 0),
 902         F(192000000, P_GPLL4, 2, 0, 0),
 903         F(384000000, P_GPLL4, 1, 0, 0),
 904         { }
 905 };
 906
 907 static struct clk_rcg2 sdcc1_apps_clk_src = {
 908         .cmd_rcgr = 0x04d0,
 909         .mnd_width = 8,
 910         .hid_width = 5,
 911         .parent_map = gcc_xo_gpll0_gpll4_map,
 912         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 913         .clkr.hw.init = &(struct clk_init_data)
 914         {
 915                 .name = "sdcc1_apps_clk_src",
 916                 .parent_names = gcc_xo_gpll0_gpll4,
 917                 .num_parents = 3,
 918                 .ops = &clk_rcg2_floor_ops,
 919         },
 920 };
 921
 922 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
 923         F(144000, P_XO, 16, 3, 25),
 924         F(400000, P_XO, 12, 1, 4),
 925         F(20000000, P_GPLL0, 15, 1, 2),
 926         F(25000000, P_GPLL0, 12, 1, 2),
 927         F(50000000, P_GPLL0, 12, 0, 0),
 928         F(100000000, P_GPLL0, 6, 0, 0),
 929         F(200000000, P_GPLL0, 3, 0, 0),
 930         { }
 931 };
 932
 933 static struct clk_rcg2 sdcc2_apps_clk_src = {
 934         .cmd_rcgr = 0x0510,
 935         .mnd_width = 8,
 936         .hid_width = 5,
 937         .parent_map = gcc_xo_gpll0_map,
 938         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 939         .clkr.hw.init = &(struct clk_init_data)
 940         {
 941                 .name = "sdcc2_apps_clk_src",
 942                 .parent_names = gcc_xo_gpll0,
 943                 .num_parents = 2,
 944                 .ops = &clk_rcg2_floor_ops,
 945         },
 946 };
 947
 948 static struct clk_rcg2 sdcc3_apps_clk_src = {
 949         .cmd_rcgr = 0x0550,
 950         .mnd_width = 8,
 951         .hid_width = 5,
 952         .parent_map = gcc_xo_gpll0_map,
 953         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 954         .clkr.hw.init = &(struct clk_init_data)
 955         {
 956                 .name = "sdcc3_apps_clk_src",
 957                 .parent_names = gcc_xo_gpll0,
 958                 .num_parents = 2,
 959                 .ops = &clk_rcg2_floor_ops,
 960         },
 961 };
 962
 963 static struct clk_rcg2 sdcc4_apps_clk_src = {
 964         .cmd_rcgr = 0x0590,
 965         .mnd_width = 8,
 966         .hid_width = 5,
 967         .parent_map = gcc_xo_gpll0_map,
 968         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 969         .clkr.hw.init = &(struct clk_init_data)
 970         {
 971                 .name = "sdcc4_apps_clk_src",
 972                 .parent_names = gcc_xo_gpll0,
 973                 .num_parents = 2,
 974                 .ops = &clk_rcg2_floor_ops,
 975         },
 976 };
 977
 978 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
 979         F(105500, P_XO, 1, 1, 182),
 980         { }
 981 };
 982
 983 static struct clk_rcg2 tsif_ref_clk_src = {
 984         .cmd_rcgr = 0x0d90,
 985         .mnd_width = 8,
 986         .hid_width = 5,
 987         .freq_tbl = ftbl_tsif_ref_clk_src,
 988         .clkr.hw.init = &(struct clk_init_data)
 989         {
 990                 .name = "tsif_ref_clk_src",
 991                 .parent_names = (const char *[]) { "xo" },
 992                 .num_parents = 1,
 993                 .ops = &clk_rcg2_ops,
 994         },
 995 };
 996
 997 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 998         F(19200000, P_XO, 1, 0, 0),
 999         F(60000000, P_GPLL0, 10, 0, 0),
1000         { }
1001 };
1002
1003 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1004         .cmd_rcgr = 0x03e8,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_gpll0_map,
1007         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1008         .clkr.hw.init = &(struct clk_init_data)
1009         {
1010                 .name = "usb30_mock_utmi_clk_src",
1011                 .parent_names = gcc_xo_gpll0,
1012                 .num_parents = 2,
1013                 .ops = &clk_rcg2_ops,
1014         },
1015 };
1016
1017 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1018         F(1200000, P_XO, 16, 0, 0),
1019         { }
1020 };
1021
1022 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1023         .cmd_rcgr = 0x1414,
1024         .hid_width = 5,
1025         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1026         .clkr.hw.init = &(struct clk_init_data)
1027         {
1028                 .name = "usb3_phy_aux_clk_src",
1029                 .parent_names = (const char *[]) { "xo" },
1030                 .num_parents = 1,
1031                 .ops = &clk_rcg2_ops,
1032         },
1033 };
1034
1035 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1036         F(75000000, P_GPLL0, 8, 0, 0),
1037         { }
1038 };
1039
1040 static struct clk_rcg2 usb_hs_system_clk_src = {
1041         .cmd_rcgr = 0x0490,
1042         .hid_width = 5,
1043         .parent_map = gcc_xo_gpll0_map,
1044         .freq_tbl = ftbl_usb_hs_system_clk_src,
1045         .clkr.hw.init = &(struct clk_init_data)
1046         {
1047                 .name = "usb_hs_system_clk_src",
1048                 .parent_names = gcc_xo_gpll0,
1049                 .num_parents = 2,
1050                 .ops = &clk_rcg2_ops,
1051         },
1052 };
1053
1054 static struct clk_branch gcc_blsp1_ahb_clk = {
1055         .halt_reg = 0x05c4,
1056         .halt_check = BRANCH_HALT_VOTED,
1057         .clkr = {
1058                 .enable_reg = 0x1484,
1059                 .enable_mask = BIT(17),
1060                 .hw.init = &(struct clk_init_data)
1061                 {
1062                         .name = "gcc_blsp1_ahb_clk",
1063                         .ops = &clk_branch2_ops,
1064                 },
1065         },
1066 };
1067
1068 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1069         .halt_reg = 0x0648,
1070         .clkr = {
1071                 .enable_reg = 0x0648,
1072                 .enable_mask = BIT(0),
1073                 .hw.init = &(struct clk_init_data)
1074                 {
1075                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1076                         .parent_names = (const char *[]) {
1077                                 "blsp1_qup1_i2c_apps_clk_src",
1078                         },
1079                         .num_parents = 1,
1080                         .flags = CLK_SET_RATE_PARENT,
1081                         .ops = &clk_branch2_ops,
1082                 },
1083         },
1084 };
1085
1086 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1087         .halt_reg = 0x0644,
1088         .clkr = {
1089                 .enable_reg = 0x0644,
1090                 .enable_mask = BIT(0),
1091                 .hw.init = &(struct clk_init_data)
1092                 {
1093                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1094                         .parent_names = (const char *[]) {
1095                                 "blsp1_qup1_spi_apps_clk_src",
1096                         },
1097                         .num_parents = 1,
1098                         .flags = CLK_SET_RATE_PARENT,
1099                         .ops = &clk_branch2_ops,
1100                 },
1101         },
1102 };
1103
1104 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1105         .halt_reg = 0x06c8,
1106         .clkr = {
1107                 .enable_reg = 0x06c8,
1108                 .enable_mask = BIT(0),
1109                 .hw.init = &(struct clk_init_data)
1110                 {
1111                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1112                         .parent_names = (const char *[]) {
1113                                 "blsp1_qup2_i2c_apps_clk_src",
1114                         },
1115                         .num_parents = 1,
1116                         .flags = CLK_SET_RATE_PARENT,
1117                         .ops = &clk_branch2_ops,
1118                 },
1119         },
1120 };
1121
1122 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1123         .halt_reg = 0x06c4,
1124         .clkr = {
1125                 .enable_reg = 0x06c4,
1126                 .enable_mask = BIT(0),
1127                 .hw.init = &(struct clk_init_data)
1128                 {
1129                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1130                         .parent_names = (const char *[]) {
1131                                 "blsp1_qup2_spi_apps_clk_src",
1132                         },
1133                         .num_parents = 1,
1134                         .flags = CLK_SET_RATE_PARENT,
1135                         .ops = &clk_branch2_ops,
1136                 },
1137         },
1138 };
1139
1140 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1141         .halt_reg = 0x0748,
1142         .clkr = {
1143                 .enable_reg = 0x0748,
1144                 .enable_mask = BIT(0),
1145                 .hw.init = &(struct clk_init_data)
1146                 {
1147                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1148                         .parent_names = (const char *[]) {
1149                                 "blsp1_qup3_i2c_apps_clk_src",
1150                         },
1151                         .num_parents = 1,
1152                         .flags = CLK_SET_RATE_PARENT,
1153                         .ops = &clk_branch2_ops,
1154                 },
1155         },
1156 };
1157
1158 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1159         .halt_reg = 0x0744,
1160         .clkr = {
1161                 .enable_reg = 0x0744,
1162                 .enable_mask = BIT(0),
1163                 .hw.init = &(struct clk_init_data)
1164                 {
1165                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1166                         .parent_names = (const char *[]) {
1167                                 "blsp1_qup3_spi_apps_clk_src",
1168                         },
1169                         .num_parents = 1,
1170                         .flags = CLK_SET_RATE_PARENT,
1171                         .ops = &clk_branch2_ops,
1172                 },
1173         },
1174 };
1175
1176 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1177         .halt_reg = 0x07c8,
1178         .clkr = {
1179                 .enable_reg = 0x07c8,
1180                 .enable_mask = BIT(0),
1181                 .hw.init = &(struct clk_init_data)
1182                 {
1183                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1184                         .parent_names = (const char *[]) {
1185                                 "blsp1_qup4_i2c_apps_clk_src",
1186                         },
1187                         .num_parents = 1,
1188                         .flags = CLK_SET_RATE_PARENT,
1189                         .ops = &clk_branch2_ops,
1190                 },
1191         },
1192 };
1193
1194 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1195         .halt_reg = 0x07c4,
1196         .clkr = {
1197                 .enable_reg = 0x07c4,
1198                 .enable_mask = BIT(0),
1199                 .hw.init = &(struct clk_init_data)
1200                 {
1201                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1202                         .parent_names = (const char *[]) {
1203                                 "blsp1_qup4_spi_apps_clk_src",
1204                         },
1205                         .num_parents = 1,
1206                         .flags = CLK_SET_RATE_PARENT,
1207                         .ops = &clk_branch2_ops,
1208                 },
1209         },
1210 };
1211
1212 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1213         .halt_reg = 0x0848,
1214         .clkr = {
1215                 .enable_reg = 0x0848,
1216                 .enable_mask = BIT(0),
1217                 .hw.init = &(struct clk_init_data)
1218                 {
1219                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1220                         .parent_names = (const char *[]) {
1221                                 "blsp1_qup5_i2c_apps_clk_src",
1222                         },
1223                         .num_parents = 1,
1224                         .flags = CLK_SET_RATE_PARENT,
1225                         .ops = &clk_branch2_ops,
1226                 },
1227         },
1228 };
1229
1230 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1231         .halt_reg = 0x0844,
1232         .clkr = {
1233                 .enable_reg = 0x0844,
1234                 .enable_mask = BIT(0),
1235                 .hw.init = &(struct clk_init_data)
1236                 {
1237                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1238                         .parent_names = (const char *[]) {
1239                                 "blsp1_qup5_spi_apps_clk_src",
1240                         },
1241                         .num_parents = 1,
1242                         .flags = CLK_SET_RATE_PARENT,
1243                         .ops = &clk_branch2_ops,
1244                 },
1245         },
1246 };
1247
1248 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1249         .halt_reg = 0x08c8,
1250         .clkr = {
1251                 .enable_reg = 0x08c8,
1252                 .enable_mask = BIT(0),
1253                 .hw.init = &(struct clk_init_data)
1254                 {
1255                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1256                         .parent_names = (const char *[]) {
1257                                 "blsp1_qup6_i2c_apps_clk_src",
1258                         },
1259                         .num_parents = 1,
1260                         .flags = CLK_SET_RATE_PARENT,
1261                         .ops = &clk_branch2_ops,
1262                 },
1263         },
1264 };
1265
1266 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1267         .halt_reg = 0x08c4,
1268         .clkr = {
1269                 .enable_reg = 0x08c4,
1270                 .enable_mask = BIT(0),
1271                 .hw.init = &(struct clk_init_data)
1272                 {
1273                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1274                         .parent_names = (const char *[]) {
1275                                 "blsp1_qup6_spi_apps_clk_src",
1276                         },
1277                         .num_parents = 1,
1278                         .flags = CLK_SET_RATE_PARENT,
1279                         .ops = &clk_branch2_ops,
1280                 },
1281         },
1282 };
1283
1284 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1285         .halt_reg = 0x0684,
1286         .clkr = {
1287                 .enable_reg = 0x0684,
1288                 .enable_mask = BIT(0),
1289                 .hw.init = &(struct clk_init_data)
1290                 {
1291                         .name = "gcc_blsp1_uart1_apps_clk",
1292                         .parent_names = (const char *[]) {
1293                                 "blsp1_uart1_apps_clk_src",
1294                         },
1295                         .num_parents = 1,
1296                         .flags = CLK_SET_RATE_PARENT,
1297                         .ops = &clk_branch2_ops,
1298                 },
1299         },
1300 };
1301
1302 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1303         .halt_reg = 0x0704,
1304         .clkr = {
1305                 .enable_reg = 0x0704,
1306                 .enable_mask = BIT(0),
1307                 .hw.init = &(struct clk_init_data)
1308                 {
1309                         .name = "gcc_blsp1_uart2_apps_clk",
1310                         .parent_names = (const char *[]) {
1311                                 "blsp1_uart2_apps_clk_src",
1312                         },
1313                         .num_parents = 1,
1314                         .flags = CLK_SET_RATE_PARENT,
1315                         .ops = &clk_branch2_ops,
1316                 },
1317         },
1318 };
1319
1320 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1321         .halt_reg = 0x0784,
1322         .clkr = {
1323                 .enable_reg = 0x0784,
1324                 .enable_mask = BIT(0),
1325                 .hw.init = &(struct clk_init_data)
1326                 {
1327                         .name = "gcc_blsp1_uart3_apps_clk",
1328                         .parent_names = (const char *[]) {
1329                                 "blsp1_uart3_apps_clk_src",
1330                         },
1331                         .num_parents = 1,
1332                         .flags = CLK_SET_RATE_PARENT,
1333                         .ops = &clk_branch2_ops,
1334                 },
1335         },
1336 };
1337
1338 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1339         .halt_reg = 0x0804,
1340         .clkr = {
1341                 .enable_reg = 0x0804,
1342                 .enable_mask = BIT(0),
1343                 .hw.init = &(struct clk_init_data)
1344                 {
1345                         .name = "gcc_blsp1_uart4_apps_clk",
1346                         .parent_names = (const char *[]) {
1347                                 "blsp1_uart4_apps_clk_src",
1348                         },
1349                         .num_parents = 1,
1350                         .flags = CLK_SET_RATE_PARENT,
1351                         .ops = &clk_branch2_ops,
1352                 },
1353         },
1354 };
1355
1356 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1357         .halt_reg = 0x0884,
1358         .clkr = {
1359                 .enable_reg = 0x0884,
1360                 .enable_mask = BIT(0),
1361                 .hw.init = &(struct clk_init_data)
1362                 {
1363                         .name = "gcc_blsp1_uart5_apps_clk",
1364                         .parent_names = (const char *[]) {
1365                                 "blsp1_uart5_apps_clk_src",
1366                         },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1375         .halt_reg = 0x0904,
1376         .clkr = {
1377                 .enable_reg = 0x0904,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data)
1380                 {
1381                         .name = "gcc_blsp1_uart6_apps_clk",
1382                         .parent_names = (const char *[]) {
1383                                 "blsp1_uart6_apps_clk_src",
1384                         },
1385                         .num_parents = 1,
1386                         .flags = CLK_SET_RATE_PARENT,
1387                         .ops = &clk_branch2_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch gcc_blsp2_ahb_clk = {
1393         .halt_reg = 0x0944,
1394         .halt_check = BRANCH_HALT_VOTED,
1395         .clkr = {
1396                 .enable_reg = 0x1484,
1397                 .enable_mask = BIT(15),
1398                 .hw.init = &(struct clk_init_data)
1399                 {
1400                         .name = "gcc_blsp2_ahb_clk",
1401                         .ops = &clk_branch2_ops,
1402                 },
1403         },
1404 };
1405
1406 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1407         .halt_reg = 0x0988,
1408         .clkr = {
1409                 .enable_reg = 0x0988,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data)
1412                 {
1413                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1414                         .parent_names = (const char *[]) {
1415                                 "blsp2_qup1_i2c_apps_clk_src",
1416                         },
1417                         .num_parents = 1,
1418                         .flags = CLK_SET_RATE_PARENT,
1419                         .ops = &clk_branch2_ops,
1420                 },
1421         },
1422 };
1423
1424 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1425         .halt_reg = 0x0984,
1426         .clkr = {
1427                 .enable_reg = 0x0984,
1428                 .enable_mask = BIT(0),
1429                 .hw.init = &(struct clk_init_data)
1430                 {
1431                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1432                         .parent_names = (const char *[]) {
1433                                 "blsp2_qup1_spi_apps_clk_src",
1434                         },
1435                         .num_parents = 1,
1436                         .flags = CLK_SET_RATE_PARENT,
1437                         .ops = &clk_branch2_ops,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1443         .halt_reg = 0x0a08,
1444         .clkr = {
1445                 .enable_reg = 0x0a08,
1446                 .enable_mask = BIT(0),
1447                 .hw.init = &(struct clk_init_data)
1448                 {
1449                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1450                         .parent_names = (const char *[]) {
1451                                 "blsp2_qup2_i2c_apps_clk_src",
1452                         },
1453                         .num_parents = 1,
1454                         .flags = CLK_SET_RATE_PARENT,
1455                         .ops = &clk_branch2_ops,
1456                 },
1457         },
1458 };
1459
1460 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1461         .halt_reg = 0x0a04,
1462         .clkr = {
1463                 .enable_reg = 0x0a04,
1464                 .enable_mask = BIT(0),
1465                 .hw.init = &(struct clk_init_data)
1466                 {
1467                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1468                         .parent_names = (const char *[]) {
1469                                 "blsp2_qup2_spi_apps_clk_src",
1470                         },
1471                         .num_parents = 1,
1472                         .flags = CLK_SET_RATE_PARENT,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1479         .halt_reg = 0x0a88,
1480         .clkr = {
1481                 .enable_reg = 0x0a88,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data)
1484                 {
1485                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1486                         .parent_names = (const char *[]) {
1487                                 "blsp2_qup3_i2c_apps_clk_src",
1488                         },
1489                         .num_parents = 1,
1490                         .flags = CLK_SET_RATE_PARENT,
1491                         .ops = &clk_branch2_ops,
1492                 },
1493         },
1494 };
1495
1496 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1497         .halt_reg = 0x0a84,
1498         .clkr = {
1499                 .enable_reg = 0x0a84,
1500                 .enable_mask = BIT(0),
1501                 .hw.init = &(struct clk_init_data)
1502                 {
1503                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1504                         .parent_names = (const char *[]) {
1505                                 "blsp2_qup3_spi_apps_clk_src",
1506                         },
1507                         .num_parents = 1,
1508                         .flags = CLK_SET_RATE_PARENT,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1515         .halt_reg = 0x0b08,
1516         .clkr = {
1517                 .enable_reg = 0x0b08,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data)
1520                 {
1521                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1522                         .parent_names = (const char *[]) {
1523                                 "blsp2_qup4_i2c_apps_clk_src",
1524                         },
1525                         .num_parents = 1,
1526                         .flags = CLK_SET_RATE_PARENT,
1527                         .ops = &clk_branch2_ops,
1528                 },
1529         },
1530 };
1531
1532 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1533         .halt_reg = 0x0b04,
1534         .clkr = {
1535                 .enable_reg = 0x0b04,
1536                 .enable_mask = BIT(0),
1537                 .hw.init = &(struct clk_init_data)
1538                 {
1539                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1540                         .parent_names = (const char *[]) {
1541                                 "blsp2_qup4_spi_apps_clk_src",
1542                         },
1543                         .num_parents = 1,
1544                         .flags = CLK_SET_RATE_PARENT,
1545                         .ops = &clk_branch2_ops,
1546                 },
1547         },
1548 };
1549
1550 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1551         .halt_reg = 0x0b88,
1552         .clkr = {
1553                 .enable_reg = 0x0b88,
1554                 .enable_mask = BIT(0),
1555                 .hw.init = &(struct clk_init_data)
1556                 {
1557                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1558                         .parent_names = (const char *[]) {
1559                                 "blsp2_qup5_i2c_apps_clk_src",
1560                         },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1569         .halt_reg = 0x0b84,
1570         .clkr = {
1571                 .enable_reg = 0x0b84,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data)
1574                 {
1575                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1576                         .parent_names = (const char *[]) {
1577                                 "blsp2_qup5_spi_apps_clk_src",
1578                         },
1579                         .num_parents = 1,
1580                         .flags = CLK_SET_RATE_PARENT,
1581                         .ops = &clk_branch2_ops,
1582                 },
1583         },
1584 };
1585
1586 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1587         .halt_reg = 0x0c08,
1588         .clkr = {
1589                 .enable_reg = 0x0c08,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data)
1592                 {
1593                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1594                         .parent_names = (const char *[]) {
1595                                 "blsp2_qup6_i2c_apps_clk_src",
1596                         },
1597                         .num_parents = 1,
1598                         .flags = CLK_SET_RATE_PARENT,
1599                         .ops = &clk_branch2_ops,
1600                 },
1601         },
1602 };
1603
1604 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1605         .halt_reg = 0x0c04,
1606         .clkr = {
1607                 .enable_reg = 0x0c04,
1608                 .enable_mask = BIT(0),
1609                 .hw.init = &(struct clk_init_data)
1610                 {
1611                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1612                         .parent_names = (const char *[]) {
1613                                 "blsp2_qup6_spi_apps_clk_src",
1614                         },
1615                         .num_parents = 1,
1616                         .flags = CLK_SET_RATE_PARENT,
1617                         .ops = &clk_branch2_ops,
1618                 },
1619         },
1620 };
1621
1622 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1623         .halt_reg = 0x09c4,
1624         .clkr = {
1625                 .enable_reg = 0x09c4,
1626                 .enable_mask = BIT(0),
1627                 .hw.init = &(struct clk_init_data)
1628                 {
1629                         .name = "gcc_blsp2_uart1_apps_clk",
1630                         .parent_names = (const char *[]) {
1631                                 "blsp2_uart1_apps_clk_src",
1632                         },
1633                         .num_parents = 1,
1634                         .flags = CLK_SET_RATE_PARENT,
1635                         .ops = &clk_branch2_ops,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1641         .halt_reg = 0x0a44,
1642         .clkr = {
1643                 .enable_reg = 0x0a44,
1644                 .enable_mask = BIT(0),
1645                 .hw.init = &(struct clk_init_data)
1646                 {
1647                         .name = "gcc_blsp2_uart2_apps_clk",
1648                         .parent_names = (const char *[]) {
1649                                 "blsp2_uart2_apps_clk_src",
1650                         },
1651                         .num_parents = 1,
1652                         .flags = CLK_SET_RATE_PARENT,
1653                         .ops = &clk_branch2_ops,
1654                 },
1655         },
1656 };
1657
1658 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1659         .halt_reg = 0x0ac4,
1660         .clkr = {
1661                 .enable_reg = 0x0ac4,
1662                 .enable_mask = BIT(0),
1663                 .hw.init = &(struct clk_init_data)
1664                 {
1665                         .name = "gcc_blsp2_uart3_apps_clk",
1666                         .parent_names = (const char *[]) {
1667                                 "blsp2_uart3_apps_clk_src",
1668                         },
1669                         .num_parents = 1,
1670                         .flags = CLK_SET_RATE_PARENT,
1671                         .ops = &clk_branch2_ops,
1672                 },
1673         },
1674 };
1675
1676 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1677         .halt_reg = 0x0b44,
1678         .clkr = {
1679                 .enable_reg = 0x0b44,
1680                 .enable_mask = BIT(0),
1681                 .hw.init = &(struct clk_init_data)
1682                 {
1683                         .name = "gcc_blsp2_uart4_apps_clk",
1684                         .parent_names = (const char *[]) {
1685                                 "blsp2_uart4_apps_clk_src",
1686                         },
1687                         .num_parents = 1,
1688                         .flags = CLK_SET_RATE_PARENT,
1689                         .ops = &clk_branch2_ops,
1690                 },
1691         },
1692 };
1693
1694 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1695         .halt_reg = 0x0bc4,
1696         .clkr = {
1697                 .enable_reg = 0x0bc4,
1698                 .enable_mask = BIT(0),
1699                 .hw.init = &(struct clk_init_data)
1700                 {
1701                         .name = "gcc_blsp2_uart5_apps_clk",
1702                         .parent_names = (const char *[]) {
1703                                 "blsp2_uart5_apps_clk_src",
1704                         },
1705                         .num_parents = 1,
1706                         .flags = CLK_SET_RATE_PARENT,
1707                         .ops = &clk_branch2_ops,
1708                 },
1709         },
1710 };
1711
1712 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1713         .halt_reg = 0x0c44,
1714         .clkr = {
1715                 .enable_reg = 0x0c44,
1716                 .enable_mask = BIT(0),
1717                 .hw.init = &(struct clk_init_data)
1718                 {
1719                         .name = "gcc_blsp2_uart6_apps_clk",
1720                         .parent_names = (const char *[]) {
1721                                 "blsp2_uart6_apps_clk_src",
1722                         },
1723                         .num_parents = 1,
1724                         .flags = CLK_SET_RATE_PARENT,
1725                         .ops = &clk_branch2_ops,
1726                 },
1727         },
1728 };
1729
1730 static struct clk_branch gcc_gp1_clk = {
1731         .halt_reg = 0x1900,
1732         .clkr = {
1733                 .enable_reg = 0x1900,
1734                 .enable_mask = BIT(0),
1735                 .hw.init = &(struct clk_init_data)
1736                 {
1737                         .name = "gcc_gp1_clk",
1738                         .parent_names = (const char *[]) {
1739                                 "gp1_clk_src",
1740                         },
1741                         .num_parents = 1,
1742                         .flags = CLK_SET_RATE_PARENT,
1743                         .ops = &clk_branch2_ops,
1744                 },
1745         },
1746 };
1747
1748 static struct clk_branch gcc_gp2_clk = {
1749         .halt_reg = 0x1940,
1750         .clkr = {
1751                 .enable_reg = 0x1940,
1752                 .enable_mask = BIT(0),
1753                 .hw.init = &(struct clk_init_data)
1754                 {
1755                         .name = "gcc_gp2_clk",
1756                         .parent_names = (const char *[]) {
1757                                 "gp2_clk_src",
1758                         },
1759                         .num_parents = 1,
1760                         .flags = CLK_SET_RATE_PARENT,
1761                         .ops = &clk_branch2_ops,
1762                 },
1763         },
1764 };
1765
1766 static struct clk_branch gcc_gp3_clk = {
1767         .halt_reg = 0x1980,
1768         .clkr = {
1769                 .enable_reg = 0x1980,
1770                 .enable_mask = BIT(0),
1771                 .hw.init = &(struct clk_init_data)
1772                 {
1773                         .name = "gcc_gp3_clk",
1774                         .parent_names = (const char *[]) {
1775                                 "gp3_clk_src",
1776                         },
1777                         .num_parents = 1,
1778                         .flags = CLK_SET_RATE_PARENT,
1779                         .ops = &clk_branch2_ops,
1780                 },
1781         },
1782 };
1783
1784 static struct clk_branch gcc_pcie_0_aux_clk = {
1785         .halt_reg = 0x1ad4,
1786         .clkr = {
1787                 .enable_reg = 0x1ad4,
1788                 .enable_mask = BIT(0),
1789                 .hw.init = &(struct clk_init_data)
1790                 {
1791                         .name = "gcc_pcie_0_aux_clk",
1792                         .parent_names = (const char *[]) {
1793                                 "pcie_0_aux_clk_src",
1794                         },
1795                         .num_parents = 1,
1796                         .flags = CLK_SET_RATE_PARENT,
1797                         .ops = &clk_branch2_ops,
1798                 },
1799         },
1800 };
1801
1802 static struct clk_branch gcc_pcie_0_pipe_clk = {
1803         .halt_reg = 0x1ad8,
1804         .halt_check = BRANCH_HALT_DELAY,
1805         .clkr = {
1806                 .enable_reg = 0x1ad8,
1807                 .enable_mask = BIT(0),
1808                 .hw.init = &(struct clk_init_data)
1809                 {
1810                         .name = "gcc_pcie_0_pipe_clk",
1811                         .parent_names = (const char *[]) {
1812                                 "pcie_0_pipe_clk_src",
1813                         },
1814                         .num_parents = 1,
1815                         .flags = CLK_SET_RATE_PARENT,
1816                         .ops = &clk_branch2_ops,
1817                 },
1818         },
1819 };
1820
1821 static struct clk_branch gcc_pcie_1_aux_clk = {
1822         .halt_reg = 0x1b54,
1823         .clkr = {
1824                 .enable_reg = 0x1b54,
1825                 .enable_mask = BIT(0),
1826                 .hw.init = &(struct clk_init_data)
1827                 {
1828                         .name = "gcc_pcie_1_aux_clk",
1829                         .parent_names = (const char *[]) {
1830                                 "pcie_1_aux_clk_src",
1831                         },
1832                         .num_parents = 1,
1833                         .flags = CLK_SET_RATE_PARENT,
1834                         .ops = &clk_branch2_ops,
1835                 },
1836         },
1837 };
1838
1839 static struct clk_branch gcc_pcie_1_pipe_clk = {
1840         .halt_reg = 0x1b58,
1841         .halt_check = BRANCH_HALT_DELAY,
1842         .clkr = {
1843                 .enable_reg = 0x1b58,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data)
1846                 {
1847                         .name = "gcc_pcie_1_pipe_clk",
1848                         .parent_names = (const char *[]) {
1849                                 "pcie_1_pipe_clk_src",
1850                         },
1851                         .num_parents = 1,
1852                         .flags = CLK_SET_RATE_PARENT,
1853                         .ops = &clk_branch2_ops,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch gcc_pdm2_clk = {
1859         .halt_reg = 0x0ccc,
1860         .clkr = {
1861                 .enable_reg = 0x0ccc,
1862                 .enable_mask = BIT(0),
1863                 .hw.init = &(struct clk_init_data)
1864                 {
1865                         .name = "gcc_pdm2_clk",
1866                         .parent_names = (const char *[]) {
1867                                 "pdm2_clk_src",
1868                         },
1869                         .num_parents = 1,
1870                         .flags = CLK_SET_RATE_PARENT,
1871                         .ops = &clk_branch2_ops,
1872                 },
1873         },
1874 };
1875
1876 static struct clk_branch gcc_sdcc1_apps_clk = {
1877         .halt_reg = 0x04c4,
1878         .clkr = {
1879                 .enable_reg = 0x04c4,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(struct clk_init_data)
1882                 {
1883                         .name = "gcc_sdcc1_apps_clk",
1884                         .parent_names = (const char *[]) {
1885                                 "sdcc1_apps_clk_src",
1886                         },
1887                         .num_parents = 1,
1888                         .flags = CLK_SET_RATE_PARENT,
1889                         .ops = &clk_branch2_ops,
1890                 },
1891         },
1892 };
1893
1894 static struct clk_branch gcc_sdcc1_ahb_clk = {
1895         .halt_reg = 0x04c8,
1896         .clkr = {
1897                 .enable_reg = 0x04c8,
1898                 .enable_mask = BIT(0),
1899                 .hw.init = &(struct clk_init_data)
1900                 {
1901                         .name = "gcc_sdcc1_ahb_clk",
1902                         .parent_names = (const char *[]){
1903                                 "periph_noc_clk_src",
1904                         },
1905                         .num_parents = 1,
1906                         .ops = &clk_branch2_ops,
1907                 },
1908         },
1909 };
1910
1911 static struct clk_branch gcc_sdcc2_apps_clk = {
1912         .halt_reg = 0x0504,
1913         .clkr = {
1914                 .enable_reg = 0x0504,
1915                 .enable_mask = BIT(0),
1916                 .hw.init = &(struct clk_init_data)
1917                 {
1918                         .name = "gcc_sdcc2_apps_clk",
1919                         .parent_names = (const char *[]) {
1920                                 "sdcc2_apps_clk_src",
1921                         },
1922                         .num_parents = 1,
1923                         .flags = CLK_SET_RATE_PARENT,
1924                         .ops = &clk_branch2_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch gcc_sdcc3_apps_clk = {
1930         .halt_reg = 0x0544,
1931         .clkr = {
1932                 .enable_reg = 0x0544,
1933                 .enable_mask = BIT(0),
1934                 .hw.init = &(struct clk_init_data)
1935                 {
1936                         .name = "gcc_sdcc3_apps_clk",
1937                         .parent_names = (const char *[]) {
1938                                 "sdcc3_apps_clk_src",
1939                         },
1940                         .num_parents = 1,
1941                         .flags = CLK_SET_RATE_PARENT,
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_sdcc4_apps_clk = {
1948         .halt_reg = 0x0584,
1949         .clkr = {
1950                 .enable_reg = 0x0584,
1951                 .enable_mask = BIT(0),
1952                 .hw.init = &(struct clk_init_data)
1953                 {
1954                         .name = "gcc_sdcc4_apps_clk",
1955                         .parent_names = (const char *[]) {
1956                                 "sdcc4_apps_clk_src",
1957                         },
1958                         .num_parents = 1,
1959                         .flags = CLK_SET_RATE_PARENT,
1960                         .ops = &clk_branch2_ops,
1961                 },
1962         },
1963 };
1964
1965 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1966         .halt_reg = 0x1d7c,
1967         .clkr = {
1968                 .enable_reg = 0x1d7c,
1969                 .enable_mask = BIT(0),
1970                 .hw.init = &(struct clk_init_data)
1971                 {
1972                         .name = "gcc_sys_noc_ufs_axi_clk",
1973                         .parent_names = (const char *[]) {
1974                                 "ufs_axi_clk_src",
1975                         },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1984         .halt_reg = 0x03fc,
1985         .clkr = {
1986                 .enable_reg = 0x03fc,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data)
1989                 {
1990                         .name = "gcc_sys_noc_usb3_axi_clk",
1991                         .parent_names = (const char *[]) {
1992                                 "usb30_master_clk_src",
1993                         },
1994                         .num_parents = 1,
1995                         .flags = CLK_SET_RATE_PARENT,
1996                         .ops = &clk_branch2_ops,
1997                 },
1998         },
1999 };
2000
2001 static struct clk_branch gcc_tsif_ref_clk = {
2002         .halt_reg = 0x0d88,
2003         .clkr = {
2004                 .enable_reg = 0x0d88,
2005                 .enable_mask = BIT(0),
2006                 .hw.init = &(struct clk_init_data)
2007                 {
2008                         .name = "gcc_tsif_ref_clk",
2009                         .parent_names = (const char *[]) {
2010                                 "tsif_ref_clk_src",
2011                         },
2012                         .num_parents = 1,
2013                         .flags = CLK_SET_RATE_PARENT,
2014                         .ops = &clk_branch2_ops,
2015                 },
2016         },
2017 };
2018
2019 static struct clk_branch gcc_ufs_axi_clk = {
2020         .halt_reg = 0x1d48,
2021         .clkr = {
2022                 .enable_reg = 0x1d48,
2023                 .enable_mask = BIT(0),
2024                 .hw.init = &(struct clk_init_data)
2025                 {
2026                         .name = "gcc_ufs_axi_clk",
2027                         .parent_names = (const char *[]) {
2028                                 "ufs_axi_clk_src",
2029                         },
2030                         .num_parents = 1,
2031                         .flags = CLK_SET_RATE_PARENT,
2032                         .ops = &clk_branch2_ops,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2038         .halt_reg = 0x1d54,
2039         .clkr = {
2040                 .enable_reg = 0x1d54,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data)
2043                 {
2044                         .name = "gcc_ufs_rx_cfg_clk",
2045                         .parent_names = (const char *[]) {
2046                                 "ufs_axi_clk_src",
2047                         },
2048                         .num_parents = 1,
2049                         .flags = CLK_SET_RATE_PARENT,
2050                         .ops = &clk_branch2_ops,
2051                 },
2052         },
2053 };
2054
2055 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2056         .halt_reg = 0x1d50,
2057         .clkr = {
2058                 .enable_reg = 0x1d50,
2059                 .enable_mask = BIT(0),
2060                 .hw.init = &(struct clk_init_data)
2061                 {
2062                         .name = "gcc_ufs_tx_cfg_clk",
2063                         .parent_names = (const char *[]) {
2064                                 "ufs_axi_clk_src",
2065                         },
2066                         .num_parents = 1,
2067                         .flags = CLK_SET_RATE_PARENT,
2068                         .ops = &clk_branch2_ops,
2069                 },
2070         },
2071 };
2072
2073 static struct clk_branch gcc_usb30_master_clk = {
2074         .halt_reg = 0x03c8,
2075         .clkr = {
2076                 .enable_reg = 0x03c8,
2077                 .enable_mask = BIT(0),
2078                 .hw.init = &(struct clk_init_data)
2079                 {
2080                         .name = "gcc_usb30_master_clk",
2081                         .parent_names = (const char *[]) {
2082                                 "usb30_master_clk_src",
2083                         },
2084                         .num_parents = 1,
2085                         .flags = CLK_SET_RATE_PARENT,
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2092         .halt_reg = 0x03d0,
2093         .clkr = {
2094                 .enable_reg = 0x03d0,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data)
2097                 {
2098                         .name = "gcc_usb30_mock_utmi_clk",
2099                         .parent_names = (const char *[]) {
2100                                 "usb30_mock_utmi_clk_src",
2101                         },
2102                         .num_parents = 1,
2103                         .flags = CLK_SET_RATE_PARENT,
2104                         .ops = &clk_branch2_ops,
2105                 },
2106         },
2107 };
2108
2109 static struct clk_branch gcc_usb3_phy_aux_clk = {
2110         .halt_reg = 0x1408,
2111         .clkr = {
2112                 .enable_reg = 0x1408,
2113                 .enable_mask = BIT(0),
2114                 .hw.init = &(struct clk_init_data)
2115                 {
2116                         .name = "gcc_usb3_phy_aux_clk",
2117                         .parent_names = (const char *[]) {
2118                                 "usb3_phy_aux_clk_src",
2119                         },
2120                         .num_parents = 1,
2121                         .flags = CLK_SET_RATE_PARENT,
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_usb_hs_system_clk = {
2128         .halt_reg = 0x0484,
2129         .clkr = {
2130                 .enable_reg = 0x0484,
2131                 .enable_mask = BIT(0),
2132                 .hw.init = &(struct clk_init_data)
2133                 {
2134                         .name = "gcc_usb_hs_system_clk",
2135                         .parent_names = (const char *[]) {
2136                                 "usb_hs_system_clk_src",
2137                         },
2138                         .num_parents = 1,
2139                         .flags = CLK_SET_RATE_PARENT,
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_regmap *gcc_msm8994_clocks[] = {
2146         [GPLL0_EARLY] = &gpll0_early.clkr,
2147         [GPLL0] = &gpll0.clkr,
2148         [GPLL4_EARLY] = &gpll4_early.clkr,
2149         [GPLL4] = &gpll4.clkr,
2150         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2151         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2152         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2153         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2154         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2155         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2156         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2157         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2158         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2159         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2160         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2161         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2162         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2163         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2164         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2165         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2166         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2167         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2168         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2169         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2170         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2171         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2172         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2173         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2174         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2175         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2176         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2177         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2178         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2179         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2180         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2181         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2182         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2183         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2184         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2185         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2186         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2187         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2188         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2189         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2190         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2191         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2192         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2193         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2194         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2195         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2196         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2197         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2198         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2199         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2200         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2201         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2202         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2203         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2204         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2205         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2206         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2207         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2208         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2209         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2210         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2211         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2212         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2213         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2214         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2215         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2216         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2217         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2218         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2219         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2220         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2221         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2222         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2223         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2224         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2225         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2226         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2227         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2228         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2229         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2230         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2231         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2232         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2233         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2234         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2235         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2236         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2237         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2238         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2239         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2240         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2241         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2242         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2243         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2244         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2245         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2246         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2247         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2248         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2249         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2250         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2251         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2252         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2253         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2254         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2255         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2256         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2257         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2258         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2259         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2260         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2261         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2262         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2263         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2264         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2265 };
2266
2267 static const struct regmap_config gcc_msm8994_regmap_config = {
2268         .reg_bits       = 32,
2269         .reg_stride     = 4,
2270         .val_bits       = 32,
2271         .max_register   = 0x2000,
2272         .fast_io        = true,
2273 };
2274
2275 static const struct qcom_cc_desc gcc_msm8994_desc = {
2276         .config = &gcc_msm8994_regmap_config,
2277         .clks = gcc_msm8994_clocks,
2278         .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2279 };
2280
2281 static const struct of_device_id gcc_msm8994_match_table[] = {
2282         { .compatible = "qcom,gcc-msm8994" },
2283         {}
2284 };
2285 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2286
2287 static int gcc_msm8994_probe(struct platform_device *pdev)
2288 {
2289         struct device *dev = &pdev->dev;
2290         struct clk *clk;
2291
2292         clk = devm_clk_register(dev, &xo.hw);
2293         if (IS_ERR(clk))
2294                 return PTR_ERR(clk);
2295
2296         return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2297 }
2298
2299 static struct platform_driver gcc_msm8994_driver = {
2300         .probe          = gcc_msm8994_probe,
2301         .driver         = {
2302                 .name   = "gcc-msm8994",
2303                 .of_match_table = gcc_msm8994_match_table,
2304         },
2305 };
2306
2307 static int __init gcc_msm8994_init(void)
2308 {
2309         return platform_driver_register(&gcc_msm8994_driver);
2310 }
2311 core_initcall(gcc_msm8994_init);
2312
2313 static void __exit gcc_msm8994_exit(void)
2314 {
2315         platform_driver_unregister(&gcc_msm8994_driver);
2316 }
2317 module_exit(gcc_msm8994_exit);
2318
2319 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2320 MODULE_LICENSE("GPL v2");
2321 MODULE_ALIAS("platform:gcc-msm8994");