drivers/clk/qcom/gcc-msm8939.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2020 Linaro Limited
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_AUX,
  32         P_BIMC,
  33         P_GPLL1,
  34         P_GPLL1_AUX,
  35         P_GPLL2,
  36         P_GPLL2_AUX,
  37         P_GPLL3,
  38         P_GPLL3_AUX,
  39         P_GPLL4,
  40         P_GPLL5,
  41         P_GPLL5_AUX,
  42         P_GPLL5_EARLY,
  43         P_GPLL6,
  44         P_GPLL6_AUX,
  45         P_SLEEP_CLK,
  46         P_DSI0_PHYPLL_BYTE,
  47         P_DSI0_PHYPLL_DSI,
  48         P_EXT_PRI_I2S,
  49         P_EXT_SEC_I2S,
  50         P_EXT_MCLK,
  51 };
  52
  53 static struct clk_pll gpll0 = {
  54         .l_reg = 0x21004,
  55         .m_reg = 0x21008,
  56         .n_reg = 0x2100c,
  57         .config_reg = 0x21010,
  58         .mode_reg = 0x21000,
  59         .status_reg = 0x2101c,
  60         .status_bit = 17,
  61         .clkr.hw.init = &(struct clk_init_data){
  62                 .name = "gpll0",
  63                 .parent_data = &(const struct clk_parent_data) {
  64                         .fw_name = "xo",
  65                 },
  66                 .num_parents = 1,
  67                 .ops = &clk_pll_ops,
  68         },
  69 };
  70
  71 static struct clk_regmap gpll0_vote = {
  72         .enable_reg = 0x45000,
  73         .enable_mask = BIT(0),
  74         .hw.init = &(struct clk_init_data){
  75                 .name = "gpll0_vote",
  76                 .parent_data = &(const struct clk_parent_data) {
  77                         .hw = &gpll0.clkr.hw,
  78                 },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_vote_ops,
  81         },
  82 };
  83
  84 static struct clk_pll gpll1 = {
  85         .l_reg = 0x20004,
  86         .m_reg = 0x20008,
  87         .n_reg = 0x2000c,
  88         .config_reg = 0x20010,
  89         .mode_reg = 0x20000,
  90         .status_reg = 0x2001c,
  91         .status_bit = 17,
  92         .clkr.hw.init = &(struct clk_init_data){
  93                 .name = "gpll1",
  94                 .parent_data = &(const struct clk_parent_data) {
  95                         .fw_name = "xo",
  96                 },
  97                 .num_parents = 1,
  98                 .ops = &clk_pll_ops,
  99         },
 100 };
 101
 102 static struct clk_regmap gpll1_vote = {
 103         .enable_reg = 0x45000,
 104         .enable_mask = BIT(1),
 105         .hw.init = &(struct clk_init_data){
 106                 .name = "gpll1_vote",
 107                 .parent_data = &(const struct clk_parent_data) {
 108                         .hw = &gpll1.clkr.hw,
 109                 },
 110                 .num_parents = 1,
 111                 .ops = &clk_pll_vote_ops,
 112         },
 113 };
 114
 115 static struct clk_pll gpll2 = {
 116         .l_reg = 0x4a004,
 117         .m_reg = 0x4a008,
 118         .n_reg = 0x4a00c,
 119         .config_reg = 0x4a010,
 120         .mode_reg = 0x4a000,
 121         .status_reg = 0x4a01c,
 122         .status_bit = 17,
 123         .clkr.hw.init = &(struct clk_init_data){
 124                 .name = "gpll2",
 125                 .parent_data = &(const struct clk_parent_data) {
 126                         .fw_name = "xo",
 127                 },
 128                 .num_parents = 1,
 129                 .ops = &clk_pll_ops,
 130         },
 131 };
 132
 133 static struct clk_regmap gpll2_vote = {
 134         .enable_reg = 0x45000,
 135         .enable_mask = BIT(2),
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "gpll2_vote",
 138                 .parent_data = &(const struct clk_parent_data) {
 139                         .hw = &gpll2.clkr.hw,
 140                 },
 141                 .num_parents = 1,
 142                 .ops = &clk_pll_vote_ops,
 143         },
 144 };
 145
 146 static struct clk_pll bimc_pll = {
 147         .l_reg = 0x23004,
 148         .m_reg = 0x23008,
 149         .n_reg = 0x2300c,
 150         .config_reg = 0x23010,
 151         .mode_reg = 0x23000,
 152         .status_reg = 0x2301c,
 153         .status_bit = 17,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "bimc_pll",
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xo",
 158                 },
 159                 .num_parents = 1,
 160                 .ops = &clk_pll_ops,
 161         },
 162 };
 163
 164 static struct clk_regmap bimc_pll_vote = {
 165         .enable_reg = 0x45000,
 166         .enable_mask = BIT(3),
 167         .hw.init = &(struct clk_init_data){
 168                 .name = "bimc_pll_vote",
 169                 .parent_data = &(const struct clk_parent_data) {
 170                         .hw = &bimc_pll.clkr.hw,
 171                 },
 172                 .num_parents = 1,
 173                 .ops = &clk_pll_vote_ops,
 174         },
 175 };
 176
 177 static struct clk_pll gpll3 = {
 178         .l_reg = 0x22004,
 179         .m_reg = 0x22008,
 180         .n_reg = 0x2200c,
 181         .config_reg = 0x22010,
 182         .mode_reg = 0x22000,
 183         .status_reg = 0x2201c,
 184         .status_bit = 17,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "gpll3",
 187                 .parent_data = &(const struct clk_parent_data) {
 188                         .fw_name = "xo",
 189                 },
 190                 .num_parents = 1,
 191                 .ops = &clk_pll_ops,
 192         },
 193 };
 194
 195 static struct clk_regmap gpll3_vote = {
 196         .enable_reg = 0x45000,
 197         .enable_mask = BIT(4),
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "gpll3_vote",
 200                 .parent_data = &(const struct clk_parent_data) {
 201                         .hw = &gpll3.clkr.hw,
 202                 },
 203                 .num_parents = 1,
 204                 .ops = &clk_pll_vote_ops,
 205         },
 206 };
 207
 208 /* GPLL3 at 1100 MHz, main output enabled. */
 209 static const struct pll_config gpll3_config = {
 210         .l = 57,
 211         .m = 7,
 212         .n = 24,
 213         .vco_val = 0x0,
 214         .vco_mask = BIT(20),
 215         .pre_div_val = 0x0,
 216         .pre_div_mask = BIT(12),
 217         .post_div_val = 0x0,
 218         .post_div_mask = BIT(9) | BIT(8),
 219         .mn_ena_mask = BIT(24),
 220         .main_output_mask = BIT(0),
 221         .aux_output_mask = BIT(1),
 222 };
 223
 224 static struct clk_pll gpll4 = {
 225         .l_reg = 0x24004,
 226         .m_reg = 0x24008,
 227         .n_reg = 0x2400c,
 228         .config_reg = 0x24010,
 229         .mode_reg = 0x24000,
 230         .status_reg = 0x2401c,
 231         .status_bit = 17,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "gpll4",
 234                 .parent_data = &(const struct clk_parent_data) {
 235                         .fw_name = "xo",
 236                 },
 237                 .num_parents = 1,
 238                 .ops = &clk_pll_ops,
 239         },
 240 };
 241
 242 static struct clk_regmap gpll4_vote = {
 243         .enable_reg = 0x45000,
 244         .enable_mask = BIT(5),
 245         .hw.init = &(struct clk_init_data){
 246                 .name = "gpll4_vote",
 247                 .parent_data = &(const struct clk_parent_data) {
 248                         .hw = &gpll4.clkr.hw,
 249                 },
 250                 .num_parents = 1,
 251                 .ops = &clk_pll_vote_ops,
 252         },
 253 };
 254
 255 /* GPLL4 at 1200 MHz, main output enabled. */
 256 static struct pll_config gpll4_config = {
 257         .l = 62,
 258         .m = 1,
 259         .n = 2,
 260         .vco_val = 0x0,
 261         .vco_mask = BIT(20),
 262         .pre_div_val = 0x0,
 263         .pre_div_mask = BIT(12),
 264         .post_div_val = 0x0,
 265         .post_div_mask = BIT(9) | BIT(8),
 266         .mn_ena_mask = BIT(24),
 267         .main_output_mask = BIT(0),
 268 };
 269
 270 static struct clk_pll gpll5 = {
 271         .l_reg = 0x25004,
 272         .m_reg = 0x25008,
 273         .n_reg = 0x2500c,
 274         .config_reg = 0x25010,
 275         .mode_reg = 0x25000,
 276         .status_reg = 0x2501c,
 277         .status_bit = 17,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll5",
 280                 .parent_data = &(const struct clk_parent_data) {
 281                         .fw_name = "xo",
 282                 },
 283                 .num_parents = 1,
 284                 .ops = &clk_pll_ops,
 285         },
 286 };
 287
 288 static struct clk_regmap gpll5_vote = {
 289         .enable_reg = 0x45000,
 290         .enable_mask = BIT(6),
 291         .hw.init = &(struct clk_init_data){
 292                 .name = "gpll5_vote",
 293                 .parent_data = &(const struct clk_parent_data) {
 294                         .hw = &gpll5.clkr.hw,
 295                 },
 296                 .num_parents = 1,
 297                 .ops = &clk_pll_vote_ops,
 298         },
 299 };
 300
 301 static struct clk_pll gpll6 = {
 302         .l_reg = 0x37004,
 303         .m_reg = 0x37008,
 304         .n_reg = 0x3700c,
 305         .config_reg = 0x37010,
 306         .mode_reg = 0x37000,
 307         .status_reg = 0x3701c,
 308         .status_bit = 17,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "gpll6",
 311                 .parent_data = &(const struct clk_parent_data) {
 312                         .fw_name = "xo",
 313                 },
 314                 .num_parents = 1,
 315                 .ops = &clk_pll_ops,
 316         },
 317 };
 318
 319 static struct clk_regmap gpll6_vote = {
 320         .enable_reg = 0x45000,
 321         .enable_mask = BIT(7),
 322         .hw.init = &(struct clk_init_data){
 323                 .name = "gpll6_vote",
 324                 .parent_data = &(const struct clk_parent_data) {
 325                         .hw = &gpll6.clkr.hw,
 326                 },
 327                 .num_parents = 1,
 328                 .ops = &clk_pll_vote_ops,
 329         },
 330 };
 331
 332 static const struct parent_map gcc_xo_gpll0_map[] = {
 333         { P_XO, 0 },
 334         { P_GPLL0, 1 },
 335 };
 336
 337 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
 338         { .fw_name = "xo" },
 339         { .hw = &gpll0_vote.hw },
 340 };
 341
 342 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 343         { P_XO, 0 },
 344         { P_GPLL0, 1 },
 345         { P_BIMC, 2 },
 346 };
 347
 348 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
 349         { .fw_name = "xo" },
 350         { .hw = &gpll0_vote.hw },
 351         { .hw = &bimc_pll_vote.hw },
 352 };
 353
 354 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
 355         { P_XO, 0 },
 356         { P_GPLL0, 1 },
 357         { P_GPLL6_AUX, 2 },
 358 };
 359
 360 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
 361         { .fw_name = "xo" },
 362         { .hw = &gpll0_vote.hw },
 363         { .hw = &gpll6_vote.hw },
 364 };
 365
 366 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
 367         { P_XO, 0 },
 368         { P_GPLL0, 1 },
 369         { P_GPLL2_AUX, 4 },
 370         { P_GPLL3, 2 },
 371         { P_GPLL6_AUX, 3 },
 372 };
 373
 374 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
 375         { .fw_name = "xo" },
 376         { .hw = &gpll0_vote.hw },
 377         { .hw = &gpll2_vote.hw },
 378         { .hw = &gpll3_vote.hw },
 379         { .hw = &gpll6_vote.hw },
 380 };
 381
 382 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 383         { P_XO, 0 },
 384         { P_GPLL0, 1 },
 385         { P_GPLL2, 2 },
 386 };
 387
 388 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
 389         { .fw_name = "xo" },
 390         { .hw = &gpll0_vote.hw },
 391         { .hw = &gpll2_vote.hw },
 392 };
 393
 394 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 395         { P_XO, 0 },
 396         { P_GPLL0, 1 },
 397         { P_GPLL2, 3 },
 398         { P_GPLL4, 2 },
 399 };
 400
 401 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
 402         { .fw_name = "xo" },
 403         { .hw = &gpll0_vote.hw },
 404         { .hw = &gpll2_vote.hw },
 405         { .hw = &gpll4_vote.hw },
 406 };
 407
 408 static const struct parent_map gcc_xo_gpll0a_map[] = {
 409         { P_XO, 0 },
 410         { P_GPLL0_AUX, 2 },
 411 };
 412
 413 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
 414         { .fw_name = "xo" },
 415         { .hw = &gpll0_vote.hw },
 416 };
 417
 418 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 419         { P_XO, 0 },
 420         { P_GPLL0, 1 },
 421         { P_GPLL1_AUX, 2 },
 422         { P_SLEEP_CLK, 6 },
 423 };
 424
 425 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
 426         { .fw_name = "xo" },
 427         { .hw = &gpll0_vote.hw },
 428         { .hw = &gpll1_vote.hw },
 429         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 430 };
 431
 432 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
 433         { P_XO, 0 },
 434         { P_GPLL0, 1 },
 435         { P_GPLL1_AUX, 2 },
 436         { P_GPLL6, 2 },
 437         { P_SLEEP_CLK, 6 },
 438 };
 439
 440 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
 441         { .fw_name = "xo" },
 442         { .hw = &gpll0_vote.hw },
 443         { .hw = &gpll1_vote.hw },
 444         { .hw = &gpll6_vote.hw },
 445         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 446 };
 447
 448 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 449         { P_XO, 0 },
 450         { P_GPLL0, 1 },
 451         { P_GPLL1_AUX, 2 },
 452 };
 453
 454 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
 455         { .fw_name = "xo" },
 456         { .hw = &gpll0_vote.hw },
 457         { .hw = &gpll1_vote.hw },
 458 };
 459
 460 static const struct parent_map gcc_xo_dsibyte_map[] = {
 461         { P_XO, 0, },
 462         { P_DSI0_PHYPLL_BYTE, 2 },
 463 };
 464
 465 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
 466         { .fw_name = "xo" },
 467         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 468 };
 469
 470 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 471         { P_XO, 0 },
 472         { P_GPLL0_AUX, 2 },
 473         { P_DSI0_PHYPLL_BYTE, 1 },
 474 };
 475
 476 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
 477         { .fw_name = "xo" },
 478         { .hw = &gpll0_vote.hw },
 479         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 480 };
 481
 482 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
 483         { P_XO, 0 },
 484         { P_GPLL1, 1 },
 485         { P_DSI0_PHYPLL_DSI, 2 },
 486         { P_GPLL6, 3 },
 487         { P_GPLL3_AUX, 4 },
 488         { P_GPLL0_AUX, 5 },
 489 };
 490
 491 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
 492         { .fw_name = "xo" },
 493         { .hw = &gpll1_vote.hw },
 494         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 495         { .hw = &gpll6_vote.hw },
 496         { .hw = &gpll3_vote.hw },
 497         { .hw = &gpll0_vote.hw },
 498 };
 499
 500 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 501         { P_XO, 0 },
 502         { P_GPLL0_AUX, 2 },
 503         { P_DSI0_PHYPLL_DSI, 1 },
 504 };
 505
 506 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
 507         { .fw_name = "xo" },
 508         { .hw = &gpll0_vote.hw },
 509         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 510 };
 511
 512 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
 513         { P_XO, 0 },
 514         { P_GPLL0, 1 },
 515         { P_GPLL5_AUX, 3 },
 516         { P_GPLL6, 2 },
 517         { P_BIMC, 4 },
 518 };
 519
 520 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
 521         { .fw_name = "xo" },
 522         { .hw = &gpll0_vote.hw },
 523         { .hw = &gpll5_vote.hw },
 524         { .hw = &gpll6_vote.hw },
 525         { .hw = &bimc_pll_vote.hw },
 526 };
 527
 528 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 529         { P_XO, 0 },
 530         { P_GPLL0, 1 },
 531         { P_GPLL1, 2 },
 532         { P_SLEEP_CLK, 6 }
 533 };
 534
 535 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
 536         { .fw_name = "xo" },
 537         { .hw = &gpll0_vote.hw },
 538         { .hw = &gpll1_vote.hw },
 539         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 540 };
 541
 542 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 543         { P_XO, 0 },
 544         { P_GPLL1, 1 },
 545         { P_EXT_PRI_I2S, 2 },
 546         { P_EXT_MCLK, 3 },
 547         { P_SLEEP_CLK, 6 }
 548 };
 549
 550 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
 551         { .fw_name = "xo" },
 552         { .hw = &gpll0_vote.hw },
 553         { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 554         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 555         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 556 };
 557
 558 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 559         { P_XO, 0 },
 560         { P_GPLL1, 1 },
 561         { P_EXT_SEC_I2S, 2 },
 562         { P_EXT_MCLK, 3 },
 563         { P_SLEEP_CLK, 6 }
 564 };
 565
 566 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
 567         { .fw_name = "xo" },
 568         { .hw = &gpll1_vote.hw },
 569         { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 570         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 571         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 572 };
 573
 574 static const struct parent_map gcc_xo_sleep_map[] = {
 575         { P_XO, 0 },
 576         { P_SLEEP_CLK, 6 }
 577 };
 578
 579 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
 580         { .fw_name = "xo" },
 581         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 582 };
 583
 584 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 585         { P_XO, 0 },
 586         { P_GPLL1, 1 },
 587         { P_EXT_MCLK, 2 },
 588         { P_SLEEP_CLK, 6 }
 589 };
 590
 591 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
 592         { .fw_name = "xo" },
 593         { .hw = &gpll1_vote.hw },
 594         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 595         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 596 };
 597
 598 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
 599         { .fw_name = "xo" },
 600         { .hw = &gpll6_vote.hw },
 601         { .hw = &gpll0_vote.hw },
 602 };
 603
 604 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
 605         { .fw_name = "xo" },
 606         { .hw = &gpll6_vote.hw },
 607         { .hw = &gpll0_vote.hw },
 608 };
 609
 610 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 611         .cmd_rcgr = 0x27000,
 612         .hid_width = 5,
 613         .parent_map = gcc_xo_gpll0_map,
 614         .clkr.hw.init = &(struct clk_init_data){
 615                 .name = "pcnoc_bfdcd_clk_src",
 616                 .parent_data = gcc_xo_gpll0_parent_data,
 617                 .num_parents = 2,
 618                 .ops = &clk_rcg2_ops,
 619         },
 620 };
 621
 622 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 623         .cmd_rcgr = 0x26004,
 624         .hid_width = 5,
 625         .parent_map = gcc_xo_gpll0_gpll6a_map,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "system_noc_bfdcd_clk_src",
 628                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 629                 .num_parents = 3,
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static struct clk_rcg2 bimc_ddr_clk_src = {
 635         .cmd_rcgr = 0x32004,
 636         .hid_width = 5,
 637         .parent_map = gcc_xo_gpll0_bimc_map,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "bimc_ddr_clk_src",
 640                 .parent_data = gcc_xo_gpll0_bimc_parent_data,
 641                 .num_parents = 3,
 642                 .ops = &clk_rcg2_ops,
 643                 .flags = CLK_GET_RATE_NOCACHE,
 644         },
 645 };
 646
 647 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 648         F(40000000, P_GPLL0, 10, 1, 2),
 649         F(80000000, P_GPLL0, 10, 0, 0),
 650         { }
 651 };
 652
 653 static struct clk_rcg2 camss_ahb_clk_src = {
 654         .cmd_rcgr = 0x5a000,
 655         .mnd_width = 8,
 656         .hid_width = 5,
 657         .parent_map = gcc_xo_gpll0_map,
 658         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 659         .clkr.hw.init = &(struct clk_init_data){
 660                 .name = "camss_ahb_clk_src",
 661                 .parent_data = gcc_xo_gpll0_parent_data,
 662                 .num_parents = 2,
 663                 .ops = &clk_rcg2_ops,
 664         },
 665 };
 666
 667 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 668         F(19200000, P_XO, 1, 0, 0),
 669         F(50000000, P_GPLL0, 16, 0, 0),
 670         F(100000000, P_GPLL0, 8, 0, 0),
 671         F(133330000, P_GPLL0, 6, 0, 0),
 672         { }
 673 };
 674
 675 static struct clk_rcg2 apss_ahb_clk_src = {
 676         .cmd_rcgr = 0x46000,
 677         .hid_width = 5,
 678         .parent_map = gcc_xo_gpll0_map,
 679         .freq_tbl = ftbl_apss_ahb_clk,
 680         .clkr.hw.init = &(struct clk_init_data){
 681                 .name = "apss_ahb_clk_src",
 682                 .parent_data = gcc_xo_gpll0_parent_data,
 683                 .num_parents = 2,
 684                 .ops = &clk_rcg2_ops,
 685         },
 686 };
 687
 688 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 689         F(100000000, P_GPLL0, 8, 0,     0),
 690         F(200000000, P_GPLL0, 4, 0,     0),
 691         { }
 692 };
 693
 694 static struct clk_rcg2 csi0_clk_src = {
 695         .cmd_rcgr = 0x4e020,
 696         .hid_width = 5,
 697         .parent_map = gcc_xo_gpll0_map,
 698         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 699         .clkr.hw.init = &(struct clk_init_data){
 700                 .name = "csi0_clk_src",
 701                 .parent_data = gcc_xo_gpll0_parent_data,
 702                 .num_parents = 2,
 703                 .ops = &clk_rcg2_ops,
 704         },
 705 };
 706
 707 static struct clk_rcg2 csi1_clk_src = {
 708         .cmd_rcgr = 0x4f020,
 709         .hid_width = 5,
 710         .parent_map = gcc_xo_gpll0_map,
 711         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "csi1_clk_src",
 714                 .parent_data = gcc_xo_gpll0_parent_data,
 715                 .num_parents = 2,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 721         F(19200000, P_XO, 1, 0, 0),
 722         F(50000000, P_GPLL0, 16, 0, 0),
 723         F(80000000, P_GPLL0, 10, 0, 0),
 724         F(100000000, P_GPLL0, 8, 0, 0),
 725         F(160000000, P_GPLL0, 5, 0, 0),
 726         F(200000000, P_GPLL0, 4, 0, 0),
 727         F(220000000, P_GPLL3, 5, 0, 0),
 728         F(266670000, P_GPLL0, 3, 0, 0),
 729         F(310000000, P_GPLL2_AUX, 3, 0, 0),
 730         F(400000000, P_GPLL0, 2, 0, 0),
 731         F(465000000, P_GPLL2_AUX, 2, 0, 0),
 732         F(550000000, P_GPLL3, 2, 0, 0),
 733         { }
 734 };
 735
 736 static struct clk_rcg2 gfx3d_clk_src = {
 737         .cmd_rcgr = 0x59000,
 738         .hid_width = 5,
 739         .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
 740         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 741         .clkr.hw.init = &(struct clk_init_data){
 742                 .name = "gfx3d_clk_src",
 743                 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
 744                 .num_parents = 5,
 745                 .ops = &clk_rcg2_ops,
 746         },
 747 };
 748
 749 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 750         F(50000000, P_GPLL0, 16, 0, 0),
 751         F(80000000, P_GPLL0, 10, 0, 0),
 752         F(100000000, P_GPLL0, 8, 0, 0),
 753         F(160000000, P_GPLL0, 5, 0, 0),
 754         F(177780000, P_GPLL0, 4.5, 0, 0),
 755         F(200000000, P_GPLL0, 4, 0, 0),
 756         F(266670000, P_GPLL0, 3, 0, 0),
 757         F(320000000, P_GPLL0, 2.5, 0, 0),
 758         F(400000000, P_GPLL0, 2, 0, 0),
 759         F(465000000, P_GPLL2, 2, 0, 0),
 760         F(480000000, P_GPLL4, 2.5, 0, 0),
 761         F(600000000, P_GPLL4, 2, 0, 0),
 762         { }
 763 };
 764
 765 static struct clk_rcg2 vfe0_clk_src = {
 766         .cmd_rcgr = 0x58000,
 767         .hid_width = 5,
 768         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
 769         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 770         .clkr.hw.init = &(struct clk_init_data){
 771                 .name = "vfe0_clk_src",
 772                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
 773                 .num_parents = 4,
 774                 .ops = &clk_rcg2_ops,
 775         },
 776 };
 777
 778 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 779         F(19200000, P_XO, 1, 0, 0),
 780         F(50000000, P_GPLL0, 16, 0, 0),
 781         { }
 782 };
 783
 784 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 785         .cmd_rcgr = 0x0200c,
 786         .hid_width = 5,
 787         .parent_map = gcc_xo_gpll0_map,
 788         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 789         .clkr.hw.init = &(struct clk_init_data){
 790                 .name = "blsp1_qup1_i2c_apps_clk_src",
 791                 .parent_data = gcc_xo_gpll0_parent_data,
 792                 .num_parents = 2,
 793                 .ops = &clk_rcg2_ops,
 794         },
 795 };
 796
 797 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 798         F(960000, P_XO, 10, 1, 2),
 799         F(4800000, P_XO, 4, 0, 0),
 800         F(9600000, P_XO, 2, 0, 0),
 801         F(16000000, P_GPLL0, 10, 1, 5),
 802         F(19200000, P_XO, 1, 0, 0),
 803         F(25000000, P_GPLL0, 16, 1, 2),
 804         F(50000000, P_GPLL0, 16, 0, 0),
 805         { }
 806 };
 807
 808 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 809         .cmd_rcgr = 0x02024,
 810         .mnd_width = 8,
 811         .hid_width = 5,
 812         .parent_map = gcc_xo_gpll0_map,
 813         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "blsp1_qup1_spi_apps_clk_src",
 816                 .parent_data = gcc_xo_gpll0_parent_data,
 817                 .num_parents = 2,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 823         .cmd_rcgr = 0x03000,
 824         .hid_width = 5,
 825         .parent_map = gcc_xo_gpll0_map,
 826         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 827         .clkr.hw.init = &(struct clk_init_data){
 828                 .name = "blsp1_qup2_i2c_apps_clk_src",
 829                 .parent_data = gcc_xo_gpll0_parent_data,
 830                 .num_parents = 2,
 831                 .ops = &clk_rcg2_ops,
 832         },
 833 };
 834
 835 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 836         .cmd_rcgr = 0x03014,
 837         .mnd_width = 8,
 838         .hid_width = 5,
 839         .parent_map = gcc_xo_gpll0_map,
 840         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 841         .clkr.hw.init = &(struct clk_init_data){
 842                 .name = "blsp1_qup2_spi_apps_clk_src",
 843                 .parent_data = gcc_xo_gpll0_parent_data,
 844                 .num_parents = 2,
 845                 .ops = &clk_rcg2_ops,
 846         },
 847 };
 848
 849 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 850         .cmd_rcgr = 0x04000,
 851         .hid_width = 5,
 852         .parent_map = gcc_xo_gpll0_map,
 853         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 854         .clkr.hw.init = &(struct clk_init_data){
 855                 .name = "blsp1_qup3_i2c_apps_clk_src",
 856                 .parent_data = gcc_xo_gpll0_parent_data,
 857                 .num_parents = 2,
 858                 .ops = &clk_rcg2_ops,
 859         },
 860 };
 861
 862 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 863         .cmd_rcgr = 0x04024,
 864         .mnd_width = 8,
 865         .hid_width = 5,
 866         .parent_map = gcc_xo_gpll0_map,
 867         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 868         .clkr.hw.init = &(struct clk_init_data){
 869                 .name = "blsp1_qup3_spi_apps_clk_src",
 870                 .parent_data = gcc_xo_gpll0_parent_data,
 871                 .num_parents = 2,
 872                 .ops = &clk_rcg2_ops,
 873         },
 874 };
 875
 876 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 877         .cmd_rcgr = 0x05000,
 878         .hid_width = 5,
 879         .parent_map = gcc_xo_gpll0_map,
 880         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 881         .clkr.hw.init = &(struct clk_init_data){
 882                 .name = "blsp1_qup4_i2c_apps_clk_src",
 883                 .parent_data = gcc_xo_gpll0_parent_data,
 884                 .num_parents = 2,
 885                 .ops = &clk_rcg2_ops,
 886         },
 887 };
 888
 889 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 890         .cmd_rcgr = 0x05024,
 891         .mnd_width = 8,
 892         .hid_width = 5,
 893         .parent_map = gcc_xo_gpll0_map,
 894         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 895         .clkr.hw.init = &(struct clk_init_data){
 896                 .name = "blsp1_qup4_spi_apps_clk_src",
 897                 .parent_data = gcc_xo_gpll0_parent_data,
 898                 .num_parents = 2,
 899                 .ops = &clk_rcg2_ops,
 900         },
 901 };
 902
 903 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 904         .cmd_rcgr = 0x06000,
 905         .hid_width = 5,
 906         .parent_map = gcc_xo_gpll0_map,
 907         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "blsp1_qup5_i2c_apps_clk_src",
 910                 .parent_data = gcc_xo_gpll0_parent_data,
 911                 .num_parents = 2,
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 917         .cmd_rcgr = 0x06024,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = gcc_xo_gpll0_map,
 921         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "blsp1_qup5_spi_apps_clk_src",
 924                 .parent_data = gcc_xo_gpll0_parent_data,
 925                 .num_parents = 2,
 926                 .ops = &clk_rcg2_ops,
 927         },
 928 };
 929
 930 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 931         .cmd_rcgr = 0x07000,
 932         .hid_width = 5,
 933         .parent_map = gcc_xo_gpll0_map,
 934         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 935         .clkr.hw.init = &(struct clk_init_data){
 936                 .name = "blsp1_qup6_i2c_apps_clk_src",
 937                 .parent_data = gcc_xo_gpll0_parent_data,
 938                 .num_parents = 2,
 939                 .ops = &clk_rcg2_ops,
 940         },
 941 };
 942
 943 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 944         .cmd_rcgr = 0x07024,
 945         .mnd_width = 8,
 946         .hid_width = 5,
 947         .parent_map = gcc_xo_gpll0_map,
 948         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 949         .clkr.hw.init = &(struct clk_init_data){
 950                 .name = "blsp1_qup6_spi_apps_clk_src",
 951                 .parent_data = gcc_xo_gpll0_parent_data,
 952                 .num_parents = 2,
 953                 .ops = &clk_rcg2_ops,
 954         },
 955 };
 956
 957 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 958         F(3686400, P_GPLL0, 1, 72, 15625),
 959         F(7372800, P_GPLL0, 1, 144, 15625),
 960         F(14745600, P_GPLL0, 1, 288, 15625),
 961         F(16000000, P_GPLL0, 10, 1, 5),
 962         F(19200000, P_XO, 1, 0, 0),
 963         F(24000000, P_GPLL0, 1, 3, 100),
 964         F(25000000, P_GPLL0, 16, 1, 2),
 965         F(32000000, P_GPLL0, 1, 1, 25),
 966         F(40000000, P_GPLL0, 1, 1, 20),
 967         F(46400000, P_GPLL0, 1, 29, 500),
 968         F(48000000, P_GPLL0, 1, 3, 50),
 969         F(51200000, P_GPLL0, 1, 8, 125),
 970         F(56000000, P_GPLL0, 1, 7, 100),
 971         F(58982400, P_GPLL0, 1, 1152, 15625),
 972         F(60000000, P_GPLL0, 1, 3, 40),
 973         { }
 974 };
 975
 976 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 977         .cmd_rcgr = 0x02044,
 978         .mnd_width = 16,
 979         .hid_width = 5,
 980         .parent_map = gcc_xo_gpll0_map,
 981         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "blsp1_uart1_apps_clk_src",
 984                 .parent_data = gcc_xo_gpll0_parent_data,
 985                 .num_parents = 2,
 986                 .ops = &clk_rcg2_ops,
 987         },
 988 };
 989
 990 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 991         .cmd_rcgr = 0x03034,
 992         .mnd_width = 16,
 993         .hid_width = 5,
 994         .parent_map = gcc_xo_gpll0_map,
 995         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 996         .clkr.hw.init = &(struct clk_init_data){
 997                 .name = "blsp1_uart2_apps_clk_src",
 998                 .parent_data = gcc_xo_gpll0_parent_data,
 999                 .num_parents = 2,
1000                 .ops = &clk_rcg2_ops,
1001         },
1002 };
1003
1004 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1005         F(19200000,     P_XO, 1, 0,     0),
1006         { }
1007 };
1008
1009 static struct clk_rcg2 cci_clk_src = {
1010         .cmd_rcgr = 0x51000,
1011         .mnd_width = 8,
1012         .hid_width = 5,
1013         .parent_map = gcc_xo_gpll0a_map,
1014         .freq_tbl = ftbl_gcc_camss_cci_clk,
1015         .clkr.hw.init = &(struct clk_init_data){
1016                 .name = "cci_clk_src",
1017                 .parent_data = gcc_xo_gpll0a_parent_data,
1018                 .num_parents = 2,
1019                 .ops = &clk_rcg2_ops,
1020         },
1021 };
1022
1023 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1024         F(100000000, P_GPLL0, 8, 0, 0),
1025         F(200000000, P_GPLL0, 4, 0, 0),
1026         { }
1027 };
1028
1029 static struct clk_rcg2 camss_gp0_clk_src = {
1030         .cmd_rcgr = 0x54000,
1031         .mnd_width = 8,
1032         .hid_width = 5,
1033         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1034         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1035         .clkr.hw.init = &(struct clk_init_data){
1036                 .name = "camss_gp0_clk_src",
1037                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1038                 .num_parents = 4,
1039                 .ops = &clk_rcg2_ops,
1040         },
1041 };
1042
1043 static struct clk_rcg2 camss_gp1_clk_src = {
1044         .cmd_rcgr = 0x55000,
1045         .mnd_width = 8,
1046         .hid_width = 5,
1047         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1048         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1049         .clkr.hw.init = &(struct clk_init_data){
1050                 .name = "camss_gp1_clk_src",
1051                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1052                 .num_parents = 4,
1053                 .ops = &clk_rcg2_ops,
1054         },
1055 };
1056
1057 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1058         F(133330000, P_GPLL0, 6, 0,     0),
1059         F(266670000, P_GPLL0, 3, 0,     0),
1060         F(320000000, P_GPLL0, 2.5, 0, 0),
1061         { }
1062 };
1063
1064 static struct clk_rcg2 jpeg0_clk_src = {
1065         .cmd_rcgr = 0x57000,
1066         .hid_width = 5,
1067         .parent_map = gcc_xo_gpll0_map,
1068         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1069         .clkr.hw.init = &(struct clk_init_data){
1070                 .name = "jpeg0_clk_src",
1071                 .parent_data = gcc_xo_gpll0_parent_data,
1072                 .num_parents = 2,
1073                 .ops = &clk_rcg2_ops,
1074         },
1075 };
1076
1077 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1078         F(24000000, P_GPLL0, 1, 1, 45),
1079         F(66670000, P_GPLL0, 12, 0, 0),
1080         { }
1081 };
1082
1083 static struct clk_rcg2 mclk0_clk_src = {
1084         .cmd_rcgr = 0x52000,
1085         .mnd_width = 8,
1086         .hid_width = 5,
1087         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1088         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1089         .clkr.hw.init = &(struct clk_init_data){
1090                 .name = "mclk0_clk_src",
1091                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1092                 .num_parents = 5,
1093                 .ops = &clk_rcg2_ops,
1094         },
1095 };
1096
1097 static struct clk_rcg2 mclk1_clk_src = {
1098         .cmd_rcgr = 0x53000,
1099         .mnd_width = 8,
1100         .hid_width = 5,
1101         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1102         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1103         .clkr.hw.init = &(struct clk_init_data){
1104                 .name = "mclk1_clk_src",
1105                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1106                 .num_parents = 5,
1107                 .ops = &clk_rcg2_ops,
1108         },
1109 };
1110
1111 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1112         F(100000000, P_GPLL0, 8, 0,     0),
1113         F(200000000, P_GPLL0, 4, 0,     0),
1114         { }
1115 };
1116
1117 static struct clk_rcg2 csi0phytimer_clk_src = {
1118         .cmd_rcgr = 0x4e000,
1119         .hid_width = 5,
1120         .parent_map = gcc_xo_gpll0_gpll1a_map,
1121         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1122         .clkr.hw.init = &(struct clk_init_data){
1123                 .name = "csi0phytimer_clk_src",
1124                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1125                 .num_parents = 3,
1126                 .ops = &clk_rcg2_ops,
1127         },
1128 };
1129
1130 static struct clk_rcg2 csi1phytimer_clk_src = {
1131         .cmd_rcgr = 0x4f000,
1132         .hid_width = 5,
1133         .parent_map = gcc_xo_gpll0_gpll1a_map,
1134         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1135         .clkr.hw.init = &(struct clk_init_data){
1136                 .name = "csi1phytimer_clk_src",
1137                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1138                 .num_parents = 3,
1139                 .ops = &clk_rcg2_ops,
1140         },
1141 };
1142
1143 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1144         F(160000000, P_GPLL0, 5, 0, 0),
1145         F(320000000, P_GPLL0, 2.5, 0, 0),
1146         F(465000000, P_GPLL2, 2, 0, 0),
1147         { }
1148 };
1149
1150 static struct clk_rcg2 cpp_clk_src = {
1151         .cmd_rcgr = 0x58018,
1152         .hid_width = 5,
1153         .parent_map = gcc_xo_gpll0_gpll2_map,
1154         .freq_tbl = ftbl_gcc_camss_cpp_clk,
1155         .clkr.hw.init = &(struct clk_init_data){
1156                 .name = "cpp_clk_src",
1157                 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1158                 .num_parents = 3,
1159                 .ops = &clk_rcg2_ops,
1160         },
1161 };
1162
1163 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1164         F(50000000, P_GPLL0, 16, 0, 0),
1165         F(80000000, P_GPLL0, 10, 0, 0),
1166         F(100000000, P_GPLL0, 8, 0, 0),
1167         F(160000000, P_GPLL0, 5, 0, 0),
1168         { }
1169 };
1170
1171 /* This is not in the documentation but is in the downstream driver */
1172 static struct clk_rcg2 crypto_clk_src = {
1173         .cmd_rcgr = 0x16004,
1174         .hid_width = 5,
1175         .parent_map = gcc_xo_gpll0_map,
1176         .freq_tbl = ftbl_gcc_crypto_clk,
1177         .clkr.hw.init = &(struct clk_init_data){
1178                 .name = "crypto_clk_src",
1179                 .parent_data = gcc_xo_gpll0_parent_data,
1180                 .num_parents = 2,
1181                 .ops = &clk_rcg2_ops,
1182         },
1183 };
1184
1185 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1186         F(19200000, P_XO, 1, 0, 0),
1187         { }
1188 };
1189
1190 static struct clk_rcg2 gp1_clk_src = {
1191         .cmd_rcgr = 0x08004,
1192         .mnd_width = 8,
1193         .hid_width = 5,
1194         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1195         .freq_tbl = ftbl_gcc_gp1_3_clk,
1196         .clkr.hw.init = &(struct clk_init_data){
1197                 .name = "gp1_clk_src",
1198                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1199                 .num_parents = 3,
1200                 .ops = &clk_rcg2_ops,
1201         },
1202 };
1203
1204 static struct clk_rcg2 gp2_clk_src = {
1205         .cmd_rcgr = 0x09004,
1206         .mnd_width = 8,
1207         .hid_width = 5,
1208         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1209         .freq_tbl = ftbl_gcc_gp1_3_clk,
1210         .clkr.hw.init = &(struct clk_init_data){
1211                 .name = "gp2_clk_src",
1212                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1213                 .num_parents = 3,
1214                 .ops = &clk_rcg2_ops,
1215         },
1216 };
1217
1218 static struct clk_rcg2 gp3_clk_src = {
1219         .cmd_rcgr = 0x0a004,
1220         .mnd_width = 8,
1221         .hid_width = 5,
1222         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1223         .freq_tbl = ftbl_gcc_gp1_3_clk,
1224         .clkr.hw.init = &(struct clk_init_data){
1225                 .name = "gp3_clk_src",
1226                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1227                 .num_parents = 3,
1228                 .ops = &clk_rcg2_ops,
1229         },
1230 };
1231
1232 static struct clk_rcg2 byte0_clk_src = {
1233         .cmd_rcgr = 0x4d044,
1234         .hid_width = 5,
1235         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1236         .clkr.hw.init = &(struct clk_init_data){
1237                 .name = "byte0_clk_src",
1238                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1239                 .num_parents = 3,
1240                 .ops = &clk_byte2_ops,
1241                 .flags = CLK_SET_RATE_PARENT,
1242         },
1243 };
1244
1245 static struct clk_rcg2 byte1_clk_src = {
1246         .cmd_rcgr = 0x4d0b0,
1247         .hid_width = 5,
1248         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1249         .clkr.hw.init = &(struct clk_init_data){
1250                 .name = "byte1_clk_src",
1251                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1252                 .num_parents = 3,
1253                 .ops = &clk_byte2_ops,
1254                 .flags = CLK_SET_RATE_PARENT,
1255         },
1256 };
1257
1258 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1259         F(19200000, P_XO, 1, 0, 0),
1260         { }
1261 };
1262
1263 static struct clk_rcg2 esc0_clk_src = {
1264         .cmd_rcgr = 0x4d060,
1265         .hid_width = 5,
1266         .parent_map = gcc_xo_dsibyte_map,
1267         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1268         .clkr.hw.init = &(struct clk_init_data){
1269                 .name = "esc0_clk_src",
1270                 .parent_data = gcc_xo_dsibyte_parent_data,
1271                 .num_parents = 2,
1272                 .ops = &clk_rcg2_ops,
1273         },
1274 };
1275
1276 static struct clk_rcg2 esc1_clk_src = {
1277         .cmd_rcgr = 0x4d0a8,
1278         .hid_width = 5,
1279         .parent_map = gcc_xo_dsibyte_map,
1280         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1281         .clkr.hw.init = &(struct clk_init_data){
1282                 .name = "esc1_clk_src",
1283                 .parent_data = gcc_xo_dsibyte_parent_data,
1284                 .num_parents = 2,
1285                 .ops = &clk_rcg2_ops,
1286         },
1287 };
1288
1289 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1290         F(50000000, P_GPLL0_AUX, 16, 0, 0),
1291         F(80000000, P_GPLL0_AUX, 10, 0, 0),
1292         F(100000000, P_GPLL0_AUX, 8, 0, 0),
1293         F(160000000, P_GPLL0_AUX, 5, 0, 0),
1294         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1295         F(200000000, P_GPLL0_AUX, 4, 0, 0),
1296         F(266670000, P_GPLL0_AUX, 3, 0, 0),
1297         F(307200000, P_GPLL1, 2, 0, 0),
1298         F(366670000, P_GPLL3_AUX, 3, 0, 0),
1299         { }
1300 };
1301
1302 static struct clk_rcg2 mdp_clk_src = {
1303         .cmd_rcgr = 0x4d014,
1304         .hid_width = 5,
1305         .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1306         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1307         .clkr.hw.init = &(struct clk_init_data){
1308                 .name = "mdp_clk_src",
1309                 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1310                 .num_parents = 6,
1311                 .ops = &clk_rcg2_ops,
1312         },
1313 };
1314
1315 static struct clk_rcg2 pclk0_clk_src = {
1316         .cmd_rcgr = 0x4d000,
1317         .mnd_width = 8,
1318         .hid_width = 5,
1319         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1320         .clkr.hw.init = &(struct clk_init_data){
1321                 .name = "pclk0_clk_src",
1322                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1323                 .num_parents = 3,
1324                 .ops = &clk_pixel_ops,
1325                 .flags = CLK_SET_RATE_PARENT,
1326         },
1327 };
1328
1329 static struct clk_rcg2 pclk1_clk_src = {
1330         .cmd_rcgr = 0x4d0b8,
1331         .mnd_width = 8,
1332         .hid_width = 5,
1333         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1334         .clkr.hw.init = &(struct clk_init_data){
1335                 .name = "pclk1_clk_src",
1336                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1337                 .num_parents = 3,
1338                 .ops = &clk_pixel_ops,
1339                 .flags = CLK_SET_RATE_PARENT,
1340         },
1341 };
1342
1343 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1344         F(19200000, P_XO, 1, 0, 0),
1345         { }
1346 };
1347
1348 static struct clk_rcg2 vsync_clk_src = {
1349         .cmd_rcgr = 0x4d02c,
1350         .hid_width = 5,
1351         .parent_map = gcc_xo_gpll0a_map,
1352         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1353         .clkr.hw.init = &(struct clk_init_data){
1354                 .name = "vsync_clk_src",
1355                 .parent_data = gcc_xo_gpll0a_parent_data,
1356                 .num_parents = 2,
1357                 .ops = &clk_rcg2_ops,
1358         },
1359 };
1360
1361 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1362         F(64000000, P_GPLL0, 12.5, 0, 0),
1363         { }
1364 };
1365
1366 /* This is not in the documentation but is in the downstream driver */
1367 static struct clk_rcg2 pdm2_clk_src = {
1368         .cmd_rcgr = 0x44010,
1369         .hid_width = 5,
1370         .parent_map = gcc_xo_gpll0_map,
1371         .freq_tbl = ftbl_gcc_pdm2_clk,
1372         .clkr.hw.init = &(struct clk_init_data){
1373                 .name = "pdm2_clk_src",
1374                 .parent_data = gcc_xo_gpll0_parent_data,
1375                 .num_parents = 2,
1376                 .ops = &clk_rcg2_ops,
1377         },
1378 };
1379
1380 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1381         F(144000, P_XO, 16, 3, 25),
1382         F(400000, P_XO, 12, 1, 4),
1383         F(20000000, P_GPLL0, 10, 1, 4),
1384         F(25000000, P_GPLL0, 16, 1, 2),
1385         F(50000000, P_GPLL0, 16, 0, 0),
1386         F(100000000, P_GPLL0, 8, 0, 0),
1387         F(177770000, P_GPLL0, 4.5, 0, 0),
1388         F(200000000, P_GPLL0, 4, 0, 0),
1389         { }
1390 };
1391
1392 static struct clk_rcg2 sdcc1_apps_clk_src = {
1393         .cmd_rcgr = 0x42004,
1394         .mnd_width = 8,
1395         .hid_width = 5,
1396         .parent_map = gcc_xo_gpll0_map,
1397         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1398         .clkr.hw.init = &(struct clk_init_data){
1399                 .name = "sdcc1_apps_clk_src",
1400                 .parent_data = gcc_xo_gpll0_parent_data,
1401                 .num_parents = 2,
1402                 .ops = &clk_rcg2_floor_ops,
1403         },
1404 };
1405
1406 static struct clk_rcg2 sdcc2_apps_clk_src = {
1407         .cmd_rcgr = 0x43004,
1408         .mnd_width = 8,
1409         .hid_width = 5,
1410         .parent_map = gcc_xo_gpll0_map,
1411         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1412         .clkr.hw.init = &(struct clk_init_data){
1413                 .name = "sdcc2_apps_clk_src",
1414                 .parent_data = gcc_xo_gpll0_parent_data,
1415                 .num_parents = 2,
1416                 .ops = &clk_rcg2_floor_ops,
1417         },
1418 };
1419
1420 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1421         F(154285000, P_GPLL6, 7, 0, 0),
1422         F(320000000, P_GPLL0, 2.5, 0, 0),
1423         F(400000000, P_GPLL0, 2, 0, 0),
1424         { }
1425 };
1426
1427 static struct clk_rcg2 apss_tcu_clk_src = {
1428         .cmd_rcgr = 0x1207c,
1429         .hid_width = 5,
1430         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1431         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1432         .clkr.hw.init = &(struct clk_init_data){
1433                 .name = "apss_tcu_clk_src",
1434                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1435                 .num_parents = 5,
1436                 .ops = &clk_rcg2_ops,
1437         },
1438 };
1439
1440 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1441         F(19200000, P_XO, 1, 0, 0),
1442         F(100000000, P_GPLL0, 8, 0, 0),
1443         F(200000000, P_GPLL0, 4, 0, 0),
1444         F(266500000, P_BIMC, 4, 0, 0),
1445         F(400000000, P_GPLL0, 2, 0, 0),
1446         F(533000000, P_BIMC, 2, 0, 0),
1447         { }
1448 };
1449
1450 static struct clk_rcg2 bimc_gpu_clk_src = {
1451         .cmd_rcgr = 0x31028,
1452         .hid_width = 5,
1453         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1454         .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1455         .clkr.hw.init = &(struct clk_init_data){
1456                 .name = "bimc_gpu_clk_src",
1457                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1458                 .num_parents = 5,
1459                 .flags = CLK_GET_RATE_NOCACHE,
1460                 .ops = &clk_rcg2_ops,
1461         },
1462 };
1463
1464 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1465         F(80000000, P_GPLL0, 10, 0, 0),
1466         { }
1467 };
1468
1469 static struct clk_rcg2 usb_hs_system_clk_src = {
1470         .cmd_rcgr = 0x41010,
1471         .hid_width = 5,
1472         .parent_map = gcc_xo_gpll0_map,
1473         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1474         .clkr.hw.init = &(struct clk_init_data){
1475                 .name = "usb_hs_system_clk_src",
1476                 .parent_data = gcc_xo_gpll0_parent_data,
1477                 .num_parents = 2,
1478                 .ops = &clk_rcg2_ops,
1479         },
1480 };
1481
1482 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1483         F(64000000, P_GPLL0, 12.5, 0, 0),
1484         { }
1485 };
1486
1487 static struct clk_rcg2 usb_fs_system_clk_src = {
1488         .cmd_rcgr = 0x3f010,
1489         .hid_width = 5,
1490         .parent_map = gcc_xo_gpll0_map,
1491         .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1492         .clkr.hw.init = &(struct clk_init_data){
1493                 .name = "usb_fs_system_clk_src",
1494                 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1495                 .num_parents = 3,
1496                 .ops = &clk_rcg2_ops,
1497         },
1498 };
1499
1500 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1501         F(60000000, P_GPLL6, 1, 1, 18),
1502         { }
1503 };
1504
1505 static struct clk_rcg2 usb_fs_ic_clk_src = {
1506         .cmd_rcgr = 0x3f034,
1507         .hid_width = 5,
1508         .parent_map = gcc_xo_gpll0_map,
1509         .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1510         .clkr.hw.init = &(struct clk_init_data){
1511                 .name = "usb_fs_ic_clk_src",
1512                 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1513                 .num_parents = 3,
1514                 .ops = &clk_rcg2_ops,
1515         },
1516 };
1517
1518 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1519         F(3200000, P_XO, 6, 0, 0),
1520         F(6400000, P_XO, 3, 0, 0),
1521         F(9600000, P_XO, 2, 0, 0),
1522         F(19200000, P_XO, 1, 0, 0),
1523         F(40000000, P_GPLL0, 10, 1, 2),
1524         F(66670000, P_GPLL0, 12, 0, 0),
1525         F(80000000, P_GPLL0, 10, 0, 0),
1526         F(100000000, P_GPLL0, 8, 0, 0),
1527         { }
1528 };
1529
1530 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1531         .cmd_rcgr = 0x1c010,
1532         .hid_width = 5,
1533         .mnd_width = 8,
1534         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1535         .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1536         .clkr.hw.init = &(struct clk_init_data){
1537                 .name = "ultaudio_ahbfabric_clk_src",
1538                 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1539                 .num_parents = 4,
1540                 .ops = &clk_rcg2_ops,
1541         },
1542 };
1543
1544 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1545         .halt_reg = 0x1c028,
1546         .clkr = {
1547                 .enable_reg = 0x1c028,
1548                 .enable_mask = BIT(0),
1549                 .hw.init = &(struct clk_init_data){
1550                         .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1551                         .parent_data = &(const struct clk_parent_data){
1552                                 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1553                         },
1554                         .num_parents = 1,
1555                         .flags = CLK_SET_RATE_PARENT,
1556                         .ops = &clk_branch2_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1562         .halt_reg = 0x1c024,
1563         .clkr = {
1564                 .enable_reg = 0x1c024,
1565                 .enable_mask = BIT(0),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1568                         .parent_data = &(const struct clk_parent_data){
1569                                 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1570                         },
1571                         .num_parents = 1,
1572                         .flags = CLK_SET_RATE_PARENT,
1573                         .ops = &clk_branch2_ops,
1574                 },
1575         },
1576 };
1577
1578 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1579         F(128000, P_XO, 10, 1, 15),
1580         F(256000, P_XO, 5, 1, 15),
1581         F(384000, P_XO, 5, 1, 10),
1582         F(512000, P_XO, 5, 2, 15),
1583         F(576000, P_XO, 5, 3, 20),
1584         F(705600, P_GPLL1, 16, 1, 80),
1585         F(768000, P_XO, 5, 1, 5),
1586         F(800000, P_XO, 5, 5, 24),
1587         F(1024000, P_XO, 5, 4, 15),
1588         F(1152000, P_XO, 1, 3, 50),
1589         F(1411200, P_GPLL1, 16, 1, 40),
1590         F(1536000, P_XO, 1, 2, 25),
1591         F(1600000, P_XO, 12, 0, 0),
1592         F(1728000, P_XO, 5, 9, 20),
1593         F(2048000, P_XO, 5, 8, 15),
1594         F(2304000, P_XO, 5, 3, 5),
1595         F(2400000, P_XO, 8, 0, 0),
1596         F(2822400, P_GPLL1, 16, 1, 20),
1597         F(3072000, P_XO, 5, 4, 5),
1598         F(4096000, P_GPLL1, 9, 2, 49),
1599         F(4800000, P_XO, 4, 0, 0),
1600         F(5644800, P_GPLL1, 16, 1, 10),
1601         F(6144000, P_GPLL1, 7, 1, 21),
1602         F(8192000, P_GPLL1, 9, 4, 49),
1603         F(9600000, P_XO, 2, 0, 0),
1604         F(11289600, P_GPLL1, 16, 1, 5),
1605         F(12288000, P_GPLL1, 7, 2, 21),
1606         { }
1607 };
1608
1609 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1610         .cmd_rcgr = 0x1c054,
1611         .hid_width = 5,
1612         .mnd_width = 8,
1613         .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1614         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1615         .clkr.hw.init = &(struct clk_init_data){
1616                 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1617                 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1618                 .num_parents = 5,
1619                 .ops = &clk_rcg2_ops,
1620         },
1621 };
1622
1623 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1624         .halt_reg = 0x1c068,
1625         .clkr = {
1626                 .enable_reg = 0x1c068,
1627                 .enable_mask = BIT(0),
1628                 .hw.init = &(struct clk_init_data){
1629                         .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1630                         .parent_data = &(const struct clk_parent_data){
1631                                 .hw = &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1632                         },
1633                         .num_parents = 1,
1634                         .flags = CLK_SET_RATE_PARENT,
1635                         .ops = &clk_branch2_ops,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1641         .cmd_rcgr = 0x1c06c,
1642         .hid_width = 5,
1643         .mnd_width = 8,
1644         .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1645         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1646         .clkr.hw.init = &(struct clk_init_data){
1647                 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1648                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1649                 .num_parents = 5,
1650                 .ops = &clk_rcg2_ops,
1651         },
1652 };
1653
1654 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1655         .halt_reg = 0x1c080,
1656         .clkr = {
1657                 .enable_reg = 0x1c080,
1658                 .enable_mask = BIT(0),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1661                         .parent_data = &(const struct clk_parent_data){
1662                                 .hw = &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1663                         },
1664                         .num_parents = 1,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1672         .cmd_rcgr = 0x1c084,
1673         .hid_width = 5,
1674         .mnd_width = 8,
1675         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1676         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1677         .clkr.hw.init = &(struct clk_init_data){
1678                 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1679                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1680                 .num_parents = 5,
1681                 .ops = &clk_rcg2_ops,
1682         },
1683 };
1684
1685 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1686         .halt_reg = 0x1c098,
1687         .clkr = {
1688                 .enable_reg = 0x1c098,
1689                 .enable_mask = BIT(0),
1690                 .hw.init = &(struct clk_init_data){
1691                         .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1692                         .parent_data = &(const struct clk_parent_data){
1693                                 .hw = &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1694                         },
1695                         .num_parents = 1,
1696                         .flags = CLK_SET_RATE_PARENT,
1697                         .ops = &clk_branch2_ops,
1698                 },
1699         },
1700 };
1701
1702 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1703         F(19200000, P_XO, 1, 0, 0),
1704         { }
1705 };
1706
1707 static struct clk_rcg2 ultaudio_xo_clk_src = {
1708         .cmd_rcgr = 0x1c034,
1709         .hid_width = 5,
1710         .parent_map = gcc_xo_sleep_map,
1711         .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1712         .clkr.hw.init = &(struct clk_init_data){
1713                 .name = "ultaudio_xo_clk_src",
1714                 .parent_data = gcc_xo_sleep_parent_data,
1715                 .num_parents = 2,
1716                 .ops = &clk_rcg2_ops,
1717         },
1718 };
1719
1720 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1721         .halt_reg = 0x1c04c,
1722         .clkr = {
1723                 .enable_reg = 0x1c04c,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_ultaudio_avsync_xo_clk",
1727                         .parent_data = &(const struct clk_parent_data){
1728                                 .hw = &ultaudio_xo_clk_src.clkr.hw,
1729                         },
1730                         .num_parents = 1,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                         .ops = &clk_branch2_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1738         .halt_reg = 0x1c050,
1739         .clkr = {
1740                 .enable_reg = 0x1c050,
1741                 .enable_mask = BIT(0),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_ultaudio_stc_xo_clk",
1744                         .parent_data = &(const struct clk_parent_data){
1745                                 .hw = &ultaudio_xo_clk_src.clkr.hw,
1746                         },
1747                         .num_parents = 1,
1748                         .flags = CLK_SET_RATE_PARENT,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static const struct freq_tbl ftbl_codec_clk[] = {
1755         F(9600000, P_XO, 2, 0, 0),
1756         F(12288000, P_XO, 1, 16, 25),
1757         F(19200000, P_XO, 1, 0, 0),
1758         F(11289600, P_EXT_MCLK, 1, 0, 0),
1759         { }
1760 };
1761
1762 static struct clk_rcg2 codec_digcodec_clk_src = {
1763         .cmd_rcgr = 0x1c09c,
1764         .mnd_width = 8,
1765         .hid_width = 5,
1766         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1767         .freq_tbl = ftbl_codec_clk,
1768         .clkr.hw.init = &(struct clk_init_data){
1769                 .name = "codec_digcodec_clk_src",
1770                 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1771                 .num_parents = 4,
1772                 .ops = &clk_rcg2_ops,
1773         },
1774 };
1775
1776 static struct clk_branch gcc_codec_digcodec_clk = {
1777         .halt_reg = 0x1c0b0,
1778         .clkr = {
1779                 .enable_reg = 0x1c0b0,
1780                 .enable_mask = BIT(0),
1781                 .hw.init = &(struct clk_init_data){
1782                         .name = "gcc_ultaudio_codec_digcodec_clk",
1783                         .parent_data = &(const struct clk_parent_data){
1784                                 .hw = &codec_digcodec_clk_src.clkr.hw,
1785                         },
1786                         .num_parents = 1,
1787                         .flags = CLK_SET_RATE_PARENT,
1788                         .ops = &clk_branch2_ops,
1789                 },
1790         },
1791 };
1792
1793 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1794         .halt_reg = 0x1c000,
1795         .clkr = {
1796                 .enable_reg = 0x1c000,
1797                 .enable_mask = BIT(0),
1798                 .hw.init = &(struct clk_init_data){
1799                         .name = "gcc_ultaudio_pcnoc_mport_clk",
1800                         .parent_data = &(const struct clk_parent_data){
1801                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1802                         },
1803                         .num_parents = 1,
1804                         .ops = &clk_branch2_ops,
1805                 },
1806         },
1807 };
1808
1809 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1810         .halt_reg = 0x1c004,
1811         .clkr = {
1812                 .enable_reg = 0x1c004,
1813                 .enable_mask = BIT(0),
1814                 .hw.init = &(struct clk_init_data){
1815                         .name = "gcc_ultaudio_pcnoc_sway_clk",
1816                         .parent_data = &(const struct clk_parent_data){
1817                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1818                         },
1819                         .num_parents = 1,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1826         F(100000000, P_GPLL0, 8, 0, 0),
1827         F(160000000, P_GPLL0, 5, 0, 0),
1828         F(228570000, P_GPLL0, 3.5, 0, 0),
1829         { }
1830 };
1831
1832 static struct clk_rcg2 vcodec0_clk_src = {
1833         .cmd_rcgr = 0x4C000,
1834         .mnd_width = 8,
1835         .hid_width = 5,
1836         .parent_map = gcc_xo_gpll0_map,
1837         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1838         .clkr.hw.init = &(struct clk_init_data){
1839                 .name = "vcodec0_clk_src",
1840                 .parent_data = gcc_xo_gpll0_parent_data,
1841                 .num_parents = 2,
1842                 .ops = &clk_rcg2_ops,
1843         },
1844 };
1845
1846 static struct clk_branch gcc_blsp1_ahb_clk = {
1847         .halt_reg = 0x01008,
1848         .halt_check = BRANCH_HALT_VOTED,
1849         .clkr = {
1850                 .enable_reg = 0x45004,
1851                 .enable_mask = BIT(10),
1852                 .hw.init = &(struct clk_init_data){
1853                         .name = "gcc_blsp1_ahb_clk",
1854                         .parent_data = &(const struct clk_parent_data){
1855                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1856                         },
1857                         .num_parents = 1,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_blsp1_sleep_clk = {
1864         .halt_reg = 0x01004,
1865         .clkr = {
1866                 .enable_reg = 0x01004,
1867                 .enable_mask = BIT(0),
1868                 .hw.init = &(struct clk_init_data){
1869                         .name = "gcc_blsp1_sleep_clk",
1870                         .ops = &clk_branch2_ops,
1871                 },
1872         },
1873 };
1874
1875 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1876         .halt_reg = 0x02008,
1877         .clkr = {
1878                 .enable_reg = 0x02008,
1879                 .enable_mask = BIT(0),
1880                 .hw.init = &(struct clk_init_data){
1881                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1882                         .parent_data = &(const struct clk_parent_data){
1883                                 .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1884                         },
1885                         .num_parents = 1,
1886                         .flags = CLK_SET_RATE_PARENT,
1887                         .ops = &clk_branch2_ops,
1888                 },
1889         },
1890 };
1891
1892 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1893         .halt_reg = 0x02004,
1894         .clkr = {
1895                 .enable_reg = 0x02004,
1896                 .enable_mask = BIT(0),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1899                         .parent_data = &(const struct clk_parent_data){
1900                                 .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1901                         },
1902                         .num_parents = 1,
1903                         .flags = CLK_SET_RATE_PARENT,
1904                         .ops = &clk_branch2_ops,
1905                 },
1906         },
1907 };
1908
1909 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1910         .halt_reg = 0x03010,
1911         .clkr = {
1912                 .enable_reg = 0x03010,
1913                 .enable_mask = BIT(0),
1914                 .hw.init = &(struct clk_init_data){
1915                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1916                         .parent_data = &(const struct clk_parent_data){
1917                                 .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1918                         },
1919                         .num_parents = 1,
1920                         .flags = CLK_SET_RATE_PARENT,
1921                         .ops = &clk_branch2_ops,
1922                 },
1923         },
1924 };
1925
1926 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1927         .halt_reg = 0x0300c,
1928         .clkr = {
1929                 .enable_reg = 0x0300c,
1930                 .enable_mask = BIT(0),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1933                         .parent_data = &(const struct clk_parent_data){
1934                                 .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1935                         },
1936                         .num_parents = 1,
1937                         .flags = CLK_SET_RATE_PARENT,
1938                         .ops = &clk_branch2_ops,
1939                 },
1940         },
1941 };
1942
1943 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1944         .halt_reg = 0x04020,
1945         .clkr = {
1946                 .enable_reg = 0x04020,
1947                 .enable_mask = BIT(0),
1948                 .hw.init = &(struct clk_init_data){
1949                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1950                         .parent_data = &(const struct clk_parent_data){
1951                                 .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1952                         },
1953                         .num_parents = 1,
1954                         .flags = CLK_SET_RATE_PARENT,
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1961         .halt_reg = 0x0401c,
1962         .clkr = {
1963                 .enable_reg = 0x0401c,
1964                 .enable_mask = BIT(0),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1967                         .parent_data = &(const struct clk_parent_data){
1968                                 .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1969                         },
1970                         .num_parents = 1,
1971                         .flags = CLK_SET_RATE_PARENT,
1972                         .ops = &clk_branch2_ops,
1973                 },
1974         },
1975 };
1976
1977 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1978         .halt_reg = 0x05020,
1979         .clkr = {
1980                 .enable_reg = 0x05020,
1981                 .enable_mask = BIT(0),
1982                 .hw.init = &(struct clk_init_data){
1983                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1984                         .parent_data = &(const struct clk_parent_data){
1985                                 .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1986                         },
1987                         .num_parents = 1,
1988                         .flags = CLK_SET_RATE_PARENT,
1989                         .ops = &clk_branch2_ops,
1990                 },
1991         },
1992 };
1993
1994 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1995         .halt_reg = 0x0501c,
1996         .clkr = {
1997                 .enable_reg = 0x0501c,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2001                         .parent_data = &(const struct clk_parent_data){
2002                                 .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2003                         },
2004                         .num_parents = 1,
2005                         .flags = CLK_SET_RATE_PARENT,
2006                         .ops = &clk_branch2_ops,
2007                 },
2008         },
2009 };
2010
2011 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2012         .halt_reg = 0x06020,
2013         .clkr = {
2014                 .enable_reg = 0x06020,
2015                 .enable_mask = BIT(0),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2018                         .parent_data = &(const struct clk_parent_data){
2019                                 .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2020                         },
2021                         .num_parents = 1,
2022                         .flags = CLK_SET_RATE_PARENT,
2023                         .ops = &clk_branch2_ops,
2024                 },
2025         },
2026 };
2027
2028 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2029         .halt_reg = 0x0601c,
2030         .clkr = {
2031                 .enable_reg = 0x0601c,
2032                 .enable_mask = BIT(0),
2033                 .hw.init = &(struct clk_init_data){
2034                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2035                         .parent_data = &(const struct clk_parent_data){
2036                                 .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2037                         },
2038                         .num_parents = 1,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                         .ops = &clk_branch2_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2046         .halt_reg = 0x07020,
2047         .clkr = {
2048                 .enable_reg = 0x07020,
2049                 .enable_mask = BIT(0),
2050                 .hw.init = &(struct clk_init_data){
2051                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2052                         .parent_data = &(const struct clk_parent_data){
2053                                 .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2054                         },
2055                         .num_parents = 1,
2056                         .flags = CLK_SET_RATE_PARENT,
2057                         .ops = &clk_branch2_ops,
2058                 },
2059         },
2060 };
2061
2062 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2063         .halt_reg = 0x0701c,
2064         .clkr = {
2065                 .enable_reg = 0x0701c,
2066                 .enable_mask = BIT(0),
2067                 .hw.init = &(struct clk_init_data){
2068                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2069                         .parent_data = &(const struct clk_parent_data){
2070                                 .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2071                         },
2072                         .num_parents = 1,
2073                         .flags = CLK_SET_RATE_PARENT,
2074                         .ops = &clk_branch2_ops,
2075                 },
2076         },
2077 };
2078
2079 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2080         .halt_reg = 0x0203c,
2081         .clkr = {
2082                 .enable_reg = 0x0203c,
2083                 .enable_mask = BIT(0),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "gcc_blsp1_uart1_apps_clk",
2086                         .parent_data = &(const struct clk_parent_data){
2087                                 .hw = &blsp1_uart1_apps_clk_src.clkr.hw,
2088                         },
2089                         .num_parents = 1,
2090                         .flags = CLK_SET_RATE_PARENT,
2091                         .ops = &clk_branch2_ops,
2092                 },
2093         },
2094 };
2095
2096 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2097         .halt_reg = 0x0302c,
2098         .clkr = {
2099                 .enable_reg = 0x0302c,
2100                 .enable_mask = BIT(0),
2101                 .hw.init = &(struct clk_init_data){
2102                         .name = "gcc_blsp1_uart2_apps_clk",
2103                         .parent_data = &(const struct clk_parent_data){
2104                                 .hw = &blsp1_uart2_apps_clk_src.clkr.hw,
2105                         },
2106                         .num_parents = 1,
2107                         .flags = CLK_SET_RATE_PARENT,
2108                         .ops = &clk_branch2_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_branch gcc_boot_rom_ahb_clk = {
2114         .halt_reg = 0x1300c,
2115         .halt_check = BRANCH_HALT_VOTED,
2116         .clkr = {
2117                 .enable_reg = 0x45004,
2118                 .enable_mask = BIT(7),
2119                 .hw.init = &(struct clk_init_data){
2120                         .name = "gcc_boot_rom_ahb_clk",
2121                         .parent_data = &(const struct clk_parent_data){
2122                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2123                         },
2124                         .num_parents = 1,
2125                         .ops = &clk_branch2_ops,
2126                 },
2127         },
2128 };
2129
2130 static struct clk_branch gcc_camss_cci_ahb_clk = {
2131         .halt_reg = 0x5101c,
2132         .clkr = {
2133                 .enable_reg = 0x5101c,
2134                 .enable_mask = BIT(0),
2135                 .hw.init = &(struct clk_init_data){
2136                         .name = "gcc_camss_cci_ahb_clk",
2137                         .parent_data = &(const struct clk_parent_data){
2138                                 .hw = &camss_ahb_clk_src.clkr.hw,
2139                         },
2140                         .num_parents = 1,
2141                         .flags = CLK_SET_RATE_PARENT,
2142                         .ops = &clk_branch2_ops,
2143                 },
2144         },
2145 };
2146
2147 static struct clk_branch gcc_camss_cci_clk = {
2148         .halt_reg = 0x51018,
2149         .clkr = {
2150                 .enable_reg = 0x51018,
2151                 .enable_mask = BIT(0),
2152                 .hw.init = &(struct clk_init_data){
2153                         .name = "gcc_camss_cci_clk",
2154                         .parent_data = &(const struct clk_parent_data){
2155                                 .hw = &cci_clk_src.clkr.hw,
2156                         },
2157                         .num_parents = 1,
2158                         .flags = CLK_SET_RATE_PARENT,
2159                         .ops = &clk_branch2_ops,
2160                 },
2161         },
2162 };
2163
2164 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2165         .halt_reg = 0x4e040,
2166         .clkr = {
2167                 .enable_reg = 0x4e040,
2168                 .enable_mask = BIT(0),
2169                 .hw.init = &(struct clk_init_data){
2170                         .name = "gcc_camss_csi0_ahb_clk",
2171                         .parent_data = &(const struct clk_parent_data){
2172                                 .hw = &camss_ahb_clk_src.clkr.hw,
2173                         },
2174                         .num_parents = 1,
2175                         .flags = CLK_SET_RATE_PARENT,
2176                         .ops = &clk_branch2_ops,
2177                 },
2178         },
2179 };
2180
2181 static struct clk_branch gcc_camss_csi0_clk = {
2182         .halt_reg = 0x4e03c,
2183         .clkr = {
2184                 .enable_reg = 0x4e03c,
2185                 .enable_mask = BIT(0),
2186                 .hw.init = &(struct clk_init_data){
2187                         .name = "gcc_camss_csi0_clk",
2188                         .parent_data = &(const struct clk_parent_data){
2189                                 .hw = &csi0_clk_src.clkr.hw,
2190                         },
2191                         .num_parents = 1,
2192                         .flags = CLK_SET_RATE_PARENT,
2193                         .ops = &clk_branch2_ops,
2194                 },
2195         },
2196 };
2197
2198 static struct clk_branch gcc_camss_csi0phy_clk = {
2199         .halt_reg = 0x4e048,
2200         .clkr = {
2201                 .enable_reg = 0x4e048,
2202                 .enable_mask = BIT(0),
2203                 .hw.init = &(struct clk_init_data){
2204                         .name = "gcc_camss_csi0phy_clk",
2205                         .parent_data = &(const struct clk_parent_data){
2206                                 .hw = &csi0_clk_src.clkr.hw,
2207                         },
2208                         .num_parents = 1,
2209                         .flags = CLK_SET_RATE_PARENT,
2210                         .ops = &clk_branch2_ops,
2211                 },
2212         },
2213 };
2214
2215 static struct clk_branch gcc_camss_csi0pix_clk = {
2216         .halt_reg = 0x4e058,
2217         .clkr = {
2218                 .enable_reg = 0x4e058,
2219                 .enable_mask = BIT(0),
2220                 .hw.init = &(struct clk_init_data){
2221                         .name = "gcc_camss_csi0pix_clk",
2222                         .parent_data = &(const struct clk_parent_data){
2223                                 .hw = &csi0_clk_src.clkr.hw,
2224                         },
2225                         .num_parents = 1,
2226                         .flags = CLK_SET_RATE_PARENT,
2227                         .ops = &clk_branch2_ops,
2228                 },
2229         },
2230 };
2231
2232 static struct clk_branch gcc_camss_csi0rdi_clk = {
2233         .halt_reg = 0x4e050,
2234         .clkr = {
2235                 .enable_reg = 0x4e050,
2236                 .enable_mask = BIT(0),
2237                 .hw.init = &(struct clk_init_data){
2238                         .name = "gcc_camss_csi0rdi_clk",
2239                         .parent_data = &(const struct clk_parent_data){
2240                                 .hw = &csi0_clk_src.clkr.hw,
2241                         },
2242                         .num_parents = 1,
2243                         .flags = CLK_SET_RATE_PARENT,
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2250         .halt_reg = 0x4f040,
2251         .clkr = {
2252                 .enable_reg = 0x4f040,
2253                 .enable_mask = BIT(0),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "gcc_camss_csi1_ahb_clk",
2256                         .parent_data = &(const struct clk_parent_data){
2257                                 .hw = &camss_ahb_clk_src.clkr.hw,
2258                         },
2259                         .num_parents = 1,
2260                         .flags = CLK_SET_RATE_PARENT,
2261                         .ops = &clk_branch2_ops,
2262                 },
2263         },
2264 };
2265
2266 static struct clk_branch gcc_camss_csi1_clk = {
2267         .halt_reg = 0x4f03c,
2268         .clkr = {
2269                 .enable_reg = 0x4f03c,
2270                 .enable_mask = BIT(0),
2271                 .hw.init = &(struct clk_init_data){
2272                         .name = "gcc_camss_csi1_clk",
2273                         .parent_data = &(const struct clk_parent_data){
2274                                 .hw = &csi1_clk_src.clkr.hw,
2275                         },
2276                         .num_parents = 1,
2277                         .flags = CLK_SET_RATE_PARENT,
2278                         .ops = &clk_branch2_ops,
2279                 },
2280         },
2281 };
2282
2283 static struct clk_branch gcc_camss_csi1phy_clk = {
2284         .halt_reg = 0x4f048,
2285         .clkr = {
2286                 .enable_reg = 0x4f048,
2287                 .enable_mask = BIT(0),
2288                 .hw.init = &(struct clk_init_data){
2289                         .name = "gcc_camss_csi1phy_clk",
2290                         .parent_data = &(const struct clk_parent_data){
2291                                 .hw = &csi1_clk_src.clkr.hw,
2292                         },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_camss_csi1pix_clk = {
2301         .halt_reg = 0x4f058,
2302         .clkr = {
2303                 .enable_reg = 0x4f058,
2304                 .enable_mask = BIT(0),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "gcc_camss_csi1pix_clk",
2307                         .parent_data = &(const struct clk_parent_data){
2308                                 .hw = &csi1_clk_src.clkr.hw,
2309                         },
2310                         .num_parents = 1,
2311                         .flags = CLK_SET_RATE_PARENT,
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static struct clk_branch gcc_camss_csi1rdi_clk = {
2318         .halt_reg = 0x4f050,
2319         .clkr = {
2320                 .enable_reg = 0x4f050,
2321                 .enable_mask = BIT(0),
2322                 .hw.init = &(struct clk_init_data){
2323                         .name = "gcc_camss_csi1rdi_clk",
2324                         .parent_data = &(const struct clk_parent_data){
2325                                 .hw = &csi1_clk_src.clkr.hw,
2326                         },
2327                         .num_parents = 1,
2328                         .flags = CLK_SET_RATE_PARENT,
2329                         .ops = &clk_branch2_ops,
2330                 },
2331         },
2332 };
2333
2334 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2335         .halt_reg = 0x58050,
2336         .clkr = {
2337                 .enable_reg = 0x58050,
2338                 .enable_mask = BIT(0),
2339                 .hw.init = &(struct clk_init_data){
2340                         .name = "gcc_camss_csi_vfe0_clk",
2341                         .parent_data = &(const struct clk_parent_data){
2342                                 .hw = &vfe0_clk_src.clkr.hw,
2343                         },
2344                         .num_parents = 1,
2345                         .flags = CLK_SET_RATE_PARENT,
2346                         .ops = &clk_branch2_ops,
2347                 },
2348         },
2349 };
2350
2351 static struct clk_branch gcc_camss_gp0_clk = {
2352         .halt_reg = 0x54018,
2353         .clkr = {
2354                 .enable_reg = 0x54018,
2355                 .enable_mask = BIT(0),
2356                 .hw.init = &(struct clk_init_data){
2357                         .name = "gcc_camss_gp0_clk",
2358                         .parent_data = &(const struct clk_parent_data){
2359                                 .hw = &camss_gp0_clk_src.clkr.hw,
2360                         },
2361                         .num_parents = 1,
2362                         .flags = CLK_SET_RATE_PARENT,
2363                         .ops = &clk_branch2_ops,
2364                 },
2365         },
2366 };
2367
2368 static struct clk_branch gcc_camss_gp1_clk = {
2369         .halt_reg = 0x55018,
2370         .clkr = {
2371                 .enable_reg = 0x55018,
2372                 .enable_mask = BIT(0),
2373                 .hw.init = &(struct clk_init_data){
2374                         .name = "gcc_camss_gp1_clk",
2375                         .parent_data = &(const struct clk_parent_data){
2376                                 .hw = &camss_gp1_clk_src.clkr.hw,
2377                         },
2378                         .num_parents = 1,
2379                         .flags = CLK_SET_RATE_PARENT,
2380                         .ops = &clk_branch2_ops,
2381                 },
2382         },
2383 };
2384
2385 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2386         .halt_reg = 0x50004,
2387         .clkr = {
2388                 .enable_reg = 0x50004,
2389                 .enable_mask = BIT(0),
2390                 .hw.init = &(struct clk_init_data){
2391                         .name = "gcc_camss_ispif_ahb_clk",
2392                         .parent_data = &(const struct clk_parent_data){
2393                                 .hw = &camss_ahb_clk_src.clkr.hw,
2394                         },
2395                         .num_parents = 1,
2396                         .flags = CLK_SET_RATE_PARENT,
2397                         .ops = &clk_branch2_ops,
2398                 },
2399         },
2400 };
2401
2402 static struct clk_branch gcc_camss_jpeg0_clk = {
2403         .halt_reg = 0x57020,
2404         .clkr = {
2405                 .enable_reg = 0x57020,
2406                 .enable_mask = BIT(0),
2407                 .hw.init = &(struct clk_init_data){
2408                         .name = "gcc_camss_jpeg0_clk",
2409                         .parent_data = &(const struct clk_parent_data){
2410                                 .hw = &jpeg0_clk_src.clkr.hw,
2411                         },
2412                         .num_parents = 1,
2413                         .flags = CLK_SET_RATE_PARENT,
2414                         .ops = &clk_branch2_ops,
2415                 },
2416         },
2417 };
2418
2419 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2420         .halt_reg = 0x57024,
2421         .clkr = {
2422                 .enable_reg = 0x57024,
2423                 .enable_mask = BIT(0),
2424                 .hw.init = &(struct clk_init_data){
2425                         .name = "gcc_camss_jpeg_ahb_clk",
2426                         .parent_data = &(const struct clk_parent_data){
2427                                 .hw = &camss_ahb_clk_src.clkr.hw,
2428                         },
2429                         .num_parents = 1,
2430                         .flags = CLK_SET_RATE_PARENT,
2431                         .ops = &clk_branch2_ops,
2432                 },
2433         },
2434 };
2435
2436 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2437         .halt_reg = 0x57028,
2438         .clkr = {
2439                 .enable_reg = 0x57028,
2440                 .enable_mask = BIT(0),
2441                 .hw.init = &(struct clk_init_data){
2442                         .name = "gcc_camss_jpeg_axi_clk",
2443                         .parent_data = &(const struct clk_parent_data){
2444                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2445                         },
2446                         .num_parents = 1,
2447                         .flags = CLK_SET_RATE_PARENT,
2448                         .ops = &clk_branch2_ops,
2449                 },
2450         },
2451 };
2452
2453 static struct clk_branch gcc_camss_mclk0_clk = {
2454         .halt_reg = 0x52018,
2455         .clkr = {
2456                 .enable_reg = 0x52018,
2457                 .enable_mask = BIT(0),
2458                 .hw.init = &(struct clk_init_data){
2459                         .name = "gcc_camss_mclk0_clk",
2460                         .parent_data = &(const struct clk_parent_data){
2461                                 .hw = &mclk0_clk_src.clkr.hw,
2462                         },
2463                         .num_parents = 1,
2464                         .flags = CLK_SET_RATE_PARENT,
2465                         .ops = &clk_branch2_ops,
2466                 },
2467         },
2468 };
2469
2470 static struct clk_branch gcc_camss_mclk1_clk = {
2471         .halt_reg = 0x53018,
2472         .clkr = {
2473                 .enable_reg = 0x53018,
2474                 .enable_mask = BIT(0),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "gcc_camss_mclk1_clk",
2477                         .parent_data = &(const struct clk_parent_data){
2478                                 .hw = &mclk1_clk_src.clkr.hw,
2479                         },
2480                         .num_parents = 1,
2481                         .flags = CLK_SET_RATE_PARENT,
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_camss_micro_ahb_clk = {
2488         .halt_reg = 0x5600c,
2489         .clkr = {
2490                 .enable_reg = 0x5600c,
2491                 .enable_mask = BIT(0),
2492                 .hw.init = &(struct clk_init_data){
2493                         .name = "gcc_camss_micro_ahb_clk",
2494                         .parent_data = &(const struct clk_parent_data){
2495                                 .hw = &camss_ahb_clk_src.clkr.hw,
2496                         },
2497                         .num_parents = 1,
2498                         .flags = CLK_SET_RATE_PARENT,
2499                         .ops = &clk_branch2_ops,
2500                 },
2501         },
2502 };
2503
2504 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2505         .halt_reg = 0x4e01c,
2506         .clkr = {
2507                 .enable_reg = 0x4e01c,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "gcc_camss_csi0phytimer_clk",
2511                         .parent_data = &(const struct clk_parent_data){
2512                                 .hw = &csi0phytimer_clk_src.clkr.hw,
2513                         },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2522         .halt_reg = 0x4f01c,
2523         .clkr = {
2524                 .enable_reg = 0x4f01c,
2525                 .enable_mask = BIT(0),
2526                 .hw.init = &(struct clk_init_data){
2527                         .name = "gcc_camss_csi1phytimer_clk",
2528                         .parent_data = &(const struct clk_parent_data){
2529                                 .hw = &csi1phytimer_clk_src.clkr.hw,
2530                         },
2531                         .num_parents = 1,
2532                         .flags = CLK_SET_RATE_PARENT,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_camss_ahb_clk = {
2539         .halt_reg = 0x5a014,
2540         .clkr = {
2541                 .enable_reg = 0x5a014,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_camss_ahb_clk",
2545                         .parent_data = &(const struct clk_parent_data){
2546                                 .hw = &camss_ahb_clk_src.clkr.hw,
2547                         },
2548                         .num_parents = 1,
2549                         .flags = CLK_SET_RATE_PARENT,
2550                         .ops = &clk_branch2_ops,
2551                 },
2552         },
2553 };
2554
2555 static struct clk_branch gcc_camss_top_ahb_clk = {
2556         .halt_reg = 0x56004,
2557         .clkr = {
2558                 .enable_reg = 0x56004,
2559                 .enable_mask = BIT(0),
2560                 .hw.init = &(struct clk_init_data){
2561                         .name = "gcc_camss_top_ahb_clk",
2562                         .parent_data = &(const struct clk_parent_data){
2563                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2564                         },
2565                         .num_parents = 1,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                         .ops = &clk_branch2_ops,
2568                 },
2569         },
2570 };
2571
2572 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2573         .halt_reg = 0x58040,
2574         .clkr = {
2575                 .enable_reg = 0x58040,
2576                 .enable_mask = BIT(0),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "gcc_camss_cpp_ahb_clk",
2579                         .parent_data = &(const struct clk_parent_data){
2580                                 .hw = &camss_ahb_clk_src.clkr.hw,
2581                         },
2582                         .num_parents = 1,
2583                         .flags = CLK_SET_RATE_PARENT,
2584                         .ops = &clk_branch2_ops,
2585                 },
2586         },
2587 };
2588
2589 static struct clk_branch gcc_camss_cpp_clk = {
2590         .halt_reg = 0x5803c,
2591         .clkr = {
2592                 .enable_reg = 0x5803c,
2593                 .enable_mask = BIT(0),
2594                 .hw.init = &(struct clk_init_data){
2595                         .name = "gcc_camss_cpp_clk",
2596                         .parent_data = &(const struct clk_parent_data){
2597                                 .hw = &cpp_clk_src.clkr.hw,
2598                         },
2599                         .num_parents = 1,
2600                         .flags = CLK_SET_RATE_PARENT,
2601                         .ops = &clk_branch2_ops,
2602                 },
2603         },
2604 };
2605
2606 static struct clk_branch gcc_camss_vfe0_clk = {
2607         .halt_reg = 0x58038,
2608         .clkr = {
2609                 .enable_reg = 0x58038,
2610                 .enable_mask = BIT(0),
2611                 .hw.init = &(struct clk_init_data){
2612                         .name = "gcc_camss_vfe0_clk",
2613                         .parent_data = &(const struct clk_parent_data){
2614                                 .hw = &vfe0_clk_src.clkr.hw,
2615                         },
2616                         .num_parents = 1,
2617                         .flags = CLK_SET_RATE_PARENT,
2618                         .ops = &clk_branch2_ops,
2619                 },
2620         },
2621 };
2622
2623 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2624         .halt_reg = 0x58044,
2625         .clkr = {
2626                 .enable_reg = 0x58044,
2627                 .enable_mask = BIT(0),
2628                 .hw.init = &(struct clk_init_data){
2629                         .name = "gcc_camss_vfe_ahb_clk",
2630                         .parent_data = &(const struct clk_parent_data){
2631                                 .hw = &camss_ahb_clk_src.clkr.hw,
2632                         },
2633                         .num_parents = 1,
2634                         .flags = CLK_SET_RATE_PARENT,
2635                         .ops = &clk_branch2_ops,
2636                 },
2637         },
2638 };
2639
2640 static struct clk_branch gcc_camss_vfe_axi_clk = {
2641         .halt_reg = 0x58048,
2642         .clkr = {
2643                 .enable_reg = 0x58048,
2644                 .enable_mask = BIT(0),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "gcc_camss_vfe_axi_clk",
2647                         .parent_data = &(const struct clk_parent_data){
2648                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2649                         },
2650                         .num_parents = 1,
2651                         .flags = CLK_SET_RATE_PARENT,
2652                         .ops = &clk_branch2_ops,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch gcc_crypto_ahb_clk = {
2658         .halt_reg = 0x16024,
2659         .halt_check = BRANCH_HALT_VOTED,
2660         .clkr = {
2661                 .enable_reg = 0x45004,
2662                 .enable_mask = BIT(0),
2663                 .hw.init = &(struct clk_init_data){
2664                         .name = "gcc_crypto_ahb_clk",
2665                         .parent_data = &(const struct clk_parent_data){
2666                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2667                         },
2668                         .num_parents = 1,
2669                         .flags = CLK_SET_RATE_PARENT,
2670                         .ops = &clk_branch2_ops,
2671                 },
2672         },
2673 };
2674
2675 static struct clk_branch gcc_crypto_axi_clk = {
2676         .halt_reg = 0x16020,
2677         .halt_check = BRANCH_HALT_VOTED,
2678         .clkr = {
2679                 .enable_reg = 0x45004,
2680                 .enable_mask = BIT(1),
2681                 .hw.init = &(struct clk_init_data){
2682                         .name = "gcc_crypto_axi_clk",
2683                         .parent_data = &(const struct clk_parent_data){
2684                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2685                         },
2686                         .num_parents = 1,
2687                         .flags = CLK_SET_RATE_PARENT,
2688                         .ops = &clk_branch2_ops,
2689                 },
2690         },
2691 };
2692
2693 static struct clk_branch gcc_crypto_clk = {
2694         .halt_reg = 0x1601c,
2695         .halt_check = BRANCH_HALT_VOTED,
2696         .clkr = {
2697                 .enable_reg = 0x45004,
2698                 .enable_mask = BIT(2),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "gcc_crypto_clk",
2701                         .parent_data = &(const struct clk_parent_data){
2702                                 .hw = &crypto_clk_src.clkr.hw,
2703                         },
2704                         .num_parents = 1,
2705                         .flags = CLK_SET_RATE_PARENT,
2706                         .ops = &clk_branch2_ops,
2707                 },
2708         },
2709 };
2710
2711 static struct clk_branch gcc_oxili_gmem_clk = {
2712         .halt_reg = 0x59024,
2713         .clkr = {
2714                 .enable_reg = 0x59024,
2715                 .enable_mask = BIT(0),
2716                 .hw.init = &(struct clk_init_data){
2717                         .name = "gcc_oxili_gmem_clk",
2718                         .parent_data = &(const struct clk_parent_data){
2719                                 .hw = &gfx3d_clk_src.clkr.hw,
2720                         },
2721                         .num_parents = 1,
2722                         .flags = CLK_SET_RATE_PARENT,
2723                         .ops = &clk_branch2_ops,
2724                 },
2725         },
2726 };
2727
2728 static struct clk_branch gcc_gp1_clk = {
2729         .halt_reg = 0x08000,
2730         .clkr = {
2731                 .enable_reg = 0x08000,
2732                 .enable_mask = BIT(0),
2733                 .hw.init = &(struct clk_init_data){
2734                         .name = "gcc_gp1_clk",
2735                         .parent_data = &(const struct clk_parent_data){
2736                                 .hw = &gp1_clk_src.clkr.hw,
2737                         },
2738                         .num_parents = 1,
2739                         .flags = CLK_SET_RATE_PARENT,
2740                         .ops = &clk_branch2_ops,
2741                 },
2742         },
2743 };
2744
2745 static struct clk_branch gcc_gp2_clk = {
2746         .halt_reg = 0x09000,
2747         .clkr = {
2748                 .enable_reg = 0x09000,
2749                 .enable_mask = BIT(0),
2750                 .hw.init = &(struct clk_init_data){
2751                         .name = "gcc_gp2_clk",
2752                         .parent_data = &(const struct clk_parent_data){
2753                                 .hw = &gp2_clk_src.clkr.hw,
2754                         },
2755                         .num_parents = 1,
2756                         .flags = CLK_SET_RATE_PARENT,
2757                         .ops = &clk_branch2_ops,
2758                 },
2759         },
2760 };
2761
2762 static struct clk_branch gcc_gp3_clk = {
2763         .halt_reg = 0x0a000,
2764         .clkr = {
2765                 .enable_reg = 0x0a000,
2766                 .enable_mask = BIT(0),
2767                 .hw.init = &(struct clk_init_data){
2768                         .name = "gcc_gp3_clk",
2769                         .parent_data = &(const struct clk_parent_data){
2770                                 .hw = &gp3_clk_src.clkr.hw,
2771                         },
2772                         .num_parents = 1,
2773                         .flags = CLK_SET_RATE_PARENT,
2774                         .ops = &clk_branch2_ops,
2775                 },
2776         },
2777 };
2778
2779 static struct clk_branch gcc_mdss_ahb_clk = {
2780         .halt_reg = 0x4d07c,
2781         .clkr = {
2782                 .enable_reg = 0x4d07c,
2783                 .enable_mask = BIT(0),
2784                 .hw.init = &(struct clk_init_data){
2785                         .name = "gcc_mdss_ahb_clk",
2786                         .parent_data = &(const struct clk_parent_data){
2787                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2788                         },
2789                         .num_parents = 1,
2790                         .flags = CLK_SET_RATE_PARENT,
2791                         .ops = &clk_branch2_ops,
2792                 },
2793         },
2794 };
2795
2796 static struct clk_branch gcc_mdss_axi_clk = {
2797         .halt_reg = 0x4d080,
2798         .clkr = {
2799                 .enable_reg = 0x4d080,
2800                 .enable_mask = BIT(0),
2801                 .hw.init = &(struct clk_init_data){
2802                         .name = "gcc_mdss_axi_clk",
2803                         .parent_data = &(const struct clk_parent_data){
2804                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2805                         },
2806                         .num_parents = 1,
2807                         .flags = CLK_SET_RATE_PARENT,
2808                         .ops = &clk_branch2_ops,
2809                 },
2810         },
2811 };
2812
2813 static struct clk_branch gcc_mdss_byte0_clk = {
2814         .halt_reg = 0x4d094,
2815         .clkr = {
2816                 .enable_reg = 0x4d094,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_mdss_byte0_clk",
2820                         .parent_data = &(const struct clk_parent_data){
2821                                 .hw = &byte0_clk_src.clkr.hw,
2822                         },
2823                         .num_parents = 1,
2824                         .flags = CLK_SET_RATE_PARENT,
2825                         .ops = &clk_branch2_ops,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch gcc_mdss_byte1_clk = {
2831         .halt_reg = 0x4d0a0,
2832         .clkr = {
2833                 .enable_reg = 0x4d0a0,
2834                 .enable_mask = BIT(0),
2835                 .hw.init = &(struct clk_init_data){
2836                         .name = "gcc_mdss_byte1_clk",
2837                         .parent_data = &(const struct clk_parent_data){
2838                                 .hw = &byte1_clk_src.clkr.hw,
2839                         },
2840                         .num_parents = 1,
2841                         .flags = CLK_SET_RATE_PARENT,
2842                         .ops = &clk_branch2_ops,
2843                 },
2844         },
2845 };
2846
2847 static struct clk_branch gcc_mdss_esc0_clk = {
2848         .halt_reg = 0x4d098,
2849         .clkr = {
2850                 .enable_reg = 0x4d098,
2851                 .enable_mask = BIT(0),
2852                 .hw.init = &(struct clk_init_data){
2853                         .name = "gcc_mdss_esc0_clk",
2854                         .parent_data = &(const struct clk_parent_data){
2855                                 .hw = &esc0_clk_src.clkr.hw,
2856                         },
2857                         .num_parents = 1,
2858                         .flags = CLK_SET_RATE_PARENT,
2859                         .ops = &clk_branch2_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch gcc_mdss_esc1_clk = {
2865         .halt_reg = 0x4d09c,
2866         .clkr = {
2867                 .enable_reg = 0x4d09c,
2868                 .enable_mask = BIT(0),
2869                 .hw.init = &(struct clk_init_data){
2870                         .name = "gcc_mdss_esc1_clk",
2871                         .parent_data = &(const struct clk_parent_data){
2872                                 .hw = &esc1_clk_src.clkr.hw,
2873                         },
2874                         .num_parents = 1,
2875                         .flags = CLK_SET_RATE_PARENT,
2876                         .ops = &clk_branch2_ops,
2877                 },
2878         },
2879 };
2880
2881 static struct clk_branch gcc_mdss_mdp_clk = {
2882         .halt_reg = 0x4D088,
2883         .clkr = {
2884                 .enable_reg = 0x4D088,
2885                 .enable_mask = BIT(0),
2886                 .hw.init = &(struct clk_init_data){
2887                         .name = "gcc_mdss_mdp_clk",
2888                         .parent_data = &(const struct clk_parent_data){
2889                                 .hw = &mdp_clk_src.clkr.hw,
2890                         },
2891                         .num_parents = 1,
2892                         .flags = CLK_SET_RATE_PARENT,
2893                         .ops = &clk_branch2_ops,
2894                 },
2895         },
2896 };
2897
2898 static struct clk_branch gcc_mdss_pclk0_clk = {
2899         .halt_reg = 0x4d084,
2900         .clkr = {
2901                 .enable_reg = 0x4d084,
2902                 .enable_mask = BIT(0),
2903                 .hw.init = &(struct clk_init_data){
2904                         .name = "gcc_mdss_pclk0_clk",
2905                         .parent_data = &(const struct clk_parent_data){
2906                                 .hw = &pclk0_clk_src.clkr.hw,
2907                         },
2908                         .num_parents = 1,
2909                         .flags = CLK_SET_RATE_PARENT,
2910                         .ops = &clk_branch2_ops,
2911                 },
2912         },
2913 };
2914
2915 static struct clk_branch gcc_mdss_pclk1_clk = {
2916         .halt_reg = 0x4d0a4,
2917         .clkr = {
2918                 .enable_reg = 0x4d0a4,
2919                 .enable_mask = BIT(0),
2920                 .hw.init = &(struct clk_init_data){
2921                         .name = "gcc_mdss_pclk1_clk",
2922                         .parent_data = &(const struct clk_parent_data){
2923                                 .hw = &pclk1_clk_src.clkr.hw,
2924                         },
2925                         .num_parents = 1,
2926                         .flags = CLK_SET_RATE_PARENT,
2927                         .ops = &clk_branch2_ops,
2928                 },
2929         },
2930 };
2931
2932 static struct clk_branch gcc_mdss_vsync_clk = {
2933         .halt_reg = 0x4d090,
2934         .clkr = {
2935                 .enable_reg = 0x4d090,
2936                 .enable_mask = BIT(0),
2937                 .hw.init = &(struct clk_init_data){
2938                         .name = "gcc_mdss_vsync_clk",
2939                         .parent_data = &(const struct clk_parent_data){
2940                                 .hw = &vsync_clk_src.clkr.hw,
2941                         },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2950         .halt_reg = 0x49000,
2951         .clkr = {
2952                 .enable_reg = 0x49000,
2953                 .enable_mask = BIT(0),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "gcc_mss_cfg_ahb_clk",
2956                         .parent_data = &(const struct clk_parent_data){
2957                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2958                         },
2959                         .num_parents = 1,
2960                         .flags = CLK_SET_RATE_PARENT,
2961                         .ops = &clk_branch2_ops,
2962                 },
2963         },
2964 };
2965
2966 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2967         .halt_reg = 0x49004,
2968         .clkr = {
2969                 .enable_reg = 0x49004,
2970                 .enable_mask = BIT(0),
2971                 .hw.init = &(struct clk_init_data){
2972                         .name = "gcc_mss_q6_bimc_axi_clk",
2973                         .parent_data = &(const struct clk_parent_data){
2974                                 .hw = &bimc_ddr_clk_src.clkr.hw,
2975                         },
2976                         .num_parents = 1,
2977                         .flags = CLK_SET_RATE_PARENT,
2978                         .ops = &clk_branch2_ops,
2979                 },
2980         },
2981 };
2982
2983 static struct clk_branch gcc_oxili_ahb_clk = {
2984         .halt_reg = 0x59028,
2985         .clkr = {
2986                 .enable_reg = 0x59028,
2987                 .enable_mask = BIT(0),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "gcc_oxili_ahb_clk",
2990                         .parent_data = &(const struct clk_parent_data){
2991                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2992                         },
2993                         .num_parents = 1,
2994                         .flags = CLK_SET_RATE_PARENT,
2995                         .ops = &clk_branch2_ops,
2996                 },
2997         },
2998 };
2999
3000 static struct clk_branch gcc_oxili_gfx3d_clk = {
3001         .halt_reg = 0x59020,
3002         .clkr = {
3003                 .enable_reg = 0x59020,
3004                 .enable_mask = BIT(0),
3005                 .hw.init = &(struct clk_init_data){
3006                         .name = "gcc_oxili_gfx3d_clk",
3007                         .parent_data = &(const struct clk_parent_data){
3008                                 .hw = &gfx3d_clk_src.clkr.hw,
3009                         },
3010                         .num_parents = 1,
3011                         .flags = CLK_SET_RATE_PARENT,
3012                         .ops = &clk_branch2_ops,
3013                 },
3014         },
3015 };
3016
3017 static struct clk_branch gcc_pdm2_clk = {
3018         .halt_reg = 0x4400c,
3019         .clkr = {
3020                 .enable_reg = 0x4400c,
3021                 .enable_mask = BIT(0),
3022                 .hw.init = &(struct clk_init_data){
3023                         .name = "gcc_pdm2_clk",
3024                         .parent_data = &(const struct clk_parent_data){
3025                                 .hw = &pdm2_clk_src.clkr.hw,
3026                         },
3027                         .num_parents = 1,
3028                         .flags = CLK_SET_RATE_PARENT,
3029                         .ops = &clk_branch2_ops,
3030                 },
3031         },
3032 };
3033
3034 static struct clk_branch gcc_pdm_ahb_clk = {
3035         .halt_reg = 0x44004,
3036         .clkr = {
3037                 .enable_reg = 0x44004,
3038                 .enable_mask = BIT(0),
3039                 .hw.init = &(struct clk_init_data){
3040                         .name = "gcc_pdm_ahb_clk",
3041                         .parent_data = &(const struct clk_parent_data){
3042                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3043                         },
3044                         .num_parents = 1,
3045                         .flags = CLK_SET_RATE_PARENT,
3046                         .ops = &clk_branch2_ops,
3047                 },
3048         },
3049 };
3050
3051 static struct clk_branch gcc_prng_ahb_clk = {
3052         .halt_reg = 0x13004,
3053         .halt_check = BRANCH_HALT_VOTED,
3054         .clkr = {
3055                 .enable_reg = 0x45004,
3056                 .enable_mask = BIT(8),
3057                 .hw.init = &(struct clk_init_data){
3058                         .name = "gcc_prng_ahb_clk",
3059                         .parent_data = &(const struct clk_parent_data){
3060                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3061                         },
3062                         .num_parents = 1,
3063                         .ops = &clk_branch2_ops,
3064                 },
3065         },
3066 };
3067
3068 static struct clk_branch gcc_sdcc1_ahb_clk = {
3069         .halt_reg = 0x4201c,
3070         .clkr = {
3071                 .enable_reg = 0x4201c,
3072                 .enable_mask = BIT(0),
3073                 .hw.init = &(struct clk_init_data){
3074                         .name = "gcc_sdcc1_ahb_clk",
3075                         .parent_data = &(const struct clk_parent_data){
3076                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3077                         },
3078                         .num_parents = 1,
3079                         .flags = CLK_SET_RATE_PARENT,
3080                         .ops = &clk_branch2_ops,
3081                 },
3082         },
3083 };
3084
3085 static struct clk_branch gcc_sdcc1_apps_clk = {
3086         .halt_reg = 0x42018,
3087         .clkr = {
3088                 .enable_reg = 0x42018,
3089                 .enable_mask = BIT(0),
3090                 .hw.init = &(struct clk_init_data){
3091                         .name = "gcc_sdcc1_apps_clk",
3092                         .parent_data = &(const struct clk_parent_data){
3093                                 .hw = &sdcc1_apps_clk_src.clkr.hw,
3094                         },
3095                         .num_parents = 1,
3096                         .flags = CLK_SET_RATE_PARENT,
3097                         .ops = &clk_branch2_ops,
3098                 },
3099         },
3100 };
3101
3102 static struct clk_branch gcc_sdcc2_ahb_clk = {
3103         .halt_reg = 0x4301c,
3104         .clkr = {
3105                 .enable_reg = 0x4301c,
3106                 .enable_mask = BIT(0),
3107                 .hw.init = &(struct clk_init_data){
3108                         .name = "gcc_sdcc2_ahb_clk",
3109                         .parent_data = &(const struct clk_parent_data){
3110                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3111                         },
3112                         .num_parents = 1,
3113                         .flags = CLK_SET_RATE_PARENT,
3114                         .ops = &clk_branch2_ops,
3115                 },
3116         },
3117 };
3118
3119 static struct clk_branch gcc_sdcc2_apps_clk = {
3120         .halt_reg = 0x43018,
3121         .clkr = {
3122                 .enable_reg = 0x43018,
3123                 .enable_mask = BIT(0),
3124                 .hw.init = &(struct clk_init_data){
3125                         .name = "gcc_sdcc2_apps_clk",
3126                         .parent_data = &(const struct clk_parent_data){
3127                                 .hw = &sdcc2_apps_clk_src.clkr.hw,
3128                         },
3129                         .num_parents = 1,
3130                         .flags = CLK_SET_RATE_PARENT,
3131                         .ops = &clk_branch2_ops,
3132                 },
3133         },
3134 };
3135
3136 static struct clk_branch gcc_apss_tcu_clk = {
3137         .halt_reg = 0x12018,
3138         .halt_check = BRANCH_HALT_VOTED,
3139         .clkr = {
3140                 .enable_reg = 0x4500c,
3141                 .enable_mask = BIT(1),
3142                 .hw.init = &(struct clk_init_data){
3143                         .name = "gcc_apss_tcu_clk",
3144                         .parent_data = &(const struct clk_parent_data){
3145                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3146                         },
3147                         .num_parents = 1,
3148                         .ops = &clk_branch2_ops,
3149                 },
3150         },
3151 };
3152
3153 static struct clk_branch gcc_gfx_tcu_clk = {
3154         .halt_reg = 0x12020,
3155         .halt_check = BRANCH_HALT_VOTED,
3156         .clkr = {
3157                 .enable_reg = 0x4500c,
3158                 .enable_mask = BIT(2),
3159                 .hw.init = &(struct clk_init_data){
3160                         .name = "gcc_gfx_tcu_clk",
3161                         .parent_data = &(const struct clk_parent_data){
3162                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3163                         },
3164                         .num_parents = 1,
3165                         .ops = &clk_branch2_ops,
3166                 },
3167         },
3168 };
3169
3170 static struct clk_branch gcc_gfx_tbu_clk = {
3171         .halt_reg = 0x12010,
3172         .halt_check = BRANCH_HALT_VOTED,
3173         .clkr = {
3174                 .enable_reg = 0x4500c,
3175                 .enable_mask = BIT(3),
3176                 .hw.init = &(struct clk_init_data){
3177                         .name = "gcc_gfx_tbu_clk",
3178                         .parent_data = &(const struct clk_parent_data){
3179                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3180                         },
3181                         .num_parents = 1,
3182                         .ops = &clk_branch2_ops,
3183                 },
3184         },
3185 };
3186
3187 static struct clk_branch gcc_mdp_tbu_clk = {
3188         .halt_reg = 0x1201c,
3189         .halt_check = BRANCH_HALT_VOTED,
3190         .clkr = {
3191                 .enable_reg = 0x4500c,
3192                 .enable_mask = BIT(4),
3193                 .hw.init = &(struct clk_init_data){
3194                         .name = "gcc_mdp_tbu_clk",
3195                         .parent_data = &(const struct clk_parent_data){
3196                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3197                         },
3198                         .num_parents = 1,
3199                         .flags = CLK_SET_RATE_PARENT,
3200                         .ops = &clk_branch2_ops,
3201                 },
3202         },
3203 };
3204
3205 static struct clk_branch gcc_venus_tbu_clk = {
3206         .halt_reg = 0x12014,
3207         .halt_check = BRANCH_HALT_VOTED,
3208         .clkr = {
3209                 .enable_reg = 0x4500c,
3210                 .enable_mask = BIT(5),
3211                 .hw.init = &(struct clk_init_data){
3212                         .name = "gcc_venus_tbu_clk",
3213                         .parent_data = &(const struct clk_parent_data){
3214                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3215                         },
3216                         .num_parents = 1,
3217                         .flags = CLK_SET_RATE_PARENT,
3218                         .ops = &clk_branch2_ops,
3219                 },
3220         },
3221 };
3222
3223 static struct clk_branch gcc_vfe_tbu_clk = {
3224         .halt_reg = 0x1203c,
3225         .halt_check = BRANCH_HALT_VOTED,
3226         .clkr = {
3227                 .enable_reg = 0x4500c,
3228                 .enable_mask = BIT(9),
3229                 .hw.init = &(struct clk_init_data){
3230                         .name = "gcc_vfe_tbu_clk",
3231                         .parent_data = &(const struct clk_parent_data){
3232                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3233                         },
3234                         .num_parents = 1,
3235                         .flags = CLK_SET_RATE_PARENT,
3236                         .ops = &clk_branch2_ops,
3237                 },
3238         },
3239 };
3240
3241 static struct clk_branch gcc_jpeg_tbu_clk = {
3242         .halt_reg = 0x12034,
3243         .halt_check = BRANCH_HALT_VOTED,
3244         .clkr = {
3245                 .enable_reg = 0x4500c,
3246                 .enable_mask = BIT(10),
3247                 .hw.init = &(struct clk_init_data){
3248                         .name = "gcc_jpeg_tbu_clk",
3249                         .parent_data = &(const struct clk_parent_data){
3250                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3251                         },
3252                         .num_parents = 1,
3253                         .flags = CLK_SET_RATE_PARENT,
3254                         .ops = &clk_branch2_ops,
3255                 },
3256         },
3257 };
3258
3259 static struct clk_branch gcc_smmu_cfg_clk = {
3260         .halt_reg = 0x12038,
3261         .halt_check = BRANCH_HALT_VOTED,
3262         .clkr = {
3263                 .enable_reg = 0x4500c,
3264                 .enable_mask = BIT(12),
3265                 .hw.init = &(struct clk_init_data){
3266                         .name = "gcc_smmu_cfg_clk",
3267                         .parent_data = &(const struct clk_parent_data){
3268                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3269                         },
3270                         .num_parents = 1,
3271                         .flags = CLK_SET_RATE_PARENT,
3272                         .ops = &clk_branch2_ops,
3273                 },
3274         },
3275 };
3276
3277 static struct clk_branch gcc_gtcu_ahb_clk = {
3278         .halt_reg = 0x12044,
3279         .halt_check = BRANCH_HALT_VOTED,
3280         .clkr = {
3281                 .enable_reg = 0x4500c,
3282                 .enable_mask = BIT(13),
3283                 .hw.init = &(struct clk_init_data){
3284                         .name = "gcc_gtcu_ahb_clk",
3285                         .parent_data = &(const struct clk_parent_data){
3286                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3287                         },
3288                         .num_parents = 1,
3289                         .flags = CLK_SET_RATE_PARENT,
3290                         .ops = &clk_branch2_ops,
3291                 },
3292         },
3293 };
3294
3295 static struct clk_branch gcc_cpp_tbu_clk = {
3296         .halt_reg = 0x12040,
3297         .halt_check = BRANCH_HALT_VOTED,
3298         .clkr = {
3299                 .enable_reg = 0x4500c,
3300                 .enable_mask = BIT(14),
3301                 .hw.init = &(struct clk_init_data){
3302                         .name = "gcc_cpp_tbu_clk",
3303                         .parent_data = &(const struct clk_parent_data){
3304                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3305                         },
3306                         .num_parents = 1,
3307                         .flags = CLK_SET_RATE_PARENT,
3308                         .ops = &clk_branch2_ops,
3309                 },
3310         },
3311 };
3312
3313 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3314         .halt_reg = 0x1201c,
3315         .halt_check = BRANCH_HALT_VOTED,
3316         .clkr = {
3317                 .enable_reg = 0x4500c,
3318                 .enable_mask = BIT(15),
3319                 .hw.init = &(struct clk_init_data){
3320                         .name = "gcc_mdp_rt_tbu_clk",
3321                         .parent_data = &(const struct clk_parent_data){
3322                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3323                         },
3324                         .num_parents = 1,
3325                         .flags = CLK_SET_RATE_PARENT,
3326                         .ops = &clk_branch2_ops,
3327                 },
3328         },
3329 };
3330
3331 static struct clk_branch gcc_bimc_gfx_clk = {
3332         .halt_reg = 0x31024,
3333         .clkr = {
3334                 .enable_reg = 0x31024,
3335                 .enable_mask = BIT(0),
3336                 .hw.init = &(struct clk_init_data){
3337                         .name = "gcc_bimc_gfx_clk",
3338                         .parent_data = &(const struct clk_parent_data){
3339                                 .hw = &bimc_gpu_clk_src.clkr.hw,
3340                         },
3341                         .num_parents = 1,
3342                         .flags = CLK_SET_RATE_PARENT,
3343                         .ops = &clk_branch2_ops,
3344                 },
3345         },
3346 };
3347
3348 static struct clk_branch gcc_bimc_gpu_clk = {
3349         .halt_reg = 0x31040,
3350         .clkr = {
3351                 .enable_reg = 0x31040,
3352                 .enable_mask = BIT(0),
3353                 .hw.init = &(struct clk_init_data){
3354                         .name = "gcc_bimc_gpu_clk",
3355                         .parent_data = &(const struct clk_parent_data){
3356                                 .hw = &bimc_gpu_clk_src.clkr.hw,
3357                         },
3358                         .num_parents = 1,
3359                         .flags = CLK_SET_RATE_PARENT,
3360                         .ops = &clk_branch2_ops,
3361                 },
3362         },
3363 };
3364
3365 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3366         .halt_reg = 0x4102c,
3367         .clkr = {
3368                 .enable_reg = 0x4102c,
3369                 .enable_mask = BIT(0),
3370                 .hw.init = &(struct clk_init_data){
3371                         .name = "gcc_usb2a_phy_sleep_clk",
3372                         .ops = &clk_branch2_ops,
3373                 },
3374         },
3375 };
3376
3377 static struct clk_branch gcc_usb_fs_ahb_clk = {
3378         .halt_reg = 0x3f008,
3379         .clkr = {
3380                 .enable_reg = 0x3f008,
3381                 .enable_mask = BIT(0),
3382                 .hw.init = &(struct clk_init_data){
3383                         .name = "gcc_usb_fs_ahb_clk",
3384                         .parent_data = &(const struct clk_parent_data){
3385                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3386                         },
3387                         .num_parents = 1,
3388                         .flags = CLK_SET_RATE_PARENT,
3389                         .ops = &clk_branch2_ops,
3390                 },
3391         },
3392 };
3393
3394 static struct clk_branch gcc_usb_fs_ic_clk = {
3395         .halt_reg = 0x3f030,
3396         .clkr = {
3397                 .enable_reg = 0x3f030,
3398                 .enable_mask = BIT(0),
3399                 .hw.init = &(struct clk_init_data){
3400                         .name = "gcc_usb_fs_ic_clk",
3401                         .parent_data = &(const struct clk_parent_data){
3402                                 .hw = &usb_fs_ic_clk_src.clkr.hw,
3403                         },
3404                         .num_parents = 1,
3405                         .flags = CLK_SET_RATE_PARENT,
3406                         .ops = &clk_branch2_ops,
3407                 },
3408         },
3409 };
3410
3411 static struct clk_branch gcc_usb_fs_system_clk = {
3412         .halt_reg = 0x3f004,
3413         .clkr = {
3414                 .enable_reg = 0x3f004,
3415                 .enable_mask = BIT(0),
3416                 .hw.init = &(struct clk_init_data){
3417                         .name = "gcc_usb_fs_system_clk",
3418                         .parent_data = &(const struct clk_parent_data){
3419                                 .hw = &usb_fs_system_clk_src.clkr.hw,
3420                         },
3421                         .num_parents = 1,
3422                         .flags = CLK_SET_RATE_PARENT,
3423                         .ops = &clk_branch2_ops,
3424                 },
3425         },
3426 };
3427
3428 static struct clk_branch gcc_usb_hs_ahb_clk = {
3429         .halt_reg = 0x41008,
3430         .clkr = {
3431                 .enable_reg = 0x41008,
3432                 .enable_mask = BIT(0),
3433                 .hw.init = &(struct clk_init_data){
3434                         .name = "gcc_usb_hs_ahb_clk",
3435                         .parent_data = &(const struct clk_parent_data){
3436                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3437                         },
3438                         .num_parents = 1,
3439                         .flags = CLK_SET_RATE_PARENT,
3440                         .ops = &clk_branch2_ops,
3441                 },
3442         },
3443 };
3444
3445 static struct clk_branch gcc_usb_hs_system_clk = {
3446         .halt_reg = 0x41004,
3447         .clkr = {
3448                 .enable_reg = 0x41004,
3449                 .enable_mask = BIT(0),
3450                 .hw.init = &(struct clk_init_data){
3451                         .name = "gcc_usb_hs_system_clk",
3452                         .parent_data = &(const struct clk_parent_data){
3453                                 .hw = &usb_hs_system_clk_src.clkr.hw,
3454                         },
3455                         .num_parents = 1,
3456                         .flags = CLK_SET_RATE_PARENT,
3457                         .ops = &clk_branch2_ops,
3458                 },
3459         },
3460 };
3461
3462 static struct clk_branch gcc_venus0_ahb_clk = {
3463         .halt_reg = 0x4c020,
3464         .clkr = {
3465                 .enable_reg = 0x4c020,
3466                 .enable_mask = BIT(0),
3467                 .hw.init = &(struct clk_init_data){
3468                         .name = "gcc_venus0_ahb_clk",
3469                         .parent_data = &(const struct clk_parent_data){
3470                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3471                         },
3472                         .num_parents = 1,
3473                         .flags = CLK_SET_RATE_PARENT,
3474                         .ops = &clk_branch2_ops,
3475                 },
3476         },
3477 };
3478
3479 static struct clk_branch gcc_venus0_axi_clk = {
3480         .halt_reg = 0x4c024,
3481         .clkr = {
3482                 .enable_reg = 0x4c024,
3483                 .enable_mask = BIT(0),
3484                 .hw.init = &(struct clk_init_data){
3485                         .name = "gcc_venus0_axi_clk",
3486                         .parent_data = &(const struct clk_parent_data){
3487                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3488                         },
3489                         .num_parents = 1,
3490                         .flags = CLK_SET_RATE_PARENT,
3491                         .ops = &clk_branch2_ops,
3492                 },
3493         },
3494 };
3495
3496 static struct clk_branch gcc_venus0_vcodec0_clk = {
3497         .halt_reg = 0x4c01c,
3498         .clkr = {
3499                 .enable_reg = 0x4c01c,
3500                 .enable_mask = BIT(0),
3501                 .hw.init = &(struct clk_init_data){
3502                         .name = "gcc_venus0_vcodec0_clk",
3503                         .parent_data = &(const struct clk_parent_data){
3504                                 .hw = &vcodec0_clk_src.clkr.hw,
3505                         },
3506                         .num_parents = 1,
3507                         .flags = CLK_SET_RATE_PARENT,
3508                         .ops = &clk_branch2_ops,
3509                 },
3510         },
3511 };
3512
3513 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3514         .halt_reg = 0x4c02c,
3515         .clkr = {
3516                 .enable_reg = 0x4c02c,
3517                 .enable_mask = BIT(0),
3518                 .hw.init = &(struct clk_init_data){
3519                         .name = "gcc_venus0_core0_vcodec0_clk",
3520                         .parent_data = &(const struct clk_parent_data){
3521                                 .hw = &vcodec0_clk_src.clkr.hw,
3522                         },
3523                         .num_parents = 1,
3524                         .flags = CLK_SET_RATE_PARENT,
3525                         .ops = &clk_branch2_ops,
3526                 },
3527         },
3528 };
3529
3530 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3531         .halt_reg = 0x4c034,
3532         .clkr = {
3533                 .enable_reg = 0x4c034,
3534                 .enable_mask = BIT(0),
3535                 .hw.init = &(struct clk_init_data){
3536                         .name = "gcc_venus0_core1_vcodec0_clk",
3537                         .parent_data = &(const struct clk_parent_data){
3538                                 .hw = &vcodec0_clk_src.clkr.hw,
3539                         },
3540                         .num_parents = 1,
3541                         .flags = CLK_SET_RATE_PARENT,
3542                         .ops = &clk_branch2_ops,
3543                 },
3544         },
3545 };
3546
3547 static struct clk_branch gcc_oxili_timer_clk = {
3548         .halt_reg = 0x59040,
3549         .clkr = {
3550                 .enable_reg = 0x59040,
3551                 .enable_mask = BIT(0),
3552                 .hw.init = &(struct clk_init_data){
3553                         .name = "gcc_oxili_timer_clk",
3554                         .ops = &clk_branch2_ops,
3555                 },
3556         },
3557 };
3558
3559 static struct gdsc venus_gdsc = {
3560         .gdscr = 0x4c018,
3561         .pd = {
3562                 .name = "venus",
3563         },
3564         .pwrsts = PWRSTS_OFF_ON,
3565 };
3566
3567 static struct gdsc mdss_gdsc = {
3568         .gdscr = 0x4d078,
3569         .pd = {
3570                 .name = "mdss",
3571         },
3572         .pwrsts = PWRSTS_OFF_ON,
3573 };
3574
3575 static struct gdsc jpeg_gdsc = {
3576         .gdscr = 0x5701c,
3577         .pd = {
3578                 .name = "jpeg",
3579         },
3580         .pwrsts = PWRSTS_OFF_ON,
3581 };
3582
3583 static struct gdsc vfe_gdsc = {
3584         .gdscr = 0x58034,
3585         .pd = {
3586                 .name = "vfe",
3587         },
3588         .pwrsts = PWRSTS_OFF_ON,
3589 };
3590
3591 static struct gdsc oxili_gdsc = {
3592         .gdscr = 0x5901c,
3593         .pd = {
3594                 .name = "oxili",
3595         },
3596         .pwrsts = PWRSTS_OFF_ON,
3597 };
3598
3599 static struct gdsc venus_core0_gdsc = {
3600         .gdscr = 0x4c028,
3601         .pd = {
3602                 .name = "venus_core0",
3603         },
3604         .pwrsts = PWRSTS_OFF_ON,
3605 };
3606
3607 static struct gdsc venus_core1_gdsc = {
3608         .gdscr = 0x4c030,
3609         .pd = {
3610                 .name = "venus_core1",
3611         },
3612         .pwrsts = PWRSTS_OFF_ON,
3613 };
3614
3615 static struct clk_regmap *gcc_msm8939_clocks[] = {
3616         [GPLL0] = &gpll0.clkr,
3617         [GPLL0_VOTE] = &gpll0_vote,
3618         [BIMC_PLL] = &bimc_pll.clkr,
3619         [BIMC_PLL_VOTE] = &bimc_pll_vote,
3620         [GPLL1] = &gpll1.clkr,
3621         [GPLL1_VOTE] = &gpll1_vote,
3622         [GPLL2] = &gpll2.clkr,
3623         [GPLL2_VOTE] = &gpll2_vote,
3624         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3625         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3626         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3627         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3628         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3629         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3630         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3631         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3632         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3633         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3634         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3635         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3636         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3637         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3638         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3639         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3640         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3641         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3642         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3643         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3644         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3645         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3646         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3647         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3648         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3649         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3650         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3651         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3652         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3653         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3654         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3655         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3656         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3657         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3658         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3659         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3660         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3661         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3662         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3663         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3664         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3665         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3666         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3667         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3668         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3669         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3670         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3671         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3672         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3673         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3674         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3675         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3676         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3677         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3678         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3679         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3680         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3681         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3682         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3683         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3684         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3685         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3686         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3687         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3688         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3689         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3690         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3691         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3692         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3693         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3694         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3695         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3696         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3697         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3698         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3699         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3700         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3701         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3702         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3703         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3704         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3705         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3706         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3707         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3708         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3709         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3710         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3711         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3712         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3713         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3714         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3715         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3716         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3717         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3718         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3719         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3720         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3721         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3722         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3723         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3724         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3725         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3726         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3727         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3728         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3729         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3730         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3731         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3732         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3733         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3734         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3735         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3736         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3737         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3738         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3739         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3740         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3741         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3742         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3743         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3744         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3745         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3746         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3747         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3748         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3749         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3750         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3751         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3752         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3753         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3754         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3755         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3756         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3757         [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3758         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3759         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3760         [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3761         [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3762         [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3763         [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3764         [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3765         [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3766         [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3767         [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3768         [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3769         [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3770         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3771         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3772         [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3773         [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3774         [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3775         [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3776         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3777         [GPLL3] = &gpll3.clkr,
3778         [GPLL3_VOTE] = &gpll3_vote,
3779         [GPLL4] = &gpll4.clkr,
3780         [GPLL4_VOTE] = &gpll4_vote,
3781         [GPLL5] = &gpll5.clkr,
3782         [GPLL5_VOTE] = &gpll5_vote,
3783         [GPLL6] = &gpll6.clkr,
3784         [GPLL6_VOTE] = &gpll6_vote,
3785         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3786         [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3787         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3788         [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3789         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3790         [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3791         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3792         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3793         [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3794         [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3795         [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3796         [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3797         [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3798         [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3799         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3800         [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3801         [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3802 };
3803
3804 static struct gdsc *gcc_msm8939_gdscs[] = {
3805         [VENUS_GDSC] = &venus_gdsc,
3806         [MDSS_GDSC] = &mdss_gdsc,
3807         [JPEG_GDSC] = &jpeg_gdsc,
3808         [VFE_GDSC] = &vfe_gdsc,
3809         [OXILI_GDSC] = &oxili_gdsc,
3810         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3811         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3812 };
3813
3814 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3815         [GCC_BLSP1_BCR] = { 0x01000 },
3816         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3817         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3818         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3819         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3820         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3821         [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3822         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3823         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3824         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3825         [GCC_IMEM_BCR] = { 0x0e000 },
3826         [GCC_SMMU_BCR] = { 0x12000 },
3827         [GCC_APSS_TCU_BCR] = { 0x12050 },
3828         [GCC_SMMU_XPU_BCR] = { 0x12054 },
3829         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3830         [GCC_PRNG_BCR] = { 0x13000 },
3831         [GCC_BOOT_ROM_BCR] = { 0x13008 },
3832         [GCC_CRYPTO_BCR] = { 0x16000 },
3833         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3834         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3835         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3836         [GCC_DEHR_BCR] = { 0x1f000 },
3837         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3838         [GCC_PCNOC_BCR] = { 0x27018 },
3839         [GCC_TCSR_BCR] = { 0x28000 },
3840         [GCC_QDSS_BCR] = { 0x29000 },
3841         [GCC_DCD_BCR] = { 0x2a000 },
3842         [GCC_MSG_RAM_BCR] = { 0x2b000 },
3843         [GCC_MPM_BCR] = { 0x2c000 },
3844         [GCC_SPMI_BCR] = { 0x2e000 },
3845         [GCC_SPDM_BCR] = { 0x2f000 },
3846         [GCC_MM_SPDM_BCR] = { 0x2f024 },
3847         [GCC_BIMC_BCR] = { 0x31000 },
3848         [GCC_RBCPR_BCR] = { 0x33000 },
3849         [GCC_TLMM_BCR] = { 0x34000 },
3850         [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3851         [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3852         [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3853         [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3854         [GCC_USB_FS_BCR] = { 0x3f000 },
3855         [GCC_USB_HS_BCR] = { 0x41000 },
3856         [GCC_USB2A_PHY_BCR] = { 0x41028 },
3857         [GCC_SDCC1_BCR] = { 0x42000 },
3858         [GCC_SDCC2_BCR] = { 0x43000 },
3859         [GCC_PDM_BCR] = { 0x44000 },
3860         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3861         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3862         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3863         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3864         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3865         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3866         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3867         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3868         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3869         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3870         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3871         [GCC_MMSS_BCR] = { 0x4b000 },
3872         [GCC_VENUS0_BCR] = { 0x4c014 },
3873         [GCC_MDSS_BCR] = { 0x4d074 },
3874         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3875         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3876         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3877         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3878         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3879         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3880         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3881         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3882         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3883         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3884         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3885         [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3886         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3887         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3888         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3889         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3890         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3891         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3892         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3893         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3894         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3895         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3896         [GCC_OXILI_BCR] = { 0x59018 },
3897         [GCC_GMEM_BCR] = { 0x5902c },
3898         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3899         [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3900         [GCC_MDP_TBU_BCR] = { 0x62000 },
3901         [GCC_GFX_TBU_BCR] = { 0x63000 },
3902         [GCC_GFX_TCU_BCR] = { 0x64000 },
3903         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3904         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3905         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3906         [GCC_GTCU_AHB_BCR] = { 0x68000 },
3907         [GCC_SMMU_CFG_BCR] = { 0x69000 },
3908         [GCC_VFE_TBU_BCR] = { 0x6a000 },
3909         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3910         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3911         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3912         [GCC_CPP_TBU_BCR] = { 0x6e000 },
3913         [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3914         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3915 };
3916
3917 static const struct regmap_config gcc_msm8939_regmap_config = {
3918         .reg_bits       = 32,
3919         .reg_stride     = 4,
3920         .val_bits       = 32,
3921         .max_register   = 0x80000,
3922         .fast_io        = true,
3923 };
3924
3925 static const struct qcom_cc_desc gcc_msm8939_desc = {
3926         .config = &gcc_msm8939_regmap_config,
3927         .clks = gcc_msm8939_clocks,
3928         .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3929         .resets = gcc_msm8939_resets,
3930         .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3931         .gdscs = gcc_msm8939_gdscs,
3932         .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3933 };
3934
3935 static const struct of_device_id gcc_msm8939_match_table[] = {
3936         { .compatible = "qcom,gcc-msm8939" },
3937         { }
3938 };
3939 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3940
3941 static int gcc_msm8939_probe(struct platform_device *pdev)
3942 {
3943         struct regmap *regmap;
3944
3945         regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
3946         if (IS_ERR(regmap))
3947                 return PTR_ERR(regmap);
3948
3949         clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
3950         clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
3951
3952         return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
3953 }
3954
3955 static struct platform_driver gcc_msm8939_driver = {
3956         .probe          = gcc_msm8939_probe,
3957         .driver         = {
3958                 .name   = "gcc-msm8939",
3959                 .of_match_table = gcc_msm8939_match_table,
3960         },
3961 };
3962
3963 static int __init gcc_msm8939_init(void)
3964 {
3965         return platform_driver_register(&gcc_msm8939_driver);
3966 }
3967 core_initcall(gcc_msm8939_init);
3968
3969 static void __exit gcc_msm8939_exit(void)
3970 {
3971         platform_driver_unregister(&gcc_msm8939_driver);
3972 }
3973 module_exit(gcc_msm8939_exit);
3974
3975 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
3976 MODULE_LICENSE("GPL v2");