2 * Copyright 2015 Linaro Limited
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
53 static const struct parent_map gcc_xo_gpll0_map[] = {
58 static const char * const gcc_xo_gpll0[] = {
63 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
69 static const char * const gcc_xo_gpll0_bimc[] = {
75 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
82 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
89 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
95 static const char * const gcc_xo_gpll0_gpll2[] = {
101 static const struct parent_map gcc_xo_gpll0a_map[] = {
106 static const char * const gcc_xo_gpll0a[] = {
111 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
118 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
125 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
131 static const char * const gcc_xo_gpll0_gpll1a[] = {
137 static const struct parent_map gcc_xo_dsibyte_map[] = {
139 { P_DSI0_PHYPLL_BYTE, 2 },
142 static const char * const gcc_xo_dsibyte[] = {
147 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
150 { P_DSI0_PHYPLL_BYTE, 1 },
153 static const char * const gcc_xo_gpll0a_dsibyte[] = {
159 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
162 { P_DSI0_PHYPLL_DSI, 2 },
165 static const char * const gcc_xo_gpll0_dsiphy[] = {
171 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
174 { P_DSI0_PHYPLL_DSI, 1 },
177 static const char * const gcc_xo_gpll0a_dsiphy[] = {
183 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
190 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
197 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
204 static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
211 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
214 { P_EXT_PRI_I2S, 2 },
219 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
227 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
230 { P_EXT_SEC_I2S, 2 },
235 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
243 static const struct parent_map gcc_xo_sleep_map[] = {
248 static const char * const gcc_xo_sleep[] = {
253 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
260 static const char * const gcc_xo_gpll1_emclk_sleep[] = {
267 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
269 static struct clk_pll gpll0 = {
273 .config_reg = 0x21010,
275 .status_reg = 0x2101c,
277 .clkr.hw.init = &(struct clk_init_data){
279 .parent_names = (const char *[]){ "xo" },
285 static struct clk_regmap gpll0_vote = {
286 .enable_reg = 0x45000,
287 .enable_mask = BIT(0),
288 .hw.init = &(struct clk_init_data){
289 .name = "gpll0_vote",
290 .parent_names = (const char *[]){ "gpll0" },
292 .ops = &clk_pll_vote_ops,
296 static struct clk_pll gpll1 = {
300 .config_reg = 0x20010,
302 .status_reg = 0x2001c,
304 .clkr.hw.init = &(struct clk_init_data){
306 .parent_names = (const char *[]){ "xo" },
312 static struct clk_regmap gpll1_vote = {
313 .enable_reg = 0x45000,
314 .enable_mask = BIT(1),
315 .hw.init = &(struct clk_init_data){
316 .name = "gpll1_vote",
317 .parent_names = (const char *[]){ "gpll1" },
319 .ops = &clk_pll_vote_ops,
323 static struct clk_pll gpll2 = {
327 .config_reg = 0x4a010,
329 .status_reg = 0x4a01c,
331 .clkr.hw.init = &(struct clk_init_data){
333 .parent_names = (const char *[]){ "xo" },
339 static struct clk_regmap gpll2_vote = {
340 .enable_reg = 0x45000,
341 .enable_mask = BIT(2),
342 .hw.init = &(struct clk_init_data){
343 .name = "gpll2_vote",
344 .parent_names = (const char *[]){ "gpll2" },
346 .ops = &clk_pll_vote_ops,
350 static struct clk_pll bimc_pll = {
354 .config_reg = 0x23010,
356 .status_reg = 0x2301c,
358 .clkr.hw.init = &(struct clk_init_data){
360 .parent_names = (const char *[]){ "xo" },
366 static struct clk_regmap bimc_pll_vote = {
367 .enable_reg = 0x45000,
368 .enable_mask = BIT(3),
369 .hw.init = &(struct clk_init_data){
370 .name = "bimc_pll_vote",
371 .parent_names = (const char *[]){ "bimc_pll" },
373 .ops = &clk_pll_vote_ops,
377 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
380 .parent_map = gcc_xo_gpll0_bimc_map,
381 .clkr.hw.init = &(struct clk_init_data){
382 .name = "pcnoc_bfdcd_clk_src",
383 .parent_names = gcc_xo_gpll0_bimc,
385 .ops = &clk_rcg2_ops,
389 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
392 .parent_map = gcc_xo_gpll0_bimc_map,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "system_noc_bfdcd_clk_src",
395 .parent_names = gcc_xo_gpll0_bimc,
397 .ops = &clk_rcg2_ops,
401 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
402 F(40000000, P_GPLL0, 10, 1, 2),
403 F(80000000, P_GPLL0, 10, 0, 0),
407 static struct clk_rcg2 camss_ahb_clk_src = {
411 .parent_map = gcc_xo_gpll0_map,
412 .freq_tbl = ftbl_gcc_camss_ahb_clk,
413 .clkr.hw.init = &(struct clk_init_data){
414 .name = "camss_ahb_clk_src",
415 .parent_names = gcc_xo_gpll0,
417 .ops = &clk_rcg2_ops,
421 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
422 F(19200000, P_XO, 1, 0, 0),
423 F(50000000, P_GPLL0, 16, 0, 0),
424 F(100000000, P_GPLL0, 8, 0, 0),
425 F(133330000, P_GPLL0, 6, 0, 0),
429 static struct clk_rcg2 apss_ahb_clk_src = {
432 .parent_map = gcc_xo_gpll0_map,
433 .freq_tbl = ftbl_apss_ahb_clk,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "apss_ahb_clk_src",
436 .parent_names = gcc_xo_gpll0,
438 .ops = &clk_rcg2_ops,
442 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
443 F(100000000, P_GPLL0, 8, 0, 0),
444 F(200000000, P_GPLL0, 4, 0, 0),
448 static struct clk_rcg2 csi0_clk_src = {
451 .parent_map = gcc_xo_gpll0_map,
452 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
453 .clkr.hw.init = &(struct clk_init_data){
454 .name = "csi0_clk_src",
455 .parent_names = gcc_xo_gpll0,
457 .ops = &clk_rcg2_ops,
461 static struct clk_rcg2 csi1_clk_src = {
464 .parent_map = gcc_xo_gpll0_map,
465 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "csi1_clk_src",
468 .parent_names = gcc_xo_gpll0,
470 .ops = &clk_rcg2_ops,
474 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
475 F(19200000, P_XO, 1, 0, 0),
476 F(50000000, P_GPLL0_AUX, 16, 0, 0),
477 F(80000000, P_GPLL0_AUX, 10, 0, 0),
478 F(100000000, P_GPLL0_AUX, 8, 0, 0),
479 F(160000000, P_GPLL0_AUX, 5, 0, 0),
480 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
481 F(200000000, P_GPLL0_AUX, 4, 0, 0),
482 F(266670000, P_GPLL0_AUX, 3, 0, 0),
483 F(294912000, P_GPLL1, 3, 0, 0),
484 F(310000000, P_GPLL2, 3, 0, 0),
485 F(400000000, P_GPLL0_AUX, 2, 0, 0),
489 static struct clk_rcg2 gfx3d_clk_src = {
492 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
493 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
494 .clkr.hw.init = &(struct clk_init_data){
495 .name = "gfx3d_clk_src",
496 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
498 .ops = &clk_rcg2_ops,
502 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
503 F(50000000, P_GPLL0, 16, 0, 0),
504 F(80000000, P_GPLL0, 10, 0, 0),
505 F(100000000, P_GPLL0, 8, 0, 0),
506 F(160000000, P_GPLL0, 5, 0, 0),
507 F(177780000, P_GPLL0, 4.5, 0, 0),
508 F(200000000, P_GPLL0, 4, 0, 0),
509 F(266670000, P_GPLL0, 3, 0, 0),
510 F(320000000, P_GPLL0, 2.5, 0, 0),
511 F(400000000, P_GPLL0, 2, 0, 0),
512 F(465000000, P_GPLL2, 2, 0, 0),
516 static struct clk_rcg2 vfe0_clk_src = {
519 .parent_map = gcc_xo_gpll0_gpll2_map,
520 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
521 .clkr.hw.init = &(struct clk_init_data){
522 .name = "vfe0_clk_src",
523 .parent_names = gcc_xo_gpll0_gpll2,
525 .ops = &clk_rcg2_ops,
529 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
530 F(19200000, P_XO, 1, 0, 0),
531 F(50000000, P_GPLL0, 16, 0, 0),
535 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
538 .parent_map = gcc_xo_gpll0_map,
539 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "blsp1_qup1_i2c_apps_clk_src",
542 .parent_names = gcc_xo_gpll0,
544 .ops = &clk_rcg2_ops,
548 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
549 F(960000, P_XO, 10, 1, 2),
550 F(4800000, P_XO, 4, 0, 0),
551 F(9600000, P_XO, 2, 0, 0),
552 F(16000000, P_GPLL0, 10, 1, 5),
553 F(19200000, P_XO, 1, 0, 0),
554 F(25000000, P_GPLL0, 16, 1, 2),
555 F(50000000, P_GPLL0, 16, 0, 0),
559 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
563 .parent_map = gcc_xo_gpll0_map,
564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "blsp1_qup1_spi_apps_clk_src",
567 .parent_names = gcc_xo_gpll0,
569 .ops = &clk_rcg2_ops,
573 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
576 .parent_map = gcc_xo_gpll0_map,
577 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "blsp1_qup2_i2c_apps_clk_src",
580 .parent_names = gcc_xo_gpll0,
582 .ops = &clk_rcg2_ops,
586 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
590 .parent_map = gcc_xo_gpll0_map,
591 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "blsp1_qup2_spi_apps_clk_src",
594 .parent_names = gcc_xo_gpll0,
596 .ops = &clk_rcg2_ops,
600 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
603 .parent_map = gcc_xo_gpll0_map,
604 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
605 .clkr.hw.init = &(struct clk_init_data){
606 .name = "blsp1_qup3_i2c_apps_clk_src",
607 .parent_names = gcc_xo_gpll0,
609 .ops = &clk_rcg2_ops,
613 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
617 .parent_map = gcc_xo_gpll0_map,
618 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "blsp1_qup3_spi_apps_clk_src",
621 .parent_names = gcc_xo_gpll0,
623 .ops = &clk_rcg2_ops,
627 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
630 .parent_map = gcc_xo_gpll0_map,
631 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
632 .clkr.hw.init = &(struct clk_init_data){
633 .name = "blsp1_qup4_i2c_apps_clk_src",
634 .parent_names = gcc_xo_gpll0,
636 .ops = &clk_rcg2_ops,
640 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
644 .parent_map = gcc_xo_gpll0_map,
645 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
646 .clkr.hw.init = &(struct clk_init_data){
647 .name = "blsp1_qup4_spi_apps_clk_src",
648 .parent_names = gcc_xo_gpll0,
650 .ops = &clk_rcg2_ops,
654 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
657 .parent_map = gcc_xo_gpll0_map,
658 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "blsp1_qup5_i2c_apps_clk_src",
661 .parent_names = gcc_xo_gpll0,
663 .ops = &clk_rcg2_ops,
667 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
671 .parent_map = gcc_xo_gpll0_map,
672 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "blsp1_qup5_spi_apps_clk_src",
675 .parent_names = gcc_xo_gpll0,
677 .ops = &clk_rcg2_ops,
681 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
684 .parent_map = gcc_xo_gpll0_map,
685 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
686 .clkr.hw.init = &(struct clk_init_data){
687 .name = "blsp1_qup6_i2c_apps_clk_src",
688 .parent_names = gcc_xo_gpll0,
690 .ops = &clk_rcg2_ops,
694 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
698 .parent_map = gcc_xo_gpll0_map,
699 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "blsp1_qup6_spi_apps_clk_src",
702 .parent_names = gcc_xo_gpll0,
704 .ops = &clk_rcg2_ops,
708 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
709 F(3686400, P_GPLL0, 1, 72, 15625),
710 F(7372800, P_GPLL0, 1, 144, 15625),
711 F(14745600, P_GPLL0, 1, 288, 15625),
712 F(16000000, P_GPLL0, 10, 1, 5),
713 F(19200000, P_XO, 1, 0, 0),
714 F(24000000, P_GPLL0, 1, 3, 100),
715 F(25000000, P_GPLL0, 16, 1, 2),
716 F(32000000, P_GPLL0, 1, 1, 25),
717 F(40000000, P_GPLL0, 1, 1, 20),
718 F(46400000, P_GPLL0, 1, 29, 500),
719 F(48000000, P_GPLL0, 1, 3, 50),
720 F(51200000, P_GPLL0, 1, 8, 125),
721 F(56000000, P_GPLL0, 1, 7, 100),
722 F(58982400, P_GPLL0, 1, 1152, 15625),
723 F(60000000, P_GPLL0, 1, 3, 40),
727 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
731 .parent_map = gcc_xo_gpll0_map,
732 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "blsp1_uart1_apps_clk_src",
735 .parent_names = gcc_xo_gpll0,
737 .ops = &clk_rcg2_ops,
741 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "blsp1_uart2_apps_clk_src",
749 .parent_names = gcc_xo_gpll0,
751 .ops = &clk_rcg2_ops,
755 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
756 F(19200000, P_XO, 1, 0, 0),
760 static struct clk_rcg2 cci_clk_src = {
764 .parent_map = gcc_xo_gpll0a_map,
765 .freq_tbl = ftbl_gcc_camss_cci_clk,
766 .clkr.hw.init = &(struct clk_init_data){
767 .name = "cci_clk_src",
768 .parent_names = gcc_xo_gpll0a,
770 .ops = &clk_rcg2_ops,
774 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
775 F(100000000, P_GPLL0, 8, 0, 0),
776 F(200000000, P_GPLL0, 4, 0, 0),
780 static struct clk_rcg2 camss_gp0_clk_src = {
784 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
785 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "camss_gp0_clk_src",
788 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
790 .ops = &clk_rcg2_ops,
794 static struct clk_rcg2 camss_gp1_clk_src = {
798 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
799 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "camss_gp1_clk_src",
802 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
804 .ops = &clk_rcg2_ops,
808 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
809 F(133330000, P_GPLL0, 6, 0, 0),
810 F(266670000, P_GPLL0, 3, 0, 0),
811 F(320000000, P_GPLL0, 2.5, 0, 0),
815 static struct clk_rcg2 jpeg0_clk_src = {
818 .parent_map = gcc_xo_gpll0_map,
819 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "jpeg0_clk_src",
822 .parent_names = gcc_xo_gpll0,
824 .ops = &clk_rcg2_ops,
828 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
829 F(9600000, P_XO, 2, 0, 0),
830 F(23880000, P_GPLL0, 1, 2, 67),
831 F(66670000, P_GPLL0, 12, 0, 0),
835 static struct clk_rcg2 mclk0_clk_src = {
839 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
840 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
841 .clkr.hw.init = &(struct clk_init_data){
842 .name = "mclk0_clk_src",
843 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
845 .ops = &clk_rcg2_ops,
849 static struct clk_rcg2 mclk1_clk_src = {
853 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
854 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "mclk1_clk_src",
857 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
859 .ops = &clk_rcg2_ops,
863 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
864 F(100000000, P_GPLL0, 8, 0, 0),
865 F(200000000, P_GPLL0, 4, 0, 0),
869 static struct clk_rcg2 csi0phytimer_clk_src = {
872 .parent_map = gcc_xo_gpll0_gpll1a_map,
873 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
874 .clkr.hw.init = &(struct clk_init_data){
875 .name = "csi0phytimer_clk_src",
876 .parent_names = gcc_xo_gpll0_gpll1a,
878 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 csi1phytimer_clk_src = {
885 .parent_map = gcc_xo_gpll0_gpll1a_map,
886 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "csi1phytimer_clk_src",
889 .parent_names = gcc_xo_gpll0_gpll1a,
891 .ops = &clk_rcg2_ops,
895 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
896 F(160000000, P_GPLL0, 5, 0, 0),
897 F(320000000, P_GPLL0, 2.5, 0, 0),
898 F(465000000, P_GPLL2, 2, 0, 0),
902 static struct clk_rcg2 cpp_clk_src = {
905 .parent_map = gcc_xo_gpll0_gpll2_map,
906 .freq_tbl = ftbl_gcc_camss_cpp_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "cpp_clk_src",
909 .parent_names = gcc_xo_gpll0_gpll2,
911 .ops = &clk_rcg2_ops,
915 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
916 F(50000000, P_GPLL0, 16, 0, 0),
917 F(80000000, P_GPLL0, 10, 0, 0),
918 F(100000000, P_GPLL0, 8, 0, 0),
919 F(160000000, P_GPLL0, 5, 0, 0),
923 static struct clk_rcg2 crypto_clk_src = {
926 .parent_map = gcc_xo_gpll0_map,
927 .freq_tbl = ftbl_gcc_crypto_clk,
928 .clkr.hw.init = &(struct clk_init_data){
929 .name = "crypto_clk_src",
930 .parent_names = gcc_xo_gpll0,
932 .ops = &clk_rcg2_ops,
936 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
937 F(19200000, P_XO, 1, 0, 0),
941 static struct clk_rcg2 gp1_clk_src = {
945 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
946 .freq_tbl = ftbl_gcc_gp1_3_clk,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "gp1_clk_src",
949 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
951 .ops = &clk_rcg2_ops,
955 static struct clk_rcg2 gp2_clk_src = {
959 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
960 .freq_tbl = ftbl_gcc_gp1_3_clk,
961 .clkr.hw.init = &(struct clk_init_data){
962 .name = "gp2_clk_src",
963 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
965 .ops = &clk_rcg2_ops,
969 static struct clk_rcg2 gp3_clk_src = {
973 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
974 .freq_tbl = ftbl_gcc_gp1_3_clk,
975 .clkr.hw.init = &(struct clk_init_data){
976 .name = "gp3_clk_src",
977 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
979 .ops = &clk_rcg2_ops,
983 static struct clk_rcg2 byte0_clk_src = {
986 .parent_map = gcc_xo_gpll0a_dsibyte_map,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "byte0_clk_src",
989 .parent_names = gcc_xo_gpll0a_dsibyte,
991 .ops = &clk_byte2_ops,
992 .flags = CLK_SET_RATE_PARENT,
996 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
997 F(19200000, P_XO, 1, 0, 0),
1001 static struct clk_rcg2 esc0_clk_src = {
1002 .cmd_rcgr = 0x4d05c,
1004 .parent_map = gcc_xo_dsibyte_map,
1005 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1006 .clkr.hw.init = &(struct clk_init_data){
1007 .name = "esc0_clk_src",
1008 .parent_names = gcc_xo_dsibyte,
1010 .ops = &clk_rcg2_ops,
1014 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1015 F(50000000, P_GPLL0, 16, 0, 0),
1016 F(80000000, P_GPLL0, 10, 0, 0),
1017 F(100000000, P_GPLL0, 8, 0, 0),
1018 F(160000000, P_GPLL0, 5, 0, 0),
1019 F(177780000, P_GPLL0, 4.5, 0, 0),
1020 F(200000000, P_GPLL0, 4, 0, 0),
1021 F(266670000, P_GPLL0, 3, 0, 0),
1022 F(320000000, P_GPLL0, 2.5, 0, 0),
1026 static struct clk_rcg2 mdp_clk_src = {
1027 .cmd_rcgr = 0x4d014,
1029 .parent_map = gcc_xo_gpll0_dsiphy_map,
1030 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "mdp_clk_src",
1033 .parent_names = gcc_xo_gpll0_dsiphy,
1035 .ops = &clk_rcg2_ops,
1039 static struct clk_rcg2 pclk0_clk_src = {
1040 .cmd_rcgr = 0x4d000,
1043 .parent_map = gcc_xo_gpll0a_dsiphy_map,
1044 .clkr.hw.init = &(struct clk_init_data){
1045 .name = "pclk0_clk_src",
1046 .parent_names = gcc_xo_gpll0a_dsiphy,
1048 .ops = &clk_pixel_ops,
1049 .flags = CLK_SET_RATE_PARENT,
1053 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1054 F(19200000, P_XO, 1, 0, 0),
1058 static struct clk_rcg2 vsync_clk_src = {
1059 .cmd_rcgr = 0x4d02c,
1061 .parent_map = gcc_xo_gpll0a_map,
1062 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1063 .clkr.hw.init = &(struct clk_init_data){
1064 .name = "vsync_clk_src",
1065 .parent_names = gcc_xo_gpll0a,
1067 .ops = &clk_rcg2_ops,
1071 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1072 F(64000000, P_GPLL0, 12.5, 0, 0),
1076 static struct clk_rcg2 pdm2_clk_src = {
1077 .cmd_rcgr = 0x44010,
1079 .parent_map = gcc_xo_gpll0_map,
1080 .freq_tbl = ftbl_gcc_pdm2_clk,
1081 .clkr.hw.init = &(struct clk_init_data){
1082 .name = "pdm2_clk_src",
1083 .parent_names = gcc_xo_gpll0,
1085 .ops = &clk_rcg2_ops,
1089 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1090 F(144000, P_XO, 16, 3, 25),
1091 F(400000, P_XO, 12, 1, 4),
1092 F(20000000, P_GPLL0, 10, 1, 4),
1093 F(25000000, P_GPLL0, 16, 1, 2),
1094 F(50000000, P_GPLL0, 16, 0, 0),
1095 F(100000000, P_GPLL0, 8, 0, 0),
1096 F(177770000, P_GPLL0, 4.5, 0, 0),
1100 static struct clk_rcg2 sdcc1_apps_clk_src = {
1101 .cmd_rcgr = 0x42004,
1104 .parent_map = gcc_xo_gpll0_map,
1105 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1106 .clkr.hw.init = &(struct clk_init_data){
1107 .name = "sdcc1_apps_clk_src",
1108 .parent_names = gcc_xo_gpll0,
1110 .ops = &clk_rcg2_floor_ops,
1114 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1115 F(144000, P_XO, 16, 3, 25),
1116 F(400000, P_XO, 12, 1, 4),
1117 F(20000000, P_GPLL0, 10, 1, 4),
1118 F(25000000, P_GPLL0, 16, 1, 2),
1119 F(50000000, P_GPLL0, 16, 0, 0),
1120 F(100000000, P_GPLL0, 8, 0, 0),
1121 F(200000000, P_GPLL0, 4, 0, 0),
1125 static struct clk_rcg2 sdcc2_apps_clk_src = {
1126 .cmd_rcgr = 0x43004,
1129 .parent_map = gcc_xo_gpll0_map,
1130 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1131 .clkr.hw.init = &(struct clk_init_data){
1132 .name = "sdcc2_apps_clk_src",
1133 .parent_names = gcc_xo_gpll0,
1135 .ops = &clk_rcg2_floor_ops,
1139 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1140 F(155000000, P_GPLL2, 6, 0, 0),
1141 F(310000000, P_GPLL2, 3, 0, 0),
1142 F(400000000, P_GPLL0, 2, 0, 0),
1146 static struct clk_rcg2 apss_tcu_clk_src = {
1147 .cmd_rcgr = 0x1207c,
1149 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1150 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1151 .clkr.hw.init = &(struct clk_init_data){
1152 .name = "apss_tcu_clk_src",
1153 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1155 .ops = &clk_rcg2_ops,
1159 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1160 F(19200000, P_XO, 1, 0, 0),
1161 F(100000000, P_GPLL0, 8, 0, 0),
1162 F(200000000, P_GPLL0, 4, 0, 0),
1163 F(266500000, P_BIMC, 4, 0, 0),
1164 F(400000000, P_GPLL0, 2, 0, 0),
1165 F(533000000, P_BIMC, 2, 0, 0),
1169 static struct clk_rcg2 bimc_gpu_clk_src = {
1170 .cmd_rcgr = 0x31028,
1172 .parent_map = gcc_xo_gpll0_bimc_map,
1173 .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1174 .clkr.hw.init = &(struct clk_init_data){
1175 .name = "bimc_gpu_clk_src",
1176 .parent_names = gcc_xo_gpll0_bimc,
1178 .flags = CLK_GET_RATE_NOCACHE,
1179 .ops = &clk_rcg2_ops,
1183 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1184 F(80000000, P_GPLL0, 10, 0, 0),
1188 static struct clk_rcg2 usb_hs_system_clk_src = {
1189 .cmd_rcgr = 0x41010,
1191 .parent_map = gcc_xo_gpll0_map,
1192 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1193 .clkr.hw.init = &(struct clk_init_data){
1194 .name = "usb_hs_system_clk_src",
1195 .parent_names = gcc_xo_gpll0,
1197 .ops = &clk_rcg2_ops,
1201 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1202 F(3200000, P_XO, 6, 0, 0),
1203 F(6400000, P_XO, 3, 0, 0),
1204 F(9600000, P_XO, 2, 0, 0),
1205 F(19200000, P_XO, 1, 0, 0),
1206 F(40000000, P_GPLL0, 10, 1, 2),
1207 F(66670000, P_GPLL0, 12, 0, 0),
1208 F(80000000, P_GPLL0, 10, 0, 0),
1209 F(100000000, P_GPLL0, 8, 0, 0),
1213 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1214 .cmd_rcgr = 0x1c010,
1217 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1218 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1219 .clkr.hw.init = &(struct clk_init_data){
1220 .name = "ultaudio_ahbfabric_clk_src",
1221 .parent_names = gcc_xo_gpll0_gpll1_sleep,
1223 .ops = &clk_rcg2_ops,
1227 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1228 .halt_reg = 0x1c028,
1230 .enable_reg = 0x1c028,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1234 .parent_names = (const char *[]){
1235 "ultaudio_ahbfabric_clk_src",
1238 .flags = CLK_SET_RATE_PARENT,
1239 .ops = &clk_branch2_ops,
1244 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1245 .halt_reg = 0x1c024,
1247 .enable_reg = 0x1c024,
1248 .enable_mask = BIT(0),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1251 .parent_names = (const char *[]){
1252 "ultaudio_ahbfabric_clk_src",
1255 .flags = CLK_SET_RATE_PARENT,
1256 .ops = &clk_branch2_ops,
1261 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1262 F(256000, P_XO, 5, 1, 15),
1263 F(512000, P_XO, 5, 2, 15),
1264 F(705600, P_GPLL1, 16, 1, 80),
1265 F(768000, P_XO, 5, 1, 5),
1266 F(800000, P_XO, 5, 5, 24),
1267 F(1024000, P_GPLL1, 14, 1, 63),
1268 F(1152000, P_XO, 1, 3, 50),
1269 F(1411200, P_GPLL1, 16, 1, 40),
1270 F(1536000, P_XO, 1, 2, 25),
1271 F(1600000, P_XO, 12, 0, 0),
1272 F(2048000, P_GPLL1, 9, 1, 49),
1273 F(2400000, P_XO, 8, 0, 0),
1274 F(2822400, P_GPLL1, 16, 1, 20),
1275 F(3072000, P_GPLL1, 14, 1, 21),
1276 F(4096000, P_GPLL1, 9, 2, 49),
1277 F(4800000, P_XO, 4, 0, 0),
1278 F(5644800, P_GPLL1, 16, 1, 10),
1279 F(6144000, P_GPLL1, 7, 1, 21),
1280 F(8192000, P_GPLL1, 9, 4, 49),
1281 F(9600000, P_XO, 2, 0, 0),
1282 F(11289600, P_GPLL1, 16, 1, 5),
1283 F(12288000, P_GPLL1, 7, 2, 21),
1287 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1288 .cmd_rcgr = 0x1c054,
1291 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1292 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1293 .clkr.hw.init = &(struct clk_init_data){
1294 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1295 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
1297 .ops = &clk_rcg2_ops,
1301 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1302 .halt_reg = 0x1c068,
1304 .enable_reg = 0x1c068,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1308 .parent_names = (const char *[]){
1309 "ultaudio_lpaif_pri_i2s_clk_src",
1312 .flags = CLK_SET_RATE_PARENT,
1313 .ops = &clk_branch2_ops,
1318 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1319 .cmd_rcgr = 0x1c06c,
1322 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1323 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1324 .clkr.hw.init = &(struct clk_init_data){
1325 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1326 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1328 .ops = &clk_rcg2_ops,
1332 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1333 .halt_reg = 0x1c080,
1335 .enable_reg = 0x1c080,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1339 .parent_names = (const char *[]){
1340 "ultaudio_lpaif_sec_i2s_clk_src",
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1349 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1350 .cmd_rcgr = 0x1c084,
1353 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1354 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1355 .clkr.hw.init = &(struct clk_init_data){
1356 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1357 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1359 .ops = &clk_rcg2_ops,
1363 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1364 .halt_reg = 0x1c098,
1366 .enable_reg = 0x1c098,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1370 .parent_names = (const char *[]){
1371 "ultaudio_lpaif_aux_i2s_clk_src",
1374 .flags = CLK_SET_RATE_PARENT,
1375 .ops = &clk_branch2_ops,
1380 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1381 F(19200000, P_XO, 1, 0, 0),
1385 static struct clk_rcg2 ultaudio_xo_clk_src = {
1386 .cmd_rcgr = 0x1c034,
1388 .parent_map = gcc_xo_sleep_map,
1389 .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1390 .clkr.hw.init = &(struct clk_init_data){
1391 .name = "ultaudio_xo_clk_src",
1392 .parent_names = gcc_xo_sleep,
1394 .ops = &clk_rcg2_ops,
1398 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1399 .halt_reg = 0x1c04c,
1401 .enable_reg = 0x1c04c,
1402 .enable_mask = BIT(0),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gcc_ultaudio_avsync_xo_clk",
1405 .parent_names = (const char *[]){
1406 "ultaudio_xo_clk_src",
1409 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_branch2_ops,
1415 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1416 .halt_reg = 0x1c050,
1418 .enable_reg = 0x1c050,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "gcc_ultaudio_stc_xo_clk",
1422 .parent_names = (const char *[]){
1423 "ultaudio_xo_clk_src",
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1432 static const struct freq_tbl ftbl_codec_clk[] = {
1433 F(9600000, P_XO, 2, 0, 0),
1434 F(19200000, P_XO, 1, 0, 0),
1435 F(11289600, P_EXT_MCLK, 1, 0, 0),
1439 static struct clk_rcg2 codec_digcodec_clk_src = {
1440 .cmd_rcgr = 0x1c09c,
1443 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1444 .freq_tbl = ftbl_codec_clk,
1445 .clkr.hw.init = &(struct clk_init_data){
1446 .name = "codec_digcodec_clk_src",
1447 .parent_names = gcc_xo_gpll1_emclk_sleep,
1449 .ops = &clk_rcg2_ops,
1453 static struct clk_branch gcc_codec_digcodec_clk = {
1454 .halt_reg = 0x1c0b0,
1456 .enable_reg = 0x1c0b0,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gcc_ultaudio_codec_digcodec_clk",
1460 .parent_names = (const char *[]){
1461 "codec_digcodec_clk_src",
1464 .flags = CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1470 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1471 .halt_reg = 0x1c000,
1473 .enable_reg = 0x1c000,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "gcc_ultaudio_pcnoc_mport_clk",
1477 .parent_names = (const char *[]){
1478 "pcnoc_bfdcd_clk_src",
1481 .ops = &clk_branch2_ops,
1486 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1487 .halt_reg = 0x1c004,
1489 .enable_reg = 0x1c004,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "gcc_ultaudio_pcnoc_sway_clk",
1493 .parent_names = (const char *[]){
1494 "pcnoc_bfdcd_clk_src",
1497 .ops = &clk_branch2_ops,
1502 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1503 F(100000000, P_GPLL0, 8, 0, 0),
1504 F(160000000, P_GPLL0, 5, 0, 0),
1505 F(228570000, P_GPLL0, 3.5, 0, 0),
1509 static struct clk_rcg2 vcodec0_clk_src = {
1510 .cmd_rcgr = 0x4C000,
1513 .parent_map = gcc_xo_gpll0_map,
1514 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1515 .clkr.hw.init = &(struct clk_init_data){
1516 .name = "vcodec0_clk_src",
1517 .parent_names = gcc_xo_gpll0,
1519 .ops = &clk_rcg2_ops,
1523 static struct clk_branch gcc_blsp1_ahb_clk = {
1524 .halt_reg = 0x01008,
1525 .halt_check = BRANCH_HALT_VOTED,
1527 .enable_reg = 0x45004,
1528 .enable_mask = BIT(10),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_blsp1_ahb_clk",
1531 .parent_names = (const char *[]){
1532 "pcnoc_bfdcd_clk_src",
1535 .ops = &clk_branch2_ops,
1540 static struct clk_branch gcc_blsp1_sleep_clk = {
1541 .halt_reg = 0x01004,
1543 .enable_reg = 0x01004,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "gcc_blsp1_sleep_clk",
1547 .parent_names = (const char *[]){
1551 .flags = CLK_SET_RATE_PARENT,
1552 .ops = &clk_branch2_ops,
1557 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1558 .halt_reg = 0x02008,
1560 .enable_reg = 0x02008,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1564 .parent_names = (const char *[]){
1565 "blsp1_qup1_i2c_apps_clk_src",
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1575 .halt_reg = 0x02004,
1577 .enable_reg = 0x02004,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "gcc_blsp1_qup1_spi_apps_clk",
1581 .parent_names = (const char *[]){
1582 "blsp1_qup1_spi_apps_clk_src",
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1591 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1592 .halt_reg = 0x03010,
1594 .enable_reg = 0x03010,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1598 .parent_names = (const char *[]){
1599 "blsp1_qup2_i2c_apps_clk_src",
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1608 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1609 .halt_reg = 0x0300c,
1611 .enable_reg = 0x0300c,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "gcc_blsp1_qup2_spi_apps_clk",
1615 .parent_names = (const char *[]){
1616 "blsp1_qup2_spi_apps_clk_src",
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1625 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1626 .halt_reg = 0x04020,
1628 .enable_reg = 0x04020,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1632 .parent_names = (const char *[]){
1633 "blsp1_qup3_i2c_apps_clk_src",
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1643 .halt_reg = 0x0401c,
1645 .enable_reg = 0x0401c,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_blsp1_qup3_spi_apps_clk",
1649 .parent_names = (const char *[]){
1650 "blsp1_qup3_spi_apps_clk_src",
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1660 .halt_reg = 0x05020,
1662 .enable_reg = 0x05020,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1666 .parent_names = (const char *[]){
1667 "blsp1_qup4_i2c_apps_clk_src",
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1677 .halt_reg = 0x0501c,
1679 .enable_reg = 0x0501c,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_blsp1_qup4_spi_apps_clk",
1683 .parent_names = (const char *[]){
1684 "blsp1_qup4_spi_apps_clk_src",
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1694 .halt_reg = 0x06020,
1696 .enable_reg = 0x06020,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1700 .parent_names = (const char *[]){
1701 "blsp1_qup5_i2c_apps_clk_src",
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1710 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1711 .halt_reg = 0x0601c,
1713 .enable_reg = 0x0601c,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "gcc_blsp1_qup5_spi_apps_clk",
1717 .parent_names = (const char *[]){
1718 "blsp1_qup5_spi_apps_clk_src",
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1728 .halt_reg = 0x07020,
1730 .enable_reg = 0x07020,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1734 .parent_names = (const char *[]){
1735 "blsp1_qup6_i2c_apps_clk_src",
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1745 .halt_reg = 0x0701c,
1747 .enable_reg = 0x0701c,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "gcc_blsp1_qup6_spi_apps_clk",
1751 .parent_names = (const char *[]){
1752 "blsp1_qup6_spi_apps_clk_src",
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1762 .halt_reg = 0x0203c,
1764 .enable_reg = 0x0203c,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "gcc_blsp1_uart1_apps_clk",
1768 .parent_names = (const char *[]){
1769 "blsp1_uart1_apps_clk_src",
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1779 .halt_reg = 0x0302c,
1781 .enable_reg = 0x0302c,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_blsp1_uart2_apps_clk",
1785 .parent_names = (const char *[]){
1786 "blsp1_uart2_apps_clk_src",
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 static struct clk_branch gcc_boot_rom_ahb_clk = {
1796 .halt_reg = 0x1300c,
1797 .halt_check = BRANCH_HALT_VOTED,
1799 .enable_reg = 0x45004,
1800 .enable_mask = BIT(7),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_boot_rom_ahb_clk",
1803 .parent_names = (const char *[]){
1804 "pcnoc_bfdcd_clk_src",
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch gcc_camss_cci_ahb_clk = {
1813 .halt_reg = 0x5101c,
1815 .enable_reg = 0x5101c,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_camss_cci_ahb_clk",
1819 .parent_names = (const char *[]){
1820 "camss_ahb_clk_src",
1823 .flags = CLK_SET_RATE_PARENT,
1824 .ops = &clk_branch2_ops,
1829 static struct clk_branch gcc_camss_cci_clk = {
1830 .halt_reg = 0x51018,
1832 .enable_reg = 0x51018,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "gcc_camss_cci_clk",
1836 .parent_names = (const char *[]){
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1846 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1847 .halt_reg = 0x4e040,
1849 .enable_reg = 0x4e040,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_camss_csi0_ahb_clk",
1853 .parent_names = (const char *[]){
1854 "camss_ahb_clk_src",
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1863 static struct clk_branch gcc_camss_csi0_clk = {
1864 .halt_reg = 0x4e03c,
1866 .enable_reg = 0x4e03c,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "gcc_camss_csi0_clk",
1870 .parent_names = (const char *[]){
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch gcc_camss_csi0phy_clk = {
1881 .halt_reg = 0x4e048,
1883 .enable_reg = 0x4e048,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "gcc_camss_csi0phy_clk",
1887 .parent_names = (const char *[]){
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch gcc_camss_csi0pix_clk = {
1898 .halt_reg = 0x4e058,
1900 .enable_reg = 0x4e058,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "gcc_camss_csi0pix_clk",
1904 .parent_names = (const char *[]){
1908 .flags = CLK_SET_RATE_PARENT,
1909 .ops = &clk_branch2_ops,
1914 static struct clk_branch gcc_camss_csi0rdi_clk = {
1915 .halt_reg = 0x4e050,
1917 .enable_reg = 0x4e050,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_camss_csi0rdi_clk",
1921 .parent_names = (const char *[]){
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1932 .halt_reg = 0x4f040,
1934 .enable_reg = 0x4f040,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_camss_csi1_ahb_clk",
1938 .parent_names = (const char *[]){
1939 "camss_ahb_clk_src",
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_camss_csi1_clk = {
1949 .halt_reg = 0x4f03c,
1951 .enable_reg = 0x4f03c,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_camss_csi1_clk",
1955 .parent_names = (const char *[]){
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch gcc_camss_csi1phy_clk = {
1966 .halt_reg = 0x4f048,
1968 .enable_reg = 0x4f048,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_camss_csi1phy_clk",
1972 .parent_names = (const char *[]){
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch gcc_camss_csi1pix_clk = {
1983 .halt_reg = 0x4f058,
1985 .enable_reg = 0x4f058,
1986 .enable_mask = BIT(0),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "gcc_camss_csi1pix_clk",
1989 .parent_names = (const char *[]){
1993 .flags = CLK_SET_RATE_PARENT,
1994 .ops = &clk_branch2_ops,
1999 static struct clk_branch gcc_camss_csi1rdi_clk = {
2000 .halt_reg = 0x4f050,
2002 .enable_reg = 0x4f050,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "gcc_camss_csi1rdi_clk",
2006 .parent_names = (const char *[]){
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2016 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2017 .halt_reg = 0x58050,
2019 .enable_reg = 0x58050,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "gcc_camss_csi_vfe0_clk",
2023 .parent_names = (const char *[]){
2027 .flags = CLK_SET_RATE_PARENT,
2028 .ops = &clk_branch2_ops,
2033 static struct clk_branch gcc_camss_gp0_clk = {
2034 .halt_reg = 0x54018,
2036 .enable_reg = 0x54018,
2037 .enable_mask = BIT(0),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gcc_camss_gp0_clk",
2040 .parent_names = (const char *[]){
2041 "camss_gp0_clk_src",
2044 .flags = CLK_SET_RATE_PARENT,
2045 .ops = &clk_branch2_ops,
2050 static struct clk_branch gcc_camss_gp1_clk = {
2051 .halt_reg = 0x55018,
2053 .enable_reg = 0x55018,
2054 .enable_mask = BIT(0),
2055 .hw.init = &(struct clk_init_data){
2056 .name = "gcc_camss_gp1_clk",
2057 .parent_names = (const char *[]){
2058 "camss_gp1_clk_src",
2061 .flags = CLK_SET_RATE_PARENT,
2062 .ops = &clk_branch2_ops,
2067 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2068 .halt_reg = 0x50004,
2070 .enable_reg = 0x50004,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_camss_ispif_ahb_clk",
2074 .parent_names = (const char *[]){
2075 "camss_ahb_clk_src",
2078 .flags = CLK_SET_RATE_PARENT,
2079 .ops = &clk_branch2_ops,
2084 static struct clk_branch gcc_camss_jpeg0_clk = {
2085 .halt_reg = 0x57020,
2087 .enable_reg = 0x57020,
2088 .enable_mask = BIT(0),
2089 .hw.init = &(struct clk_init_data){
2090 .name = "gcc_camss_jpeg0_clk",
2091 .parent_names = (const char *[]){
2095 .flags = CLK_SET_RATE_PARENT,
2096 .ops = &clk_branch2_ops,
2101 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2102 .halt_reg = 0x57024,
2104 .enable_reg = 0x57024,
2105 .enable_mask = BIT(0),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "gcc_camss_jpeg_ahb_clk",
2108 .parent_names = (const char *[]){
2109 "camss_ahb_clk_src",
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2118 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2119 .halt_reg = 0x57028,
2121 .enable_reg = 0x57028,
2122 .enable_mask = BIT(0),
2123 .hw.init = &(struct clk_init_data){
2124 .name = "gcc_camss_jpeg_axi_clk",
2125 .parent_names = (const char *[]){
2126 "system_noc_bfdcd_clk_src",
2129 .flags = CLK_SET_RATE_PARENT,
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch gcc_camss_mclk0_clk = {
2136 .halt_reg = 0x52018,
2138 .enable_reg = 0x52018,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "gcc_camss_mclk0_clk",
2142 .parent_names = (const char *[]){
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2152 static struct clk_branch gcc_camss_mclk1_clk = {
2153 .halt_reg = 0x53018,
2155 .enable_reg = 0x53018,
2156 .enable_mask = BIT(0),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "gcc_camss_mclk1_clk",
2159 .parent_names = (const char *[]){
2163 .flags = CLK_SET_RATE_PARENT,
2164 .ops = &clk_branch2_ops,
2169 static struct clk_branch gcc_camss_micro_ahb_clk = {
2170 .halt_reg = 0x5600c,
2172 .enable_reg = 0x5600c,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "gcc_camss_micro_ahb_clk",
2176 .parent_names = (const char *[]){
2177 "camss_ahb_clk_src",
2180 .flags = CLK_SET_RATE_PARENT,
2181 .ops = &clk_branch2_ops,
2186 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2187 .halt_reg = 0x4e01c,
2189 .enable_reg = 0x4e01c,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_camss_csi0phytimer_clk",
2193 .parent_names = (const char *[]){
2194 "csi0phytimer_clk_src",
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2204 .halt_reg = 0x4f01c,
2206 .enable_reg = 0x4f01c,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_camss_csi1phytimer_clk",
2210 .parent_names = (const char *[]){
2211 "csi1phytimer_clk_src",
2214 .flags = CLK_SET_RATE_PARENT,
2215 .ops = &clk_branch2_ops,
2220 static struct clk_branch gcc_camss_ahb_clk = {
2221 .halt_reg = 0x5a014,
2223 .enable_reg = 0x5a014,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "gcc_camss_ahb_clk",
2227 .parent_names = (const char *[]){
2228 "camss_ahb_clk_src",
2231 .flags = CLK_SET_RATE_PARENT,
2232 .ops = &clk_branch2_ops,
2237 static struct clk_branch gcc_camss_top_ahb_clk = {
2238 .halt_reg = 0x56004,
2240 .enable_reg = 0x56004,
2241 .enable_mask = BIT(0),
2242 .hw.init = &(struct clk_init_data){
2243 .name = "gcc_camss_top_ahb_clk",
2244 .parent_names = (const char *[]){
2245 "pcnoc_bfdcd_clk_src",
2248 .flags = CLK_SET_RATE_PARENT,
2249 .ops = &clk_branch2_ops,
2254 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2255 .halt_reg = 0x58040,
2257 .enable_reg = 0x58040,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "gcc_camss_cpp_ahb_clk",
2261 .parent_names = (const char *[]){
2262 "camss_ahb_clk_src",
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch gcc_camss_cpp_clk = {
2272 .halt_reg = 0x5803c,
2274 .enable_reg = 0x5803c,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "gcc_camss_cpp_clk",
2278 .parent_names = (const char *[]){
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch gcc_camss_vfe0_clk = {
2289 .halt_reg = 0x58038,
2291 .enable_reg = 0x58038,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "gcc_camss_vfe0_clk",
2295 .parent_names = (const char *[]){
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2306 .halt_reg = 0x58044,
2308 .enable_reg = 0x58044,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_camss_vfe_ahb_clk",
2312 .parent_names = (const char *[]){
2313 "camss_ahb_clk_src",
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2322 static struct clk_branch gcc_camss_vfe_axi_clk = {
2323 .halt_reg = 0x58048,
2325 .enable_reg = 0x58048,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_camss_vfe_axi_clk",
2329 .parent_names = (const char *[]){
2330 "system_noc_bfdcd_clk_src",
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2339 static struct clk_branch gcc_crypto_ahb_clk = {
2340 .halt_reg = 0x16024,
2341 .halt_check = BRANCH_HALT_VOTED,
2343 .enable_reg = 0x45004,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_crypto_ahb_clk",
2347 .parent_names = (const char *[]){
2348 "pcnoc_bfdcd_clk_src",
2351 .flags = CLK_SET_RATE_PARENT,
2352 .ops = &clk_branch2_ops,
2357 static struct clk_branch gcc_crypto_axi_clk = {
2358 .halt_reg = 0x16020,
2359 .halt_check = BRANCH_HALT_VOTED,
2361 .enable_reg = 0x45004,
2362 .enable_mask = BIT(1),
2363 .hw.init = &(struct clk_init_data){
2364 .name = "gcc_crypto_axi_clk",
2365 .parent_names = (const char *[]){
2366 "pcnoc_bfdcd_clk_src",
2369 .flags = CLK_SET_RATE_PARENT,
2370 .ops = &clk_branch2_ops,
2375 static struct clk_branch gcc_crypto_clk = {
2376 .halt_reg = 0x1601c,
2377 .halt_check = BRANCH_HALT_VOTED,
2379 .enable_reg = 0x45004,
2380 .enable_mask = BIT(2),
2381 .hw.init = &(struct clk_init_data){
2382 .name = "gcc_crypto_clk",
2383 .parent_names = (const char *[]){
2387 .flags = CLK_SET_RATE_PARENT,
2388 .ops = &clk_branch2_ops,
2393 static struct clk_branch gcc_oxili_gmem_clk = {
2394 .halt_reg = 0x59024,
2396 .enable_reg = 0x59024,
2397 .enable_mask = BIT(0),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_oxili_gmem_clk",
2400 .parent_names = (const char *[]){
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_gp1_clk = {
2411 .halt_reg = 0x08000,
2413 .enable_reg = 0x08000,
2414 .enable_mask = BIT(0),
2415 .hw.init = &(struct clk_init_data){
2416 .name = "gcc_gp1_clk",
2417 .parent_names = (const char *[]){
2421 .flags = CLK_SET_RATE_PARENT,
2422 .ops = &clk_branch2_ops,
2427 static struct clk_branch gcc_gp2_clk = {
2428 .halt_reg = 0x09000,
2430 .enable_reg = 0x09000,
2431 .enable_mask = BIT(0),
2432 .hw.init = &(struct clk_init_data){
2433 .name = "gcc_gp2_clk",
2434 .parent_names = (const char *[]){
2438 .flags = CLK_SET_RATE_PARENT,
2439 .ops = &clk_branch2_ops,
2444 static struct clk_branch gcc_gp3_clk = {
2445 .halt_reg = 0x0a000,
2447 .enable_reg = 0x0a000,
2448 .enable_mask = BIT(0),
2449 .hw.init = &(struct clk_init_data){
2450 .name = "gcc_gp3_clk",
2451 .parent_names = (const char *[]){
2455 .flags = CLK_SET_RATE_PARENT,
2456 .ops = &clk_branch2_ops,
2461 static struct clk_branch gcc_mdss_ahb_clk = {
2462 .halt_reg = 0x4d07c,
2464 .enable_reg = 0x4d07c,
2465 .enable_mask = BIT(0),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_mdss_ahb_clk",
2468 .parent_names = (const char *[]){
2469 "pcnoc_bfdcd_clk_src",
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2478 static struct clk_branch gcc_mdss_axi_clk = {
2479 .halt_reg = 0x4d080,
2481 .enable_reg = 0x4d080,
2482 .enable_mask = BIT(0),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "gcc_mdss_axi_clk",
2485 .parent_names = (const char *[]){
2486 "system_noc_bfdcd_clk_src",
2489 .flags = CLK_SET_RATE_PARENT,
2490 .ops = &clk_branch2_ops,
2495 static struct clk_branch gcc_mdss_byte0_clk = {
2496 .halt_reg = 0x4d094,
2498 .enable_reg = 0x4d094,
2499 .enable_mask = BIT(0),
2500 .hw.init = &(struct clk_init_data){
2501 .name = "gcc_mdss_byte0_clk",
2502 .parent_names = (const char *[]){
2506 .flags = CLK_SET_RATE_PARENT,
2507 .ops = &clk_branch2_ops,
2512 static struct clk_branch gcc_mdss_esc0_clk = {
2513 .halt_reg = 0x4d098,
2515 .enable_reg = 0x4d098,
2516 .enable_mask = BIT(0),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "gcc_mdss_esc0_clk",
2519 .parent_names = (const char *[]){
2523 .flags = CLK_SET_RATE_PARENT,
2524 .ops = &clk_branch2_ops,
2529 static struct clk_branch gcc_mdss_mdp_clk = {
2530 .halt_reg = 0x4D088,
2532 .enable_reg = 0x4D088,
2533 .enable_mask = BIT(0),
2534 .hw.init = &(struct clk_init_data){
2535 .name = "gcc_mdss_mdp_clk",
2536 .parent_names = (const char *[]){
2540 .flags = CLK_SET_RATE_PARENT,
2541 .ops = &clk_branch2_ops,
2546 static struct clk_branch gcc_mdss_pclk0_clk = {
2547 .halt_reg = 0x4d084,
2549 .enable_reg = 0x4d084,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "gcc_mdss_pclk0_clk",
2553 .parent_names = (const char *[]){
2557 .flags = CLK_SET_RATE_PARENT,
2558 .ops = &clk_branch2_ops,
2563 static struct clk_branch gcc_mdss_vsync_clk = {
2564 .halt_reg = 0x4d090,
2566 .enable_reg = 0x4d090,
2567 .enable_mask = BIT(0),
2568 .hw.init = &(struct clk_init_data){
2569 .name = "gcc_mdss_vsync_clk",
2570 .parent_names = (const char *[]){
2574 .flags = CLK_SET_RATE_PARENT,
2575 .ops = &clk_branch2_ops,
2580 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2581 .halt_reg = 0x49000,
2583 .enable_reg = 0x49000,
2584 .enable_mask = BIT(0),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gcc_mss_cfg_ahb_clk",
2587 .parent_names = (const char *[]){
2588 "pcnoc_bfdcd_clk_src",
2591 .flags = CLK_SET_RATE_PARENT,
2592 .ops = &clk_branch2_ops,
2597 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2598 .halt_reg = 0x49004,
2600 .enable_reg = 0x49004,
2601 .enable_mask = BIT(0),
2602 .hw.init = &(struct clk_init_data){
2603 .name = "gcc_mss_q6_bimc_axi_clk",
2604 .parent_names = (const char *[]){
2608 .flags = CLK_SET_RATE_PARENT,
2609 .ops = &clk_branch2_ops,
2614 static struct clk_branch gcc_oxili_ahb_clk = {
2615 .halt_reg = 0x59028,
2617 .enable_reg = 0x59028,
2618 .enable_mask = BIT(0),
2619 .hw.init = &(struct clk_init_data){
2620 .name = "gcc_oxili_ahb_clk",
2621 .parent_names = (const char *[]){
2622 "pcnoc_bfdcd_clk_src",
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_branch2_ops,
2631 static struct clk_branch gcc_oxili_gfx3d_clk = {
2632 .halt_reg = 0x59020,
2634 .enable_reg = 0x59020,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "gcc_oxili_gfx3d_clk",
2638 .parent_names = (const char *[]){
2642 .flags = CLK_SET_RATE_PARENT,
2643 .ops = &clk_branch2_ops,
2648 static struct clk_branch gcc_pdm2_clk = {
2649 .halt_reg = 0x4400c,
2651 .enable_reg = 0x4400c,
2652 .enable_mask = BIT(0),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gcc_pdm2_clk",
2655 .parent_names = (const char *[]){
2659 .flags = CLK_SET_RATE_PARENT,
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_pdm_ahb_clk = {
2666 .halt_reg = 0x44004,
2668 .enable_reg = 0x44004,
2669 .enable_mask = BIT(0),
2670 .hw.init = &(struct clk_init_data){
2671 .name = "gcc_pdm_ahb_clk",
2672 .parent_names = (const char *[]){
2673 "pcnoc_bfdcd_clk_src",
2676 .flags = CLK_SET_RATE_PARENT,
2677 .ops = &clk_branch2_ops,
2682 static struct clk_branch gcc_prng_ahb_clk = {
2683 .halt_reg = 0x13004,
2684 .halt_check = BRANCH_HALT_VOTED,
2686 .enable_reg = 0x45004,
2687 .enable_mask = BIT(8),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "gcc_prng_ahb_clk",
2690 .parent_names = (const char *[]){
2691 "pcnoc_bfdcd_clk_src",
2694 .ops = &clk_branch2_ops,
2699 static struct clk_branch gcc_sdcc1_ahb_clk = {
2700 .halt_reg = 0x4201c,
2702 .enable_reg = 0x4201c,
2703 .enable_mask = BIT(0),
2704 .hw.init = &(struct clk_init_data){
2705 .name = "gcc_sdcc1_ahb_clk",
2706 .parent_names = (const char *[]){
2707 "pcnoc_bfdcd_clk_src",
2710 .flags = CLK_SET_RATE_PARENT,
2711 .ops = &clk_branch2_ops,
2716 static struct clk_branch gcc_sdcc1_apps_clk = {
2717 .halt_reg = 0x42018,
2719 .enable_reg = 0x42018,
2720 .enable_mask = BIT(0),
2721 .hw.init = &(struct clk_init_data){
2722 .name = "gcc_sdcc1_apps_clk",
2723 .parent_names = (const char *[]){
2724 "sdcc1_apps_clk_src",
2727 .flags = CLK_SET_RATE_PARENT,
2728 .ops = &clk_branch2_ops,
2733 static struct clk_branch gcc_sdcc2_ahb_clk = {
2734 .halt_reg = 0x4301c,
2736 .enable_reg = 0x4301c,
2737 .enable_mask = BIT(0),
2738 .hw.init = &(struct clk_init_data){
2739 .name = "gcc_sdcc2_ahb_clk",
2740 .parent_names = (const char *[]){
2741 "pcnoc_bfdcd_clk_src",
2744 .flags = CLK_SET_RATE_PARENT,
2745 .ops = &clk_branch2_ops,
2750 static struct clk_branch gcc_sdcc2_apps_clk = {
2751 .halt_reg = 0x43018,
2753 .enable_reg = 0x43018,
2754 .enable_mask = BIT(0),
2755 .hw.init = &(struct clk_init_data){
2756 .name = "gcc_sdcc2_apps_clk",
2757 .parent_names = (const char *[]){
2758 "sdcc2_apps_clk_src",
2761 .flags = CLK_SET_RATE_PARENT,
2762 .ops = &clk_branch2_ops,
2767 static struct clk_rcg2 bimc_ddr_clk_src = {
2768 .cmd_rcgr = 0x32004,
2770 .parent_map = gcc_xo_gpll0_bimc_map,
2771 .clkr.hw.init = &(struct clk_init_data){
2772 .name = "bimc_ddr_clk_src",
2773 .parent_names = gcc_xo_gpll0_bimc,
2775 .ops = &clk_rcg2_ops,
2776 .flags = CLK_GET_RATE_NOCACHE,
2780 static struct clk_branch gcc_apss_tcu_clk = {
2781 .halt_reg = 0x12018,
2783 .enable_reg = 0x4500c,
2784 .enable_mask = BIT(1),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_apss_tcu_clk",
2787 .parent_names = (const char *[]){
2791 .ops = &clk_branch2_ops,
2796 static struct clk_branch gcc_gfx_tcu_clk = {
2797 .halt_reg = 0x12020,
2799 .enable_reg = 0x4500c,
2800 .enable_mask = BIT(2),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "gcc_gfx_tcu_clk",
2803 .parent_names = (const char *[]){
2807 .ops = &clk_branch2_ops,
2812 static struct clk_branch gcc_gtcu_ahb_clk = {
2813 .halt_reg = 0x12044,
2815 .enable_reg = 0x4500c,
2816 .enable_mask = BIT(13),
2817 .hw.init = &(struct clk_init_data){
2818 .name = "gcc_gtcu_ahb_clk",
2819 .parent_names = (const char *[]){
2820 "pcnoc_bfdcd_clk_src",
2823 .flags = CLK_SET_RATE_PARENT,
2824 .ops = &clk_branch2_ops,
2829 static struct clk_branch gcc_bimc_gfx_clk = {
2830 .halt_reg = 0x31024,
2832 .enable_reg = 0x31024,
2833 .enable_mask = BIT(0),
2834 .hw.init = &(struct clk_init_data){
2835 .name = "gcc_bimc_gfx_clk",
2836 .parent_names = (const char *[]){
2840 .flags = CLK_SET_RATE_PARENT,
2841 .ops = &clk_branch2_ops,
2846 static struct clk_branch gcc_bimc_gpu_clk = {
2847 .halt_reg = 0x31040,
2849 .enable_reg = 0x31040,
2850 .enable_mask = BIT(0),
2851 .hw.init = &(struct clk_init_data){
2852 .name = "gcc_bimc_gpu_clk",
2853 .parent_names = (const char *[]){
2857 .flags = CLK_SET_RATE_PARENT,
2858 .ops = &clk_branch2_ops,
2863 static struct clk_branch gcc_jpeg_tbu_clk = {
2864 .halt_reg = 0x12034,
2866 .enable_reg = 0x4500c,
2867 .enable_mask = BIT(10),
2868 .hw.init = &(struct clk_init_data){
2869 .name = "gcc_jpeg_tbu_clk",
2870 .parent_names = (const char *[]){
2871 "system_noc_bfdcd_clk_src",
2874 .flags = CLK_SET_RATE_PARENT,
2875 .ops = &clk_branch2_ops,
2880 static struct clk_branch gcc_mdp_tbu_clk = {
2881 .halt_reg = 0x1201c,
2883 .enable_reg = 0x4500c,
2884 .enable_mask = BIT(4),
2885 .hw.init = &(struct clk_init_data){
2886 .name = "gcc_mdp_tbu_clk",
2887 .parent_names = (const char *[]){
2888 "system_noc_bfdcd_clk_src",
2891 .flags = CLK_SET_RATE_PARENT,
2892 .ops = &clk_branch2_ops,
2897 static struct clk_branch gcc_smmu_cfg_clk = {
2898 .halt_reg = 0x12038,
2900 .enable_reg = 0x4500c,
2901 .enable_mask = BIT(12),
2902 .hw.init = &(struct clk_init_data){
2903 .name = "gcc_smmu_cfg_clk",
2904 .parent_names = (const char *[]){
2905 "pcnoc_bfdcd_clk_src",
2908 .flags = CLK_SET_RATE_PARENT,
2909 .ops = &clk_branch2_ops,
2914 static struct clk_branch gcc_venus_tbu_clk = {
2915 .halt_reg = 0x12014,
2917 .enable_reg = 0x4500c,
2918 .enable_mask = BIT(5),
2919 .hw.init = &(struct clk_init_data){
2920 .name = "gcc_venus_tbu_clk",
2921 .parent_names = (const char *[]){
2922 "system_noc_bfdcd_clk_src",
2925 .flags = CLK_SET_RATE_PARENT,
2926 .ops = &clk_branch2_ops,
2931 static struct clk_branch gcc_vfe_tbu_clk = {
2932 .halt_reg = 0x1203c,
2934 .enable_reg = 0x4500c,
2935 .enable_mask = BIT(9),
2936 .hw.init = &(struct clk_init_data){
2937 .name = "gcc_vfe_tbu_clk",
2938 .parent_names = (const char *[]){
2939 "system_noc_bfdcd_clk_src",
2942 .flags = CLK_SET_RATE_PARENT,
2943 .ops = &clk_branch2_ops,
2948 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2949 .halt_reg = 0x4102c,
2951 .enable_reg = 0x4102c,
2952 .enable_mask = BIT(0),
2953 .hw.init = &(struct clk_init_data){
2954 .name = "gcc_usb2a_phy_sleep_clk",
2955 .parent_names = (const char *[]){
2959 .flags = CLK_SET_RATE_PARENT,
2960 .ops = &clk_branch2_ops,
2965 static struct clk_branch gcc_usb_hs_ahb_clk = {
2966 .halt_reg = 0x41008,
2968 .enable_reg = 0x41008,
2969 .enable_mask = BIT(0),
2970 .hw.init = &(struct clk_init_data){
2971 .name = "gcc_usb_hs_ahb_clk",
2972 .parent_names = (const char *[]){
2973 "pcnoc_bfdcd_clk_src",
2976 .flags = CLK_SET_RATE_PARENT,
2977 .ops = &clk_branch2_ops,
2982 static struct clk_branch gcc_usb_hs_system_clk = {
2983 .halt_reg = 0x41004,
2985 .enable_reg = 0x41004,
2986 .enable_mask = BIT(0),
2987 .hw.init = &(struct clk_init_data){
2988 .name = "gcc_usb_hs_system_clk",
2989 .parent_names = (const char *[]){
2990 "usb_hs_system_clk_src",
2993 .flags = CLK_SET_RATE_PARENT,
2994 .ops = &clk_branch2_ops,
2999 static struct clk_branch gcc_venus0_ahb_clk = {
3000 .halt_reg = 0x4c020,
3002 .enable_reg = 0x4c020,
3003 .enable_mask = BIT(0),
3004 .hw.init = &(struct clk_init_data){
3005 .name = "gcc_venus0_ahb_clk",
3006 .parent_names = (const char *[]){
3007 "pcnoc_bfdcd_clk_src",
3010 .flags = CLK_SET_RATE_PARENT,
3011 .ops = &clk_branch2_ops,
3016 static struct clk_branch gcc_venus0_axi_clk = {
3017 .halt_reg = 0x4c024,
3019 .enable_reg = 0x4c024,
3020 .enable_mask = BIT(0),
3021 .hw.init = &(struct clk_init_data){
3022 .name = "gcc_venus0_axi_clk",
3023 .parent_names = (const char *[]){
3024 "system_noc_bfdcd_clk_src",
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_branch2_ops,
3033 static struct clk_branch gcc_venus0_vcodec0_clk = {
3034 .halt_reg = 0x4c01c,
3036 .enable_reg = 0x4c01c,
3037 .enable_mask = BIT(0),
3038 .hw.init = &(struct clk_init_data){
3039 .name = "gcc_venus0_vcodec0_clk",
3040 .parent_names = (const char *[]){
3044 .flags = CLK_SET_RATE_PARENT,
3045 .ops = &clk_branch2_ops,
3050 static struct gdsc venus_gdsc = {
3055 .pwrsts = PWRSTS_OFF_ON,
3058 static struct gdsc mdss_gdsc = {
3063 .pwrsts = PWRSTS_OFF_ON,
3066 static struct gdsc jpeg_gdsc = {
3071 .pwrsts = PWRSTS_OFF_ON,
3074 static struct gdsc vfe_gdsc = {
3079 .pwrsts = PWRSTS_OFF_ON,
3082 static struct gdsc oxili_gdsc = {
3087 .pwrsts = PWRSTS_OFF_ON,
3090 static struct clk_regmap *gcc_msm8916_clocks[] = {
3091 [GPLL0] = &gpll0.clkr,
3092 [GPLL0_VOTE] = &gpll0_vote,
3093 [BIMC_PLL] = &bimc_pll.clkr,
3094 [BIMC_PLL_VOTE] = &bimc_pll_vote,
3095 [GPLL1] = &gpll1.clkr,
3096 [GPLL1_VOTE] = &gpll1_vote,
3097 [GPLL2] = &gpll2.clkr,
3098 [GPLL2_VOTE] = &gpll2_vote,
3099 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3100 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3101 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3102 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3103 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3104 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3105 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3106 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3107 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3108 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3109 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3110 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3111 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3112 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3113 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3114 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3115 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3116 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3117 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3118 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3119 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3120 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3121 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3122 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3123 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3124 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3125 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3126 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3127 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3128 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3129 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3130 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3131 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3132 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3133 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3134 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3135 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3136 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3137 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3138 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3139 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3140 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3141 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3142 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3143 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3144 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3145 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3146 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3147 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3148 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3149 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3150 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3151 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3152 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3153 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3154 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3155 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3156 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3157 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3158 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3159 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3160 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3161 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3162 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3163 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3164 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3165 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3166 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3167 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3168 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3169 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3170 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3171 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3172 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3173 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3174 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3175 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3176 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3177 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3178 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3179 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3180 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3181 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3182 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3183 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3184 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3185 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3186 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3187 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3188 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3189 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3190 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3191 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3192 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3193 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3194 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3195 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3196 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3197 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3198 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3199 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3200 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3201 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3202 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3203 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3204 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3205 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3206 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3207 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3208 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3209 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3210 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3211 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3212 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3213 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3214 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3215 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3216 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3217 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3218 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3219 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3220 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3221 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3222 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3223 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3224 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3225 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3226 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3227 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3228 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3229 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3230 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3231 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3232 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3233 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3234 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3235 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3236 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3237 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3238 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3239 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3240 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3241 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3242 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3243 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3244 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3245 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3246 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3247 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3248 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3249 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3250 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3251 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3254 static struct gdsc *gcc_msm8916_gdscs[] = {
3255 [VENUS_GDSC] = &venus_gdsc,
3256 [MDSS_GDSC] = &mdss_gdsc,
3257 [JPEG_GDSC] = &jpeg_gdsc,
3258 [VFE_GDSC] = &vfe_gdsc,
3259 [OXILI_GDSC] = &oxili_gdsc,
3262 static const struct qcom_reset_map gcc_msm8916_resets[] = {
3263 [GCC_BLSP1_BCR] = { 0x01000 },
3264 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3265 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3266 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3267 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3268 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3269 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3270 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3271 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3272 [GCC_IMEM_BCR] = { 0x0e000 },
3273 [GCC_SMMU_BCR] = { 0x12000 },
3274 [GCC_APSS_TCU_BCR] = { 0x12050 },
3275 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3276 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3277 [GCC_PRNG_BCR] = { 0x13000 },
3278 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3279 [GCC_CRYPTO_BCR] = { 0x16000 },
3280 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3281 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3282 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3283 [GCC_DEHR_BCR] = { 0x1f000 },
3284 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3285 [GCC_PCNOC_BCR] = { 0x27018 },
3286 [GCC_TCSR_BCR] = { 0x28000 },
3287 [GCC_QDSS_BCR] = { 0x29000 },
3288 [GCC_DCD_BCR] = { 0x2a000 },
3289 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3290 [GCC_MPM_BCR] = { 0x2c000 },
3291 [GCC_SPMI_BCR] = { 0x2e000 },
3292 [GCC_SPDM_BCR] = { 0x2f000 },
3293 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3294 [GCC_BIMC_BCR] = { 0x31000 },
3295 [GCC_RBCPR_BCR] = { 0x33000 },
3296 [GCC_TLMM_BCR] = { 0x34000 },
3297 [GCC_USB_HS_BCR] = { 0x41000 },
3298 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3299 [GCC_SDCC1_BCR] = { 0x42000 },
3300 [GCC_SDCC2_BCR] = { 0x43000 },
3301 [GCC_PDM_BCR] = { 0x44000 },
3302 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3303 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3304 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3305 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3306 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3307 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3308 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3309 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3310 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3311 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3312 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3313 [GCC_MMSS_BCR] = { 0x4b000 },
3314 [GCC_VENUS0_BCR] = { 0x4c014 },
3315 [GCC_MDSS_BCR] = { 0x4d074 },
3316 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3317 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3318 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3319 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3320 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3321 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3322 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3323 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3324 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3325 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3326 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3327 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3328 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3329 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3330 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3331 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3332 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3333 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3334 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3335 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3336 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3337 [GCC_OXILI_BCR] = { 0x59018 },
3338 [GCC_GMEM_BCR] = { 0x5902c },
3339 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3340 [GCC_MDP_TBU_BCR] = { 0x62000 },
3341 [GCC_GFX_TBU_BCR] = { 0x63000 },
3342 [GCC_GFX_TCU_BCR] = { 0x64000 },
3343 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3344 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3345 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3346 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3347 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3348 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3349 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3350 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3351 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3352 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3355 static const struct regmap_config gcc_msm8916_regmap_config = {
3359 .max_register = 0x80000,
3363 static const struct qcom_cc_desc gcc_msm8916_desc = {
3364 .config = &gcc_msm8916_regmap_config,
3365 .clks = gcc_msm8916_clocks,
3366 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3367 .resets = gcc_msm8916_resets,
3368 .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3369 .gdscs = gcc_msm8916_gdscs,
3370 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3373 static const struct of_device_id gcc_msm8916_match_table[] = {
3374 { .compatible = "qcom,gcc-msm8916" },
3377 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3379 static int gcc_msm8916_probe(struct platform_device *pdev)
3382 struct device *dev = &pdev->dev;
3384 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3388 ret = qcom_cc_register_sleep_clk(dev);
3392 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3395 static struct platform_driver gcc_msm8916_driver = {
3396 .probe = gcc_msm8916_probe,
3398 .name = "gcc-msm8916",
3399 .of_match_table = gcc_msm8916_match_table,
3403 static int __init gcc_msm8916_init(void)
3405 return platform_driver_register(&gcc_msm8916_driver);
3407 core_initcall(gcc_msm8916_init);
3409 static void __exit gcc_msm8916_exit(void)
3411 platform_driver_unregister(&gcc_msm8916_driver);
3413 module_exit(gcc_msm8916_exit);
3415 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3416 MODULE_LICENSE("GPL v2");
3417 MODULE_ALIAS("platform:gcc-msm8916");