1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8660.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
27 static struct clk_pll pll8 = {
35 .clkr.hw.init = &(struct clk_init_data){
37 .parent_names = (const char *[]){ "pxo" },
43 static struct clk_regmap pll8_vote = {
45 .enable_mask = BIT(8),
46 .hw.init = &(struct clk_init_data){
48 .parent_names = (const char *[]){ "pll8" },
50 .ops = &clk_pll_vote_ops,
60 static const struct parent_map gcc_pxo_pll8_map[] = {
65 static const char * const gcc_pxo_pll8[] = {
70 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
76 static const char * const gcc_pxo_pll8_cxo[] = {
82 static struct freq_tbl clk_tbl_gsbi_uart[] = {
83 { 1843200, P_PLL8, 2, 6, 625 },
84 { 3686400, P_PLL8, 2, 12, 625 },
85 { 7372800, P_PLL8, 2, 24, 625 },
86 { 14745600, P_PLL8, 2, 48, 625 },
87 { 16000000, P_PLL8, 4, 1, 6 },
88 { 24000000, P_PLL8, 4, 1, 4 },
89 { 32000000, P_PLL8, 4, 1, 3 },
90 { 40000000, P_PLL8, 1, 5, 48 },
91 { 46400000, P_PLL8, 1, 29, 240 },
92 { 48000000, P_PLL8, 4, 1, 2 },
93 { 51200000, P_PLL8, 1, 2, 15 },
94 { 56000000, P_PLL8, 1, 7, 48 },
95 { 58982400, P_PLL8, 1, 96, 625 },
96 { 64000000, P_PLL8, 2, 1, 3 },
100 static struct clk_rcg gsbi1_uart_src = {
105 .mnctr_reset_bit = 7,
106 .mnctr_mode_shift = 5,
117 .parent_map = gcc_pxo_pll8_map,
119 .freq_tbl = clk_tbl_gsbi_uart,
121 .enable_reg = 0x29d4,
122 .enable_mask = BIT(11),
123 .hw.init = &(struct clk_init_data){
124 .name = "gsbi1_uart_src",
125 .parent_names = gcc_pxo_pll8,
128 .flags = CLK_SET_PARENT_GATE,
133 static struct clk_branch gsbi1_uart_clk = {
137 .enable_reg = 0x29d4,
138 .enable_mask = BIT(9),
139 .hw.init = &(struct clk_init_data){
140 .name = "gsbi1_uart_clk",
141 .parent_names = (const char *[]){
145 .ops = &clk_branch_ops,
146 .flags = CLK_SET_RATE_PARENT,
151 static struct clk_rcg gsbi2_uart_src = {
156 .mnctr_reset_bit = 7,
157 .mnctr_mode_shift = 5,
168 .parent_map = gcc_pxo_pll8_map,
170 .freq_tbl = clk_tbl_gsbi_uart,
172 .enable_reg = 0x29f4,
173 .enable_mask = BIT(11),
174 .hw.init = &(struct clk_init_data){
175 .name = "gsbi2_uart_src",
176 .parent_names = gcc_pxo_pll8,
179 .flags = CLK_SET_PARENT_GATE,
184 static struct clk_branch gsbi2_uart_clk = {
188 .enable_reg = 0x29f4,
189 .enable_mask = BIT(9),
190 .hw.init = &(struct clk_init_data){
191 .name = "gsbi2_uart_clk",
192 .parent_names = (const char *[]){
196 .ops = &clk_branch_ops,
197 .flags = CLK_SET_RATE_PARENT,
202 static struct clk_rcg gsbi3_uart_src = {
207 .mnctr_reset_bit = 7,
208 .mnctr_mode_shift = 5,
219 .parent_map = gcc_pxo_pll8_map,
221 .freq_tbl = clk_tbl_gsbi_uart,
223 .enable_reg = 0x2a14,
224 .enable_mask = BIT(11),
225 .hw.init = &(struct clk_init_data){
226 .name = "gsbi3_uart_src",
227 .parent_names = gcc_pxo_pll8,
230 .flags = CLK_SET_PARENT_GATE,
235 static struct clk_branch gsbi3_uart_clk = {
239 .enable_reg = 0x2a14,
240 .enable_mask = BIT(9),
241 .hw.init = &(struct clk_init_data){
242 .name = "gsbi3_uart_clk",
243 .parent_names = (const char *[]){
247 .ops = &clk_branch_ops,
248 .flags = CLK_SET_RATE_PARENT,
253 static struct clk_rcg gsbi4_uart_src = {
258 .mnctr_reset_bit = 7,
259 .mnctr_mode_shift = 5,
270 .parent_map = gcc_pxo_pll8_map,
272 .freq_tbl = clk_tbl_gsbi_uart,
274 .enable_reg = 0x2a34,
275 .enable_mask = BIT(11),
276 .hw.init = &(struct clk_init_data){
277 .name = "gsbi4_uart_src",
278 .parent_names = gcc_pxo_pll8,
281 .flags = CLK_SET_PARENT_GATE,
286 static struct clk_branch gsbi4_uart_clk = {
290 .enable_reg = 0x2a34,
291 .enable_mask = BIT(9),
292 .hw.init = &(struct clk_init_data){
293 .name = "gsbi4_uart_clk",
294 .parent_names = (const char *[]){
298 .ops = &clk_branch_ops,
299 .flags = CLK_SET_RATE_PARENT,
304 static struct clk_rcg gsbi5_uart_src = {
309 .mnctr_reset_bit = 7,
310 .mnctr_mode_shift = 5,
321 .parent_map = gcc_pxo_pll8_map,
323 .freq_tbl = clk_tbl_gsbi_uart,
325 .enable_reg = 0x2a54,
326 .enable_mask = BIT(11),
327 .hw.init = &(struct clk_init_data){
328 .name = "gsbi5_uart_src",
329 .parent_names = gcc_pxo_pll8,
332 .flags = CLK_SET_PARENT_GATE,
337 static struct clk_branch gsbi5_uart_clk = {
341 .enable_reg = 0x2a54,
342 .enable_mask = BIT(9),
343 .hw.init = &(struct clk_init_data){
344 .name = "gsbi5_uart_clk",
345 .parent_names = (const char *[]){
349 .ops = &clk_branch_ops,
350 .flags = CLK_SET_RATE_PARENT,
355 static struct clk_rcg gsbi6_uart_src = {
360 .mnctr_reset_bit = 7,
361 .mnctr_mode_shift = 5,
372 .parent_map = gcc_pxo_pll8_map,
374 .freq_tbl = clk_tbl_gsbi_uart,
376 .enable_reg = 0x2a74,
377 .enable_mask = BIT(11),
378 .hw.init = &(struct clk_init_data){
379 .name = "gsbi6_uart_src",
380 .parent_names = gcc_pxo_pll8,
383 .flags = CLK_SET_PARENT_GATE,
388 static struct clk_branch gsbi6_uart_clk = {
392 .enable_reg = 0x2a74,
393 .enable_mask = BIT(9),
394 .hw.init = &(struct clk_init_data){
395 .name = "gsbi6_uart_clk",
396 .parent_names = (const char *[]){
400 .ops = &clk_branch_ops,
401 .flags = CLK_SET_RATE_PARENT,
406 static struct clk_rcg gsbi7_uart_src = {
411 .mnctr_reset_bit = 7,
412 .mnctr_mode_shift = 5,
423 .parent_map = gcc_pxo_pll8_map,
425 .freq_tbl = clk_tbl_gsbi_uart,
427 .enable_reg = 0x2a94,
428 .enable_mask = BIT(11),
429 .hw.init = &(struct clk_init_data){
430 .name = "gsbi7_uart_src",
431 .parent_names = gcc_pxo_pll8,
434 .flags = CLK_SET_PARENT_GATE,
439 static struct clk_branch gsbi7_uart_clk = {
443 .enable_reg = 0x2a94,
444 .enable_mask = BIT(9),
445 .hw.init = &(struct clk_init_data){
446 .name = "gsbi7_uart_clk",
447 .parent_names = (const char *[]){
451 .ops = &clk_branch_ops,
452 .flags = CLK_SET_RATE_PARENT,
457 static struct clk_rcg gsbi8_uart_src = {
462 .mnctr_reset_bit = 7,
463 .mnctr_mode_shift = 5,
474 .parent_map = gcc_pxo_pll8_map,
476 .freq_tbl = clk_tbl_gsbi_uart,
478 .enable_reg = 0x2ab4,
479 .enable_mask = BIT(11),
480 .hw.init = &(struct clk_init_data){
481 .name = "gsbi8_uart_src",
482 .parent_names = gcc_pxo_pll8,
485 .flags = CLK_SET_PARENT_GATE,
490 static struct clk_branch gsbi8_uart_clk = {
494 .enable_reg = 0x2ab4,
495 .enable_mask = BIT(9),
496 .hw.init = &(struct clk_init_data){
497 .name = "gsbi8_uart_clk",
498 .parent_names = (const char *[]){ "gsbi8_uart_src" },
500 .ops = &clk_branch_ops,
501 .flags = CLK_SET_RATE_PARENT,
506 static struct clk_rcg gsbi9_uart_src = {
511 .mnctr_reset_bit = 7,
512 .mnctr_mode_shift = 5,
523 .parent_map = gcc_pxo_pll8_map,
525 .freq_tbl = clk_tbl_gsbi_uart,
527 .enable_reg = 0x2ad4,
528 .enable_mask = BIT(11),
529 .hw.init = &(struct clk_init_data){
530 .name = "gsbi9_uart_src",
531 .parent_names = gcc_pxo_pll8,
534 .flags = CLK_SET_PARENT_GATE,
539 static struct clk_branch gsbi9_uart_clk = {
543 .enable_reg = 0x2ad4,
544 .enable_mask = BIT(9),
545 .hw.init = &(struct clk_init_data){
546 .name = "gsbi9_uart_clk",
547 .parent_names = (const char *[]){ "gsbi9_uart_src" },
549 .ops = &clk_branch_ops,
550 .flags = CLK_SET_RATE_PARENT,
555 static struct clk_rcg gsbi10_uart_src = {
560 .mnctr_reset_bit = 7,
561 .mnctr_mode_shift = 5,
572 .parent_map = gcc_pxo_pll8_map,
574 .freq_tbl = clk_tbl_gsbi_uart,
576 .enable_reg = 0x2af4,
577 .enable_mask = BIT(11),
578 .hw.init = &(struct clk_init_data){
579 .name = "gsbi10_uart_src",
580 .parent_names = gcc_pxo_pll8,
583 .flags = CLK_SET_PARENT_GATE,
588 static struct clk_branch gsbi10_uart_clk = {
592 .enable_reg = 0x2af4,
593 .enable_mask = BIT(9),
594 .hw.init = &(struct clk_init_data){
595 .name = "gsbi10_uart_clk",
596 .parent_names = (const char *[]){ "gsbi10_uart_src" },
598 .ops = &clk_branch_ops,
599 .flags = CLK_SET_RATE_PARENT,
604 static struct clk_rcg gsbi11_uart_src = {
609 .mnctr_reset_bit = 7,
610 .mnctr_mode_shift = 5,
621 .parent_map = gcc_pxo_pll8_map,
623 .freq_tbl = clk_tbl_gsbi_uart,
625 .enable_reg = 0x2b14,
626 .enable_mask = BIT(11),
627 .hw.init = &(struct clk_init_data){
628 .name = "gsbi11_uart_src",
629 .parent_names = gcc_pxo_pll8,
632 .flags = CLK_SET_PARENT_GATE,
637 static struct clk_branch gsbi11_uart_clk = {
641 .enable_reg = 0x2b14,
642 .enable_mask = BIT(9),
643 .hw.init = &(struct clk_init_data){
644 .name = "gsbi11_uart_clk",
645 .parent_names = (const char *[]){ "gsbi11_uart_src" },
647 .ops = &clk_branch_ops,
648 .flags = CLK_SET_RATE_PARENT,
653 static struct clk_rcg gsbi12_uart_src = {
658 .mnctr_reset_bit = 7,
659 .mnctr_mode_shift = 5,
670 .parent_map = gcc_pxo_pll8_map,
672 .freq_tbl = clk_tbl_gsbi_uart,
674 .enable_reg = 0x2b34,
675 .enable_mask = BIT(11),
676 .hw.init = &(struct clk_init_data){
677 .name = "gsbi12_uart_src",
678 .parent_names = gcc_pxo_pll8,
681 .flags = CLK_SET_PARENT_GATE,
686 static struct clk_branch gsbi12_uart_clk = {
690 .enable_reg = 0x2b34,
691 .enable_mask = BIT(9),
692 .hw.init = &(struct clk_init_data){
693 .name = "gsbi12_uart_clk",
694 .parent_names = (const char *[]){ "gsbi12_uart_src" },
696 .ops = &clk_branch_ops,
697 .flags = CLK_SET_RATE_PARENT,
702 static struct freq_tbl clk_tbl_gsbi_qup[] = {
703 { 1100000, P_PXO, 1, 2, 49 },
704 { 5400000, P_PXO, 1, 1, 5 },
705 { 10800000, P_PXO, 1, 2, 5 },
706 { 15060000, P_PLL8, 1, 2, 51 },
707 { 24000000, P_PLL8, 4, 1, 4 },
708 { 25600000, P_PLL8, 1, 1, 15 },
709 { 27000000, P_PXO, 1, 0, 0 },
710 { 48000000, P_PLL8, 4, 1, 2 },
711 { 51200000, P_PLL8, 1, 2, 15 },
715 static struct clk_rcg gsbi1_qup_src = {
720 .mnctr_reset_bit = 7,
721 .mnctr_mode_shift = 5,
732 .parent_map = gcc_pxo_pll8_map,
734 .freq_tbl = clk_tbl_gsbi_qup,
736 .enable_reg = 0x29cc,
737 .enable_mask = BIT(11),
738 .hw.init = &(struct clk_init_data){
739 .name = "gsbi1_qup_src",
740 .parent_names = gcc_pxo_pll8,
743 .flags = CLK_SET_PARENT_GATE,
748 static struct clk_branch gsbi1_qup_clk = {
752 .enable_reg = 0x29cc,
753 .enable_mask = BIT(9),
754 .hw.init = &(struct clk_init_data){
755 .name = "gsbi1_qup_clk",
756 .parent_names = (const char *[]){ "gsbi1_qup_src" },
758 .ops = &clk_branch_ops,
759 .flags = CLK_SET_RATE_PARENT,
764 static struct clk_rcg gsbi2_qup_src = {
769 .mnctr_reset_bit = 7,
770 .mnctr_mode_shift = 5,
781 .parent_map = gcc_pxo_pll8_map,
783 .freq_tbl = clk_tbl_gsbi_qup,
785 .enable_reg = 0x29ec,
786 .enable_mask = BIT(11),
787 .hw.init = &(struct clk_init_data){
788 .name = "gsbi2_qup_src",
789 .parent_names = gcc_pxo_pll8,
792 .flags = CLK_SET_PARENT_GATE,
797 static struct clk_branch gsbi2_qup_clk = {
801 .enable_reg = 0x29ec,
802 .enable_mask = BIT(9),
803 .hw.init = &(struct clk_init_data){
804 .name = "gsbi2_qup_clk",
805 .parent_names = (const char *[]){ "gsbi2_qup_src" },
807 .ops = &clk_branch_ops,
808 .flags = CLK_SET_RATE_PARENT,
813 static struct clk_rcg gsbi3_qup_src = {
818 .mnctr_reset_bit = 7,
819 .mnctr_mode_shift = 5,
830 .parent_map = gcc_pxo_pll8_map,
832 .freq_tbl = clk_tbl_gsbi_qup,
834 .enable_reg = 0x2a0c,
835 .enable_mask = BIT(11),
836 .hw.init = &(struct clk_init_data){
837 .name = "gsbi3_qup_src",
838 .parent_names = gcc_pxo_pll8,
841 .flags = CLK_SET_PARENT_GATE,
846 static struct clk_branch gsbi3_qup_clk = {
850 .enable_reg = 0x2a0c,
851 .enable_mask = BIT(9),
852 .hw.init = &(struct clk_init_data){
853 .name = "gsbi3_qup_clk",
854 .parent_names = (const char *[]){ "gsbi3_qup_src" },
856 .ops = &clk_branch_ops,
857 .flags = CLK_SET_RATE_PARENT,
862 static struct clk_rcg gsbi4_qup_src = {
867 .mnctr_reset_bit = 7,
868 .mnctr_mode_shift = 5,
879 .parent_map = gcc_pxo_pll8_map,
881 .freq_tbl = clk_tbl_gsbi_qup,
883 .enable_reg = 0x2a2c,
884 .enable_mask = BIT(11),
885 .hw.init = &(struct clk_init_data){
886 .name = "gsbi4_qup_src",
887 .parent_names = gcc_pxo_pll8,
890 .flags = CLK_SET_PARENT_GATE,
895 static struct clk_branch gsbi4_qup_clk = {
899 .enable_reg = 0x2a2c,
900 .enable_mask = BIT(9),
901 .hw.init = &(struct clk_init_data){
902 .name = "gsbi4_qup_clk",
903 .parent_names = (const char *[]){ "gsbi4_qup_src" },
905 .ops = &clk_branch_ops,
906 .flags = CLK_SET_RATE_PARENT,
911 static struct clk_rcg gsbi5_qup_src = {
916 .mnctr_reset_bit = 7,
917 .mnctr_mode_shift = 5,
928 .parent_map = gcc_pxo_pll8_map,
930 .freq_tbl = clk_tbl_gsbi_qup,
932 .enable_reg = 0x2a4c,
933 .enable_mask = BIT(11),
934 .hw.init = &(struct clk_init_data){
935 .name = "gsbi5_qup_src",
936 .parent_names = gcc_pxo_pll8,
939 .flags = CLK_SET_PARENT_GATE,
944 static struct clk_branch gsbi5_qup_clk = {
948 .enable_reg = 0x2a4c,
949 .enable_mask = BIT(9),
950 .hw.init = &(struct clk_init_data){
951 .name = "gsbi5_qup_clk",
952 .parent_names = (const char *[]){ "gsbi5_qup_src" },
954 .ops = &clk_branch_ops,
955 .flags = CLK_SET_RATE_PARENT,
960 static struct clk_rcg gsbi6_qup_src = {
965 .mnctr_reset_bit = 7,
966 .mnctr_mode_shift = 5,
977 .parent_map = gcc_pxo_pll8_map,
979 .freq_tbl = clk_tbl_gsbi_qup,
981 .enable_reg = 0x2a6c,
982 .enable_mask = BIT(11),
983 .hw.init = &(struct clk_init_data){
984 .name = "gsbi6_qup_src",
985 .parent_names = gcc_pxo_pll8,
988 .flags = CLK_SET_PARENT_GATE,
993 static struct clk_branch gsbi6_qup_clk = {
997 .enable_reg = 0x2a6c,
998 .enable_mask = BIT(9),
999 .hw.init = &(struct clk_init_data){
1000 .name = "gsbi6_qup_clk",
1001 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1003 .ops = &clk_branch_ops,
1004 .flags = CLK_SET_RATE_PARENT,
1009 static struct clk_rcg gsbi7_qup_src = {
1014 .mnctr_reset_bit = 7,
1015 .mnctr_mode_shift = 5,
1026 .parent_map = gcc_pxo_pll8_map,
1028 .freq_tbl = clk_tbl_gsbi_qup,
1030 .enable_reg = 0x2a8c,
1031 .enable_mask = BIT(11),
1032 .hw.init = &(struct clk_init_data){
1033 .name = "gsbi7_qup_src",
1034 .parent_names = gcc_pxo_pll8,
1036 .ops = &clk_rcg_ops,
1037 .flags = CLK_SET_PARENT_GATE,
1042 static struct clk_branch gsbi7_qup_clk = {
1046 .enable_reg = 0x2a8c,
1047 .enable_mask = BIT(9),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gsbi7_qup_clk",
1050 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1052 .ops = &clk_branch_ops,
1053 .flags = CLK_SET_RATE_PARENT,
1058 static struct clk_rcg gsbi8_qup_src = {
1063 .mnctr_reset_bit = 7,
1064 .mnctr_mode_shift = 5,
1075 .parent_map = gcc_pxo_pll8_map,
1077 .freq_tbl = clk_tbl_gsbi_qup,
1079 .enable_reg = 0x2aac,
1080 .enable_mask = BIT(11),
1081 .hw.init = &(struct clk_init_data){
1082 .name = "gsbi8_qup_src",
1083 .parent_names = gcc_pxo_pll8,
1085 .ops = &clk_rcg_ops,
1086 .flags = CLK_SET_PARENT_GATE,
1091 static struct clk_branch gsbi8_qup_clk = {
1095 .enable_reg = 0x2aac,
1096 .enable_mask = BIT(9),
1097 .hw.init = &(struct clk_init_data){
1098 .name = "gsbi8_qup_clk",
1099 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1101 .ops = &clk_branch_ops,
1102 .flags = CLK_SET_RATE_PARENT,
1107 static struct clk_rcg gsbi9_qup_src = {
1112 .mnctr_reset_bit = 7,
1113 .mnctr_mode_shift = 5,
1124 .parent_map = gcc_pxo_pll8_map,
1126 .freq_tbl = clk_tbl_gsbi_qup,
1128 .enable_reg = 0x2acc,
1129 .enable_mask = BIT(11),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "gsbi9_qup_src",
1132 .parent_names = gcc_pxo_pll8,
1134 .ops = &clk_rcg_ops,
1135 .flags = CLK_SET_PARENT_GATE,
1140 static struct clk_branch gsbi9_qup_clk = {
1144 .enable_reg = 0x2acc,
1145 .enable_mask = BIT(9),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gsbi9_qup_clk",
1148 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1150 .ops = &clk_branch_ops,
1151 .flags = CLK_SET_RATE_PARENT,
1156 static struct clk_rcg gsbi10_qup_src = {
1161 .mnctr_reset_bit = 7,
1162 .mnctr_mode_shift = 5,
1173 .parent_map = gcc_pxo_pll8_map,
1175 .freq_tbl = clk_tbl_gsbi_qup,
1177 .enable_reg = 0x2aec,
1178 .enable_mask = BIT(11),
1179 .hw.init = &(struct clk_init_data){
1180 .name = "gsbi10_qup_src",
1181 .parent_names = gcc_pxo_pll8,
1183 .ops = &clk_rcg_ops,
1184 .flags = CLK_SET_PARENT_GATE,
1189 static struct clk_branch gsbi10_qup_clk = {
1193 .enable_reg = 0x2aec,
1194 .enable_mask = BIT(9),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gsbi10_qup_clk",
1197 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1199 .ops = &clk_branch_ops,
1200 .flags = CLK_SET_RATE_PARENT,
1205 static struct clk_rcg gsbi11_qup_src = {
1210 .mnctr_reset_bit = 7,
1211 .mnctr_mode_shift = 5,
1222 .parent_map = gcc_pxo_pll8_map,
1224 .freq_tbl = clk_tbl_gsbi_qup,
1226 .enable_reg = 0x2b0c,
1227 .enable_mask = BIT(11),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gsbi11_qup_src",
1230 .parent_names = gcc_pxo_pll8,
1232 .ops = &clk_rcg_ops,
1233 .flags = CLK_SET_PARENT_GATE,
1238 static struct clk_branch gsbi11_qup_clk = {
1242 .enable_reg = 0x2b0c,
1243 .enable_mask = BIT(9),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "gsbi11_qup_clk",
1246 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1248 .ops = &clk_branch_ops,
1249 .flags = CLK_SET_RATE_PARENT,
1254 static struct clk_rcg gsbi12_qup_src = {
1259 .mnctr_reset_bit = 7,
1260 .mnctr_mode_shift = 5,
1271 .parent_map = gcc_pxo_pll8_map,
1273 .freq_tbl = clk_tbl_gsbi_qup,
1275 .enable_reg = 0x2b2c,
1276 .enable_mask = BIT(11),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gsbi12_qup_src",
1279 .parent_names = gcc_pxo_pll8,
1281 .ops = &clk_rcg_ops,
1282 .flags = CLK_SET_PARENT_GATE,
1287 static struct clk_branch gsbi12_qup_clk = {
1291 .enable_reg = 0x2b2c,
1292 .enable_mask = BIT(9),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "gsbi12_qup_clk",
1295 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1297 .ops = &clk_branch_ops,
1298 .flags = CLK_SET_RATE_PARENT,
1303 static const struct freq_tbl clk_tbl_gp[] = {
1304 { 9600000, P_CXO, 2, 0, 0 },
1305 { 13500000, P_PXO, 2, 0, 0 },
1306 { 19200000, P_CXO, 1, 0, 0 },
1307 { 27000000, P_PXO, 1, 0, 0 },
1308 { 64000000, P_PLL8, 2, 1, 3 },
1309 { 76800000, P_PLL8, 1, 1, 5 },
1310 { 96000000, P_PLL8, 4, 0, 0 },
1311 { 128000000, P_PLL8, 3, 0, 0 },
1312 { 192000000, P_PLL8, 2, 0, 0 },
1316 static struct clk_rcg gp0_src = {
1321 .mnctr_reset_bit = 7,
1322 .mnctr_mode_shift = 5,
1333 .parent_map = gcc_pxo_pll8_cxo_map,
1335 .freq_tbl = clk_tbl_gp,
1337 .enable_reg = 0x2d24,
1338 .enable_mask = BIT(11),
1339 .hw.init = &(struct clk_init_data){
1341 .parent_names = gcc_pxo_pll8_cxo,
1343 .ops = &clk_rcg_ops,
1344 .flags = CLK_SET_PARENT_GATE,
1349 static struct clk_branch gp0_clk = {
1353 .enable_reg = 0x2d24,
1354 .enable_mask = BIT(9),
1355 .hw.init = &(struct clk_init_data){
1357 .parent_names = (const char *[]){ "gp0_src" },
1359 .ops = &clk_branch_ops,
1360 .flags = CLK_SET_RATE_PARENT,
1365 static struct clk_rcg gp1_src = {
1370 .mnctr_reset_bit = 7,
1371 .mnctr_mode_shift = 5,
1382 .parent_map = gcc_pxo_pll8_cxo_map,
1384 .freq_tbl = clk_tbl_gp,
1386 .enable_reg = 0x2d44,
1387 .enable_mask = BIT(11),
1388 .hw.init = &(struct clk_init_data){
1390 .parent_names = gcc_pxo_pll8_cxo,
1392 .ops = &clk_rcg_ops,
1393 .flags = CLK_SET_RATE_GATE,
1398 static struct clk_branch gp1_clk = {
1402 .enable_reg = 0x2d44,
1403 .enable_mask = BIT(9),
1404 .hw.init = &(struct clk_init_data){
1406 .parent_names = (const char *[]){ "gp1_src" },
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1414 static struct clk_rcg gp2_src = {
1419 .mnctr_reset_bit = 7,
1420 .mnctr_mode_shift = 5,
1431 .parent_map = gcc_pxo_pll8_cxo_map,
1433 .freq_tbl = clk_tbl_gp,
1435 .enable_reg = 0x2d64,
1436 .enable_mask = BIT(11),
1437 .hw.init = &(struct clk_init_data){
1439 .parent_names = gcc_pxo_pll8_cxo,
1441 .ops = &clk_rcg_ops,
1442 .flags = CLK_SET_RATE_GATE,
1447 static struct clk_branch gp2_clk = {
1451 .enable_reg = 0x2d64,
1452 .enable_mask = BIT(9),
1453 .hw.init = &(struct clk_init_data){
1455 .parent_names = (const char *[]){ "gp2_src" },
1457 .ops = &clk_branch_ops,
1458 .flags = CLK_SET_RATE_PARENT,
1463 static struct clk_branch pmem_clk = {
1469 .enable_reg = 0x25a0,
1470 .enable_mask = BIT(4),
1471 .hw.init = &(struct clk_init_data){
1473 .ops = &clk_branch_ops,
1478 static struct clk_rcg prng_src = {
1486 .parent_map = gcc_pxo_pll8_map,
1489 .init = &(struct clk_init_data){
1491 .parent_names = gcc_pxo_pll8,
1493 .ops = &clk_rcg_ops,
1498 static struct clk_branch prng_clk = {
1500 .halt_check = BRANCH_HALT_VOTED,
1503 .enable_reg = 0x3080,
1504 .enable_mask = BIT(10),
1505 .hw.init = &(struct clk_init_data){
1507 .parent_names = (const char *[]){ "prng_src" },
1509 .ops = &clk_branch_ops,
1514 static const struct freq_tbl clk_tbl_sdc[] = {
1515 { 144000, P_PXO, 3, 2, 125 },
1516 { 400000, P_PLL8, 4, 1, 240 },
1517 { 16000000, P_PLL8, 4, 1, 6 },
1518 { 17070000, P_PLL8, 1, 2, 45 },
1519 { 20210000, P_PLL8, 1, 1, 19 },
1520 { 24000000, P_PLL8, 4, 1, 4 },
1521 { 48000000, P_PLL8, 4, 1, 2 },
1525 static struct clk_rcg sdc1_src = {
1530 .mnctr_reset_bit = 7,
1531 .mnctr_mode_shift = 5,
1542 .parent_map = gcc_pxo_pll8_map,
1544 .freq_tbl = clk_tbl_sdc,
1546 .enable_reg = 0x282c,
1547 .enable_mask = BIT(11),
1548 .hw.init = &(struct clk_init_data){
1550 .parent_names = gcc_pxo_pll8,
1552 .ops = &clk_rcg_ops,
1557 static struct clk_branch sdc1_clk = {
1561 .enable_reg = 0x282c,
1562 .enable_mask = BIT(9),
1563 .hw.init = &(struct clk_init_data){
1565 .parent_names = (const char *[]){ "sdc1_src" },
1567 .ops = &clk_branch_ops,
1568 .flags = CLK_SET_RATE_PARENT,
1573 static struct clk_rcg sdc2_src = {
1578 .mnctr_reset_bit = 7,
1579 .mnctr_mode_shift = 5,
1590 .parent_map = gcc_pxo_pll8_map,
1592 .freq_tbl = clk_tbl_sdc,
1594 .enable_reg = 0x284c,
1595 .enable_mask = BIT(11),
1596 .hw.init = &(struct clk_init_data){
1598 .parent_names = gcc_pxo_pll8,
1600 .ops = &clk_rcg_ops,
1605 static struct clk_branch sdc2_clk = {
1609 .enable_reg = 0x284c,
1610 .enable_mask = BIT(9),
1611 .hw.init = &(struct clk_init_data){
1613 .parent_names = (const char *[]){ "sdc2_src" },
1615 .ops = &clk_branch_ops,
1616 .flags = CLK_SET_RATE_PARENT,
1621 static struct clk_rcg sdc3_src = {
1626 .mnctr_reset_bit = 7,
1627 .mnctr_mode_shift = 5,
1638 .parent_map = gcc_pxo_pll8_map,
1640 .freq_tbl = clk_tbl_sdc,
1642 .enable_reg = 0x286c,
1643 .enable_mask = BIT(11),
1644 .hw.init = &(struct clk_init_data){
1646 .parent_names = gcc_pxo_pll8,
1648 .ops = &clk_rcg_ops,
1653 static struct clk_branch sdc3_clk = {
1657 .enable_reg = 0x286c,
1658 .enable_mask = BIT(9),
1659 .hw.init = &(struct clk_init_data){
1661 .parent_names = (const char *[]){ "sdc3_src" },
1663 .ops = &clk_branch_ops,
1664 .flags = CLK_SET_RATE_PARENT,
1669 static struct clk_rcg sdc4_src = {
1674 .mnctr_reset_bit = 7,
1675 .mnctr_mode_shift = 5,
1686 .parent_map = gcc_pxo_pll8_map,
1688 .freq_tbl = clk_tbl_sdc,
1690 .enable_reg = 0x288c,
1691 .enable_mask = BIT(11),
1692 .hw.init = &(struct clk_init_data){
1694 .parent_names = gcc_pxo_pll8,
1696 .ops = &clk_rcg_ops,
1701 static struct clk_branch sdc4_clk = {
1705 .enable_reg = 0x288c,
1706 .enable_mask = BIT(9),
1707 .hw.init = &(struct clk_init_data){
1709 .parent_names = (const char *[]){ "sdc4_src" },
1711 .ops = &clk_branch_ops,
1712 .flags = CLK_SET_RATE_PARENT,
1717 static struct clk_rcg sdc5_src = {
1722 .mnctr_reset_bit = 7,
1723 .mnctr_mode_shift = 5,
1734 .parent_map = gcc_pxo_pll8_map,
1736 .freq_tbl = clk_tbl_sdc,
1738 .enable_reg = 0x28ac,
1739 .enable_mask = BIT(11),
1740 .hw.init = &(struct clk_init_data){
1742 .parent_names = gcc_pxo_pll8,
1744 .ops = &clk_rcg_ops,
1749 static struct clk_branch sdc5_clk = {
1753 .enable_reg = 0x28ac,
1754 .enable_mask = BIT(9),
1755 .hw.init = &(struct clk_init_data){
1757 .parent_names = (const char *[]){ "sdc5_src" },
1759 .ops = &clk_branch_ops,
1760 .flags = CLK_SET_RATE_PARENT,
1765 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1766 { 105000, P_PXO, 1, 1, 256 },
1770 static struct clk_rcg tsif_ref_src = {
1775 .mnctr_reset_bit = 7,
1776 .mnctr_mode_shift = 5,
1787 .parent_map = gcc_pxo_pll8_map,
1789 .freq_tbl = clk_tbl_tsif_ref,
1791 .enable_reg = 0x2710,
1792 .enable_mask = BIT(11),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "tsif_ref_src",
1795 .parent_names = gcc_pxo_pll8,
1797 .ops = &clk_rcg_ops,
1798 .flags = CLK_SET_RATE_GATE,
1803 static struct clk_branch tsif_ref_clk = {
1807 .enable_reg = 0x2710,
1808 .enable_mask = BIT(9),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "tsif_ref_clk",
1811 .parent_names = (const char *[]){ "tsif_ref_src" },
1813 .ops = &clk_branch_ops,
1814 .flags = CLK_SET_RATE_PARENT,
1819 static const struct freq_tbl clk_tbl_usb[] = {
1820 { 60000000, P_PLL8, 1, 5, 32 },
1824 static struct clk_rcg usb_hs1_xcvr_src = {
1829 .mnctr_reset_bit = 7,
1830 .mnctr_mode_shift = 5,
1841 .parent_map = gcc_pxo_pll8_map,
1843 .freq_tbl = clk_tbl_usb,
1845 .enable_reg = 0x290c,
1846 .enable_mask = BIT(11),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "usb_hs1_xcvr_src",
1849 .parent_names = gcc_pxo_pll8,
1851 .ops = &clk_rcg_ops,
1852 .flags = CLK_SET_RATE_GATE,
1857 static struct clk_branch usb_hs1_xcvr_clk = {
1861 .enable_reg = 0x290c,
1862 .enable_mask = BIT(9),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "usb_hs1_xcvr_clk",
1865 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1867 .ops = &clk_branch_ops,
1868 .flags = CLK_SET_RATE_PARENT,
1873 static struct clk_rcg usb_fs1_xcvr_fs_src = {
1878 .mnctr_reset_bit = 7,
1879 .mnctr_mode_shift = 5,
1890 .parent_map = gcc_pxo_pll8_map,
1892 .freq_tbl = clk_tbl_usb,
1894 .enable_reg = 0x2968,
1895 .enable_mask = BIT(11),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "usb_fs1_xcvr_fs_src",
1898 .parent_names = gcc_pxo_pll8,
1900 .ops = &clk_rcg_ops,
1901 .flags = CLK_SET_RATE_GATE,
1906 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
1908 static struct clk_branch usb_fs1_xcvr_fs_clk = {
1912 .enable_reg = 0x2968,
1913 .enable_mask = BIT(9),
1914 .hw.init = &(struct clk_init_data){
1915 .name = "usb_fs1_xcvr_fs_clk",
1916 .parent_names = usb_fs1_xcvr_fs_src_p,
1918 .ops = &clk_branch_ops,
1919 .flags = CLK_SET_RATE_PARENT,
1924 static struct clk_branch usb_fs1_system_clk = {
1928 .enable_reg = 0x296c,
1929 .enable_mask = BIT(4),
1930 .hw.init = &(struct clk_init_data){
1931 .parent_names = usb_fs1_xcvr_fs_src_p,
1933 .name = "usb_fs1_system_clk",
1934 .ops = &clk_branch_ops,
1935 .flags = CLK_SET_RATE_PARENT,
1940 static struct clk_rcg usb_fs2_xcvr_fs_src = {
1945 .mnctr_reset_bit = 7,
1946 .mnctr_mode_shift = 5,
1957 .parent_map = gcc_pxo_pll8_map,
1959 .freq_tbl = clk_tbl_usb,
1961 .enable_reg = 0x2988,
1962 .enable_mask = BIT(11),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "usb_fs2_xcvr_fs_src",
1965 .parent_names = gcc_pxo_pll8,
1967 .ops = &clk_rcg_ops,
1968 .flags = CLK_SET_RATE_GATE,
1973 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
1975 static struct clk_branch usb_fs2_xcvr_fs_clk = {
1979 .enable_reg = 0x2988,
1980 .enable_mask = BIT(9),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "usb_fs2_xcvr_fs_clk",
1983 .parent_names = usb_fs2_xcvr_fs_src_p,
1985 .ops = &clk_branch_ops,
1986 .flags = CLK_SET_RATE_PARENT,
1991 static struct clk_branch usb_fs2_system_clk = {
1995 .enable_reg = 0x298c,
1996 .enable_mask = BIT(4),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "usb_fs2_system_clk",
1999 .parent_names = usb_fs2_xcvr_fs_src_p,
2001 .ops = &clk_branch_ops,
2002 .flags = CLK_SET_RATE_PARENT,
2007 static struct clk_branch gsbi1_h_clk = {
2011 .enable_reg = 0x29c0,
2012 .enable_mask = BIT(4),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gsbi1_h_clk",
2015 .ops = &clk_branch_ops,
2020 static struct clk_branch gsbi2_h_clk = {
2024 .enable_reg = 0x29e0,
2025 .enable_mask = BIT(4),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gsbi2_h_clk",
2028 .ops = &clk_branch_ops,
2033 static struct clk_branch gsbi3_h_clk = {
2037 .enable_reg = 0x2a00,
2038 .enable_mask = BIT(4),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gsbi3_h_clk",
2041 .ops = &clk_branch_ops,
2046 static struct clk_branch gsbi4_h_clk = {
2050 .enable_reg = 0x2a20,
2051 .enable_mask = BIT(4),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gsbi4_h_clk",
2054 .ops = &clk_branch_ops,
2059 static struct clk_branch gsbi5_h_clk = {
2063 .enable_reg = 0x2a40,
2064 .enable_mask = BIT(4),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "gsbi5_h_clk",
2067 .ops = &clk_branch_ops,
2072 static struct clk_branch gsbi6_h_clk = {
2076 .enable_reg = 0x2a60,
2077 .enable_mask = BIT(4),
2078 .hw.init = &(struct clk_init_data){
2079 .name = "gsbi6_h_clk",
2080 .ops = &clk_branch_ops,
2085 static struct clk_branch gsbi7_h_clk = {
2089 .enable_reg = 0x2a80,
2090 .enable_mask = BIT(4),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "gsbi7_h_clk",
2093 .ops = &clk_branch_ops,
2098 static struct clk_branch gsbi8_h_clk = {
2102 .enable_reg = 0x2aa0,
2103 .enable_mask = BIT(4),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gsbi8_h_clk",
2106 .ops = &clk_branch_ops,
2111 static struct clk_branch gsbi9_h_clk = {
2115 .enable_reg = 0x2ac0,
2116 .enable_mask = BIT(4),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gsbi9_h_clk",
2119 .ops = &clk_branch_ops,
2124 static struct clk_branch gsbi10_h_clk = {
2128 .enable_reg = 0x2ae0,
2129 .enable_mask = BIT(4),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gsbi10_h_clk",
2132 .ops = &clk_branch_ops,
2137 static struct clk_branch gsbi11_h_clk = {
2141 .enable_reg = 0x2b00,
2142 .enable_mask = BIT(4),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gsbi11_h_clk",
2145 .ops = &clk_branch_ops,
2150 static struct clk_branch gsbi12_h_clk = {
2154 .enable_reg = 0x2b20,
2155 .enable_mask = BIT(4),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "gsbi12_h_clk",
2158 .ops = &clk_branch_ops,
2163 static struct clk_branch tsif_h_clk = {
2167 .enable_reg = 0x2700,
2168 .enable_mask = BIT(4),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "tsif_h_clk",
2171 .ops = &clk_branch_ops,
2176 static struct clk_branch usb_fs1_h_clk = {
2180 .enable_reg = 0x2960,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "usb_fs1_h_clk",
2184 .ops = &clk_branch_ops,
2189 static struct clk_branch usb_fs2_h_clk = {
2193 .enable_reg = 0x2980,
2194 .enable_mask = BIT(4),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "usb_fs2_h_clk",
2197 .ops = &clk_branch_ops,
2202 static struct clk_branch usb_hs1_h_clk = {
2206 .enable_reg = 0x2900,
2207 .enable_mask = BIT(4),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "usb_hs1_h_clk",
2210 .ops = &clk_branch_ops,
2215 static struct clk_branch sdc1_h_clk = {
2219 .enable_reg = 0x2820,
2220 .enable_mask = BIT(4),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "sdc1_h_clk",
2223 .ops = &clk_branch_ops,
2228 static struct clk_branch sdc2_h_clk = {
2232 .enable_reg = 0x2840,
2233 .enable_mask = BIT(4),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "sdc2_h_clk",
2236 .ops = &clk_branch_ops,
2241 static struct clk_branch sdc3_h_clk = {
2245 .enable_reg = 0x2860,
2246 .enable_mask = BIT(4),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "sdc3_h_clk",
2249 .ops = &clk_branch_ops,
2254 static struct clk_branch sdc4_h_clk = {
2258 .enable_reg = 0x2880,
2259 .enable_mask = BIT(4),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "sdc4_h_clk",
2262 .ops = &clk_branch_ops,
2267 static struct clk_branch sdc5_h_clk = {
2271 .enable_reg = 0x28a0,
2272 .enable_mask = BIT(4),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "sdc5_h_clk",
2275 .ops = &clk_branch_ops,
2280 static struct clk_branch ebi2_2x_clk = {
2284 .enable_reg = 0x2660,
2285 .enable_mask = BIT(4),
2286 .hw.init = &(struct clk_init_data){
2287 .name = "ebi2_2x_clk",
2288 .ops = &clk_branch_ops,
2293 static struct clk_branch ebi2_clk = {
2297 .enable_reg = 0x2664,
2298 .enable_mask = BIT(4),
2299 .hw.init = &(struct clk_init_data){
2301 .ops = &clk_branch_ops,
2306 static struct clk_branch adm0_clk = {
2308 .halt_check = BRANCH_HALT_VOTED,
2311 .enable_reg = 0x3080,
2312 .enable_mask = BIT(2),
2313 .hw.init = &(struct clk_init_data){
2315 .ops = &clk_branch_ops,
2320 static struct clk_branch adm0_pbus_clk = {
2322 .halt_check = BRANCH_HALT_VOTED,
2325 .enable_reg = 0x3080,
2326 .enable_mask = BIT(3),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "adm0_pbus_clk",
2329 .ops = &clk_branch_ops,
2334 static struct clk_branch adm1_clk = {
2337 .halt_check = BRANCH_HALT_VOTED,
2339 .enable_reg = 0x3080,
2340 .enable_mask = BIT(4),
2341 .hw.init = &(struct clk_init_data){
2343 .ops = &clk_branch_ops,
2348 static struct clk_branch adm1_pbus_clk = {
2351 .halt_check = BRANCH_HALT_VOTED,
2353 .enable_reg = 0x3080,
2354 .enable_mask = BIT(5),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "adm1_pbus_clk",
2357 .ops = &clk_branch_ops,
2362 static struct clk_branch modem_ahb1_h_clk = {
2365 .halt_check = BRANCH_HALT_VOTED,
2367 .enable_reg = 0x3080,
2368 .enable_mask = BIT(0),
2369 .hw.init = &(struct clk_init_data){
2370 .name = "modem_ahb1_h_clk",
2371 .ops = &clk_branch_ops,
2376 static struct clk_branch modem_ahb2_h_clk = {
2379 .halt_check = BRANCH_HALT_VOTED,
2381 .enable_reg = 0x3080,
2382 .enable_mask = BIT(1),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "modem_ahb2_h_clk",
2385 .ops = &clk_branch_ops,
2390 static struct clk_branch pmic_arb0_h_clk = {
2392 .halt_check = BRANCH_HALT_VOTED,
2395 .enable_reg = 0x3080,
2396 .enable_mask = BIT(8),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "pmic_arb0_h_clk",
2399 .ops = &clk_branch_ops,
2404 static struct clk_branch pmic_arb1_h_clk = {
2406 .halt_check = BRANCH_HALT_VOTED,
2409 .enable_reg = 0x3080,
2410 .enable_mask = BIT(9),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "pmic_arb1_h_clk",
2413 .ops = &clk_branch_ops,
2418 static struct clk_branch pmic_ssbi2_clk = {
2420 .halt_check = BRANCH_HALT_VOTED,
2423 .enable_reg = 0x3080,
2424 .enable_mask = BIT(7),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "pmic_ssbi2_clk",
2427 .ops = &clk_branch_ops,
2432 static struct clk_branch rpm_msg_ram_h_clk = {
2436 .halt_check = BRANCH_HALT_VOTED,
2439 .enable_reg = 0x3080,
2440 .enable_mask = BIT(6),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "rpm_msg_ram_h_clk",
2443 .ops = &clk_branch_ops,
2448 static struct clk_regmap *gcc_msm8660_clks[] = {
2449 [PLL8] = &pll8.clkr,
2450 [PLL8_VOTE] = &pll8_vote,
2451 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2452 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2453 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2454 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2455 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2456 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2457 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2458 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2459 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2460 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2461 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2462 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2463 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2464 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2465 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2466 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2467 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2468 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2469 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2470 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2471 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2472 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2473 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2474 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2475 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2476 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2477 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2478 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2479 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2480 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2481 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2482 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2483 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2484 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2485 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2486 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2487 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2488 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2489 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2490 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2491 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2492 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2493 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2494 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2495 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2496 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2497 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2498 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2499 [GP0_SRC] = &gp0_src.clkr,
2500 [GP0_CLK] = &gp0_clk.clkr,
2501 [GP1_SRC] = &gp1_src.clkr,
2502 [GP1_CLK] = &gp1_clk.clkr,
2503 [GP2_SRC] = &gp2_src.clkr,
2504 [GP2_CLK] = &gp2_clk.clkr,
2505 [PMEM_CLK] = &pmem_clk.clkr,
2506 [PRNG_SRC] = &prng_src.clkr,
2507 [PRNG_CLK] = &prng_clk.clkr,
2508 [SDC1_SRC] = &sdc1_src.clkr,
2509 [SDC1_CLK] = &sdc1_clk.clkr,
2510 [SDC2_SRC] = &sdc2_src.clkr,
2511 [SDC2_CLK] = &sdc2_clk.clkr,
2512 [SDC3_SRC] = &sdc3_src.clkr,
2513 [SDC3_CLK] = &sdc3_clk.clkr,
2514 [SDC4_SRC] = &sdc4_src.clkr,
2515 [SDC4_CLK] = &sdc4_clk.clkr,
2516 [SDC5_SRC] = &sdc5_src.clkr,
2517 [SDC5_CLK] = &sdc5_clk.clkr,
2518 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2519 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2520 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2521 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2522 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2523 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2524 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2525 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2526 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2527 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2528 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2529 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2530 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2531 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2532 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2533 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2534 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2535 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2536 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2537 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2538 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2539 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2540 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2541 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2542 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2543 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2544 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2545 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2546 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2547 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2548 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2549 [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
2550 [EBI2_CLK] = &ebi2_clk.clkr,
2551 [ADM0_CLK] = &adm0_clk.clkr,
2552 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2553 [ADM1_CLK] = &adm1_clk.clkr,
2554 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2555 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2556 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2557 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2558 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2559 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2560 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2563 static const struct qcom_reset_map gcc_msm8660_resets[] = {
2564 [AFAB_CORE_RESET] = { 0x2080, 7 },
2565 [SCSS_SYS_RESET] = { 0x20b4, 1 },
2566 [SCSS_SYS_POR_RESET] = { 0x20b4 },
2567 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2568 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2569 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2570 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2571 [SFAB_CORE_RESET] = { 0x2120, 7 },
2572 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2573 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2574 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2575 [ADM0_C2_RESET] = { 0x220c, 4 },
2576 [ADM0_C1_RESET] = { 0x220c, 3 },
2577 [ADM0_C0_RESET] = { 0x220c, 2 },
2578 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2579 [ADM0_RESET] = { 0x220c },
2580 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2581 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2582 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2583 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2584 [ADM1_C3_RESET] = { 0x226c, 5 },
2585 [ADM1_C2_RESET] = { 0x226c, 4 },
2586 [ADM1_C1_RESET] = { 0x226c, 3 },
2587 [ADM1_C0_RESET] = { 0x226c, 2 },
2588 [ADM1_PBUS_RESET] = { 0x226c, 1 },
2589 [ADM1_RESET] = { 0x226c },
2590 [IMEM0_RESET] = { 0x2280, 7 },
2591 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2592 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2593 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2594 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2595 [DFAB_CORE_RESET] = { 0x24ac, 7 },
2596 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2597 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2598 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2599 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2600 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2601 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2602 [PPSS_PROC_RESET] = { 0x2594, 1 },
2603 [PPSS_RESET] = { 0x2594 },
2604 [PMEM_RESET] = { 0x25a0, 7 },
2605 [DMA_BAM_RESET] = { 0x25c0, 7 },
2606 [SIC_RESET] = { 0x25e0, 7 },
2607 [SPS_TIC_RESET] = { 0x2600, 7 },
2608 [CFBP0_RESET] = { 0x2650, 7 },
2609 [CFBP1_RESET] = { 0x2654, 7 },
2610 [CFBP2_RESET] = { 0x2658, 7 },
2611 [EBI2_RESET] = { 0x2664, 7 },
2612 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2613 [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2614 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2615 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2616 [TSIF_RESET] = { 0x2700, 7 },
2617 [CE1_RESET] = { 0x2720, 7 },
2618 [CE2_RESET] = { 0x2740, 7 },
2619 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2620 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2621 [RPM_PROC_RESET] = { 0x27c0, 7 },
2622 [RPM_BUS_RESET] = { 0x27c4, 7 },
2623 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2624 [PMIC_ARB0_RESET] = { 0x2800, 7 },
2625 [PMIC_ARB1_RESET] = { 0x2804, 7 },
2626 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2627 [SDC1_RESET] = { 0x2830 },
2628 [SDC2_RESET] = { 0x2850 },
2629 [SDC3_RESET] = { 0x2870 },
2630 [SDC4_RESET] = { 0x2890 },
2631 [SDC5_RESET] = { 0x28b0 },
2632 [USB_HS1_RESET] = { 0x2910 },
2633 [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2634 [USB_HS2_RESET] = { 0x2934 },
2635 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2636 [USB_FS1_RESET] = { 0x2974 },
2637 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2638 [USB_FS2_RESET] = { 0x2994 },
2639 [GSBI1_RESET] = { 0x29dc },
2640 [GSBI2_RESET] = { 0x29fc },
2641 [GSBI3_RESET] = { 0x2a1c },
2642 [GSBI4_RESET] = { 0x2a3c },
2643 [GSBI5_RESET] = { 0x2a5c },
2644 [GSBI6_RESET] = { 0x2a7c },
2645 [GSBI7_RESET] = { 0x2a9c },
2646 [GSBI8_RESET] = { 0x2abc },
2647 [GSBI9_RESET] = { 0x2adc },
2648 [GSBI10_RESET] = { 0x2afc },
2649 [GSBI11_RESET] = { 0x2b1c },
2650 [GSBI12_RESET] = { 0x2b3c },
2651 [SPDM_RESET] = { 0x2b6c },
2652 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2653 [TLMM_H_RESET] = { 0x2ba0, 7 },
2654 [TLMM_RESET] = { 0x2ba4, 7 },
2655 [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2656 [MARM_RESET] = { 0x2bd4 },
2657 [MAHB1_RESET] = { 0x2be4, 7 },
2658 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2659 [MAHB2_RESET] = { 0x2c20, 7 },
2660 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2661 [MODEM_RESET] = { 0x2c48 },
2662 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2663 [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2664 [MSS_SLP_RESET] = { 0x2c60, 7 },
2665 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2666 [MSS_WDOG_RESET] = { 0x2c68 },
2667 [TSSC_RESET] = { 0x2ca0, 7 },
2668 [PDM_RESET] = { 0x2cc0, 12 },
2669 [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2670 [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2671 [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2672 [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2673 [MPM_RESET] = { 0x2da4, 1 },
2674 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2675 [EBI1_RESET] = { 0x2dec, 7 },
2676 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2677 [USB_PHY0_RESET] = { 0x2e20 },
2678 [USB_PHY1_RESET] = { 0x2e40 },
2679 [PRNG_RESET] = { 0x2e80, 12 },
2682 static const struct regmap_config gcc_msm8660_regmap_config = {
2686 .max_register = 0x363c,
2690 static const struct qcom_cc_desc gcc_msm8660_desc = {
2691 .config = &gcc_msm8660_regmap_config,
2692 .clks = gcc_msm8660_clks,
2693 .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2694 .resets = gcc_msm8660_resets,
2695 .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2698 static const struct of_device_id gcc_msm8660_match_table[] = {
2699 { .compatible = "qcom,gcc-msm8660" },
2702 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2704 static int gcc_msm8660_probe(struct platform_device *pdev)
2707 struct device *dev = &pdev->dev;
2709 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2713 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2717 return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2720 static struct platform_driver gcc_msm8660_driver = {
2721 .probe = gcc_msm8660_probe,
2723 .name = "gcc-msm8660",
2724 .of_match_table = gcc_msm8660_match_table,
2728 static int __init gcc_msm8660_init(void)
2730 return platform_driver_register(&gcc_msm8660_driver);
2732 core_initcall(gcc_msm8660_init);
2734 static void __exit gcc_msm8660_exit(void)
2736 platform_driver_unregister(&gcc_msm8660_driver);
2738 module_exit(gcc_msm8660_exit);
2740 MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2741 MODULE_LICENSE("GPL v2");
2742 MODULE_ALIAS("platform:gcc-msm8660");