2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
3 * Copyright (c) BayLibre, SAS.
4 * Author : Neil Armstrong <narmstrong@baylibre.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/bitops.h>
18 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/reset-controller.h>
27 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
28 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
31 #include "clk-regmap.h"
34 #include "clk-branch.h"
37 static struct clk_fixed_factor cxo = {
40 .hw.init = &(struct clk_init_data){
42 .parent_names = (const char *[]){ "cxo_board" },
44 .ops = &clk_fixed_factor_ops,
48 static struct clk_pll pll0 = {
56 .clkr.hw.init = &(struct clk_init_data){
58 .parent_names = (const char *[]){ "cxo" },
64 static struct clk_regmap pll0_vote = {
66 .enable_mask = BIT(0),
67 .hw.init = &(struct clk_init_data){
69 .parent_names = (const char *[]){ "pll8" },
71 .ops = &clk_pll_vote_ops,
75 static struct clk_regmap pll4_vote = {
77 .enable_mask = BIT(4),
78 .hw.init = &(struct clk_init_data){
80 .parent_names = (const char *[]){ "pll4" },
82 .ops = &clk_pll_vote_ops,
86 static struct clk_pll pll8 = {
94 .clkr.hw.init = &(struct clk_init_data){
96 .parent_names = (const char *[]){ "cxo" },
102 static struct clk_regmap pll8_vote = {
103 .enable_reg = 0x34c0,
104 .enable_mask = BIT(8),
105 .hw.init = &(struct clk_init_data){
107 .parent_names = (const char *[]){ "pll8" },
109 .ops = &clk_pll_vote_ops,
113 static struct clk_pll pll14 = {
117 .config_reg = 0x31d4,
119 .status_reg = 0x31d8,
121 .clkr.hw.init = &(struct clk_init_data){
123 .parent_names = (const char *[]){ "cxo" },
129 static struct clk_regmap pll14_vote = {
130 .enable_reg = 0x34c0,
131 .enable_mask = BIT(11),
132 .hw.init = &(struct clk_init_data){
133 .name = "pll14_vote",
134 .parent_names = (const char *[]){ "pll14" },
136 .ops = &clk_pll_vote_ops,
146 static const struct parent_map gcc_cxo_pll8_map[] = {
151 static const char * const gcc_cxo_pll8[] = {
156 static const struct parent_map gcc_cxo_pll14_map[] = {
161 static const char * const gcc_cxo_pll14[] = {
166 static const struct parent_map gcc_cxo_map[] = {
170 static const char * const gcc_cxo[] = {
174 static struct freq_tbl clk_tbl_gsbi_uart[] = {
175 { 1843200, P_PLL8, 2, 6, 625 },
176 { 3686400, P_PLL8, 2, 12, 625 },
177 { 7372800, P_PLL8, 2, 24, 625 },
178 { 14745600, P_PLL8, 2, 48, 625 },
179 { 16000000, P_PLL8, 4, 1, 6 },
180 { 24000000, P_PLL8, 4, 1, 4 },
181 { 32000000, P_PLL8, 4, 1, 3 },
182 { 40000000, P_PLL8, 1, 5, 48 },
183 { 46400000, P_PLL8, 1, 29, 240 },
184 { 48000000, P_PLL8, 4, 1, 2 },
185 { 51200000, P_PLL8, 1, 2, 15 },
186 { 56000000, P_PLL8, 1, 7, 48 },
187 { 58982400, P_PLL8, 1, 96, 625 },
188 { 64000000, P_PLL8, 2, 1, 3 },
192 static struct clk_rcg gsbi1_uart_src = {
197 .mnctr_reset_bit = 7,
198 .mnctr_mode_shift = 5,
209 .parent_map = gcc_cxo_pll8_map,
211 .freq_tbl = clk_tbl_gsbi_uart,
213 .enable_reg = 0x29d4,
214 .enable_mask = BIT(11),
215 .hw.init = &(struct clk_init_data){
216 .name = "gsbi1_uart_src",
217 .parent_names = gcc_cxo_pll8,
220 .flags = CLK_SET_PARENT_GATE,
225 static struct clk_branch gsbi1_uart_clk = {
229 .enable_reg = 0x29d4,
230 .enable_mask = BIT(9),
231 .hw.init = &(struct clk_init_data){
232 .name = "gsbi1_uart_clk",
233 .parent_names = (const char *[]){
237 .ops = &clk_branch_ops,
238 .flags = CLK_SET_RATE_PARENT,
243 static struct clk_rcg gsbi2_uart_src = {
248 .mnctr_reset_bit = 7,
249 .mnctr_mode_shift = 5,
260 .parent_map = gcc_cxo_pll8_map,
262 .freq_tbl = clk_tbl_gsbi_uart,
264 .enable_reg = 0x29f4,
265 .enable_mask = BIT(11),
266 .hw.init = &(struct clk_init_data){
267 .name = "gsbi2_uart_src",
268 .parent_names = gcc_cxo_pll8,
271 .flags = CLK_SET_PARENT_GATE,
276 static struct clk_branch gsbi2_uart_clk = {
280 .enable_reg = 0x29f4,
281 .enable_mask = BIT(9),
282 .hw.init = &(struct clk_init_data){
283 .name = "gsbi2_uart_clk",
284 .parent_names = (const char *[]){
288 .ops = &clk_branch_ops,
289 .flags = CLK_SET_RATE_PARENT,
294 static struct clk_rcg gsbi3_uart_src = {
299 .mnctr_reset_bit = 7,
300 .mnctr_mode_shift = 5,
311 .parent_map = gcc_cxo_pll8_map,
313 .freq_tbl = clk_tbl_gsbi_uart,
315 .enable_reg = 0x2a14,
316 .enable_mask = BIT(11),
317 .hw.init = &(struct clk_init_data){
318 .name = "gsbi3_uart_src",
319 .parent_names = gcc_cxo_pll8,
322 .flags = CLK_SET_PARENT_GATE,
327 static struct clk_branch gsbi3_uart_clk = {
331 .enable_reg = 0x2a14,
332 .enable_mask = BIT(9),
333 .hw.init = &(struct clk_init_data){
334 .name = "gsbi3_uart_clk",
335 .parent_names = (const char *[]){
339 .ops = &clk_branch_ops,
340 .flags = CLK_SET_RATE_PARENT,
345 static struct clk_rcg gsbi4_uart_src = {
350 .mnctr_reset_bit = 7,
351 .mnctr_mode_shift = 5,
362 .parent_map = gcc_cxo_pll8_map,
364 .freq_tbl = clk_tbl_gsbi_uart,
366 .enable_reg = 0x2a34,
367 .enable_mask = BIT(11),
368 .hw.init = &(struct clk_init_data){
369 .name = "gsbi4_uart_src",
370 .parent_names = gcc_cxo_pll8,
373 .flags = CLK_SET_PARENT_GATE,
378 static struct clk_branch gsbi4_uart_clk = {
382 .enable_reg = 0x2a34,
383 .enable_mask = BIT(9),
384 .hw.init = &(struct clk_init_data){
385 .name = "gsbi4_uart_clk",
386 .parent_names = (const char *[]){
390 .ops = &clk_branch_ops,
391 .flags = CLK_SET_RATE_PARENT,
396 static struct clk_rcg gsbi5_uart_src = {
401 .mnctr_reset_bit = 7,
402 .mnctr_mode_shift = 5,
413 .parent_map = gcc_cxo_pll8_map,
415 .freq_tbl = clk_tbl_gsbi_uart,
417 .enable_reg = 0x2a54,
418 .enable_mask = BIT(11),
419 .hw.init = &(struct clk_init_data){
420 .name = "gsbi5_uart_src",
421 .parent_names = gcc_cxo_pll8,
424 .flags = CLK_SET_PARENT_GATE,
429 static struct clk_branch gsbi5_uart_clk = {
433 .enable_reg = 0x2a54,
434 .enable_mask = BIT(9),
435 .hw.init = &(struct clk_init_data){
436 .name = "gsbi5_uart_clk",
437 .parent_names = (const char *[]){
441 .ops = &clk_branch_ops,
442 .flags = CLK_SET_RATE_PARENT,
447 static struct freq_tbl clk_tbl_gsbi_qup[] = {
448 { 960000, P_CXO, 4, 1, 5 },
449 { 4800000, P_CXO, 4, 0, 1 },
450 { 9600000, P_CXO, 2, 0, 1 },
451 { 15060000, P_PLL8, 1, 2, 51 },
452 { 24000000, P_PLL8, 4, 1, 4 },
453 { 25600000, P_PLL8, 1, 1, 15 },
454 { 48000000, P_PLL8, 4, 1, 2 },
455 { 51200000, P_PLL8, 1, 2, 15 },
459 static struct clk_rcg gsbi1_qup_src = {
464 .mnctr_reset_bit = 7,
465 .mnctr_mode_shift = 5,
476 .parent_map = gcc_cxo_pll8_map,
478 .freq_tbl = clk_tbl_gsbi_qup,
480 .enable_reg = 0x29cc,
481 .enable_mask = BIT(11),
482 .hw.init = &(struct clk_init_data){
483 .name = "gsbi1_qup_src",
484 .parent_names = gcc_cxo_pll8,
487 .flags = CLK_SET_PARENT_GATE,
492 static struct clk_branch gsbi1_qup_clk = {
496 .enable_reg = 0x29cc,
497 .enable_mask = BIT(9),
498 .hw.init = &(struct clk_init_data){
499 .name = "gsbi1_qup_clk",
500 .parent_names = (const char *[]){ "gsbi1_qup_src" },
502 .ops = &clk_branch_ops,
503 .flags = CLK_SET_RATE_PARENT,
508 static struct clk_rcg gsbi2_qup_src = {
513 .mnctr_reset_bit = 7,
514 .mnctr_mode_shift = 5,
525 .parent_map = gcc_cxo_pll8_map,
527 .freq_tbl = clk_tbl_gsbi_qup,
529 .enable_reg = 0x29ec,
530 .enable_mask = BIT(11),
531 .hw.init = &(struct clk_init_data){
532 .name = "gsbi2_qup_src",
533 .parent_names = gcc_cxo_pll8,
536 .flags = CLK_SET_PARENT_GATE,
541 static struct clk_branch gsbi2_qup_clk = {
545 .enable_reg = 0x29ec,
546 .enable_mask = BIT(9),
547 .hw.init = &(struct clk_init_data){
548 .name = "gsbi2_qup_clk",
549 .parent_names = (const char *[]){ "gsbi2_qup_src" },
551 .ops = &clk_branch_ops,
552 .flags = CLK_SET_RATE_PARENT,
557 static struct clk_rcg gsbi3_qup_src = {
562 .mnctr_reset_bit = 7,
563 .mnctr_mode_shift = 5,
574 .parent_map = gcc_cxo_pll8_map,
576 .freq_tbl = clk_tbl_gsbi_qup,
578 .enable_reg = 0x2a0c,
579 .enable_mask = BIT(11),
580 .hw.init = &(struct clk_init_data){
581 .name = "gsbi3_qup_src",
582 .parent_names = gcc_cxo_pll8,
585 .flags = CLK_SET_PARENT_GATE,
590 static struct clk_branch gsbi3_qup_clk = {
594 .enable_reg = 0x2a0c,
595 .enable_mask = BIT(9),
596 .hw.init = &(struct clk_init_data){
597 .name = "gsbi3_qup_clk",
598 .parent_names = (const char *[]){ "gsbi3_qup_src" },
600 .ops = &clk_branch_ops,
601 .flags = CLK_SET_RATE_PARENT,
606 static struct clk_rcg gsbi4_qup_src = {
611 .mnctr_reset_bit = 7,
612 .mnctr_mode_shift = 5,
623 .parent_map = gcc_cxo_pll8_map,
625 .freq_tbl = clk_tbl_gsbi_qup,
627 .enable_reg = 0x2a2c,
628 .enable_mask = BIT(11),
629 .hw.init = &(struct clk_init_data){
630 .name = "gsbi4_qup_src",
631 .parent_names = gcc_cxo_pll8,
634 .flags = CLK_SET_PARENT_GATE,
639 static struct clk_branch gsbi4_qup_clk = {
643 .enable_reg = 0x2a2c,
644 .enable_mask = BIT(9),
645 .hw.init = &(struct clk_init_data){
646 .name = "gsbi4_qup_clk",
647 .parent_names = (const char *[]){ "gsbi4_qup_src" },
649 .ops = &clk_branch_ops,
650 .flags = CLK_SET_RATE_PARENT,
655 static struct clk_rcg gsbi5_qup_src = {
660 .mnctr_reset_bit = 7,
661 .mnctr_mode_shift = 5,
672 .parent_map = gcc_cxo_pll8_map,
674 .freq_tbl = clk_tbl_gsbi_qup,
676 .enable_reg = 0x2a4c,
677 .enable_mask = BIT(11),
678 .hw.init = &(struct clk_init_data){
679 .name = "gsbi5_qup_src",
680 .parent_names = gcc_cxo_pll8,
683 .flags = CLK_SET_PARENT_GATE,
688 static struct clk_branch gsbi5_qup_clk = {
692 .enable_reg = 0x2a4c,
693 .enable_mask = BIT(9),
694 .hw.init = &(struct clk_init_data){
695 .name = "gsbi5_qup_clk",
696 .parent_names = (const char *[]){ "gsbi5_qup_src" },
698 .ops = &clk_branch_ops,
699 .flags = CLK_SET_RATE_PARENT,
704 static const struct freq_tbl clk_tbl_gp[] = {
705 { 9600000, P_CXO, 2, 0, 0 },
706 { 19200000, P_CXO, 1, 0, 0 },
710 static struct clk_rcg gp0_src = {
715 .mnctr_reset_bit = 7,
716 .mnctr_mode_shift = 5,
727 .parent_map = gcc_cxo_map,
729 .freq_tbl = clk_tbl_gp,
731 .enable_reg = 0x2d24,
732 .enable_mask = BIT(11),
733 .hw.init = &(struct clk_init_data){
735 .parent_names = gcc_cxo,
738 .flags = CLK_SET_PARENT_GATE,
743 static struct clk_branch gp0_clk = {
747 .enable_reg = 0x2d24,
748 .enable_mask = BIT(9),
749 .hw.init = &(struct clk_init_data){
751 .parent_names = (const char *[]){ "gp0_src" },
753 .ops = &clk_branch_ops,
754 .flags = CLK_SET_RATE_PARENT,
759 static struct clk_rcg gp1_src = {
764 .mnctr_reset_bit = 7,
765 .mnctr_mode_shift = 5,
776 .parent_map = gcc_cxo_map,
778 .freq_tbl = clk_tbl_gp,
780 .enable_reg = 0x2d44,
781 .enable_mask = BIT(11),
782 .hw.init = &(struct clk_init_data){
784 .parent_names = gcc_cxo,
787 .flags = CLK_SET_RATE_GATE,
792 static struct clk_branch gp1_clk = {
796 .enable_reg = 0x2d44,
797 .enable_mask = BIT(9),
798 .hw.init = &(struct clk_init_data){
800 .parent_names = (const char *[]){ "gp1_src" },
802 .ops = &clk_branch_ops,
803 .flags = CLK_SET_RATE_PARENT,
808 static struct clk_rcg gp2_src = {
813 .mnctr_reset_bit = 7,
814 .mnctr_mode_shift = 5,
825 .parent_map = gcc_cxo_map,
827 .freq_tbl = clk_tbl_gp,
829 .enable_reg = 0x2d64,
830 .enable_mask = BIT(11),
831 .hw.init = &(struct clk_init_data){
833 .parent_names = gcc_cxo,
836 .flags = CLK_SET_RATE_GATE,
841 static struct clk_branch gp2_clk = {
845 .enable_reg = 0x2d64,
846 .enable_mask = BIT(9),
847 .hw.init = &(struct clk_init_data){
849 .parent_names = (const char *[]){ "gp2_src" },
851 .ops = &clk_branch_ops,
852 .flags = CLK_SET_RATE_PARENT,
857 static struct clk_branch pmem_clk = {
863 .enable_reg = 0x25a0,
864 .enable_mask = BIT(4),
865 .hw.init = &(struct clk_init_data){
867 .ops = &clk_branch_ops,
872 static struct clk_rcg prng_src = {
880 .parent_map = gcc_cxo_pll8_map,
883 .hw.init = &(struct clk_init_data){
885 .parent_names = gcc_cxo_pll8,
892 static struct clk_branch prng_clk = {
894 .halt_check = BRANCH_HALT_VOTED,
897 .enable_reg = 0x3080,
898 .enable_mask = BIT(10),
899 .hw.init = &(struct clk_init_data){
901 .parent_names = (const char *[]){ "prng_src" },
903 .ops = &clk_branch_ops,
908 static const struct freq_tbl clk_tbl_sdc[] = {
909 { 144000, P_CXO, 1, 1, 133 },
910 { 400000, P_PLL8, 4, 1, 240 },
911 { 16000000, P_PLL8, 4, 1, 6 },
912 { 17070000, P_PLL8, 1, 2, 45 },
913 { 20210000, P_PLL8, 1, 1, 19 },
914 { 24000000, P_PLL8, 4, 1, 4 },
915 { 38400000, P_PLL8, 2, 1, 5 },
916 { 48000000, P_PLL8, 4, 1, 2 },
917 { 64000000, P_PLL8, 3, 1, 2 },
918 { 76800000, P_PLL8, 1, 1, 5 },
922 static struct clk_rcg sdc1_src = {
927 .mnctr_reset_bit = 7,
928 .mnctr_mode_shift = 5,
939 .parent_map = gcc_cxo_pll8_map,
941 .freq_tbl = clk_tbl_sdc,
943 .enable_reg = 0x282c,
944 .enable_mask = BIT(11),
945 .hw.init = &(struct clk_init_data){
947 .parent_names = gcc_cxo_pll8,
954 static struct clk_branch sdc1_clk = {
958 .enable_reg = 0x282c,
959 .enable_mask = BIT(9),
960 .hw.init = &(struct clk_init_data){
962 .parent_names = (const char *[]){ "sdc1_src" },
964 .ops = &clk_branch_ops,
965 .flags = CLK_SET_RATE_PARENT,
970 static struct clk_rcg sdc2_src = {
975 .mnctr_reset_bit = 7,
976 .mnctr_mode_shift = 5,
987 .parent_map = gcc_cxo_pll8_map,
989 .freq_tbl = clk_tbl_sdc,
991 .enable_reg = 0x284c,
992 .enable_mask = BIT(11),
993 .hw.init = &(struct clk_init_data){
995 .parent_names = gcc_cxo_pll8,
1002 static struct clk_branch sdc2_clk = {
1006 .enable_reg = 0x284c,
1007 .enable_mask = BIT(9),
1008 .hw.init = &(struct clk_init_data){
1010 .parent_names = (const char *[]){ "sdc2_src" },
1012 .ops = &clk_branch_ops,
1013 .flags = CLK_SET_RATE_PARENT,
1018 static const struct freq_tbl clk_tbl_usb[] = {
1019 { 60000000, P_PLL8, 1, 5, 32 },
1023 static struct clk_rcg usb_hs1_xcvr_src = {
1028 .mnctr_reset_bit = 7,
1029 .mnctr_mode_shift = 5,
1040 .parent_map = gcc_cxo_pll8_map,
1042 .freq_tbl = clk_tbl_usb,
1044 .enable_reg = 0x290c,
1045 .enable_mask = BIT(11),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "usb_hs1_xcvr_src",
1048 .parent_names = gcc_cxo_pll8,
1050 .ops = &clk_rcg_ops,
1051 .flags = CLK_SET_RATE_GATE,
1056 static struct clk_branch usb_hs1_xcvr_clk = {
1060 .enable_reg = 0x290c,
1061 .enable_mask = BIT(9),
1062 .hw.init = &(struct clk_init_data){
1063 .name = "usb_hs1_xcvr_clk",
1064 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1066 .ops = &clk_branch_ops,
1067 .flags = CLK_SET_RATE_PARENT,
1072 static struct clk_rcg usb_hsic_xcvr_fs_src = {
1077 .mnctr_reset_bit = 7,
1078 .mnctr_mode_shift = 5,
1089 .parent_map = gcc_cxo_pll8_map,
1091 .freq_tbl = clk_tbl_usb,
1093 .enable_reg = 0x2928,
1094 .enable_mask = BIT(11),
1095 .hw.init = &(struct clk_init_data){
1096 .name = "usb_hsic_xcvr_fs_src",
1097 .parent_names = gcc_cxo_pll8,
1099 .ops = &clk_rcg_ops,
1100 .flags = CLK_SET_RATE_GATE,
1105 static struct clk_branch usb_hsic_xcvr_fs_clk = {
1109 .enable_reg = 0x2928,
1110 .enable_mask = BIT(9),
1111 .hw.init = &(struct clk_init_data){
1112 .name = "usb_hsic_xcvr_fs_clk",
1114 (const char *[]){ "usb_hsic_xcvr_fs_src" },
1116 .ops = &clk_branch_ops,
1117 .flags = CLK_SET_RATE_PARENT,
1122 static const struct freq_tbl clk_tbl_usb_hs1_system[] = {
1123 { 60000000, P_PLL8, 1, 5, 32 },
1127 static struct clk_rcg usb_hs1_system_src = {
1132 .mnctr_reset_bit = 7,
1133 .mnctr_mode_shift = 5,
1144 .parent_map = gcc_cxo_pll8_map,
1146 .freq_tbl = clk_tbl_usb_hs1_system,
1148 .enable_reg = 0x36a4,
1149 .enable_mask = BIT(11),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "usb_hs1_system_src",
1152 .parent_names = gcc_cxo_pll8,
1154 .ops = &clk_rcg_ops,
1155 .flags = CLK_SET_RATE_GATE,
1160 static struct clk_branch usb_hs1_system_clk = {
1164 .enable_reg = 0x36a4,
1165 .enable_mask = BIT(9),
1166 .hw.init = &(struct clk_init_data){
1168 (const char *[]){ "usb_hs1_system_src" },
1170 .name = "usb_hs1_system_clk",
1171 .ops = &clk_branch_ops,
1172 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1177 static const struct freq_tbl clk_tbl_usb_hsic_system[] = {
1178 { 64000000, P_PLL8, 1, 1, 6 },
1182 static struct clk_rcg usb_hsic_system_src = {
1187 .mnctr_reset_bit = 7,
1188 .mnctr_mode_shift = 5,
1199 .parent_map = gcc_cxo_pll8_map,
1201 .freq_tbl = clk_tbl_usb_hsic_system,
1203 .enable_reg = 0x2b58,
1204 .enable_mask = BIT(11),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "usb_hsic_system_src",
1207 .parent_names = gcc_cxo_pll8,
1209 .ops = &clk_rcg_ops,
1210 .flags = CLK_SET_RATE_GATE,
1215 static struct clk_branch usb_hsic_system_clk = {
1219 .enable_reg = 0x2b58,
1220 .enable_mask = BIT(9),
1221 .hw.init = &(struct clk_init_data){
1223 (const char *[]){ "usb_hsic_system_src" },
1225 .name = "usb_hsic_system_clk",
1226 .ops = &clk_branch_ops,
1227 .flags = CLK_SET_RATE_PARENT,
1232 static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {
1233 { 48000000, P_PLL14, 1, 0, 0 },
1237 static struct clk_rcg usb_hsic_hsic_src = {
1242 .mnctr_reset_bit = 7,
1243 .mnctr_mode_shift = 5,
1254 .parent_map = gcc_cxo_pll14_map,
1256 .freq_tbl = clk_tbl_usb_hsic_hsic,
1258 .enable_reg = 0x2b50,
1259 .enable_mask = BIT(11),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "usb_hsic_hsic_src",
1262 .parent_names = gcc_cxo_pll14,
1264 .ops = &clk_rcg_ops,
1265 .flags = CLK_SET_RATE_GATE,
1270 static struct clk_branch usb_hsic_hsic_clk = {
1271 .halt_check = BRANCH_HALT_DELAY,
1273 .enable_reg = 0x2b50,
1274 .enable_mask = BIT(9),
1275 .hw.init = &(struct clk_init_data){
1276 .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
1278 .name = "usb_hsic_hsic_clk",
1279 .ops = &clk_branch_ops,
1280 .flags = CLK_SET_RATE_PARENT,
1285 static struct clk_branch usb_hsic_hsio_cal_clk = {
1289 .enable_reg = 0x2b48,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .parent_names = (const char *[]){ "cxo" },
1294 .name = "usb_hsic_hsio_cal_clk",
1295 .ops = &clk_branch_ops,
1300 static struct clk_branch ce1_core_clk = {
1306 .enable_reg = 0x2724,
1307 .enable_mask = BIT(4),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "ce1_core_clk",
1310 .ops = &clk_branch_ops,
1315 static struct clk_branch ce1_h_clk = {
1319 .enable_reg = 0x2720,
1320 .enable_mask = BIT(4),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "ce1_h_clk",
1323 .ops = &clk_branch_ops,
1328 static struct clk_branch dma_bam_h_clk = {
1334 .enable_reg = 0x25c0,
1335 .enable_mask = BIT(4),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "dma_bam_h_clk",
1338 .ops = &clk_branch_ops,
1343 static struct clk_branch gsbi1_h_clk = {
1349 .enable_reg = 0x29c0,
1350 .enable_mask = BIT(4),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "gsbi1_h_clk",
1353 .ops = &clk_branch_ops,
1358 static struct clk_branch gsbi2_h_clk = {
1364 .enable_reg = 0x29e0,
1365 .enable_mask = BIT(4),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "gsbi2_h_clk",
1368 .ops = &clk_branch_ops,
1373 static struct clk_branch gsbi3_h_clk = {
1379 .enable_reg = 0x2a00,
1380 .enable_mask = BIT(4),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gsbi3_h_clk",
1383 .ops = &clk_branch_ops,
1388 static struct clk_branch gsbi4_h_clk = {
1394 .enable_reg = 0x2a20,
1395 .enable_mask = BIT(4),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "gsbi4_h_clk",
1398 .ops = &clk_branch_ops,
1403 static struct clk_branch gsbi5_h_clk = {
1409 .enable_reg = 0x2a40,
1410 .enable_mask = BIT(4),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "gsbi5_h_clk",
1413 .ops = &clk_branch_ops,
1418 static struct clk_branch usb_hs1_h_clk = {
1424 .enable_reg = 0x2900,
1425 .enable_mask = BIT(4),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "usb_hs1_h_clk",
1428 .ops = &clk_branch_ops,
1433 static struct clk_branch usb_hsic_h_clk = {
1437 .enable_reg = 0x2920,
1438 .enable_mask = BIT(4),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "usb_hsic_h_clk",
1441 .ops = &clk_branch_ops,
1446 static struct clk_branch sdc1_h_clk = {
1452 .enable_reg = 0x2820,
1453 .enable_mask = BIT(4),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "sdc1_h_clk",
1456 .ops = &clk_branch_ops,
1461 static struct clk_branch sdc2_h_clk = {
1467 .enable_reg = 0x2840,
1468 .enable_mask = BIT(4),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "sdc2_h_clk",
1471 .ops = &clk_branch_ops,
1476 static struct clk_branch adm0_clk = {
1478 .halt_check = BRANCH_HALT_VOTED,
1481 .enable_reg = 0x3080,
1482 .enable_mask = BIT(2),
1483 .hw.init = &(struct clk_init_data){
1485 .ops = &clk_branch_ops,
1490 static struct clk_branch adm0_pbus_clk = {
1494 .halt_check = BRANCH_HALT_VOTED,
1497 .enable_reg = 0x3080,
1498 .enable_mask = BIT(3),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "adm0_pbus_clk",
1501 .ops = &clk_branch_ops,
1506 static struct clk_branch pmic_arb0_h_clk = {
1508 .halt_check = BRANCH_HALT_VOTED,
1511 .enable_reg = 0x3080,
1512 .enable_mask = BIT(8),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "pmic_arb0_h_clk",
1515 .ops = &clk_branch_ops,
1520 static struct clk_branch pmic_arb1_h_clk = {
1522 .halt_check = BRANCH_HALT_VOTED,
1525 .enable_reg = 0x3080,
1526 .enable_mask = BIT(9),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "pmic_arb1_h_clk",
1529 .ops = &clk_branch_ops,
1534 static struct clk_branch pmic_ssbi2_clk = {
1536 .halt_check = BRANCH_HALT_VOTED,
1539 .enable_reg = 0x3080,
1540 .enable_mask = BIT(7),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "pmic_ssbi2_clk",
1543 .ops = &clk_branch_ops,
1548 static struct clk_branch rpm_msg_ram_h_clk = {
1552 .halt_check = BRANCH_HALT_VOTED,
1555 .enable_reg = 0x3080,
1556 .enable_mask = BIT(6),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "rpm_msg_ram_h_clk",
1559 .ops = &clk_branch_ops,
1564 static struct clk_branch ebi2_clk = {
1570 .enable_reg = 0x2664,
1571 .enable_mask = BIT(6) | BIT(4),
1572 .hw.init = &(struct clk_init_data){
1574 .ops = &clk_branch_ops,
1579 static struct clk_branch ebi2_aon_clk = {
1583 .enable_reg = 0x2664,
1584 .enable_mask = BIT(8),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "ebi2_aon_clk",
1587 .ops = &clk_branch_ops,
1592 static struct clk_hw *gcc_mdm9615_hws[] = {
1596 static struct clk_regmap *gcc_mdm9615_clks[] = {
1597 [PLL0] = &pll0.clkr,
1598 [PLL0_VOTE] = &pll0_vote,
1599 [PLL4_VOTE] = &pll4_vote,
1600 [PLL8] = &pll8.clkr,
1601 [PLL8_VOTE] = &pll8_vote,
1602 [PLL14] = &pll14.clkr,
1603 [PLL14_VOTE] = &pll14_vote,
1604 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
1605 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
1606 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
1607 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
1608 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
1609 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
1610 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
1611 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
1612 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
1613 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
1614 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
1615 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
1616 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
1617 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
1618 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
1619 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
1620 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
1621 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
1622 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
1623 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
1624 [GP0_SRC] = &gp0_src.clkr,
1625 [GP0_CLK] = &gp0_clk.clkr,
1626 [GP1_SRC] = &gp1_src.clkr,
1627 [GP1_CLK] = &gp1_clk.clkr,
1628 [GP2_SRC] = &gp2_src.clkr,
1629 [GP2_CLK] = &gp2_clk.clkr,
1630 [PMEM_A_CLK] = &pmem_clk.clkr,
1631 [PRNG_SRC] = &prng_src.clkr,
1632 [PRNG_CLK] = &prng_clk.clkr,
1633 [SDC1_SRC] = &sdc1_src.clkr,
1634 [SDC1_CLK] = &sdc1_clk.clkr,
1635 [SDC2_SRC] = &sdc2_src.clkr,
1636 [SDC2_CLK] = &sdc2_clk.clkr,
1637 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
1638 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
1639 [USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,
1640 [USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,
1641 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
1642 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
1643 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,
1644 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
1645 [USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,
1646 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
1647 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
1648 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
1649 [CE1_H_CLK] = &ce1_h_clk.clkr,
1650 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
1651 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
1652 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
1653 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
1654 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
1655 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
1656 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
1657 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
1658 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
1659 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
1660 [ADM0_CLK] = &adm0_clk.clkr,
1661 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
1662 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
1663 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
1664 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
1665 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
1666 [EBI2_CLK] = &ebi2_clk.clkr,
1667 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
1670 static const struct qcom_reset_map gcc_mdm9615_resets[] = {
1671 [DMA_BAM_RESET] = { 0x25c0, 7 },
1672 [CE1_H_RESET] = { 0x2720, 7 },
1673 [CE1_CORE_RESET] = { 0x2724, 7 },
1674 [SDC1_RESET] = { 0x2830 },
1675 [SDC2_RESET] = { 0x2850 },
1676 [ADM0_C2_RESET] = { 0x220c, 4 },
1677 [ADM0_C1_RESET] = { 0x220c, 3 },
1678 [ADM0_C0_RESET] = { 0x220c, 2 },
1679 [ADM0_PBUS_RESET] = { 0x220c, 1 },
1680 [ADM0_RESET] = { 0x220c },
1681 [USB_HS1_RESET] = { 0x2910 },
1682 [USB_HSIC_RESET] = { 0x2934 },
1683 [GSBI1_RESET] = { 0x29dc },
1684 [GSBI2_RESET] = { 0x29fc },
1685 [GSBI3_RESET] = { 0x2a1c },
1686 [GSBI4_RESET] = { 0x2a3c },
1687 [GSBI5_RESET] = { 0x2a5c },
1688 [PDM_RESET] = { 0x2CC0, 12 },
1691 static const struct regmap_config gcc_mdm9615_regmap_config = {
1695 .max_register = 0x3660,
1699 static const struct qcom_cc_desc gcc_mdm9615_desc = {
1700 .config = &gcc_mdm9615_regmap_config,
1701 .clks = gcc_mdm9615_clks,
1702 .num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
1703 .resets = gcc_mdm9615_resets,
1704 .num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
1707 static const struct of_device_id gcc_mdm9615_match_table[] = {
1708 { .compatible = "qcom,gcc-mdm9615" },
1711 MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
1713 static int gcc_mdm9615_probe(struct platform_device *pdev)
1715 struct device *dev = &pdev->dev;
1716 struct regmap *regmap;
1720 regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
1722 return PTR_ERR(regmap);
1724 for (i = 0; i < ARRAY_SIZE(gcc_mdm9615_hws); i++) {
1725 ret = devm_clk_hw_register(dev, gcc_mdm9615_hws[i]);
1730 return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
1733 static struct platform_driver gcc_mdm9615_driver = {
1734 .probe = gcc_mdm9615_probe,
1736 .name = "gcc-mdm9615",
1737 .of_match_table = gcc_mdm9615_match_table,
1741 static int __init gcc_mdm9615_init(void)
1743 return platform_driver_register(&gcc_mdm9615_driver);
1745 core_initcall(gcc_mdm9615_init);
1747 static void __exit gcc_mdm9615_exit(void)
1749 platform_driver_unregister(&gcc_mdm9615_driver);
1751 module_exit(gcc_mdm9615_exit);
1753 MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");
1754 MODULE_LICENSE("GPL v2");
1755 MODULE_ALIAS("platform:gcc-mdm9615");