drivers/clk/qcom/gcc-ipq8074.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  16
  17 #include "common.h"
  18 #include "clk-regmap.h"
  19 #include "clk-pll.h"
  20 #include "clk-rcg.h"
  21 #include "clk-branch.h"
  22 #include "clk-alpha-pll.h"
  23 #include "clk-regmap-divider.h"
  24 #include "clk-regmap-mux.h"
  25 #include "reset.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL0_DIV2,
  31         P_GPLL2,
  32         P_GPLL4,
  33         P_GPLL6,
  34         P_SLEEP_CLK,
  35         P_PCIE20_PHY0_PIPE,
  36         P_PCIE20_PHY1_PIPE,
  37         P_USB3PHY_0_PIPE,
  38         P_USB3PHY_1_PIPE,
  39         P_UBI32_PLL,
  40         P_NSS_CRYPTO_PLL,
  41         P_BIAS_PLL,
  42         P_BIAS_PLL_NSS_NOC,
  43         P_UNIPHY0_RX,
  44         P_UNIPHY0_TX,
  45         P_UNIPHY1_RX,
  46         P_UNIPHY1_TX,
  47         P_UNIPHY2_RX,
  48         P_UNIPHY2_TX,
  49 };
  50
  51 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  52         "xo",
  53         "gpll0",
  54         "gpll0_out_main_div2",
  55 };
  56
  57 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  58         { P_XO, 0 },
  59         { P_GPLL0, 1 },
  60         { P_GPLL0_DIV2, 4 },
  61 };
  62
  63 static const struct parent_map gcc_xo_gpll0_map[] = {
  64         { P_XO, 0 },
  65         { P_GPLL0, 1 },
  66 };
  67
  68 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  69         "xo",
  70         "gpll0",
  71         "gpll2",
  72         "gpll0_out_main_div2",
  73 };
  74
  75 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  76         { P_XO, 0 },
  77         { P_GPLL0, 1 },
  78         { P_GPLL2, 2 },
  79         { P_GPLL0_DIV2, 4 },
  80 };
  81
  82 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  83         "xo",
  84         "gpll0",
  85         "sleep_clk",
  86 };
  87
  88 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
  89         { P_XO, 0 },
  90         { P_GPLL0, 2 },
  91         { P_SLEEP_CLK, 6 },
  92 };
  93
  94 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
  95         "xo",
  96         "gpll6",
  97         "gpll0",
  98         "gpll0_out_main_div2",
  99 };
 100
 101 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 102         { P_XO, 0 },
 103         { P_GPLL6, 1 },
 104         { P_GPLL0, 3 },
 105         { P_GPLL0_DIV2, 4 },
 106 };
 107
 108 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 109         "xo",
 110         "gpll0_out_main_div2",
 111         "gpll0",
 112 };
 113
 114 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 115         { P_XO, 0 },
 116         { P_GPLL0_DIV2, 2 },
 117         { P_GPLL0, 1 },
 118 };
 119
 120 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 121         "usb3phy_0_cc_pipe_clk",
 122         "xo",
 123 };
 124
 125 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 126         { P_USB3PHY_0_PIPE, 0 },
 127         { P_XO, 2 },
 128 };
 129
 130 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 131         "usb3phy_1_cc_pipe_clk",
 132         "xo",
 133 };
 134
 135 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 136         { P_USB3PHY_1_PIPE, 0 },
 137         { P_XO, 2 },
 138 };
 139
 140 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 141         "pcie20_phy0_pipe_clk",
 142         "xo",
 143 };
 144
 145 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 146         { P_PCIE20_PHY0_PIPE, 0 },
 147         { P_XO, 2 },
 148 };
 149
 150 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 151         "pcie20_phy1_pipe_clk",
 152         "xo",
 153 };
 154
 155 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 156         { P_PCIE20_PHY1_PIPE, 0 },
 157         { P_XO, 2 },
 158 };
 159
 160 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 161         "xo",
 162         "gpll0",
 163         "gpll6",
 164         "gpll0_out_main_div2",
 165 };
 166
 167 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 168         { P_XO, 0 },
 169         { P_GPLL0, 1 },
 170         { P_GPLL6, 2 },
 171         { P_GPLL0_DIV2, 4 },
 172 };
 173
 174 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 175         "xo",
 176         "gpll0",
 177         "gpll6",
 178         "gpll0_out_main_div2",
 179 };
 180
 181 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 182         { P_XO, 0 },
 183         { P_GPLL0, 1 },
 184         { P_GPLL6, 2 },
 185         { P_GPLL0_DIV2, 3 },
 186 };
 187
 188 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 189         "xo",
 190         "bias_pll_nss_noc_clk",
 191         "gpll0",
 192         "gpll2",
 193 };
 194
 195 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 196         { P_XO, 0 },
 197         { P_BIAS_PLL_NSS_NOC, 1 },
 198         { P_GPLL0, 2 },
 199         { P_GPLL2, 3 },
 200 };
 201
 202 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 203         "xo",
 204         "nss_crypto_pll",
 205         "gpll0",
 206 };
 207
 208 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 209         { P_XO, 0 },
 210         { P_NSS_CRYPTO_PLL, 1 },
 211         { P_GPLL0, 2 },
 212 };
 213
 214 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 215         "xo",
 216         "ubi32_pll",
 217         "gpll0",
 218         "gpll2",
 219         "gpll4",
 220         "gpll6",
 221 };
 222
 223 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 224         { P_XO, 0 },
 225         { P_UBI32_PLL, 1 },
 226         { P_GPLL0, 2 },
 227         { P_GPLL2, 3 },
 228         { P_GPLL4, 4 },
 229         { P_GPLL6, 5 },
 230 };
 231
 232 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 233         "xo",
 234         "gpll0_out_main_div2",
 235 };
 236
 237 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 238         { P_XO, 0 },
 239         { P_GPLL0_DIV2, 1 },
 240 };
 241
 242 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 243         "xo",
 244         "bias_pll_cc_clk",
 245         "gpll0",
 246         "gpll4",
 247         "nss_crypto_pll",
 248         "ubi32_pll",
 249 };
 250
 251 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 252         { P_XO, 0 },
 253         { P_BIAS_PLL, 1 },
 254         { P_GPLL0, 2 },
 255         { P_GPLL4, 3 },
 256         { P_NSS_CRYPTO_PLL, 4 },
 257         { P_UBI32_PLL, 5 },
 258 };
 259
 260 static const char * const gcc_xo_gpll0_gpll4[] = {
 261         "xo",
 262         "gpll0",
 263         "gpll4",
 264 };
 265
 266 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 267         { P_XO, 0 },
 268         { P_GPLL0, 1 },
 269         { P_GPLL4, 2 },
 270 };
 271
 272 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 273         "xo",
 274         "uniphy0_gcc_rx_clk",
 275         "uniphy0_gcc_tx_clk",
 276         "ubi32_pll",
 277         "bias_pll_cc_clk",
 278 };
 279
 280 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 281         { P_XO, 0 },
 282         { P_UNIPHY0_RX, 1 },
 283         { P_UNIPHY0_TX, 2 },
 284         { P_UBI32_PLL, 5 },
 285         { P_BIAS_PLL, 6 },
 286 };
 287
 288 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 289         "xo",
 290         "uniphy0_gcc_tx_clk",
 291         "uniphy0_gcc_rx_clk",
 292         "ubi32_pll",
 293         "bias_pll_cc_clk",
 294 };
 295
 296 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 297         { P_XO, 0 },
 298         { P_UNIPHY0_TX, 1 },
 299         { P_UNIPHY0_RX, 2 },
 300         { P_UBI32_PLL, 5 },
 301         { P_BIAS_PLL, 6 },
 302 };
 303
 304 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 305         "xo",
 306         "uniphy0_gcc_rx_clk",
 307         "uniphy0_gcc_tx_clk",
 308         "uniphy1_gcc_rx_clk",
 309         "uniphy1_gcc_tx_clk",
 310         "ubi32_pll",
 311         "bias_pll_cc_clk",
 312 };
 313
 314 static const struct parent_map
 315 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 316         { P_XO, 0 },
 317         { P_UNIPHY0_RX, 1 },
 318         { P_UNIPHY0_TX, 2 },
 319         { P_UNIPHY1_RX, 3 },
 320         { P_UNIPHY1_TX, 4 },
 321         { P_UBI32_PLL, 5 },
 322         { P_BIAS_PLL, 6 },
 323 };
 324
 325 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 326         "xo",
 327         "uniphy0_gcc_tx_clk",
 328         "uniphy0_gcc_rx_clk",
 329         "uniphy1_gcc_tx_clk",
 330         "uniphy1_gcc_rx_clk",
 331         "ubi32_pll",
 332         "bias_pll_cc_clk",
 333 };
 334
 335 static const struct parent_map
 336 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 337         { P_XO, 0 },
 338         { P_UNIPHY0_TX, 1 },
 339         { P_UNIPHY0_RX, 2 },
 340         { P_UNIPHY1_TX, 3 },
 341         { P_UNIPHY1_RX, 4 },
 342         { P_UBI32_PLL, 5 },
 343         { P_BIAS_PLL, 6 },
 344 };
 345
 346 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 347         "xo",
 348         "uniphy2_gcc_rx_clk",
 349         "uniphy2_gcc_tx_clk",
 350         "ubi32_pll",
 351         "bias_pll_cc_clk",
 352 };
 353
 354 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
 355         { P_XO, 0 },
 356         { P_UNIPHY2_RX, 1 },
 357         { P_UNIPHY2_TX, 2 },
 358         { P_UBI32_PLL, 5 },
 359         { P_BIAS_PLL, 6 },
 360 };
 361
 362 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 363         "xo",
 364         "uniphy2_gcc_tx_clk",
 365         "uniphy2_gcc_rx_clk",
 366         "ubi32_pll",
 367         "bias_pll_cc_clk",
 368 };
 369
 370 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
 371         { P_XO, 0 },
 372         { P_UNIPHY2_TX, 1 },
 373         { P_UNIPHY2_RX, 2 },
 374         { P_UBI32_PLL, 5 },
 375         { P_BIAS_PLL, 6 },
 376 };
 377
 378 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
 379         "xo",
 380         "gpll0",
 381         "gpll6",
 382         "gpll0_out_main_div2",
 383         "sleep_clk",
 384 };
 385
 386 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
 387         { P_XO, 0 },
 388         { P_GPLL0, 1 },
 389         { P_GPLL6, 2 },
 390         { P_GPLL0_DIV2, 4 },
 391         { P_SLEEP_CLK, 6 },
 392 };
 393
 394 static struct clk_alpha_pll gpll0_main = {
 395         .offset = 0x21000,
 396         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 397         .clkr = {
 398                 .enable_reg = 0x0b000,
 399                 .enable_mask = BIT(0),
 400                 .hw.init = &(struct clk_init_data){
 401                         .name = "gpll0_main",
 402                         .parent_names = (const char *[]){
 403                                 "xo"
 404                         },
 405                         .num_parents = 1,
 406                         .ops = &clk_alpha_pll_ops,
 407                 },
 408         },
 409 };
 410
 411 static struct clk_fixed_factor gpll0_out_main_div2 = {
 412         .mult = 1,
 413         .div = 2,
 414         .hw.init = &(struct clk_init_data){
 415                 .name = "gpll0_out_main_div2",
 416                 .parent_names = (const char *[]){
 417                         "gpll0_main"
 418                 },
 419                 .num_parents = 1,
 420                 .ops = &clk_fixed_factor_ops,
 421                 .flags = CLK_SET_RATE_PARENT,
 422         },
 423 };
 424
 425 static struct clk_alpha_pll_postdiv gpll0 = {
 426         .offset = 0x21000,
 427         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 428         .width = 4,
 429         .clkr.hw.init = &(struct clk_init_data){
 430                 .name = "gpll0",
 431                 .parent_names = (const char *[]){
 432                         "gpll0_main"
 433                 },
 434                 .num_parents = 1,
 435                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 436         },
 437 };
 438
 439 static struct clk_alpha_pll gpll2_main = {
 440         .offset = 0x4a000,
 441         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 442         .clkr = {
 443                 .enable_reg = 0x0b000,
 444                 .enable_mask = BIT(2),
 445                 .hw.init = &(struct clk_init_data){
 446                         .name = "gpll2_main",
 447                         .parent_names = (const char *[]){
 448                                 "xo"
 449                         },
 450                         .num_parents = 1,
 451                         .ops = &clk_alpha_pll_ops,
 452                         .flags = CLK_IS_CRITICAL,
 453                 },
 454         },
 455 };
 456
 457 static struct clk_alpha_pll_postdiv gpll2 = {
 458         .offset = 0x4a000,
 459         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 460         .width = 4,
 461         .clkr.hw.init = &(struct clk_init_data){
 462                 .name = "gpll2",
 463                 .parent_names = (const char *[]){
 464                         "gpll2_main"
 465                 },
 466                 .num_parents = 1,
 467                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 468                 .flags = CLK_SET_RATE_PARENT,
 469         },
 470 };
 471
 472 static struct clk_alpha_pll gpll4_main = {
 473         .offset = 0x24000,
 474         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 475         .clkr = {
 476                 .enable_reg = 0x0b000,
 477                 .enable_mask = BIT(5),
 478                 .hw.init = &(struct clk_init_data){
 479                         .name = "gpll4_main",
 480                         .parent_names = (const char *[]){
 481                                 "xo"
 482                         },
 483                         .num_parents = 1,
 484                         .ops = &clk_alpha_pll_ops,
 485                         .flags = CLK_IS_CRITICAL,
 486                 },
 487         },
 488 };
 489
 490 static struct clk_alpha_pll_postdiv gpll4 = {
 491         .offset = 0x24000,
 492         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 493         .width = 4,
 494         .clkr.hw.init = &(struct clk_init_data){
 495                 .name = "gpll4",
 496                 .parent_names = (const char *[]){
 497                         "gpll4_main"
 498                 },
 499                 .num_parents = 1,
 500                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 501                 .flags = CLK_SET_RATE_PARENT,
 502         },
 503 };
 504
 505 static struct clk_alpha_pll gpll6_main = {
 506         .offset = 0x37000,
 507         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 508         .flags = SUPPORTS_DYNAMIC_UPDATE,
 509         .clkr = {
 510                 .enable_reg = 0x0b000,
 511                 .enable_mask = BIT(7),
 512                 .hw.init = &(struct clk_init_data){
 513                         .name = "gpll6_main",
 514                         .parent_names = (const char *[]){
 515                                 "xo"
 516                         },
 517                         .num_parents = 1,
 518                         .ops = &clk_alpha_pll_ops,
 519                         .flags = CLK_IS_CRITICAL,
 520                 },
 521         },
 522 };
 523
 524 static struct clk_alpha_pll_postdiv gpll6 = {
 525         .offset = 0x37000,
 526         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 527         .width = 2,
 528         .clkr.hw.init = &(struct clk_init_data){
 529                 .name = "gpll6",
 530                 .parent_names = (const char *[]){
 531                         "gpll6_main"
 532                 },
 533                 .num_parents = 1,
 534                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 535                 .flags = CLK_SET_RATE_PARENT,
 536         },
 537 };
 538
 539 static struct clk_fixed_factor gpll6_out_main_div2 = {
 540         .mult = 1,
 541         .div = 2,
 542         .hw.init = &(struct clk_init_data){
 543                 .name = "gpll6_out_main_div2",
 544                 .parent_names = (const char *[]){
 545                         "gpll6_main"
 546                 },
 547                 .num_parents = 1,
 548                 .ops = &clk_fixed_factor_ops,
 549                 .flags = CLK_SET_RATE_PARENT,
 550         },
 551 };
 552
 553 static struct clk_alpha_pll ubi32_pll_main = {
 554         .offset = 0x25000,
 555         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 556         .flags = SUPPORTS_DYNAMIC_UPDATE,
 557         .clkr = {
 558                 .enable_reg = 0x0b000,
 559                 .enable_mask = BIT(6),
 560                 .hw.init = &(struct clk_init_data){
 561                         .name = "ubi32_pll_main",
 562                         .parent_names = (const char *[]){
 563                                 "xo"
 564                         },
 565                         .num_parents = 1,
 566                         .ops = &clk_alpha_pll_huayra_ops,
 567                 },
 568         },
 569 };
 570
 571 static struct clk_alpha_pll_postdiv ubi32_pll = {
 572         .offset = 0x25000,
 573         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 574         .width = 2,
 575         .clkr.hw.init = &(struct clk_init_data){
 576                 .name = "ubi32_pll",
 577                 .parent_names = (const char *[]){
 578                         "ubi32_pll_main"
 579                 },
 580                 .num_parents = 1,
 581                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 582                 .flags = CLK_SET_RATE_PARENT,
 583         },
 584 };
 585
 586 static struct clk_alpha_pll nss_crypto_pll_main = {
 587         .offset = 0x22000,
 588         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 589         .clkr = {
 590                 .enable_reg = 0x0b000,
 591                 .enable_mask = BIT(4),
 592                 .hw.init = &(struct clk_init_data){
 593                         .name = "nss_crypto_pll_main",
 594                         .parent_names = (const char *[]){
 595                                 "xo"
 596                         },
 597                         .num_parents = 1,
 598                         .ops = &clk_alpha_pll_ops,
 599                 },
 600         },
 601 };
 602
 603 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 604         .offset = 0x22000,
 605         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 606         .width = 4,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "nss_crypto_pll",
 609                 .parent_names = (const char *[]){
 610                         "nss_crypto_pll_main"
 611                 },
 612                 .num_parents = 1,
 613                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 614                 .flags = CLK_SET_RATE_PARENT,
 615         },
 616 };
 617
 618 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 619         F(19200000, P_XO, 1, 0, 0),
 620         F(50000000, P_GPLL0, 16, 0, 0),
 621         F(100000000, P_GPLL0, 8, 0, 0),
 622         { }
 623 };
 624
 625 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 626         .cmd_rcgr = 0x27000,
 627         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 628         .hid_width = 5,
 629         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "pcnoc_bfdcd_clk_src",
 632                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 633                 .num_parents = 3,
 634                 .ops = &clk_rcg2_ops,
 635                 .flags = CLK_IS_CRITICAL,
 636         },
 637 };
 638
 639 static struct clk_fixed_factor pcnoc_clk_src = {
 640         .mult = 1,
 641         .div = 1,
 642         .hw.init = &(struct clk_init_data){
 643                 .name = "pcnoc_clk_src",
 644                 .parent_names = (const char *[]){
 645                         "pcnoc_bfdcd_clk_src"
 646                 },
 647                 .num_parents = 1,
 648                 .ops = &clk_fixed_factor_ops,
 649                 .flags = CLK_SET_RATE_PARENT,
 650         },
 651 };
 652
 653 static struct clk_branch gcc_sleep_clk_src = {
 654         .halt_reg = 0x30000,
 655         .clkr = {
 656                 .enable_reg = 0x30000,
 657                 .enable_mask = BIT(1),
 658                 .hw.init = &(struct clk_init_data){
 659                         .name = "gcc_sleep_clk_src",
 660                         .parent_names = (const char *[]){
 661                                 "sleep_clk"
 662                         },
 663                         .num_parents = 1,
 664                         .ops = &clk_branch2_ops,
 665                         .flags = CLK_IS_CRITICAL,
 666                 },
 667         },
 668 };
 669
 670 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 671         F(19200000, P_XO, 1, 0, 0),
 672         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 673         F(50000000, P_GPLL0, 16, 0, 0),
 674         { }
 675 };
 676
 677 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 678         .cmd_rcgr = 0x0200c,
 679         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 680         .hid_width = 5,
 681         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 682         .clkr.hw.init = &(struct clk_init_data){
 683                 .name = "blsp1_qup1_i2c_apps_clk_src",
 684                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 685                 .num_parents = 3,
 686                 .ops = &clk_rcg2_ops,
 687         },
 688 };
 689
 690 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 691         F(960000, P_XO, 10, 1, 2),
 692         F(4800000, P_XO, 4, 0, 0),
 693         F(9600000, P_XO, 2, 0, 0),
 694         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 695         F(16000000, P_GPLL0, 10, 1, 5),
 696         F(19200000, P_XO, 1, 0, 0),
 697         F(25000000, P_GPLL0, 16, 1, 2),
 698         F(50000000, P_GPLL0, 16, 0, 0),
 699         { }
 700 };
 701
 702 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 703         .cmd_rcgr = 0x02024,
 704         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 705         .mnd_width = 8,
 706         .hid_width = 5,
 707         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 708         .clkr.hw.init = &(struct clk_init_data){
 709                 .name = "blsp1_qup1_spi_apps_clk_src",
 710                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 711                 .num_parents = 3,
 712                 .ops = &clk_rcg2_ops,
 713         },
 714 };
 715
 716 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 717         .cmd_rcgr = 0x03000,
 718         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 719         .hid_width = 5,
 720         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 721         .clkr.hw.init = &(struct clk_init_data){
 722                 .name = "blsp1_qup2_i2c_apps_clk_src",
 723                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 724                 .num_parents = 3,
 725                 .ops = &clk_rcg2_ops,
 726         },
 727 };
 728
 729 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 730         .cmd_rcgr = 0x03014,
 731         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 732         .mnd_width = 8,
 733         .hid_width = 5,
 734         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "blsp1_qup2_spi_apps_clk_src",
 737                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 738                 .num_parents = 3,
 739                 .ops = &clk_rcg2_ops,
 740         },
 741 };
 742
 743 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 744         .cmd_rcgr = 0x04000,
 745         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 746         .hid_width = 5,
 747         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 748         .clkr.hw.init = &(struct clk_init_data){
 749                 .name = "blsp1_qup3_i2c_apps_clk_src",
 750                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 751                 .num_parents = 3,
 752                 .ops = &clk_rcg2_ops,
 753         },
 754 };
 755
 756 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 757         .cmd_rcgr = 0x04014,
 758         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 759         .mnd_width = 8,
 760         .hid_width = 5,
 761         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 762         .clkr.hw.init = &(struct clk_init_data){
 763                 .name = "blsp1_qup3_spi_apps_clk_src",
 764                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 765                 .num_parents = 3,
 766                 .ops = &clk_rcg2_ops,
 767         },
 768 };
 769
 770 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 771         .cmd_rcgr = 0x05000,
 772         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 773         .hid_width = 5,
 774         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 775         .clkr.hw.init = &(struct clk_init_data){
 776                 .name = "blsp1_qup4_i2c_apps_clk_src",
 777                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 778                 .num_parents = 3,
 779                 .ops = &clk_rcg2_ops,
 780         },
 781 };
 782
 783 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 784         .cmd_rcgr = 0x05014,
 785         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 786         .mnd_width = 8,
 787         .hid_width = 5,
 788         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 789         .clkr.hw.init = &(struct clk_init_data){
 790                 .name = "blsp1_qup4_spi_apps_clk_src",
 791                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 792                 .num_parents = 3,
 793                 .ops = &clk_rcg2_ops,
 794         },
 795 };
 796
 797 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 798         .cmd_rcgr = 0x06000,
 799         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 800         .hid_width = 5,
 801         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 802         .clkr.hw.init = &(struct clk_init_data){
 803                 .name = "blsp1_qup5_i2c_apps_clk_src",
 804                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 805                 .num_parents = 3,
 806                 .ops = &clk_rcg2_ops,
 807         },
 808 };
 809
 810 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 811         .cmd_rcgr = 0x06014,
 812         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 813         .mnd_width = 8,
 814         .hid_width = 5,
 815         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 816         .clkr.hw.init = &(struct clk_init_data){
 817                 .name = "blsp1_qup5_spi_apps_clk_src",
 818                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 819                 .num_parents = 3,
 820                 .ops = &clk_rcg2_ops,
 821         },
 822 };
 823
 824 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 825         .cmd_rcgr = 0x07000,
 826         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 827         .hid_width = 5,
 828         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 829         .clkr.hw.init = &(struct clk_init_data){
 830                 .name = "blsp1_qup6_i2c_apps_clk_src",
 831                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 832                 .num_parents = 3,
 833                 .ops = &clk_rcg2_ops,
 834         },
 835 };
 836
 837 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 838         .cmd_rcgr = 0x07014,
 839         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 840         .mnd_width = 8,
 841         .hid_width = 5,
 842         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "blsp1_qup6_spi_apps_clk_src",
 845                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 846                 .num_parents = 3,
 847                 .ops = &clk_rcg2_ops,
 848         },
 849 };
 850
 851 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 852         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 853         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 854         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 855         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 856         F(19200000, P_XO, 1, 0, 0),
 857         F(24000000, P_GPLL0, 1, 3, 100),
 858         F(25000000, P_GPLL0, 16, 1, 2),
 859         F(32000000, P_GPLL0, 1, 1, 25),
 860         F(40000000, P_GPLL0, 1, 1, 20),
 861         F(46400000, P_GPLL0, 1, 29, 500),
 862         F(48000000, P_GPLL0, 1, 3, 50),
 863         F(51200000, P_GPLL0, 1, 8, 125),
 864         F(56000000, P_GPLL0, 1, 7, 100),
 865         F(58982400, P_GPLL0, 1, 1152, 15625),
 866         F(60000000, P_GPLL0, 1, 3, 40),
 867         F(64000000, P_GPLL0, 12.5, 1, 1),
 868         { }
 869 };
 870
 871 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 872         .cmd_rcgr = 0x02044,
 873         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 874         .mnd_width = 16,
 875         .hid_width = 5,
 876         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 877         .clkr.hw.init = &(struct clk_init_data){
 878                 .name = "blsp1_uart1_apps_clk_src",
 879                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 880                 .num_parents = 3,
 881                 .ops = &clk_rcg2_ops,
 882         },
 883 };
 884
 885 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 886         .cmd_rcgr = 0x03034,
 887         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 888         .mnd_width = 16,
 889         .hid_width = 5,
 890         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 891         .clkr.hw.init = &(struct clk_init_data){
 892                 .name = "blsp1_uart2_apps_clk_src",
 893                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 894                 .num_parents = 3,
 895                 .ops = &clk_rcg2_ops,
 896         },
 897 };
 898
 899 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 900         .cmd_rcgr = 0x04034,
 901         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 902         .mnd_width = 16,
 903         .hid_width = 5,
 904         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 905         .clkr.hw.init = &(struct clk_init_data){
 906                 .name = "blsp1_uart3_apps_clk_src",
 907                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 908                 .num_parents = 3,
 909                 .ops = &clk_rcg2_ops,
 910         },
 911 };
 912
 913 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 914         .cmd_rcgr = 0x05034,
 915         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 916         .mnd_width = 16,
 917         .hid_width = 5,
 918         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 919         .clkr.hw.init = &(struct clk_init_data){
 920                 .name = "blsp1_uart4_apps_clk_src",
 921                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 922                 .num_parents = 3,
 923                 .ops = &clk_rcg2_ops,
 924         },
 925 };
 926
 927 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 928         .cmd_rcgr = 0x06034,
 929         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 930         .mnd_width = 16,
 931         .hid_width = 5,
 932         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 933         .clkr.hw.init = &(struct clk_init_data){
 934                 .name = "blsp1_uart5_apps_clk_src",
 935                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 936                 .num_parents = 3,
 937                 .ops = &clk_rcg2_ops,
 938         },
 939 };
 940
 941 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 942         .cmd_rcgr = 0x07034,
 943         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 944         .mnd_width = 16,
 945         .hid_width = 5,
 946         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "blsp1_uart6_apps_clk_src",
 949                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 950                 .num_parents = 3,
 951                 .ops = &clk_rcg2_ops,
 952         },
 953 };
 954
 955 static const struct clk_parent_data gcc_xo_gpll0[] = {
 956         { .fw_name = "xo" },
 957         { .hw = &gpll0.clkr.hw },
 958 };
 959
 960 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 961         F(19200000, P_XO, 1, 0, 0),
 962         F(200000000, P_GPLL0, 4, 0, 0),
 963         { }
 964 };
 965
 966 static struct clk_rcg2 pcie0_axi_clk_src = {
 967         .cmd_rcgr = 0x75054,
 968         .freq_tbl = ftbl_pcie_axi_clk_src,
 969         .hid_width = 5,
 970         .parent_map = gcc_xo_gpll0_map,
 971         .clkr.hw.init = &(struct clk_init_data){
 972                 .name = "pcie0_axi_clk_src",
 973                 .parent_data = gcc_xo_gpll0,
 974                 .num_parents = 2,
 975                 .ops = &clk_rcg2_ops,
 976         },
 977 };
 978
 979 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 980         F(19200000, P_XO, 1, 0, 0),
 981 };
 982
 983 static struct clk_rcg2 pcie0_aux_clk_src = {
 984         .cmd_rcgr = 0x75024,
 985         .freq_tbl = ftbl_pcie_aux_clk_src,
 986         .mnd_width = 16,
 987         .hid_width = 5,
 988         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 989         .clkr.hw.init = &(struct clk_init_data){
 990                 .name = "pcie0_aux_clk_src",
 991                 .parent_names = gcc_xo_gpll0_sleep_clk,
 992                 .num_parents = 3,
 993                 .ops = &clk_rcg2_ops,
 994         },
 995 };
 996
 997 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 998         .reg = 0x7501c,
 999         .shift = 8,
1000         .width = 2,
1001         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1002         .clkr = {
1003                 .hw.init = &(struct clk_init_data){
1004                         .name = "pcie0_pipe_clk_src",
1005                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1006                         .num_parents = 2,
1007                         .ops = &clk_regmap_mux_closest_ops,
1008                         .flags = CLK_SET_RATE_PARENT,
1009                 },
1010         },
1011 };
1012
1013 static struct clk_rcg2 pcie1_axi_clk_src = {
1014         .cmd_rcgr = 0x76054,
1015         .freq_tbl = ftbl_pcie_axi_clk_src,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_gpll0_map,
1018         .clkr.hw.init = &(struct clk_init_data){
1019                 .name = "pcie1_axi_clk_src",
1020                 .parent_data = gcc_xo_gpll0,
1021                 .num_parents = 2,
1022                 .ops = &clk_rcg2_ops,
1023         },
1024 };
1025
1026 static struct clk_rcg2 pcie1_aux_clk_src = {
1027         .cmd_rcgr = 0x76024,
1028         .freq_tbl = ftbl_pcie_aux_clk_src,
1029         .mnd_width = 16,
1030         .hid_width = 5,
1031         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1032         .clkr.hw.init = &(struct clk_init_data){
1033                 .name = "pcie1_aux_clk_src",
1034                 .parent_names = gcc_xo_gpll0_sleep_clk,
1035                 .num_parents = 3,
1036                 .ops = &clk_rcg2_ops,
1037         },
1038 };
1039
1040 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1041         .reg = 0x7601c,
1042         .shift = 8,
1043         .width = 2,
1044         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1045         .clkr = {
1046                 .hw.init = &(struct clk_init_data){
1047                         .name = "pcie1_pipe_clk_src",
1048                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1049                         .num_parents = 2,
1050                         .ops = &clk_regmap_mux_closest_ops,
1051                         .flags = CLK_SET_RATE_PARENT,
1052                 },
1053         },
1054 };
1055
1056 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1057         F(144000, P_XO, 16, 3, 25),
1058         F(400000, P_XO, 12, 1, 4),
1059         F(24000000, P_GPLL2, 12, 1, 4),
1060         F(48000000, P_GPLL2, 12, 1, 2),
1061         F(96000000, P_GPLL2, 12, 0, 0),
1062         F(177777778, P_GPLL0, 4.5, 0, 0),
1063         F(192000000, P_GPLL2, 6, 0, 0),
1064         F(384000000, P_GPLL2, 3, 0, 0),
1065         { }
1066 };
1067
1068 static struct clk_rcg2 sdcc1_apps_clk_src = {
1069         .cmd_rcgr = 0x42004,
1070         .freq_tbl = ftbl_sdcc_apps_clk_src,
1071         .mnd_width = 8,
1072         .hid_width = 5,
1073         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1074         .clkr.hw.init = &(struct clk_init_data){
1075                 .name = "sdcc1_apps_clk_src",
1076                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1077                 .num_parents = 4,
1078                 .ops = &clk_rcg2_floor_ops,
1079         },
1080 };
1081
1082 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1083         F(19200000, P_XO, 1, 0, 0),
1084         F(160000000, P_GPLL0, 5, 0, 0),
1085         F(308570000, P_GPLL6, 3.5, 0, 0),
1086 };
1087
1088 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1089         .cmd_rcgr = 0x5d000,
1090         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1091         .mnd_width = 8,
1092         .hid_width = 5,
1093         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1094         .clkr.hw.init = &(struct clk_init_data){
1095                 .name = "sdcc1_ice_core_clk_src",
1096                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1097                 .num_parents = 4,
1098                 .ops = &clk_rcg2_ops,
1099         },
1100 };
1101
1102 static struct clk_rcg2 sdcc2_apps_clk_src = {
1103         .cmd_rcgr = 0x43004,
1104         .freq_tbl = ftbl_sdcc_apps_clk_src,
1105         .mnd_width = 8,
1106         .hid_width = 5,
1107         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1108         .clkr.hw.init = &(struct clk_init_data){
1109                 .name = "sdcc2_apps_clk_src",
1110                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1111                 .num_parents = 4,
1112                 .ops = &clk_rcg2_floor_ops,
1113         },
1114 };
1115
1116 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1117         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1118         F(100000000, P_GPLL0, 8, 0, 0),
1119         F(133330000, P_GPLL0, 6, 0, 0),
1120         { }
1121 };
1122
1123 static struct clk_rcg2 usb0_master_clk_src = {
1124         .cmd_rcgr = 0x3e00c,
1125         .freq_tbl = ftbl_usb_master_clk_src,
1126         .mnd_width = 8,
1127         .hid_width = 5,
1128         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1129         .clkr.hw.init = &(struct clk_init_data){
1130                 .name = "usb0_master_clk_src",
1131                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1132                 .num_parents = 3,
1133                 .ops = &clk_rcg2_ops,
1134         },
1135 };
1136
1137 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1138         F(19200000, P_XO, 1, 0, 0),
1139         { }
1140 };
1141
1142 static struct clk_rcg2 usb0_aux_clk_src = {
1143         .cmd_rcgr = 0x3e05c,
1144         .freq_tbl = ftbl_usb_aux_clk_src,
1145         .mnd_width = 16,
1146         .hid_width = 5,
1147         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "usb0_aux_clk_src",
1150                 .parent_names = gcc_xo_gpll0_sleep_clk,
1151                 .num_parents = 3,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1157         F(19200000, P_XO, 1, 0, 0),
1158         F(20000000, P_GPLL6, 6, 1, 9),
1159         F(60000000, P_GPLL6, 6, 1, 3),
1160         { }
1161 };
1162
1163 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1164         .cmd_rcgr = 0x3e020,
1165         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1166         .mnd_width = 8,
1167         .hid_width = 5,
1168         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1169         .clkr.hw.init = &(struct clk_init_data){
1170                 .name = "usb0_mock_utmi_clk_src",
1171                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1172                 .num_parents = 4,
1173                 .ops = &clk_rcg2_ops,
1174         },
1175 };
1176
1177 static struct clk_regmap_mux usb0_pipe_clk_src = {
1178         .reg = 0x3e048,
1179         .shift = 8,
1180         .width = 2,
1181         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1182         .clkr = {
1183                 .hw.init = &(struct clk_init_data){
1184                         .name = "usb0_pipe_clk_src",
1185                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1186                         .num_parents = 2,
1187                         .ops = &clk_regmap_mux_closest_ops,
1188                         .flags = CLK_SET_RATE_PARENT,
1189                 },
1190         },
1191 };
1192
1193 static struct clk_rcg2 usb1_master_clk_src = {
1194         .cmd_rcgr = 0x3f00c,
1195         .freq_tbl = ftbl_usb_master_clk_src,
1196         .mnd_width = 8,
1197         .hid_width = 5,
1198         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1199         .clkr.hw.init = &(struct clk_init_data){
1200                 .name = "usb1_master_clk_src",
1201                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1202                 .num_parents = 3,
1203                 .ops = &clk_rcg2_ops,
1204         },
1205 };
1206
1207 static struct clk_rcg2 usb1_aux_clk_src = {
1208         .cmd_rcgr = 0x3f05c,
1209         .freq_tbl = ftbl_usb_aux_clk_src,
1210         .mnd_width = 16,
1211         .hid_width = 5,
1212         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1213         .clkr.hw.init = &(struct clk_init_data){
1214                 .name = "usb1_aux_clk_src",
1215                 .parent_names = gcc_xo_gpll0_sleep_clk,
1216                 .num_parents = 3,
1217                 .ops = &clk_rcg2_ops,
1218         },
1219 };
1220
1221 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1222         .cmd_rcgr = 0x3f020,
1223         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1224         .mnd_width = 8,
1225         .hid_width = 5,
1226         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1227         .clkr.hw.init = &(struct clk_init_data){
1228                 .name = "usb1_mock_utmi_clk_src",
1229                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1230                 .num_parents = 4,
1231                 .ops = &clk_rcg2_ops,
1232         },
1233 };
1234
1235 static struct clk_regmap_mux usb1_pipe_clk_src = {
1236         .reg = 0x3f048,
1237         .shift = 8,
1238         .width = 2,
1239         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1240         .clkr = {
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "usb1_pipe_clk_src",
1243                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1244                         .num_parents = 2,
1245                         .ops = &clk_regmap_mux_closest_ops,
1246                         .flags = CLK_SET_RATE_PARENT,
1247                 },
1248         },
1249 };
1250
1251 static struct clk_branch gcc_xo_clk_src = {
1252         .halt_reg = 0x30018,
1253         .clkr = {
1254                 .enable_reg = 0x30018,
1255                 .enable_mask = BIT(1),
1256                 .hw.init = &(struct clk_init_data){
1257                         .name = "gcc_xo_clk_src",
1258                         .parent_names = (const char *[]){
1259                                 "xo"
1260                         },
1261                         .num_parents = 1,
1262                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1263                         .ops = &clk_branch2_ops,
1264                 },
1265         },
1266 };
1267
1268 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1269         .mult = 1,
1270         .div = 4,
1271         .hw.init = &(struct clk_init_data){
1272                 .name = "gcc_xo_div4_clk_src",
1273                 .parent_names = (const char *[]){
1274                         "gcc_xo_clk_src"
1275                 },
1276                 .num_parents = 1,
1277                 .ops = &clk_fixed_factor_ops,
1278                 .flags = CLK_SET_RATE_PARENT,
1279         },
1280 };
1281
1282 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1283         F(19200000, P_XO, 1, 0, 0),
1284         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1285         F(100000000, P_GPLL0, 8, 0, 0),
1286         F(133333333, P_GPLL0, 6, 0, 0),
1287         F(160000000, P_GPLL0, 5, 0, 0),
1288         F(200000000, P_GPLL0, 4, 0, 0),
1289         F(266666667, P_GPLL0, 3, 0, 0),
1290         { }
1291 };
1292
1293 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1294         .cmd_rcgr = 0x26004,
1295         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1296         .hid_width = 5,
1297         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1298         .clkr.hw.init = &(struct clk_init_data){
1299                 .name = "system_noc_bfdcd_clk_src",
1300                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1301                 .num_parents = 4,
1302                 .ops = &clk_rcg2_ops,
1303                 .flags = CLK_IS_CRITICAL,
1304         },
1305 };
1306
1307 static struct clk_fixed_factor system_noc_clk_src = {
1308         .mult = 1,
1309         .div = 1,
1310         .hw.init = &(struct clk_init_data){
1311                 .name = "system_noc_clk_src",
1312                 .parent_names = (const char *[]){
1313                         "system_noc_bfdcd_clk_src"
1314                 },
1315                 .num_parents = 1,
1316                 .ops = &clk_fixed_factor_ops,
1317                 .flags = CLK_SET_RATE_PARENT,
1318         },
1319 };
1320
1321 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1322         F(19200000, P_XO, 1, 0, 0),
1323         F(200000000, P_GPLL0, 4, 0, 0),
1324         { }
1325 };
1326
1327 static struct clk_rcg2 nss_ce_clk_src = {
1328         .cmd_rcgr = 0x68098,
1329         .freq_tbl = ftbl_nss_ce_clk_src,
1330         .hid_width = 5,
1331         .parent_map = gcc_xo_gpll0_map,
1332         .clkr.hw.init = &(struct clk_init_data){
1333                 .name = "nss_ce_clk_src",
1334                 .parent_data = gcc_xo_gpll0,
1335                 .num_parents = 2,
1336                 .ops = &clk_rcg2_ops,
1337         },
1338 };
1339
1340 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1341         F(19200000, P_XO, 1, 0, 0),
1342         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1343         { }
1344 };
1345
1346 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1347         .cmd_rcgr = 0x68088,
1348         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1349         .hid_width = 5,
1350         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1351         .clkr.hw.init = &(struct clk_init_data){
1352                 .name = "nss_noc_bfdcd_clk_src",
1353                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1354                 .num_parents = 4,
1355                 .ops = &clk_rcg2_ops,
1356         },
1357 };
1358
1359 static struct clk_fixed_factor nss_noc_clk_src = {
1360         .mult = 1,
1361         .div = 1,
1362         .hw.init = &(struct clk_init_data){
1363                 .name = "nss_noc_clk_src",
1364                 .parent_names = (const char *[]){
1365                         "nss_noc_bfdcd_clk_src"
1366                 },
1367                 .num_parents = 1,
1368                 .ops = &clk_fixed_factor_ops,
1369                 .flags = CLK_SET_RATE_PARENT,
1370         },
1371 };
1372
1373 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1374         F(19200000, P_XO, 1, 0, 0),
1375         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1376         { }
1377 };
1378
1379 static struct clk_rcg2 nss_crypto_clk_src = {
1380         .cmd_rcgr = 0x68144,
1381         .freq_tbl = ftbl_nss_crypto_clk_src,
1382         .mnd_width = 16,
1383         .hid_width = 5,
1384         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1385         .clkr.hw.init = &(struct clk_init_data){
1386                 .name = "nss_crypto_clk_src",
1387                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1388                 .num_parents = 3,
1389                 .ops = &clk_rcg2_ops,
1390         },
1391 };
1392
1393 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1394         F(19200000, P_XO, 1, 0, 0),
1395         F(187200000, P_UBI32_PLL, 8, 0, 0),
1396         F(748800000, P_UBI32_PLL, 2, 0, 0),
1397         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1398         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1399         { }
1400 };
1401
1402 static struct clk_rcg2 nss_ubi0_clk_src = {
1403         .cmd_rcgr = 0x68104,
1404         .freq_tbl = ftbl_nss_ubi_clk_src,
1405         .hid_width = 5,
1406         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1407         .clkr.hw.init = &(struct clk_init_data){
1408                 .name = "nss_ubi0_clk_src",
1409                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1410                 .num_parents = 6,
1411                 .ops = &clk_rcg2_ops,
1412                 .flags = CLK_SET_RATE_PARENT,
1413         },
1414 };
1415
1416 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1417         .reg = 0x68118,
1418         .shift = 0,
1419         .width = 4,
1420         .clkr = {
1421                 .hw.init = &(struct clk_init_data){
1422                         .name = "nss_ubi0_div_clk_src",
1423                         .parent_names = (const char *[]){
1424                                 "nss_ubi0_clk_src"
1425                         },
1426                         .num_parents = 1,
1427                         .ops = &clk_regmap_div_ro_ops,
1428                         .flags = CLK_SET_RATE_PARENT,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_rcg2 nss_ubi1_clk_src = {
1434         .cmd_rcgr = 0x68124,
1435         .freq_tbl = ftbl_nss_ubi_clk_src,
1436         .hid_width = 5,
1437         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1438         .clkr.hw.init = &(struct clk_init_data){
1439                 .name = "nss_ubi1_clk_src",
1440                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1441                 .num_parents = 6,
1442                 .ops = &clk_rcg2_ops,
1443                 .flags = CLK_SET_RATE_PARENT,
1444         },
1445 };
1446
1447 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1448         .reg = 0x68138,
1449         .shift = 0,
1450         .width = 4,
1451         .clkr = {
1452                 .hw.init = &(struct clk_init_data){
1453                         .name = "nss_ubi1_div_clk_src",
1454                         .parent_names = (const char *[]){
1455                                 "nss_ubi1_clk_src"
1456                         },
1457                         .num_parents = 1,
1458                         .ops = &clk_regmap_div_ro_ops,
1459                         .flags = CLK_SET_RATE_PARENT,
1460                 },
1461         },
1462 };
1463
1464 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1465         F(19200000, P_XO, 1, 0, 0),
1466         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1467         { }
1468 };
1469
1470 static struct clk_rcg2 ubi_mpt_clk_src = {
1471         .cmd_rcgr = 0x68090,
1472         .freq_tbl = ftbl_ubi_mpt_clk_src,
1473         .hid_width = 5,
1474         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1475         .clkr.hw.init = &(struct clk_init_data){
1476                 .name = "ubi_mpt_clk_src",
1477                 .parent_names = gcc_xo_gpll0_out_main_div2,
1478                 .num_parents = 2,
1479                 .ops = &clk_rcg2_ops,
1480         },
1481 };
1482
1483 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1484         F(19200000, P_XO, 1, 0, 0),
1485         F(400000000, P_GPLL0, 2, 0, 0),
1486         { }
1487 };
1488
1489 static struct clk_rcg2 nss_imem_clk_src = {
1490         .cmd_rcgr = 0x68158,
1491         .freq_tbl = ftbl_nss_imem_clk_src,
1492         .hid_width = 5,
1493         .parent_map = gcc_xo_gpll0_gpll4_map,
1494         .clkr.hw.init = &(struct clk_init_data){
1495                 .name = "nss_imem_clk_src",
1496                 .parent_names = gcc_xo_gpll0_gpll4,
1497                 .num_parents = 3,
1498                 .ops = &clk_rcg2_ops,
1499         },
1500 };
1501
1502 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1503         F(19200000, P_XO, 1, 0, 0),
1504         F(300000000, P_BIAS_PLL, 1, 0, 0),
1505         { }
1506 };
1507
1508 static struct clk_rcg2 nss_ppe_clk_src = {
1509         .cmd_rcgr = 0x68080,
1510         .freq_tbl = ftbl_nss_ppe_clk_src,
1511         .hid_width = 5,
1512         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1513         .clkr.hw.init = &(struct clk_init_data){
1514                 .name = "nss_ppe_clk_src",
1515                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1516                 .num_parents = 6,
1517                 .ops = &clk_rcg2_ops,
1518         },
1519 };
1520
1521 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1522         .mult = 1,
1523         .div = 4,
1524         .hw.init = &(struct clk_init_data){
1525                 .name = "nss_ppe_cdiv_clk_src",
1526                 .parent_names = (const char *[]){
1527                         "nss_ppe_clk_src"
1528                 },
1529                 .num_parents = 1,
1530                 .ops = &clk_fixed_factor_ops,
1531                 .flags = CLK_SET_RATE_PARENT,
1532         },
1533 };
1534
1535 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1536         F(19200000, P_XO, 1, 0, 0),
1537         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1538         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1539         { }
1540 };
1541
1542 static struct clk_rcg2 nss_port1_rx_clk_src = {
1543         .cmd_rcgr = 0x68020,
1544         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1545         .hid_width = 5,
1546         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1547         .clkr.hw.init = &(struct clk_init_data){
1548                 .name = "nss_port1_rx_clk_src",
1549                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1550                 .num_parents = 5,
1551                 .ops = &clk_rcg2_ops,
1552         },
1553 };
1554
1555 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1556         .reg = 0x68400,
1557         .shift = 0,
1558         .width = 4,
1559         .clkr = {
1560                 .hw.init = &(struct clk_init_data){
1561                         .name = "nss_port1_rx_div_clk_src",
1562                         .parent_names = (const char *[]){
1563                                 "nss_port1_rx_clk_src"
1564                         },
1565                         .num_parents = 1,
1566                         .ops = &clk_regmap_div_ops,
1567                         .flags = CLK_SET_RATE_PARENT,
1568                 },
1569         },
1570 };
1571
1572 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1573         F(19200000, P_XO, 1, 0, 0),
1574         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1575         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1576         { }
1577 };
1578
1579 static struct clk_rcg2 nss_port1_tx_clk_src = {
1580         .cmd_rcgr = 0x68028,
1581         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1582         .hid_width = 5,
1583         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1584         .clkr.hw.init = &(struct clk_init_data){
1585                 .name = "nss_port1_tx_clk_src",
1586                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1587                 .num_parents = 5,
1588                 .ops = &clk_rcg2_ops,
1589         },
1590 };
1591
1592 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1593         .reg = 0x68404,
1594         .shift = 0,
1595         .width = 4,
1596         .clkr = {
1597                 .hw.init = &(struct clk_init_data){
1598                         .name = "nss_port1_tx_div_clk_src",
1599                         .parent_names = (const char *[]){
1600                                 "nss_port1_tx_clk_src"
1601                         },
1602                         .num_parents = 1,
1603                         .ops = &clk_regmap_div_ops,
1604                         .flags = CLK_SET_RATE_PARENT,
1605                 },
1606         },
1607 };
1608
1609 static struct clk_rcg2 nss_port2_rx_clk_src = {
1610         .cmd_rcgr = 0x68030,
1611         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1612         .hid_width = 5,
1613         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1614         .clkr.hw.init = &(struct clk_init_data){
1615                 .name = "nss_port2_rx_clk_src",
1616                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1617                 .num_parents = 5,
1618                 .ops = &clk_rcg2_ops,
1619         },
1620 };
1621
1622 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1623         .reg = 0x68410,
1624         .shift = 0,
1625         .width = 4,
1626         .clkr = {
1627                 .hw.init = &(struct clk_init_data){
1628                         .name = "nss_port2_rx_div_clk_src",
1629                         .parent_names = (const char *[]){
1630                                 "nss_port2_rx_clk_src"
1631                         },
1632                         .num_parents = 1,
1633                         .ops = &clk_regmap_div_ops,
1634                         .flags = CLK_SET_RATE_PARENT,
1635                 },
1636         },
1637 };
1638
1639 static struct clk_rcg2 nss_port2_tx_clk_src = {
1640         .cmd_rcgr = 0x68038,
1641         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1642         .hid_width = 5,
1643         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1644         .clkr.hw.init = &(struct clk_init_data){
1645                 .name = "nss_port2_tx_clk_src",
1646                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1647                 .num_parents = 5,
1648                 .ops = &clk_rcg2_ops,
1649         },
1650 };
1651
1652 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1653         .reg = 0x68414,
1654         .shift = 0,
1655         .width = 4,
1656         .clkr = {
1657                 .hw.init = &(struct clk_init_data){
1658                         .name = "nss_port2_tx_div_clk_src",
1659                         .parent_names = (const char *[]){
1660                                 "nss_port2_tx_clk_src"
1661                         },
1662                         .num_parents = 1,
1663                         .ops = &clk_regmap_div_ops,
1664                         .flags = CLK_SET_RATE_PARENT,
1665                 },
1666         },
1667 };
1668
1669 static struct clk_rcg2 nss_port3_rx_clk_src = {
1670         .cmd_rcgr = 0x68040,
1671         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1672         .hid_width = 5,
1673         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1674         .clkr.hw.init = &(struct clk_init_data){
1675                 .name = "nss_port3_rx_clk_src",
1676                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1677                 .num_parents = 5,
1678                 .ops = &clk_rcg2_ops,
1679         },
1680 };
1681
1682 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1683         .reg = 0x68420,
1684         .shift = 0,
1685         .width = 4,
1686         .clkr = {
1687                 .hw.init = &(struct clk_init_data){
1688                         .name = "nss_port3_rx_div_clk_src",
1689                         .parent_names = (const char *[]){
1690                                 "nss_port3_rx_clk_src"
1691                         },
1692                         .num_parents = 1,
1693                         .ops = &clk_regmap_div_ops,
1694                         .flags = CLK_SET_RATE_PARENT,
1695                 },
1696         },
1697 };
1698
1699 static struct clk_rcg2 nss_port3_tx_clk_src = {
1700         .cmd_rcgr = 0x68048,
1701         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1702         .hid_width = 5,
1703         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1704         .clkr.hw.init = &(struct clk_init_data){
1705                 .name = "nss_port3_tx_clk_src",
1706                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1707                 .num_parents = 5,
1708                 .ops = &clk_rcg2_ops,
1709         },
1710 };
1711
1712 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1713         .reg = 0x68424,
1714         .shift = 0,
1715         .width = 4,
1716         .clkr = {
1717                 .hw.init = &(struct clk_init_data){
1718                         .name = "nss_port3_tx_div_clk_src",
1719                         .parent_names = (const char *[]){
1720                                 "nss_port3_tx_clk_src"
1721                         },
1722                         .num_parents = 1,
1723                         .ops = &clk_regmap_div_ops,
1724                         .flags = CLK_SET_RATE_PARENT,
1725                 },
1726         },
1727 };
1728
1729 static struct clk_rcg2 nss_port4_rx_clk_src = {
1730         .cmd_rcgr = 0x68050,
1731         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1732         .hid_width = 5,
1733         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1734         .clkr.hw.init = &(struct clk_init_data){
1735                 .name = "nss_port4_rx_clk_src",
1736                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1737                 .num_parents = 5,
1738                 .ops = &clk_rcg2_ops,
1739         },
1740 };
1741
1742 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1743         .reg = 0x68430,
1744         .shift = 0,
1745         .width = 4,
1746         .clkr = {
1747                 .hw.init = &(struct clk_init_data){
1748                         .name = "nss_port4_rx_div_clk_src",
1749                         .parent_names = (const char *[]){
1750                                 "nss_port4_rx_clk_src"
1751                         },
1752                         .num_parents = 1,
1753                         .ops = &clk_regmap_div_ops,
1754                         .flags = CLK_SET_RATE_PARENT,
1755                 },
1756         },
1757 };
1758
1759 static struct clk_rcg2 nss_port4_tx_clk_src = {
1760         .cmd_rcgr = 0x68058,
1761         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1762         .hid_width = 5,
1763         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1764         .clkr.hw.init = &(struct clk_init_data){
1765                 .name = "nss_port4_tx_clk_src",
1766                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1767                 .num_parents = 5,
1768                 .ops = &clk_rcg2_ops,
1769         },
1770 };
1771
1772 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1773         .reg = 0x68434,
1774         .shift = 0,
1775         .width = 4,
1776         .clkr = {
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "nss_port4_tx_div_clk_src",
1779                         .parent_names = (const char *[]){
1780                                 "nss_port4_tx_clk_src"
1781                         },
1782                         .num_parents = 1,
1783                         .ops = &clk_regmap_div_ops,
1784                         .flags = CLK_SET_RATE_PARENT,
1785                 },
1786         },
1787 };
1788
1789 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1790         F(19200000, P_XO, 1, 0, 0),
1791         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1792         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1793         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1794         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1795         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1796         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1797         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1798         { }
1799 };
1800
1801 static struct clk_rcg2 nss_port5_rx_clk_src = {
1802         .cmd_rcgr = 0x68060,
1803         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1804         .hid_width = 5,
1805         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1806         .clkr.hw.init = &(struct clk_init_data){
1807                 .name = "nss_port5_rx_clk_src",
1808                 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1809                 .num_parents = 7,
1810                 .ops = &clk_rcg2_ops,
1811         },
1812 };
1813
1814 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1815         .reg = 0x68440,
1816         .shift = 0,
1817         .width = 4,
1818         .clkr = {
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "nss_port5_rx_div_clk_src",
1821                         .parent_names = (const char *[]){
1822                                 "nss_port5_rx_clk_src"
1823                         },
1824                         .num_parents = 1,
1825                         .ops = &clk_regmap_div_ops,
1826                         .flags = CLK_SET_RATE_PARENT,
1827                 },
1828         },
1829 };
1830
1831 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1832         F(19200000, P_XO, 1, 0, 0),
1833         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1834         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1835         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1836         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1837         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1838         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1839         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1840         { }
1841 };
1842
1843 static struct clk_rcg2 nss_port5_tx_clk_src = {
1844         .cmd_rcgr = 0x68068,
1845         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1846         .hid_width = 5,
1847         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1848         .clkr.hw.init = &(struct clk_init_data){
1849                 .name = "nss_port5_tx_clk_src",
1850                 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1851                 .num_parents = 7,
1852                 .ops = &clk_rcg2_ops,
1853         },
1854 };
1855
1856 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1857         .reg = 0x68444,
1858         .shift = 0,
1859         .width = 4,
1860         .clkr = {
1861                 .hw.init = &(struct clk_init_data){
1862                         .name = "nss_port5_tx_div_clk_src",
1863                         .parent_names = (const char *[]){
1864                                 "nss_port5_tx_clk_src"
1865                         },
1866                         .num_parents = 1,
1867                         .ops = &clk_regmap_div_ops,
1868                         .flags = CLK_SET_RATE_PARENT,
1869                 },
1870         },
1871 };
1872
1873 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1874         F(19200000, P_XO, 1, 0, 0),
1875         F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1876         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1877         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1878         F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1879         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1880         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1881         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1882         { }
1883 };
1884
1885 static struct clk_rcg2 nss_port6_rx_clk_src = {
1886         .cmd_rcgr = 0x68070,
1887         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1888         .hid_width = 5,
1889         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1890         .clkr.hw.init = &(struct clk_init_data){
1891                 .name = "nss_port6_rx_clk_src",
1892                 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1893                 .num_parents = 5,
1894                 .ops = &clk_rcg2_ops,
1895         },
1896 };
1897
1898 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1899         .reg = 0x68450,
1900         .shift = 0,
1901         .width = 4,
1902         .clkr = {
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "nss_port6_rx_div_clk_src",
1905                         .parent_names = (const char *[]){
1906                                 "nss_port6_rx_clk_src"
1907                         },
1908                         .num_parents = 1,
1909                         .ops = &clk_regmap_div_ops,
1910                         .flags = CLK_SET_RATE_PARENT,
1911                 },
1912         },
1913 };
1914
1915 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1916         F(19200000, P_XO, 1, 0, 0),
1917         F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1918         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1920         F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1921         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1922         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1923         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1924         { }
1925 };
1926
1927 static struct clk_rcg2 nss_port6_tx_clk_src = {
1928         .cmd_rcgr = 0x68078,
1929         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1930         .hid_width = 5,
1931         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1932         .clkr.hw.init = &(struct clk_init_data){
1933                 .name = "nss_port6_tx_clk_src",
1934                 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1935                 .num_parents = 5,
1936                 .ops = &clk_rcg2_ops,
1937         },
1938 };
1939
1940 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1941         .reg = 0x68454,
1942         .shift = 0,
1943         .width = 4,
1944         .clkr = {
1945                 .hw.init = &(struct clk_init_data){
1946                         .name = "nss_port6_tx_div_clk_src",
1947                         .parent_names = (const char *[]){
1948                                 "nss_port6_tx_clk_src"
1949                         },
1950                         .num_parents = 1,
1951                         .ops = &clk_regmap_div_ops,
1952                         .flags = CLK_SET_RATE_PARENT,
1953                 },
1954         },
1955 };
1956
1957 static struct freq_tbl ftbl_crypto_clk_src[] = {
1958         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1959         F(80000000, P_GPLL0, 10, 0, 0),
1960         F(100000000, P_GPLL0, 8, 0, 0),
1961         F(160000000, P_GPLL0, 5, 0, 0),
1962         { }
1963 };
1964
1965 static struct clk_rcg2 crypto_clk_src = {
1966         .cmd_rcgr = 0x16004,
1967         .freq_tbl = ftbl_crypto_clk_src,
1968         .hid_width = 5,
1969         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1970         .clkr.hw.init = &(struct clk_init_data){
1971                 .name = "crypto_clk_src",
1972                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1973                 .num_parents = 3,
1974                 .ops = &clk_rcg2_ops,
1975         },
1976 };
1977
1978 static struct freq_tbl ftbl_gp_clk_src[] = {
1979         F(19200000, P_XO, 1, 0, 0),
1980         { }
1981 };
1982
1983 static struct clk_rcg2 gp1_clk_src = {
1984         .cmd_rcgr = 0x08004,
1985         .freq_tbl = ftbl_gp_clk_src,
1986         .mnd_width = 8,
1987         .hid_width = 5,
1988         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1989         .clkr.hw.init = &(struct clk_init_data){
1990                 .name = "gp1_clk_src",
1991                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1992                 .num_parents = 5,
1993                 .ops = &clk_rcg2_ops,
1994         },
1995 };
1996
1997 static struct clk_rcg2 gp2_clk_src = {
1998         .cmd_rcgr = 0x09004,
1999         .freq_tbl = ftbl_gp_clk_src,
2000         .mnd_width = 8,
2001         .hid_width = 5,
2002         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2003         .clkr.hw.init = &(struct clk_init_data){
2004                 .name = "gp2_clk_src",
2005                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2006                 .num_parents = 5,
2007                 .ops = &clk_rcg2_ops,
2008         },
2009 };
2010
2011 static struct clk_rcg2 gp3_clk_src = {
2012         .cmd_rcgr = 0x0a004,
2013         .freq_tbl = ftbl_gp_clk_src,
2014         .mnd_width = 8,
2015         .hid_width = 5,
2016         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2017         .clkr.hw.init = &(struct clk_init_data){
2018                 .name = "gp3_clk_src",
2019                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2020                 .num_parents = 5,
2021                 .ops = &clk_rcg2_ops,
2022         },
2023 };
2024
2025 static struct clk_branch gcc_blsp1_ahb_clk = {
2026         .halt_reg = 0x01008,
2027         .clkr = {
2028                 .enable_reg = 0x01008,
2029                 .enable_mask = BIT(0),
2030                 .hw.init = &(struct clk_init_data){
2031                         .name = "gcc_blsp1_ahb_clk",
2032                         .parent_names = (const char *[]){
2033                                 "pcnoc_clk_src"
2034                         },
2035                         .num_parents = 1,
2036                         .flags = CLK_SET_RATE_PARENT,
2037                         .ops = &clk_branch2_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2043         .halt_reg = 0x02008,
2044         .clkr = {
2045                 .enable_reg = 0x02008,
2046                 .enable_mask = BIT(0),
2047                 .hw.init = &(struct clk_init_data){
2048                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2049                         .parent_names = (const char *[]){
2050                                 "blsp1_qup1_i2c_apps_clk_src"
2051                         },
2052                         .num_parents = 1,
2053                         .flags = CLK_SET_RATE_PARENT,
2054                         .ops = &clk_branch2_ops,
2055                 },
2056         },
2057 };
2058
2059 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2060         .halt_reg = 0x02004,
2061         .clkr = {
2062                 .enable_reg = 0x02004,
2063                 .enable_mask = BIT(0),
2064                 .hw.init = &(struct clk_init_data){
2065                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2066                         .parent_names = (const char *[]){
2067                                 "blsp1_qup1_spi_apps_clk_src"
2068                         },
2069                         .num_parents = 1,
2070                         .flags = CLK_SET_RATE_PARENT,
2071                         .ops = &clk_branch2_ops,
2072                 },
2073         },
2074 };
2075
2076 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2077         .halt_reg = 0x03010,
2078         .clkr = {
2079                 .enable_reg = 0x03010,
2080                 .enable_mask = BIT(0),
2081                 .hw.init = &(struct clk_init_data){
2082                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2083                         .parent_names = (const char *[]){
2084                                 "blsp1_qup2_i2c_apps_clk_src"
2085                         },
2086                         .num_parents = 1,
2087                         .flags = CLK_SET_RATE_PARENT,
2088                         .ops = &clk_branch2_ops,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2094         .halt_reg = 0x0300c,
2095         .clkr = {
2096                 .enable_reg = 0x0300c,
2097                 .enable_mask = BIT(0),
2098                 .hw.init = &(struct clk_init_data){
2099                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2100                         .parent_names = (const char *[]){
2101                                 "blsp1_qup2_spi_apps_clk_src"
2102                         },
2103                         .num_parents = 1,
2104                         .flags = CLK_SET_RATE_PARENT,
2105                         .ops = &clk_branch2_ops,
2106                 },
2107         },
2108 };
2109
2110 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2111         .halt_reg = 0x04010,
2112         .clkr = {
2113                 .enable_reg = 0x04010,
2114                 .enable_mask = BIT(0),
2115                 .hw.init = &(struct clk_init_data){
2116                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2117                         .parent_names = (const char *[]){
2118                                 "blsp1_qup3_i2c_apps_clk_src"
2119                         },
2120                         .num_parents = 1,
2121                         .flags = CLK_SET_RATE_PARENT,
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2128         .halt_reg = 0x0400c,
2129         .clkr = {
2130                 .enable_reg = 0x0400c,
2131                 .enable_mask = BIT(0),
2132                 .hw.init = &(struct clk_init_data){
2133                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2134                         .parent_names = (const char *[]){
2135                                 "blsp1_qup3_spi_apps_clk_src"
2136                         },
2137                         .num_parents = 1,
2138                         .flags = CLK_SET_RATE_PARENT,
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2145         .halt_reg = 0x05010,
2146         .clkr = {
2147                 .enable_reg = 0x05010,
2148                 .enable_mask = BIT(0),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2151                         .parent_names = (const char *[]){
2152                                 "blsp1_qup4_i2c_apps_clk_src"
2153                         },
2154                         .num_parents = 1,
2155                         .flags = CLK_SET_RATE_PARENT,
2156                         .ops = &clk_branch2_ops,
2157                 },
2158         },
2159 };
2160
2161 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2162         .halt_reg = 0x0500c,
2163         .clkr = {
2164                 .enable_reg = 0x0500c,
2165                 .enable_mask = BIT(0),
2166                 .hw.init = &(struct clk_init_data){
2167                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2168                         .parent_names = (const char *[]){
2169                                 "blsp1_qup4_spi_apps_clk_src"
2170                         },
2171                         .num_parents = 1,
2172                         .flags = CLK_SET_RATE_PARENT,
2173                         .ops = &clk_branch2_ops,
2174                 },
2175         },
2176 };
2177
2178 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2179         .halt_reg = 0x06010,
2180         .clkr = {
2181                 .enable_reg = 0x06010,
2182                 .enable_mask = BIT(0),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2185                         .parent_names = (const char *[]){
2186                                 "blsp1_qup5_i2c_apps_clk_src"
2187                         },
2188                         .num_parents = 1,
2189                         .flags = CLK_SET_RATE_PARENT,
2190                         .ops = &clk_branch2_ops,
2191                 },
2192         },
2193 };
2194
2195 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2196         .halt_reg = 0x0600c,
2197         .clkr = {
2198                 .enable_reg = 0x0600c,
2199                 .enable_mask = BIT(0),
2200                 .hw.init = &(struct clk_init_data){
2201                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2202                         .parent_names = (const char *[]){
2203                                 "blsp1_qup5_spi_apps_clk_src"
2204                         },
2205                         .num_parents = 1,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                         .ops = &clk_branch2_ops,
2208                 },
2209         },
2210 };
2211
2212 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2213         .halt_reg = 0x07010,
2214         .clkr = {
2215                 .enable_reg = 0x07010,
2216                 .enable_mask = BIT(0),
2217                 .hw.init = &(struct clk_init_data){
2218                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2219                         .parent_names = (const char *[]){
2220                                 "blsp1_qup6_i2c_apps_clk_src"
2221                         },
2222                         .num_parents = 1,
2223                         .flags = CLK_SET_RATE_PARENT,
2224                         .ops = &clk_branch2_ops,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2230         .halt_reg = 0x0700c,
2231         .clkr = {
2232                 .enable_reg = 0x0700c,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2236                         .parent_names = (const char *[]){
2237                                 "blsp1_qup6_spi_apps_clk_src"
2238                         },
2239                         .num_parents = 1,
2240                         .flags = CLK_SET_RATE_PARENT,
2241                         .ops = &clk_branch2_ops,
2242                 },
2243         },
2244 };
2245
2246 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2247         .halt_reg = 0x0203c,
2248         .clkr = {
2249                 .enable_reg = 0x0203c,
2250                 .enable_mask = BIT(0),
2251                 .hw.init = &(struct clk_init_data){
2252                         .name = "gcc_blsp1_uart1_apps_clk",
2253                         .parent_names = (const char *[]){
2254                                 "blsp1_uart1_apps_clk_src"
2255                         },
2256                         .num_parents = 1,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2264         .halt_reg = 0x0302c,
2265         .clkr = {
2266                 .enable_reg = 0x0302c,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gcc_blsp1_uart2_apps_clk",
2270                         .parent_names = (const char *[]){
2271                                 "blsp1_uart2_apps_clk_src"
2272                         },
2273                         .num_parents = 1,
2274                         .flags = CLK_SET_RATE_PARENT,
2275                         .ops = &clk_branch2_ops,
2276                 },
2277         },
2278 };
2279
2280 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2281         .halt_reg = 0x0402c,
2282         .clkr = {
2283                 .enable_reg = 0x0402c,
2284                 .enable_mask = BIT(0),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "gcc_blsp1_uart3_apps_clk",
2287                         .parent_names = (const char *[]){
2288                                 "blsp1_uart3_apps_clk_src"
2289                         },
2290                         .num_parents = 1,
2291                         .flags = CLK_SET_RATE_PARENT,
2292                         .ops = &clk_branch2_ops,
2293                 },
2294         },
2295 };
2296
2297 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2298         .halt_reg = 0x0502c,
2299         .clkr = {
2300                 .enable_reg = 0x0502c,
2301                 .enable_mask = BIT(0),
2302                 .hw.init = &(struct clk_init_data){
2303                         .name = "gcc_blsp1_uart4_apps_clk",
2304                         .parent_names = (const char *[]){
2305                                 "blsp1_uart4_apps_clk_src"
2306                         },
2307                         .num_parents = 1,
2308                         .flags = CLK_SET_RATE_PARENT,
2309                         .ops = &clk_branch2_ops,
2310                 },
2311         },
2312 };
2313
2314 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2315         .halt_reg = 0x0602c,
2316         .clkr = {
2317                 .enable_reg = 0x0602c,
2318                 .enable_mask = BIT(0),
2319                 .hw.init = &(struct clk_init_data){
2320                         .name = "gcc_blsp1_uart5_apps_clk",
2321                         .parent_names = (const char *[]){
2322                                 "blsp1_uart5_apps_clk_src"
2323                         },
2324                         .num_parents = 1,
2325                         .flags = CLK_SET_RATE_PARENT,
2326                         .ops = &clk_branch2_ops,
2327                 },
2328         },
2329 };
2330
2331 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2332         .halt_reg = 0x0702c,
2333         .clkr = {
2334                 .enable_reg = 0x0702c,
2335                 .enable_mask = BIT(0),
2336                 .hw.init = &(struct clk_init_data){
2337                         .name = "gcc_blsp1_uart6_apps_clk",
2338                         .parent_names = (const char *[]){
2339                                 "blsp1_uart6_apps_clk_src"
2340                         },
2341                         .num_parents = 1,
2342                         .flags = CLK_SET_RATE_PARENT,
2343                         .ops = &clk_branch2_ops,
2344                 },
2345         },
2346 };
2347
2348 static struct clk_branch gcc_prng_ahb_clk = {
2349         .halt_reg = 0x13004,
2350         .halt_check = BRANCH_HALT_VOTED,
2351         .clkr = {
2352                 .enable_reg = 0x0b004,
2353                 .enable_mask = BIT(8),
2354                 .hw.init = &(struct clk_init_data){
2355                         .name = "gcc_prng_ahb_clk",
2356                         .parent_names = (const char *[]){
2357                                 "pcnoc_clk_src"
2358                         },
2359                         .num_parents = 1,
2360                         .flags = CLK_SET_RATE_PARENT,
2361                         .ops = &clk_branch2_ops,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch gcc_qpic_ahb_clk = {
2367         .halt_reg = 0x57024,
2368         .clkr = {
2369                 .enable_reg = 0x57024,
2370                 .enable_mask = BIT(0),
2371                 .hw.init = &(struct clk_init_data){
2372                         .name = "gcc_qpic_ahb_clk",
2373                         .parent_names = (const char *[]){
2374                                 "pcnoc_clk_src"
2375                         },
2376                         .num_parents = 1,
2377                         .flags = CLK_SET_RATE_PARENT,
2378                         .ops = &clk_branch2_ops,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch gcc_qpic_clk = {
2384         .halt_reg = 0x57020,
2385         .clkr = {
2386                 .enable_reg = 0x57020,
2387                 .enable_mask = BIT(0),
2388                 .hw.init = &(struct clk_init_data){
2389                         .name = "gcc_qpic_clk",
2390                         .parent_names = (const char *[]){
2391                                 "pcnoc_clk_src"
2392                         },
2393                         .num_parents = 1,
2394                         .flags = CLK_SET_RATE_PARENT,
2395                         .ops = &clk_branch2_ops,
2396                 },
2397         },
2398 };
2399
2400 static struct clk_branch gcc_pcie0_ahb_clk = {
2401         .halt_reg = 0x75010,
2402         .clkr = {
2403                 .enable_reg = 0x75010,
2404                 .enable_mask = BIT(0),
2405                 .hw.init = &(struct clk_init_data){
2406                         .name = "gcc_pcie0_ahb_clk",
2407                         .parent_names = (const char *[]){
2408                                 "pcnoc_clk_src"
2409                         },
2410                         .num_parents = 1,
2411                         .flags = CLK_SET_RATE_PARENT,
2412                         .ops = &clk_branch2_ops,
2413                 },
2414         },
2415 };
2416
2417 static struct clk_branch gcc_pcie0_aux_clk = {
2418         .halt_reg = 0x75014,
2419         .clkr = {
2420                 .enable_reg = 0x75014,
2421                 .enable_mask = BIT(0),
2422                 .hw.init = &(struct clk_init_data){
2423                         .name = "gcc_pcie0_aux_clk",
2424                         .parent_names = (const char *[]){
2425                                 "pcie0_aux_clk_src"
2426                         },
2427                         .num_parents = 1,
2428                         .flags = CLK_SET_RATE_PARENT,
2429                         .ops = &clk_branch2_ops,
2430                 },
2431         },
2432 };
2433
2434 static struct clk_branch gcc_pcie0_axi_m_clk = {
2435         .halt_reg = 0x75008,
2436         .clkr = {
2437                 .enable_reg = 0x75008,
2438                 .enable_mask = BIT(0),
2439                 .hw.init = &(struct clk_init_data){
2440                         .name = "gcc_pcie0_axi_m_clk",
2441                         .parent_names = (const char *[]){
2442                                 "pcie0_axi_clk_src"
2443                         },
2444                         .num_parents = 1,
2445                         .flags = CLK_SET_RATE_PARENT,
2446                         .ops = &clk_branch2_ops,
2447                 },
2448         },
2449 };
2450
2451 static struct clk_branch gcc_pcie0_axi_s_clk = {
2452         .halt_reg = 0x7500c,
2453         .clkr = {
2454                 .enable_reg = 0x7500c,
2455                 .enable_mask = BIT(0),
2456                 .hw.init = &(struct clk_init_data){
2457                         .name = "gcc_pcie0_axi_s_clk",
2458                         .parent_names = (const char *[]){
2459                                 "pcie0_axi_clk_src"
2460                         },
2461                         .num_parents = 1,
2462                         .flags = CLK_SET_RATE_PARENT,
2463                         .ops = &clk_branch2_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch gcc_pcie0_pipe_clk = {
2469         .halt_reg = 0x75018,
2470         .halt_check = BRANCH_HALT_DELAY,
2471         .clkr = {
2472                 .enable_reg = 0x75018,
2473                 .enable_mask = BIT(0),
2474                 .hw.init = &(struct clk_init_data){
2475                         .name = "gcc_pcie0_pipe_clk",
2476                         .parent_names = (const char *[]){
2477                                 "pcie0_pipe_clk_src"
2478                         },
2479                         .num_parents = 1,
2480                         .flags = CLK_SET_RATE_PARENT,
2481                         .ops = &clk_branch2_ops,
2482                 },
2483         },
2484 };
2485
2486 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2487         .halt_reg = 0x26048,
2488         .clkr = {
2489                 .enable_reg = 0x26048,
2490                 .enable_mask = BIT(0),
2491                 .hw.init = &(struct clk_init_data){
2492                         .name = "gcc_sys_noc_pcie0_axi_clk",
2493                         .parent_names = (const char *[]){
2494                                 "pcie0_axi_clk_src"
2495                         },
2496                         .num_parents = 1,
2497                         .flags = CLK_SET_RATE_PARENT,
2498                         .ops = &clk_branch2_ops,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch gcc_pcie1_ahb_clk = {
2504         .halt_reg = 0x76010,
2505         .clkr = {
2506                 .enable_reg = 0x76010,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_pcie1_ahb_clk",
2510                         .parent_names = (const char *[]){
2511                                 "pcnoc_clk_src"
2512                         },
2513                         .num_parents = 1,
2514                         .flags = CLK_SET_RATE_PARENT,
2515                         .ops = &clk_branch2_ops,
2516                 },
2517         },
2518 };
2519
2520 static struct clk_branch gcc_pcie1_aux_clk = {
2521         .halt_reg = 0x76014,
2522         .clkr = {
2523                 .enable_reg = 0x76014,
2524                 .enable_mask = BIT(0),
2525                 .hw.init = &(struct clk_init_data){
2526                         .name = "gcc_pcie1_aux_clk",
2527                         .parent_names = (const char *[]){
2528                                 "pcie1_aux_clk_src"
2529                         },
2530                         .num_parents = 1,
2531                         .flags = CLK_SET_RATE_PARENT,
2532                         .ops = &clk_branch2_ops,
2533                 },
2534         },
2535 };
2536
2537 static struct clk_branch gcc_pcie1_axi_m_clk = {
2538         .halt_reg = 0x76008,
2539         .clkr = {
2540                 .enable_reg = 0x76008,
2541                 .enable_mask = BIT(0),
2542                 .hw.init = &(struct clk_init_data){
2543                         .name = "gcc_pcie1_axi_m_clk",
2544                         .parent_names = (const char *[]){
2545                                 "pcie1_axi_clk_src"
2546                         },
2547                         .num_parents = 1,
2548                         .flags = CLK_SET_RATE_PARENT,
2549                         .ops = &clk_branch2_ops,
2550                 },
2551         },
2552 };
2553
2554 static struct clk_branch gcc_pcie1_axi_s_clk = {
2555         .halt_reg = 0x7600c,
2556         .clkr = {
2557                 .enable_reg = 0x7600c,
2558                 .enable_mask = BIT(0),
2559                 .hw.init = &(struct clk_init_data){
2560                         .name = "gcc_pcie1_axi_s_clk",
2561                         .parent_names = (const char *[]){
2562                                 "pcie1_axi_clk_src"
2563                         },
2564                         .num_parents = 1,
2565                         .flags = CLK_SET_RATE_PARENT,
2566                         .ops = &clk_branch2_ops,
2567                 },
2568         },
2569 };
2570
2571 static struct clk_branch gcc_pcie1_pipe_clk = {
2572         .halt_reg = 0x76018,
2573         .halt_check = BRANCH_HALT_DELAY,
2574         .clkr = {
2575                 .enable_reg = 0x76018,
2576                 .enable_mask = BIT(0),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "gcc_pcie1_pipe_clk",
2579                         .parent_names = (const char *[]){
2580                                 "pcie1_pipe_clk_src"
2581                         },
2582                         .num_parents = 1,
2583                         .flags = CLK_SET_RATE_PARENT,
2584                         .ops = &clk_branch2_ops,
2585                 },
2586         },
2587 };
2588
2589 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2590         .halt_reg = 0x2604c,
2591         .clkr = {
2592                 .enable_reg = 0x2604c,
2593                 .enable_mask = BIT(0),
2594                 .hw.init = &(struct clk_init_data){
2595                         .name = "gcc_sys_noc_pcie1_axi_clk",
2596                         .parent_names = (const char *[]){
2597                                 "pcie1_axi_clk_src"
2598                         },
2599                         .num_parents = 1,
2600                         .flags = CLK_SET_RATE_PARENT,
2601                         .ops = &clk_branch2_ops,
2602                 },
2603         },
2604 };
2605
2606 static struct clk_branch gcc_usb0_aux_clk = {
2607         .halt_reg = 0x3e044,
2608         .clkr = {
2609                 .enable_reg = 0x3e044,
2610                 .enable_mask = BIT(0),
2611                 .hw.init = &(struct clk_init_data){
2612                         .name = "gcc_usb0_aux_clk",
2613                         .parent_names = (const char *[]){
2614                                 "usb0_aux_clk_src"
2615                         },
2616                         .num_parents = 1,
2617                         .flags = CLK_SET_RATE_PARENT,
2618                         .ops = &clk_branch2_ops,
2619                 },
2620         },
2621 };
2622
2623 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2624         .halt_reg = 0x26040,
2625         .clkr = {
2626                 .enable_reg = 0x26040,
2627                 .enable_mask = BIT(0),
2628                 .hw.init = &(struct clk_init_data){
2629                         .name = "gcc_sys_noc_usb0_axi_clk",
2630                         .parent_names = (const char *[]){
2631                                 "usb0_master_clk_src"
2632                         },
2633                         .num_parents = 1,
2634                         .flags = CLK_SET_RATE_PARENT,
2635                         .ops = &clk_branch2_ops,
2636                 },
2637         },
2638 };
2639
2640 static struct clk_branch gcc_usb0_master_clk = {
2641         .halt_reg = 0x3e000,
2642         .clkr = {
2643                 .enable_reg = 0x3e000,
2644                 .enable_mask = BIT(0),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "gcc_usb0_master_clk",
2647                         .parent_names = (const char *[]){
2648                                 "usb0_master_clk_src"
2649                         },
2650                         .num_parents = 1,
2651                         .flags = CLK_SET_RATE_PARENT,
2652                         .ops = &clk_branch2_ops,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2658         .halt_reg = 0x3e008,
2659         .clkr = {
2660                 .enable_reg = 0x3e008,
2661                 .enable_mask = BIT(0),
2662                 .hw.init = &(struct clk_init_data){
2663                         .name = "gcc_usb0_mock_utmi_clk",
2664                         .parent_names = (const char *[]){
2665                                 "usb0_mock_utmi_clk_src"
2666                         },
2667                         .num_parents = 1,
2668                         .flags = CLK_SET_RATE_PARENT,
2669                         .ops = &clk_branch2_ops,
2670                 },
2671         },
2672 };
2673
2674 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2675         .halt_reg = 0x3e080,
2676         .clkr = {
2677                 .enable_reg = 0x3e080,
2678                 .enable_mask = BIT(0),
2679                 .hw.init = &(struct clk_init_data){
2680                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2681                         .parent_names = (const char *[]){
2682                                 "pcnoc_clk_src"
2683                         },
2684                         .num_parents = 1,
2685                         .flags = CLK_SET_RATE_PARENT,
2686                         .ops = &clk_branch2_ops,
2687                 },
2688         },
2689 };
2690
2691 static struct clk_branch gcc_usb0_pipe_clk = {
2692         .halt_reg = 0x3e040,
2693         .halt_check = BRANCH_HALT_DELAY,
2694         .clkr = {
2695                 .enable_reg = 0x3e040,
2696                 .enable_mask = BIT(0),
2697                 .hw.init = &(struct clk_init_data){
2698                         .name = "gcc_usb0_pipe_clk",
2699                         .parent_names = (const char *[]){
2700                                 "usb0_pipe_clk_src"
2701                         },
2702                         .num_parents = 1,
2703                         .flags = CLK_SET_RATE_PARENT,
2704                         .ops = &clk_branch2_ops,
2705                 },
2706         },
2707 };
2708
2709 static struct clk_branch gcc_usb0_sleep_clk = {
2710         .halt_reg = 0x3e004,
2711         .clkr = {
2712                 .enable_reg = 0x3e004,
2713                 .enable_mask = BIT(0),
2714                 .hw.init = &(struct clk_init_data){
2715                         .name = "gcc_usb0_sleep_clk",
2716                         .parent_names = (const char *[]){
2717                                 "gcc_sleep_clk_src"
2718                         },
2719                         .num_parents = 1,
2720                         .flags = CLK_SET_RATE_PARENT,
2721                         .ops = &clk_branch2_ops,
2722                 },
2723         },
2724 };
2725
2726 static struct clk_branch gcc_usb1_aux_clk = {
2727         .halt_reg = 0x3f044,
2728         .clkr = {
2729                 .enable_reg = 0x3f044,
2730                 .enable_mask = BIT(0),
2731                 .hw.init = &(struct clk_init_data){
2732                         .name = "gcc_usb1_aux_clk",
2733                         .parent_names = (const char *[]){
2734                                 "usb1_aux_clk_src"
2735                         },
2736                         .num_parents = 1,
2737                         .flags = CLK_SET_RATE_PARENT,
2738                         .ops = &clk_branch2_ops,
2739                 },
2740         },
2741 };
2742
2743 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2744         .halt_reg = 0x26044,
2745         .clkr = {
2746                 .enable_reg = 0x26044,
2747                 .enable_mask = BIT(0),
2748                 .hw.init = &(struct clk_init_data){
2749                         .name = "gcc_sys_noc_usb1_axi_clk",
2750                         .parent_names = (const char *[]){
2751                                 "usb1_master_clk_src"
2752                         },
2753                         .num_parents = 1,
2754                         .flags = CLK_SET_RATE_PARENT,
2755                         .ops = &clk_branch2_ops,
2756                 },
2757         },
2758 };
2759
2760 static struct clk_branch gcc_usb1_master_clk = {
2761         .halt_reg = 0x3f000,
2762         .clkr = {
2763                 .enable_reg = 0x3f000,
2764                 .enable_mask = BIT(0),
2765                 .hw.init = &(struct clk_init_data){
2766                         .name = "gcc_usb1_master_clk",
2767                         .parent_names = (const char *[]){
2768                                 "usb1_master_clk_src"
2769                         },
2770                         .num_parents = 1,
2771                         .flags = CLK_SET_RATE_PARENT,
2772                         .ops = &clk_branch2_ops,
2773                 },
2774         },
2775 };
2776
2777 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2778         .halt_reg = 0x3f008,
2779         .clkr = {
2780                 .enable_reg = 0x3f008,
2781                 .enable_mask = BIT(0),
2782                 .hw.init = &(struct clk_init_data){
2783                         .name = "gcc_usb1_mock_utmi_clk",
2784                         .parent_names = (const char *[]){
2785                                 "usb1_mock_utmi_clk_src"
2786                         },
2787                         .num_parents = 1,
2788                         .flags = CLK_SET_RATE_PARENT,
2789                         .ops = &clk_branch2_ops,
2790                 },
2791         },
2792 };
2793
2794 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2795         .halt_reg = 0x3f080,
2796         .clkr = {
2797                 .enable_reg = 0x3f080,
2798                 .enable_mask = BIT(0),
2799                 .hw.init = &(struct clk_init_data){
2800                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2801                         .parent_names = (const char *[]){
2802                                 "pcnoc_clk_src"
2803                         },
2804                         .num_parents = 1,
2805                         .flags = CLK_SET_RATE_PARENT,
2806                         .ops = &clk_branch2_ops,
2807                 },
2808         },
2809 };
2810
2811 static struct clk_branch gcc_usb1_pipe_clk = {
2812         .halt_reg = 0x3f040,
2813         .halt_check = BRANCH_HALT_DELAY,
2814         .clkr = {
2815                 .enable_reg = 0x3f040,
2816                 .enable_mask = BIT(0),
2817                 .hw.init = &(struct clk_init_data){
2818                         .name = "gcc_usb1_pipe_clk",
2819                         .parent_names = (const char *[]){
2820                                 "usb1_pipe_clk_src"
2821                         },
2822                         .num_parents = 1,
2823                         .flags = CLK_SET_RATE_PARENT,
2824                         .ops = &clk_branch2_ops,
2825                 },
2826         },
2827 };
2828
2829 static struct clk_branch gcc_usb1_sleep_clk = {
2830         .halt_reg = 0x3f004,
2831         .clkr = {
2832                 .enable_reg = 0x3f004,
2833                 .enable_mask = BIT(0),
2834                 .hw.init = &(struct clk_init_data){
2835                         .name = "gcc_usb1_sleep_clk",
2836                         .parent_names = (const char *[]){
2837                                 "gcc_sleep_clk_src"
2838                         },
2839                         .num_parents = 1,
2840                         .flags = CLK_SET_RATE_PARENT,
2841                         .ops = &clk_branch2_ops,
2842                 },
2843         },
2844 };
2845
2846 static struct clk_branch gcc_sdcc1_ahb_clk = {
2847         .halt_reg = 0x4201c,
2848         .clkr = {
2849                 .enable_reg = 0x4201c,
2850                 .enable_mask = BIT(0),
2851                 .hw.init = &(struct clk_init_data){
2852                         .name = "gcc_sdcc1_ahb_clk",
2853                         .parent_names = (const char *[]){
2854                                 "pcnoc_clk_src"
2855                         },
2856                         .num_parents = 1,
2857                         .flags = CLK_SET_RATE_PARENT,
2858                         .ops = &clk_branch2_ops,
2859                 },
2860         },
2861 };
2862
2863 static struct clk_branch gcc_sdcc1_apps_clk = {
2864         .halt_reg = 0x42018,
2865         .clkr = {
2866                 .enable_reg = 0x42018,
2867                 .enable_mask = BIT(0),
2868                 .hw.init = &(struct clk_init_data){
2869                         .name = "gcc_sdcc1_apps_clk",
2870                         .parent_names = (const char *[]){
2871                                 "sdcc1_apps_clk_src"
2872                         },
2873                         .num_parents = 1,
2874                         .flags = CLK_SET_RATE_PARENT,
2875                         .ops = &clk_branch2_ops,
2876                 },
2877         },
2878 };
2879
2880 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2881         .halt_reg = 0x5d014,
2882         .clkr = {
2883                 .enable_reg = 0x5d014,
2884                 .enable_mask = BIT(0),
2885                 .hw.init = &(struct clk_init_data){
2886                         .name = "gcc_sdcc1_ice_core_clk",
2887                         .parent_names = (const char *[]){
2888                                 "sdcc1_ice_core_clk_src"
2889                         },
2890                         .num_parents = 1,
2891                         .flags = CLK_SET_RATE_PARENT,
2892                         .ops = &clk_branch2_ops,
2893                 },
2894         },
2895 };
2896
2897 static struct clk_branch gcc_sdcc2_ahb_clk = {
2898         .halt_reg = 0x4301c,
2899         .clkr = {
2900                 .enable_reg = 0x4301c,
2901                 .enable_mask = BIT(0),
2902                 .hw.init = &(struct clk_init_data){
2903                         .name = "gcc_sdcc2_ahb_clk",
2904                         .parent_names = (const char *[]){
2905                                 "pcnoc_clk_src"
2906                         },
2907                         .num_parents = 1,
2908                         .flags = CLK_SET_RATE_PARENT,
2909                         .ops = &clk_branch2_ops,
2910                 },
2911         },
2912 };
2913
2914 static struct clk_branch gcc_sdcc2_apps_clk = {
2915         .halt_reg = 0x43018,
2916         .clkr = {
2917                 .enable_reg = 0x43018,
2918                 .enable_mask = BIT(0),
2919                 .hw.init = &(struct clk_init_data){
2920                         .name = "gcc_sdcc2_apps_clk",
2921                         .parent_names = (const char *[]){
2922                                 "sdcc2_apps_clk_src"
2923                         },
2924                         .num_parents = 1,
2925                         .flags = CLK_SET_RATE_PARENT,
2926                         .ops = &clk_branch2_ops,
2927                 },
2928         },
2929 };
2930
2931 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2932         .halt_reg = 0x1d03c,
2933         .clkr = {
2934                 .enable_reg = 0x1d03c,
2935                 .enable_mask = BIT(0),
2936                 .hw.init = &(struct clk_init_data){
2937                         .name = "gcc_mem_noc_nss_axi_clk",
2938                         .parent_names = (const char *[]){
2939                                 "nss_noc_clk_src"
2940                         },
2941                         .num_parents = 1,
2942                         .flags = CLK_SET_RATE_PARENT,
2943                         .ops = &clk_branch2_ops,
2944                 },
2945         },
2946 };
2947
2948 static struct clk_branch gcc_nss_ce_apb_clk = {
2949         .halt_reg = 0x68174,
2950         .clkr = {
2951                 .enable_reg = 0x68174,
2952                 .enable_mask = BIT(0),
2953                 .hw.init = &(struct clk_init_data){
2954                         .name = "gcc_nss_ce_apb_clk",
2955                         .parent_names = (const char *[]){
2956                                 "nss_ce_clk_src"
2957                         },
2958                         .num_parents = 1,
2959                         .flags = CLK_SET_RATE_PARENT,
2960                         .ops = &clk_branch2_ops,
2961                 },
2962         },
2963 };
2964
2965 static struct clk_branch gcc_nss_ce_axi_clk = {
2966         .halt_reg = 0x68170,
2967         .clkr = {
2968                 .enable_reg = 0x68170,
2969                 .enable_mask = BIT(0),
2970                 .hw.init = &(struct clk_init_data){
2971                         .name = "gcc_nss_ce_axi_clk",
2972                         .parent_names = (const char *[]){
2973                                 "nss_ce_clk_src"
2974                         },
2975                         .num_parents = 1,
2976                         .flags = CLK_SET_RATE_PARENT,
2977                         .ops = &clk_branch2_ops,
2978                 },
2979         },
2980 };
2981
2982 static struct clk_branch gcc_nss_cfg_clk = {
2983         .halt_reg = 0x68160,
2984         .clkr = {
2985                 .enable_reg = 0x68160,
2986                 .enable_mask = BIT(0),
2987                 .hw.init = &(struct clk_init_data){
2988                         .name = "gcc_nss_cfg_clk",
2989                         .parent_names = (const char *[]){
2990                                 "pcnoc_clk_src"
2991                         },
2992                         .num_parents = 1,
2993                         .flags = CLK_SET_RATE_PARENT,
2994                         .ops = &clk_branch2_ops,
2995                 },
2996         },
2997 };
2998
2999 static struct clk_branch gcc_nss_crypto_clk = {
3000         .halt_reg = 0x68164,
3001         .clkr = {
3002                 .enable_reg = 0x68164,
3003                 .enable_mask = BIT(0),
3004                 .hw.init = &(struct clk_init_data){
3005                         .name = "gcc_nss_crypto_clk",
3006                         .parent_names = (const char *[]){
3007                                 "nss_crypto_clk_src"
3008                         },
3009                         .num_parents = 1,
3010                         .flags = CLK_SET_RATE_PARENT,
3011                         .ops = &clk_branch2_ops,
3012                 },
3013         },
3014 };
3015
3016 static struct clk_branch gcc_nss_csr_clk = {
3017         .halt_reg = 0x68318,
3018         .clkr = {
3019                 .enable_reg = 0x68318,
3020                 .enable_mask = BIT(0),
3021                 .hw.init = &(struct clk_init_data){
3022                         .name = "gcc_nss_csr_clk",
3023                         .parent_names = (const char *[]){
3024                                 "nss_ce_clk_src"
3025                         },
3026                         .num_parents = 1,
3027                         .flags = CLK_SET_RATE_PARENT,
3028                         .ops = &clk_branch2_ops,
3029                 },
3030         },
3031 };
3032
3033 static struct clk_branch gcc_nss_edma_cfg_clk = {
3034         .halt_reg = 0x6819c,
3035         .clkr = {
3036                 .enable_reg = 0x6819c,
3037                 .enable_mask = BIT(0),
3038                 .hw.init = &(struct clk_init_data){
3039                         .name = "gcc_nss_edma_cfg_clk",
3040                         .parent_names = (const char *[]){
3041                                 "nss_ppe_clk_src"
3042                         },
3043                         .num_parents = 1,
3044                         .flags = CLK_SET_RATE_PARENT,
3045                         .ops = &clk_branch2_ops,
3046                 },
3047         },
3048 };
3049
3050 static struct clk_branch gcc_nss_edma_clk = {
3051         .halt_reg = 0x68198,
3052         .clkr = {
3053                 .enable_reg = 0x68198,
3054                 .enable_mask = BIT(0),
3055                 .hw.init = &(struct clk_init_data){
3056                         .name = "gcc_nss_edma_clk",
3057                         .parent_names = (const char *[]){
3058                                 "nss_ppe_clk_src"
3059                         },
3060                         .num_parents = 1,
3061                         .flags = CLK_SET_RATE_PARENT,
3062                         .ops = &clk_branch2_ops,
3063                 },
3064         },
3065 };
3066
3067 static struct clk_branch gcc_nss_imem_clk = {
3068         .halt_reg = 0x68178,
3069         .clkr = {
3070                 .enable_reg = 0x68178,
3071                 .enable_mask = BIT(0),
3072                 .hw.init = &(struct clk_init_data){
3073                         .name = "gcc_nss_imem_clk",
3074                         .parent_names = (const char *[]){
3075                                 "nss_imem_clk_src"
3076                         },
3077                         .num_parents = 1,
3078                         .flags = CLK_SET_RATE_PARENT,
3079                         .ops = &clk_branch2_ops,
3080                 },
3081         },
3082 };
3083
3084 static struct clk_branch gcc_nss_noc_clk = {
3085         .halt_reg = 0x68168,
3086         .clkr = {
3087                 .enable_reg = 0x68168,
3088                 .enable_mask = BIT(0),
3089                 .hw.init = &(struct clk_init_data){
3090                         .name = "gcc_nss_noc_clk",
3091                         .parent_names = (const char *[]){
3092                                 "nss_noc_clk_src"
3093                         },
3094                         .num_parents = 1,
3095                         .flags = CLK_SET_RATE_PARENT,
3096                         .ops = &clk_branch2_ops,
3097                 },
3098         },
3099 };
3100
3101 static struct clk_branch gcc_nss_ppe_btq_clk = {
3102         .halt_reg = 0x6833c,
3103         .clkr = {
3104                 .enable_reg = 0x6833c,
3105                 .enable_mask = BIT(0),
3106                 .hw.init = &(struct clk_init_data){
3107                         .name = "gcc_nss_ppe_btq_clk",
3108                         .parent_names = (const char *[]){
3109                                 "nss_ppe_clk_src"
3110                         },
3111                         .num_parents = 1,
3112                         .flags = CLK_SET_RATE_PARENT,
3113                         .ops = &clk_branch2_ops,
3114                 },
3115         },
3116 };
3117
3118 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3119         .halt_reg = 0x68194,
3120         .clkr = {
3121                 .enable_reg = 0x68194,
3122                 .enable_mask = BIT(0),
3123                 .hw.init = &(struct clk_init_data){
3124                         .name = "gcc_nss_ppe_cfg_clk",
3125                         .parent_names = (const char *[]){
3126                                 "nss_ppe_clk_src"
3127                         },
3128                         .num_parents = 1,
3129                         .flags = CLK_SET_RATE_PARENT,
3130                         .ops = &clk_branch2_ops,
3131                 },
3132         },
3133 };
3134
3135 static struct clk_branch gcc_nss_ppe_clk = {
3136         .halt_reg = 0x68190,
3137         .clkr = {
3138                 .enable_reg = 0x68190,
3139                 .enable_mask = BIT(0),
3140                 .hw.init = &(struct clk_init_data){
3141                         .name = "gcc_nss_ppe_clk",
3142                         .parent_names = (const char *[]){
3143                                 "nss_ppe_clk_src"
3144                         },
3145                         .num_parents = 1,
3146                         .flags = CLK_SET_RATE_PARENT,
3147                         .ops = &clk_branch2_ops,
3148                 },
3149         },
3150 };
3151
3152 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3153         .halt_reg = 0x68338,
3154         .clkr = {
3155                 .enable_reg = 0x68338,
3156                 .enable_mask = BIT(0),
3157                 .hw.init = &(struct clk_init_data){
3158                         .name = "gcc_nss_ppe_ipe_clk",
3159                         .parent_names = (const char *[]){
3160                                 "nss_ppe_clk_src"
3161                         },
3162                         .num_parents = 1,
3163                         .flags = CLK_SET_RATE_PARENT,
3164                         .ops = &clk_branch2_ops,
3165                 },
3166         },
3167 };
3168
3169 static struct clk_branch gcc_nss_ptp_ref_clk = {
3170         .halt_reg = 0x6816c,
3171         .clkr = {
3172                 .enable_reg = 0x6816c,
3173                 .enable_mask = BIT(0),
3174                 .hw.init = &(struct clk_init_data){
3175                         .name = "gcc_nss_ptp_ref_clk",
3176                         .parent_names = (const char *[]){
3177                                 "nss_ppe_cdiv_clk_src"
3178                         },
3179                         .num_parents = 1,
3180                         .flags = CLK_SET_RATE_PARENT,
3181                         .ops = &clk_branch2_ops,
3182                 },
3183         },
3184 };
3185
3186 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3187         .halt_reg = 0x6830c,
3188         .clkr = {
3189                 .enable_reg = 0x6830c,
3190                 .enable_mask = BIT(0),
3191                 .hw.init = &(struct clk_init_data){
3192                         .name = "gcc_nssnoc_ce_apb_clk",
3193                         .parent_names = (const char *[]){
3194                                 "nss_ce_clk_src"
3195                         },
3196                         .num_parents = 1,
3197                         .flags = CLK_SET_RATE_PARENT,
3198                         .ops = &clk_branch2_ops,
3199                 },
3200         },
3201 };
3202
3203 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3204         .halt_reg = 0x68308,
3205         .clkr = {
3206                 .enable_reg = 0x68308,
3207                 .enable_mask = BIT(0),
3208                 .hw.init = &(struct clk_init_data){
3209                         .name = "gcc_nssnoc_ce_axi_clk",
3210                         .parent_names = (const char *[]){
3211                                 "nss_ce_clk_src"
3212                         },
3213                         .num_parents = 1,
3214                         .flags = CLK_SET_RATE_PARENT,
3215                         .ops = &clk_branch2_ops,
3216                 },
3217         },
3218 };
3219
3220 static struct clk_branch gcc_nssnoc_crypto_clk = {
3221         .halt_reg = 0x68314,
3222         .clkr = {
3223                 .enable_reg = 0x68314,
3224                 .enable_mask = BIT(0),
3225                 .hw.init = &(struct clk_init_data){
3226                         .name = "gcc_nssnoc_crypto_clk",
3227                         .parent_names = (const char *[]){
3228                                 "nss_crypto_clk_src"
3229                         },
3230                         .num_parents = 1,
3231                         .flags = CLK_SET_RATE_PARENT,
3232                         .ops = &clk_branch2_ops,
3233                 },
3234         },
3235 };
3236
3237 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3238         .halt_reg = 0x68304,
3239         .clkr = {
3240                 .enable_reg = 0x68304,
3241                 .enable_mask = BIT(0),
3242                 .hw.init = &(struct clk_init_data){
3243                         .name = "gcc_nssnoc_ppe_cfg_clk",
3244                         .parent_names = (const char *[]){
3245                                 "nss_ppe_clk_src"
3246                         },
3247                         .num_parents = 1,
3248                         .flags = CLK_SET_RATE_PARENT,
3249                         .ops = &clk_branch2_ops,
3250                 },
3251         },
3252 };
3253
3254 static struct clk_branch gcc_nssnoc_ppe_clk = {
3255         .halt_reg = 0x68300,
3256         .clkr = {
3257                 .enable_reg = 0x68300,
3258                 .enable_mask = BIT(0),
3259                 .hw.init = &(struct clk_init_data){
3260                         .name = "gcc_nssnoc_ppe_clk",
3261                         .parent_names = (const char *[]){
3262                                 "nss_ppe_clk_src"
3263                         },
3264                         .num_parents = 1,
3265                         .flags = CLK_SET_RATE_PARENT,
3266                         .ops = &clk_branch2_ops,
3267                 },
3268         },
3269 };
3270
3271 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3272         .halt_reg = 0x68180,
3273         .clkr = {
3274                 .enable_reg = 0x68180,
3275                 .enable_mask = BIT(0),
3276                 .hw.init = &(struct clk_init_data){
3277                         .name = "gcc_nssnoc_qosgen_ref_clk",
3278                         .parent_names = (const char *[]){
3279                                 "gcc_xo_clk_src"
3280                         },
3281                         .num_parents = 1,
3282                         .flags = CLK_SET_RATE_PARENT,
3283                         .ops = &clk_branch2_ops,
3284                 },
3285         },
3286 };
3287
3288 static struct clk_branch gcc_nssnoc_snoc_clk = {
3289         .halt_reg = 0x68188,
3290         .clkr = {
3291                 .enable_reg = 0x68188,
3292                 .enable_mask = BIT(0),
3293                 .hw.init = &(struct clk_init_data){
3294                         .name = "gcc_nssnoc_snoc_clk",
3295                         .parent_names = (const char *[]){
3296                                 "system_noc_clk_src"
3297                         },
3298                         .num_parents = 1,
3299                         .flags = CLK_SET_RATE_PARENT,
3300                         .ops = &clk_branch2_ops,
3301                 },
3302         },
3303 };
3304
3305 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3306         .halt_reg = 0x68184,
3307         .clkr = {
3308                 .enable_reg = 0x68184,
3309                 .enable_mask = BIT(0),
3310                 .hw.init = &(struct clk_init_data){
3311                         .name = "gcc_nssnoc_timeout_ref_clk",
3312                         .parent_names = (const char *[]){
3313                                 "gcc_xo_div4_clk_src"
3314                         },
3315                         .num_parents = 1,
3316                         .flags = CLK_SET_RATE_PARENT,
3317                         .ops = &clk_branch2_ops,
3318                 },
3319         },
3320 };
3321
3322 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3323         .halt_reg = 0x68270,
3324         .clkr = {
3325                 .enable_reg = 0x68270,
3326                 .enable_mask = BIT(0),
3327                 .hw.init = &(struct clk_init_data){
3328                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3329                         .parent_names = (const char *[]){
3330                                 "nss_ce_clk_src"
3331                         },
3332                         .num_parents = 1,
3333                         .flags = CLK_SET_RATE_PARENT,
3334                         .ops = &clk_branch2_ops,
3335                 },
3336         },
3337 };
3338
3339 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3340         .halt_reg = 0x68274,
3341         .clkr = {
3342                 .enable_reg = 0x68274,
3343                 .enable_mask = BIT(0),
3344                 .hw.init = &(struct clk_init_data){
3345                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3346                         .parent_names = (const char *[]){
3347                                 "nss_ce_clk_src"
3348                         },
3349                         .num_parents = 1,
3350                         .flags = CLK_SET_RATE_PARENT,
3351                         .ops = &clk_branch2_ops,
3352                 },
3353         },
3354 };
3355
3356 static struct clk_branch gcc_ubi0_ahb_clk = {
3357         .halt_reg = 0x6820c,
3358         .halt_check = BRANCH_HALT_DELAY,
3359         .clkr = {
3360                 .enable_reg = 0x6820c,
3361                 .enable_mask = BIT(0),
3362                 .hw.init = &(struct clk_init_data){
3363                         .name = "gcc_ubi0_ahb_clk",
3364                         .parent_names = (const char *[]){
3365                                 "nss_ce_clk_src"
3366                         },
3367                         .num_parents = 1,
3368                         .flags = CLK_SET_RATE_PARENT,
3369                         .ops = &clk_branch2_ops,
3370                 },
3371         },
3372 };
3373
3374 static struct clk_branch gcc_ubi0_axi_clk = {
3375         .halt_reg = 0x68200,
3376         .halt_check = BRANCH_HALT_DELAY,
3377         .clkr = {
3378                 .enable_reg = 0x68200,
3379                 .enable_mask = BIT(0),
3380                 .hw.init = &(struct clk_init_data){
3381                         .name = "gcc_ubi0_axi_clk",
3382                         .parent_names = (const char *[]){
3383                                 "nss_noc_clk_src"
3384                         },
3385                         .num_parents = 1,
3386                         .flags = CLK_SET_RATE_PARENT,
3387                         .ops = &clk_branch2_ops,
3388                 },
3389         },
3390 };
3391
3392 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3393         .halt_reg = 0x68204,
3394         .halt_check = BRANCH_HALT_DELAY,
3395         .clkr = {
3396                 .enable_reg = 0x68204,
3397                 .enable_mask = BIT(0),
3398                 .hw.init = &(struct clk_init_data){
3399                         .name = "gcc_ubi0_nc_axi_clk",
3400                         .parent_names = (const char *[]){
3401                                 "nss_noc_clk_src"
3402                         },
3403                         .num_parents = 1,
3404                         .flags = CLK_SET_RATE_PARENT,
3405                         .ops = &clk_branch2_ops,
3406                 },
3407         },
3408 };
3409
3410 static struct clk_branch gcc_ubi0_core_clk = {
3411         .halt_reg = 0x68210,
3412         .halt_check = BRANCH_HALT_DELAY,
3413         .clkr = {
3414                 .enable_reg = 0x68210,
3415                 .enable_mask = BIT(0),
3416                 .hw.init = &(struct clk_init_data){
3417                         .name = "gcc_ubi0_core_clk",
3418                         .parent_names = (const char *[]){
3419                                 "nss_ubi0_div_clk_src"
3420                         },
3421                         .num_parents = 1,
3422                         .flags = CLK_SET_RATE_PARENT,
3423                         .ops = &clk_branch2_ops,
3424                 },
3425         },
3426 };
3427
3428 static struct clk_branch gcc_ubi0_mpt_clk = {
3429         .halt_reg = 0x68208,
3430         .halt_check = BRANCH_HALT_DELAY,
3431         .clkr = {
3432                 .enable_reg = 0x68208,
3433                 .enable_mask = BIT(0),
3434                 .hw.init = &(struct clk_init_data){
3435                         .name = "gcc_ubi0_mpt_clk",
3436                         .parent_names = (const char *[]){
3437                                 "ubi_mpt_clk_src"
3438                         },
3439                         .num_parents = 1,
3440                         .flags = CLK_SET_RATE_PARENT,
3441                         .ops = &clk_branch2_ops,
3442                 },
3443         },
3444 };
3445
3446 static struct clk_branch gcc_ubi1_ahb_clk = {
3447         .halt_reg = 0x6822c,
3448         .halt_check = BRANCH_HALT_DELAY,
3449         .clkr = {
3450                 .enable_reg = 0x6822c,
3451                 .enable_mask = BIT(0),
3452                 .hw.init = &(struct clk_init_data){
3453                         .name = "gcc_ubi1_ahb_clk",
3454                         .parent_names = (const char *[]){
3455                                 "nss_ce_clk_src"
3456                         },
3457                         .num_parents = 1,
3458                         .flags = CLK_SET_RATE_PARENT,
3459                         .ops = &clk_branch2_ops,
3460                 },
3461         },
3462 };
3463
3464 static struct clk_branch gcc_ubi1_axi_clk = {
3465         .halt_reg = 0x68220,
3466         .halt_check = BRANCH_HALT_DELAY,
3467         .clkr = {
3468                 .enable_reg = 0x68220,
3469                 .enable_mask = BIT(0),
3470                 .hw.init = &(struct clk_init_data){
3471                         .name = "gcc_ubi1_axi_clk",
3472                         .parent_names = (const char *[]){
3473                                 "nss_noc_clk_src"
3474                         },
3475                         .num_parents = 1,
3476                         .flags = CLK_SET_RATE_PARENT,
3477                         .ops = &clk_branch2_ops,
3478                 },
3479         },
3480 };
3481
3482 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3483         .halt_reg = 0x68224,
3484         .halt_check = BRANCH_HALT_DELAY,
3485         .clkr = {
3486                 .enable_reg = 0x68224,
3487                 .enable_mask = BIT(0),
3488                 .hw.init = &(struct clk_init_data){
3489                         .name = "gcc_ubi1_nc_axi_clk",
3490                         .parent_names = (const char *[]){
3491                                 "nss_noc_clk_src"
3492                         },
3493                         .num_parents = 1,
3494                         .flags = CLK_SET_RATE_PARENT,
3495                         .ops = &clk_branch2_ops,
3496                 },
3497         },
3498 };
3499
3500 static struct clk_branch gcc_ubi1_core_clk = {
3501         .halt_reg = 0x68230,
3502         .halt_check = BRANCH_HALT_DELAY,
3503         .clkr = {
3504                 .enable_reg = 0x68230,
3505                 .enable_mask = BIT(0),
3506                 .hw.init = &(struct clk_init_data){
3507                         .name = "gcc_ubi1_core_clk",
3508                         .parent_names = (const char *[]){
3509                                 "nss_ubi1_div_clk_src"
3510                         },
3511                         .num_parents = 1,
3512                         .flags = CLK_SET_RATE_PARENT,
3513                         .ops = &clk_branch2_ops,
3514                 },
3515         },
3516 };
3517
3518 static struct clk_branch gcc_ubi1_mpt_clk = {
3519         .halt_reg = 0x68228,
3520         .halt_check = BRANCH_HALT_DELAY,
3521         .clkr = {
3522                 .enable_reg = 0x68228,
3523                 .enable_mask = BIT(0),
3524                 .hw.init = &(struct clk_init_data){
3525                         .name = "gcc_ubi1_mpt_clk",
3526                         .parent_names = (const char *[]){
3527                                 "ubi_mpt_clk_src"
3528                         },
3529                         .num_parents = 1,
3530                         .flags = CLK_SET_RATE_PARENT,
3531                         .ops = &clk_branch2_ops,
3532                 },
3533         },
3534 };
3535
3536 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3537         .halt_reg = 0x56308,
3538         .clkr = {
3539                 .enable_reg = 0x56308,
3540                 .enable_mask = BIT(0),
3541                 .hw.init = &(struct clk_init_data){
3542                         .name = "gcc_cmn_12gpll_ahb_clk",
3543                         .parent_names = (const char *[]){
3544                                 "pcnoc_clk_src"
3545                         },
3546                         .num_parents = 1,
3547                         .flags = CLK_SET_RATE_PARENT,
3548                         .ops = &clk_branch2_ops,
3549                 },
3550         },
3551 };
3552
3553 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3554         .halt_reg = 0x5630c,
3555         .clkr = {
3556                 .enable_reg = 0x5630c,
3557                 .enable_mask = BIT(0),
3558                 .hw.init = &(struct clk_init_data){
3559                         .name = "gcc_cmn_12gpll_sys_clk",
3560                         .parent_names = (const char *[]){
3561                                 "gcc_xo_clk_src"
3562                         },
3563                         .num_parents = 1,
3564                         .flags = CLK_SET_RATE_PARENT,
3565                         .ops = &clk_branch2_ops,
3566                 },
3567         },
3568 };
3569
3570 static struct clk_branch gcc_mdio_ahb_clk = {
3571         .halt_reg = 0x58004,
3572         .clkr = {
3573                 .enable_reg = 0x58004,
3574                 .enable_mask = BIT(0),
3575                 .hw.init = &(struct clk_init_data){
3576                         .name = "gcc_mdio_ahb_clk",
3577                         .parent_names = (const char *[]){
3578                                 "pcnoc_clk_src"
3579                         },
3580                         .num_parents = 1,
3581                         .flags = CLK_SET_RATE_PARENT,
3582                         .ops = &clk_branch2_ops,
3583                 },
3584         },
3585 };
3586
3587 static struct clk_branch gcc_uniphy0_ahb_clk = {
3588         .halt_reg = 0x56008,
3589         .clkr = {
3590                 .enable_reg = 0x56008,
3591                 .enable_mask = BIT(0),
3592                 .hw.init = &(struct clk_init_data){
3593                         .name = "gcc_uniphy0_ahb_clk",
3594                         .parent_names = (const char *[]){
3595                                 "pcnoc_clk_src"
3596                         },
3597                         .num_parents = 1,
3598                         .flags = CLK_SET_RATE_PARENT,
3599                         .ops = &clk_branch2_ops,
3600                 },
3601         },
3602 };
3603
3604 static struct clk_branch gcc_uniphy0_sys_clk = {
3605         .halt_reg = 0x5600c,
3606         .clkr = {
3607                 .enable_reg = 0x5600c,
3608                 .enable_mask = BIT(0),
3609                 .hw.init = &(struct clk_init_data){
3610                         .name = "gcc_uniphy0_sys_clk",
3611                         .parent_names = (const char *[]){
3612                                 "gcc_xo_clk_src"
3613                         },
3614                         .num_parents = 1,
3615                         .flags = CLK_SET_RATE_PARENT,
3616                         .ops = &clk_branch2_ops,
3617                 },
3618         },
3619 };
3620
3621 static struct clk_branch gcc_uniphy1_ahb_clk = {
3622         .halt_reg = 0x56108,
3623         .clkr = {
3624                 .enable_reg = 0x56108,
3625                 .enable_mask = BIT(0),
3626                 .hw.init = &(struct clk_init_data){
3627                         .name = "gcc_uniphy1_ahb_clk",
3628                         .parent_names = (const char *[]){
3629                                 "pcnoc_clk_src"
3630                         },
3631                         .num_parents = 1,
3632                         .flags = CLK_SET_RATE_PARENT,
3633                         .ops = &clk_branch2_ops,
3634                 },
3635         },
3636 };
3637
3638 static struct clk_branch gcc_uniphy1_sys_clk = {
3639         .halt_reg = 0x5610c,
3640         .clkr = {
3641                 .enable_reg = 0x5610c,
3642                 .enable_mask = BIT(0),
3643                 .hw.init = &(struct clk_init_data){
3644                         .name = "gcc_uniphy1_sys_clk",
3645                         .parent_names = (const char *[]){
3646                                 "gcc_xo_clk_src"
3647                         },
3648                         .num_parents = 1,
3649                         .flags = CLK_SET_RATE_PARENT,
3650                         .ops = &clk_branch2_ops,
3651                 },
3652         },
3653 };
3654
3655 static struct clk_branch gcc_uniphy2_ahb_clk = {
3656         .halt_reg = 0x56208,
3657         .clkr = {
3658                 .enable_reg = 0x56208,
3659                 .enable_mask = BIT(0),
3660                 .hw.init = &(struct clk_init_data){
3661                         .name = "gcc_uniphy2_ahb_clk",
3662                         .parent_names = (const char *[]){
3663                                 "pcnoc_clk_src"
3664                         },
3665                         .num_parents = 1,
3666                         .flags = CLK_SET_RATE_PARENT,
3667                         .ops = &clk_branch2_ops,
3668                 },
3669         },
3670 };
3671
3672 static struct clk_branch gcc_uniphy2_sys_clk = {
3673         .halt_reg = 0x5620c,
3674         .clkr = {
3675                 .enable_reg = 0x5620c,
3676                 .enable_mask = BIT(0),
3677                 .hw.init = &(struct clk_init_data){
3678                         .name = "gcc_uniphy2_sys_clk",
3679                         .parent_names = (const char *[]){
3680                                 "gcc_xo_clk_src"
3681                         },
3682                         .num_parents = 1,
3683                         .flags = CLK_SET_RATE_PARENT,
3684                         .ops = &clk_branch2_ops,
3685                 },
3686         },
3687 };
3688
3689 static struct clk_branch gcc_nss_port1_rx_clk = {
3690         .halt_reg = 0x68240,
3691         .clkr = {
3692                 .enable_reg = 0x68240,
3693                 .enable_mask = BIT(0),
3694                 .hw.init = &(struct clk_init_data){
3695                         .name = "gcc_nss_port1_rx_clk",
3696                         .parent_names = (const char *[]){
3697                                 "nss_port1_rx_div_clk_src"
3698                         },
3699                         .num_parents = 1,
3700                         .flags = CLK_SET_RATE_PARENT,
3701                         .ops = &clk_branch2_ops,
3702                 },
3703         },
3704 };
3705
3706 static struct clk_branch gcc_nss_port1_tx_clk = {
3707         .halt_reg = 0x68244,
3708         .clkr = {
3709                 .enable_reg = 0x68244,
3710                 .enable_mask = BIT(0),
3711                 .hw.init = &(struct clk_init_data){
3712                         .name = "gcc_nss_port1_tx_clk",
3713                         .parent_names = (const char *[]){
3714                                 "nss_port1_tx_div_clk_src"
3715                         },
3716                         .num_parents = 1,
3717                         .flags = CLK_SET_RATE_PARENT,
3718                         .ops = &clk_branch2_ops,
3719                 },
3720         },
3721 };
3722
3723 static struct clk_branch gcc_nss_port2_rx_clk = {
3724         .halt_reg = 0x68248,
3725         .clkr = {
3726                 .enable_reg = 0x68248,
3727                 .enable_mask = BIT(0),
3728                 .hw.init = &(struct clk_init_data){
3729                         .name = "gcc_nss_port2_rx_clk",
3730                         .parent_names = (const char *[]){
3731                                 "nss_port2_rx_div_clk_src"
3732                         },
3733                         .num_parents = 1,
3734                         .flags = CLK_SET_RATE_PARENT,
3735                         .ops = &clk_branch2_ops,
3736                 },
3737         },
3738 };
3739
3740 static struct clk_branch gcc_nss_port2_tx_clk = {
3741         .halt_reg = 0x6824c,
3742         .clkr = {
3743                 .enable_reg = 0x6824c,
3744                 .enable_mask = BIT(0),
3745                 .hw.init = &(struct clk_init_data){
3746                         .name = "gcc_nss_port2_tx_clk",
3747                         .parent_names = (const char *[]){
3748                                 "nss_port2_tx_div_clk_src"
3749                         },
3750                         .num_parents = 1,
3751                         .flags = CLK_SET_RATE_PARENT,
3752                         .ops = &clk_branch2_ops,
3753                 },
3754         },
3755 };
3756
3757 static struct clk_branch gcc_nss_port3_rx_clk = {
3758         .halt_reg = 0x68250,
3759         .clkr = {
3760                 .enable_reg = 0x68250,
3761                 .enable_mask = BIT(0),
3762                 .hw.init = &(struct clk_init_data){
3763                         .name = "gcc_nss_port3_rx_clk",
3764                         .parent_names = (const char *[]){
3765                                 "nss_port3_rx_div_clk_src"
3766                         },
3767                         .num_parents = 1,
3768                         .flags = CLK_SET_RATE_PARENT,
3769                         .ops = &clk_branch2_ops,
3770                 },
3771         },
3772 };
3773
3774 static struct clk_branch gcc_nss_port3_tx_clk = {
3775         .halt_reg = 0x68254,
3776         .clkr = {
3777                 .enable_reg = 0x68254,
3778                 .enable_mask = BIT(0),
3779                 .hw.init = &(struct clk_init_data){
3780                         .name = "gcc_nss_port3_tx_clk",
3781                         .parent_names = (const char *[]){
3782                                 "nss_port3_tx_div_clk_src"
3783                         },
3784                         .num_parents = 1,
3785                         .flags = CLK_SET_RATE_PARENT,
3786                         .ops = &clk_branch2_ops,
3787                 },
3788         },
3789 };
3790
3791 static struct clk_branch gcc_nss_port4_rx_clk = {
3792         .halt_reg = 0x68258,
3793         .clkr = {
3794                 .enable_reg = 0x68258,
3795                 .enable_mask = BIT(0),
3796                 .hw.init = &(struct clk_init_data){
3797                         .name = "gcc_nss_port4_rx_clk",
3798                         .parent_names = (const char *[]){
3799                                 "nss_port4_rx_div_clk_src"
3800                         },
3801                         .num_parents = 1,
3802                         .flags = CLK_SET_RATE_PARENT,
3803                         .ops = &clk_branch2_ops,
3804                 },
3805         },
3806 };
3807
3808 static struct clk_branch gcc_nss_port4_tx_clk = {
3809         .halt_reg = 0x6825c,
3810         .clkr = {
3811                 .enable_reg = 0x6825c,
3812                 .enable_mask = BIT(0),
3813                 .hw.init = &(struct clk_init_data){
3814                         .name = "gcc_nss_port4_tx_clk",
3815                         .parent_names = (const char *[]){
3816                                 "nss_port4_tx_div_clk_src"
3817                         },
3818                         .num_parents = 1,
3819                         .flags = CLK_SET_RATE_PARENT,
3820                         .ops = &clk_branch2_ops,
3821                 },
3822         },
3823 };
3824
3825 static struct clk_branch gcc_nss_port5_rx_clk = {
3826         .halt_reg = 0x68260,
3827         .clkr = {
3828                 .enable_reg = 0x68260,
3829                 .enable_mask = BIT(0),
3830                 .hw.init = &(struct clk_init_data){
3831                         .name = "gcc_nss_port5_rx_clk",
3832                         .parent_names = (const char *[]){
3833                                 "nss_port5_rx_div_clk_src"
3834                         },
3835                         .num_parents = 1,
3836                         .flags = CLK_SET_RATE_PARENT,
3837                         .ops = &clk_branch2_ops,
3838                 },
3839         },
3840 };
3841
3842 static struct clk_branch gcc_nss_port5_tx_clk = {
3843         .halt_reg = 0x68264,
3844         .clkr = {
3845                 .enable_reg = 0x68264,
3846                 .enable_mask = BIT(0),
3847                 .hw.init = &(struct clk_init_data){
3848                         .name = "gcc_nss_port5_tx_clk",
3849                         .parent_names = (const char *[]){
3850                                 "nss_port5_tx_div_clk_src"
3851                         },
3852                         .num_parents = 1,
3853                         .flags = CLK_SET_RATE_PARENT,
3854                         .ops = &clk_branch2_ops,
3855                 },
3856         },
3857 };
3858
3859 static struct clk_branch gcc_nss_port6_rx_clk = {
3860         .halt_reg = 0x68268,
3861         .clkr = {
3862                 .enable_reg = 0x68268,
3863                 .enable_mask = BIT(0),
3864                 .hw.init = &(struct clk_init_data){
3865                         .name = "gcc_nss_port6_rx_clk",
3866                         .parent_names = (const char *[]){
3867                                 "nss_port6_rx_div_clk_src"
3868                         },
3869                         .num_parents = 1,
3870                         .flags = CLK_SET_RATE_PARENT,
3871                         .ops = &clk_branch2_ops,
3872                 },
3873         },
3874 };
3875
3876 static struct clk_branch gcc_nss_port6_tx_clk = {
3877         .halt_reg = 0x6826c,
3878         .clkr = {
3879                 .enable_reg = 0x6826c,
3880                 .enable_mask = BIT(0),
3881                 .hw.init = &(struct clk_init_data){
3882                         .name = "gcc_nss_port6_tx_clk",
3883                         .parent_names = (const char *[]){
3884                                 "nss_port6_tx_div_clk_src"
3885                         },
3886                         .num_parents = 1,
3887                         .flags = CLK_SET_RATE_PARENT,
3888                         .ops = &clk_branch2_ops,
3889                 },
3890         },
3891 };
3892
3893 static struct clk_branch gcc_port1_mac_clk = {
3894         .halt_reg = 0x68320,
3895         .clkr = {
3896                 .enable_reg = 0x68320,
3897                 .enable_mask = BIT(0),
3898                 .hw.init = &(struct clk_init_data){
3899                         .name = "gcc_port1_mac_clk",
3900                         .parent_names = (const char *[]){
3901                                 "nss_ppe_clk_src"
3902                         },
3903                         .num_parents = 1,
3904                         .flags = CLK_SET_RATE_PARENT,
3905                         .ops = &clk_branch2_ops,
3906                 },
3907         },
3908 };
3909
3910 static struct clk_branch gcc_port2_mac_clk = {
3911         .halt_reg = 0x68324,
3912         .clkr = {
3913                 .enable_reg = 0x68324,
3914                 .enable_mask = BIT(0),
3915                 .hw.init = &(struct clk_init_data){
3916                         .name = "gcc_port2_mac_clk",
3917                         .parent_names = (const char *[]){
3918                                 "nss_ppe_clk_src"
3919                         },
3920                         .num_parents = 1,
3921                         .flags = CLK_SET_RATE_PARENT,
3922                         .ops = &clk_branch2_ops,
3923                 },
3924         },
3925 };
3926
3927 static struct clk_branch gcc_port3_mac_clk = {
3928         .halt_reg = 0x68328,
3929         .clkr = {
3930                 .enable_reg = 0x68328,
3931                 .enable_mask = BIT(0),
3932                 .hw.init = &(struct clk_init_data){
3933                         .name = "gcc_port3_mac_clk",
3934                         .parent_names = (const char *[]){
3935                                 "nss_ppe_clk_src"
3936                         },
3937                         .num_parents = 1,
3938                         .flags = CLK_SET_RATE_PARENT,
3939                         .ops = &clk_branch2_ops,
3940                 },
3941         },
3942 };
3943
3944 static struct clk_branch gcc_port4_mac_clk = {
3945         .halt_reg = 0x6832c,
3946         .clkr = {
3947                 .enable_reg = 0x6832c,
3948                 .enable_mask = BIT(0),
3949                 .hw.init = &(struct clk_init_data){
3950                         .name = "gcc_port4_mac_clk",
3951                         .parent_names = (const char *[]){
3952                                 "nss_ppe_clk_src"
3953                         },
3954                         .num_parents = 1,
3955                         .flags = CLK_SET_RATE_PARENT,
3956                         .ops = &clk_branch2_ops,
3957                 },
3958         },
3959 };
3960
3961 static struct clk_branch gcc_port5_mac_clk = {
3962         .halt_reg = 0x68330,
3963         .clkr = {
3964                 .enable_reg = 0x68330,
3965                 .enable_mask = BIT(0),
3966                 .hw.init = &(struct clk_init_data){
3967                         .name = "gcc_port5_mac_clk",
3968                         .parent_names = (const char *[]){
3969                                 "nss_ppe_clk_src"
3970                         },
3971                         .num_parents = 1,
3972                         .flags = CLK_SET_RATE_PARENT,
3973                         .ops = &clk_branch2_ops,
3974                 },
3975         },
3976 };
3977
3978 static struct clk_branch gcc_port6_mac_clk = {
3979         .halt_reg = 0x68334,
3980         .clkr = {
3981                 .enable_reg = 0x68334,
3982                 .enable_mask = BIT(0),
3983                 .hw.init = &(struct clk_init_data){
3984                         .name = "gcc_port6_mac_clk",
3985                         .parent_names = (const char *[]){
3986                                 "nss_ppe_clk_src"
3987                         },
3988                         .num_parents = 1,
3989                         .flags = CLK_SET_RATE_PARENT,
3990                         .ops = &clk_branch2_ops,
3991                 },
3992         },
3993 };
3994
3995 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3996         .halt_reg = 0x56010,
3997         .clkr = {
3998                 .enable_reg = 0x56010,
3999                 .enable_mask = BIT(0),
4000                 .hw.init = &(struct clk_init_data){
4001                         .name = "gcc_uniphy0_port1_rx_clk",
4002                         .parent_names = (const char *[]){
4003                                 "nss_port1_rx_div_clk_src"
4004                         },
4005                         .num_parents = 1,
4006                         .flags = CLK_SET_RATE_PARENT,
4007                         .ops = &clk_branch2_ops,
4008                 },
4009         },
4010 };
4011
4012 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
4013         .halt_reg = 0x56014,
4014         .clkr = {
4015                 .enable_reg = 0x56014,
4016                 .enable_mask = BIT(0),
4017                 .hw.init = &(struct clk_init_data){
4018                         .name = "gcc_uniphy0_port1_tx_clk",
4019                         .parent_names = (const char *[]){
4020                                 "nss_port1_tx_div_clk_src"
4021                         },
4022                         .num_parents = 1,
4023                         .flags = CLK_SET_RATE_PARENT,
4024                         .ops = &clk_branch2_ops,
4025                 },
4026         },
4027 };
4028
4029 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4030         .halt_reg = 0x56018,
4031         .clkr = {
4032                 .enable_reg = 0x56018,
4033                 .enable_mask = BIT(0),
4034                 .hw.init = &(struct clk_init_data){
4035                         .name = "gcc_uniphy0_port2_rx_clk",
4036                         .parent_names = (const char *[]){
4037                                 "nss_port2_rx_div_clk_src"
4038                         },
4039                         .num_parents = 1,
4040                         .flags = CLK_SET_RATE_PARENT,
4041                         .ops = &clk_branch2_ops,
4042                 },
4043         },
4044 };
4045
4046 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4047         .halt_reg = 0x5601c,
4048         .clkr = {
4049                 .enable_reg = 0x5601c,
4050                 .enable_mask = BIT(0),
4051                 .hw.init = &(struct clk_init_data){
4052                         .name = "gcc_uniphy0_port2_tx_clk",
4053                         .parent_names = (const char *[]){
4054                                 "nss_port2_tx_div_clk_src"
4055                         },
4056                         .num_parents = 1,
4057                         .flags = CLK_SET_RATE_PARENT,
4058                         .ops = &clk_branch2_ops,
4059                 },
4060         },
4061 };
4062
4063 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4064         .halt_reg = 0x56020,
4065         .clkr = {
4066                 .enable_reg = 0x56020,
4067                 .enable_mask = BIT(0),
4068                 .hw.init = &(struct clk_init_data){
4069                         .name = "gcc_uniphy0_port3_rx_clk",
4070                         .parent_names = (const char *[]){
4071                                 "nss_port3_rx_div_clk_src"
4072                         },
4073                         .num_parents = 1,
4074                         .flags = CLK_SET_RATE_PARENT,
4075                         .ops = &clk_branch2_ops,
4076                 },
4077         },
4078 };
4079
4080 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4081         .halt_reg = 0x56024,
4082         .clkr = {
4083                 .enable_reg = 0x56024,
4084                 .enable_mask = BIT(0),
4085                 .hw.init = &(struct clk_init_data){
4086                         .name = "gcc_uniphy0_port3_tx_clk",
4087                         .parent_names = (const char *[]){
4088                                 "nss_port3_tx_div_clk_src"
4089                         },
4090                         .num_parents = 1,
4091                         .flags = CLK_SET_RATE_PARENT,
4092                         .ops = &clk_branch2_ops,
4093                 },
4094         },
4095 };
4096
4097 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4098         .halt_reg = 0x56028,
4099         .clkr = {
4100                 .enable_reg = 0x56028,
4101                 .enable_mask = BIT(0),
4102                 .hw.init = &(struct clk_init_data){
4103                         .name = "gcc_uniphy0_port4_rx_clk",
4104                         .parent_names = (const char *[]){
4105                                 "nss_port4_rx_div_clk_src"
4106                         },
4107                         .num_parents = 1,
4108                         .flags = CLK_SET_RATE_PARENT,
4109                         .ops = &clk_branch2_ops,
4110                 },
4111         },
4112 };
4113
4114 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4115         .halt_reg = 0x5602c,
4116         .clkr = {
4117                 .enable_reg = 0x5602c,
4118                 .enable_mask = BIT(0),
4119                 .hw.init = &(struct clk_init_data){
4120                         .name = "gcc_uniphy0_port4_tx_clk",
4121                         .parent_names = (const char *[]){
4122                                 "nss_port4_tx_div_clk_src"
4123                         },
4124                         .num_parents = 1,
4125                         .flags = CLK_SET_RATE_PARENT,
4126                         .ops = &clk_branch2_ops,
4127                 },
4128         },
4129 };
4130
4131 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4132         .halt_reg = 0x56030,
4133         .clkr = {
4134                 .enable_reg = 0x56030,
4135                 .enable_mask = BIT(0),
4136                 .hw.init = &(struct clk_init_data){
4137                         .name = "gcc_uniphy0_port5_rx_clk",
4138                         .parent_names = (const char *[]){
4139                                 "nss_port5_rx_div_clk_src"
4140                         },
4141                         .num_parents = 1,
4142                         .flags = CLK_SET_RATE_PARENT,
4143                         .ops = &clk_branch2_ops,
4144                 },
4145         },
4146 };
4147
4148 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4149         .halt_reg = 0x56034,
4150         .clkr = {
4151                 .enable_reg = 0x56034,
4152                 .enable_mask = BIT(0),
4153                 .hw.init = &(struct clk_init_data){
4154                         .name = "gcc_uniphy0_port5_tx_clk",
4155                         .parent_names = (const char *[]){
4156                                 "nss_port5_tx_div_clk_src"
4157                         },
4158                         .num_parents = 1,
4159                         .flags = CLK_SET_RATE_PARENT,
4160                         .ops = &clk_branch2_ops,
4161                 },
4162         },
4163 };
4164
4165 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4166         .halt_reg = 0x56110,
4167         .clkr = {
4168                 .enable_reg = 0x56110,
4169                 .enable_mask = BIT(0),
4170                 .hw.init = &(struct clk_init_data){
4171                         .name = "gcc_uniphy1_port5_rx_clk",
4172                         .parent_names = (const char *[]){
4173                                 "nss_port5_rx_div_clk_src"
4174                         },
4175                         .num_parents = 1,
4176                         .flags = CLK_SET_RATE_PARENT,
4177                         .ops = &clk_branch2_ops,
4178                 },
4179         },
4180 };
4181
4182 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4183         .halt_reg = 0x56114,
4184         .clkr = {
4185                 .enable_reg = 0x56114,
4186                 .enable_mask = BIT(0),
4187                 .hw.init = &(struct clk_init_data){
4188                         .name = "gcc_uniphy1_port5_tx_clk",
4189                         .parent_names = (const char *[]){
4190                                 "nss_port5_tx_div_clk_src"
4191                         },
4192                         .num_parents = 1,
4193                         .flags = CLK_SET_RATE_PARENT,
4194                         .ops = &clk_branch2_ops,
4195                 },
4196         },
4197 };
4198
4199 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4200         .halt_reg = 0x56210,
4201         .clkr = {
4202                 .enable_reg = 0x56210,
4203                 .enable_mask = BIT(0),
4204                 .hw.init = &(struct clk_init_data){
4205                         .name = "gcc_uniphy2_port6_rx_clk",
4206                         .parent_names = (const char *[]){
4207                                 "nss_port6_rx_div_clk_src"
4208                         },
4209                         .num_parents = 1,
4210                         .flags = CLK_SET_RATE_PARENT,
4211                         .ops = &clk_branch2_ops,
4212                 },
4213         },
4214 };
4215
4216 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4217         .halt_reg = 0x56214,
4218         .clkr = {
4219                 .enable_reg = 0x56214,
4220                 .enable_mask = BIT(0),
4221                 .hw.init = &(struct clk_init_data){
4222                         .name = "gcc_uniphy2_port6_tx_clk",
4223                         .parent_names = (const char *[]){
4224                                 "nss_port6_tx_div_clk_src"
4225                         },
4226                         .num_parents = 1,
4227                         .flags = CLK_SET_RATE_PARENT,
4228                         .ops = &clk_branch2_ops,
4229                 },
4230         },
4231 };
4232
4233 static struct clk_branch gcc_crypto_ahb_clk = {
4234         .halt_reg = 0x16024,
4235         .halt_check = BRANCH_HALT_VOTED,
4236         .clkr = {
4237                 .enable_reg = 0x0b004,
4238                 .enable_mask = BIT(0),
4239                 .hw.init = &(struct clk_init_data){
4240                         .name = "gcc_crypto_ahb_clk",
4241                         .parent_names = (const char *[]){
4242                                 "pcnoc_clk_src"
4243                         },
4244                         .num_parents = 1,
4245                         .flags = CLK_SET_RATE_PARENT,
4246                         .ops = &clk_branch2_ops,
4247                 },
4248         },
4249 };
4250
4251 static struct clk_branch gcc_crypto_axi_clk = {
4252         .halt_reg = 0x16020,
4253         .halt_check = BRANCH_HALT_VOTED,
4254         .clkr = {
4255                 .enable_reg = 0x0b004,
4256                 .enable_mask = BIT(1),
4257                 .hw.init = &(struct clk_init_data){
4258                         .name = "gcc_crypto_axi_clk",
4259                         .parent_names = (const char *[]){
4260                                 "pcnoc_clk_src"
4261                         },
4262                         .num_parents = 1,
4263                         .flags = CLK_SET_RATE_PARENT,
4264                         .ops = &clk_branch2_ops,
4265                 },
4266         },
4267 };
4268
4269 static struct clk_branch gcc_crypto_clk = {
4270         .halt_reg = 0x1601c,
4271         .halt_check = BRANCH_HALT_VOTED,
4272         .clkr = {
4273                 .enable_reg = 0x0b004,
4274                 .enable_mask = BIT(2),
4275                 .hw.init = &(struct clk_init_data){
4276                         .name = "gcc_crypto_clk",
4277                         .parent_names = (const char *[]){
4278                                 "crypto_clk_src"
4279                         },
4280                         .num_parents = 1,
4281                         .flags = CLK_SET_RATE_PARENT,
4282                         .ops = &clk_branch2_ops,
4283                 },
4284         },
4285 };
4286
4287 static struct clk_branch gcc_gp1_clk = {
4288         .halt_reg = 0x08000,
4289         .clkr = {
4290                 .enable_reg = 0x08000,
4291                 .enable_mask = BIT(0),
4292                 .hw.init = &(struct clk_init_data){
4293                         .name = "gcc_gp1_clk",
4294                         .parent_names = (const char *[]){
4295                                 "gp1_clk_src"
4296                         },
4297                         .num_parents = 1,
4298                         .flags = CLK_SET_RATE_PARENT,
4299                         .ops = &clk_branch2_ops,
4300                 },
4301         },
4302 };
4303
4304 static struct clk_branch gcc_gp2_clk = {
4305         .halt_reg = 0x09000,
4306         .clkr = {
4307                 .enable_reg = 0x09000,
4308                 .enable_mask = BIT(0),
4309                 .hw.init = &(struct clk_init_data){
4310                         .name = "gcc_gp2_clk",
4311                         .parent_names = (const char *[]){
4312                                 "gp2_clk_src"
4313                         },
4314                         .num_parents = 1,
4315                         .flags = CLK_SET_RATE_PARENT,
4316                         .ops = &clk_branch2_ops,
4317                 },
4318         },
4319 };
4320
4321 static struct clk_branch gcc_gp3_clk = {
4322         .halt_reg = 0x0a000,
4323         .clkr = {
4324                 .enable_reg = 0x0a000,
4325                 .enable_mask = BIT(0),
4326                 .hw.init = &(struct clk_init_data){
4327                         .name = "gcc_gp3_clk",
4328                         .parent_names = (const char *[]){
4329                                 "gp3_clk_src"
4330                         },
4331                         .num_parents = 1,
4332                         .flags = CLK_SET_RATE_PARENT,
4333                         .ops = &clk_branch2_ops,
4334                 },
4335         },
4336 };
4337
4338 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
4339         F(19200000, P_XO, 1, 0, 0),
4340         F(100000000, P_GPLL0, 8, 0, 0),
4341         { }
4342 };
4343
4344 static struct clk_rcg2 pcie0_rchng_clk_src = {
4345         .cmd_rcgr = 0x75070,
4346         .freq_tbl = ftbl_pcie_rchng_clk_src,
4347         .hid_width = 5,
4348         .parent_map = gcc_xo_gpll0_map,
4349         .clkr.hw.init = &(struct clk_init_data){
4350                 .name = "pcie0_rchng_clk_src",
4351                 .parent_data = gcc_xo_gpll0,
4352                 .num_parents = 2,
4353                 .ops = &clk_rcg2_ops,
4354         },
4355 };
4356
4357 static struct clk_branch gcc_pcie0_rchng_clk = {
4358         .halt_reg = 0x75070,
4359         .halt_bit = 31,
4360         .clkr = {
4361                 .enable_reg = 0x75070,
4362                 .enable_mask = BIT(1),
4363                 .hw.init = &(struct clk_init_data){
4364                         .name = "gcc_pcie0_rchng_clk",
4365                         .parent_hws = (const struct clk_hw *[]){
4366                                 &pcie0_rchng_clk_src.clkr.hw,
4367                         },
4368                         .num_parents = 1,
4369                         .flags = CLK_SET_RATE_PARENT,
4370                         .ops = &clk_branch2_ops,
4371                 },
4372         },
4373 };
4374
4375 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
4376         .halt_reg = 0x75048,
4377         .halt_bit = 31,
4378         .clkr = {
4379                 .enable_reg = 0x75048,
4380                 .enable_mask = BIT(0),
4381                 .hw.init = &(struct clk_init_data){
4382                         .name = "gcc_pcie0_axi_s_bridge_clk",
4383                         .parent_hws = (const struct clk_hw *[]){
4384                                 &pcie0_axi_clk_src.clkr.hw,
4385                         },
4386                         .num_parents = 1,
4387                         .flags = CLK_SET_RATE_PARENT,
4388                         .ops = &clk_branch2_ops,
4389                 },
4390         },
4391 };
4392
4393 static const struct alpha_pll_config ubi32_pll_config = {
4394         .l = 0x4e,
4395         .config_ctl_val = 0x200d4aa8,
4396         .config_ctl_hi_val = 0x3c2,
4397         .main_output_mask = BIT(0),
4398         .aux_output_mask = BIT(1),
4399         .pre_div_val = 0x0,
4400         .pre_div_mask = BIT(12),
4401         .post_div_val = 0x0,
4402         .post_div_mask = GENMASK(9, 8),
4403 };
4404
4405 static const struct alpha_pll_config nss_crypto_pll_config = {
4406         .l = 0x3e,
4407         .alpha = 0x0,
4408         .alpha_hi = 0x80,
4409         .config_ctl_val = 0x4001055b,
4410         .main_output_mask = BIT(0),
4411         .pre_div_val = 0x0,
4412         .pre_div_mask = GENMASK(14, 12),
4413         .post_div_val = 0x1 << 8,
4414         .post_div_mask = GENMASK(11, 8),
4415         .vco_mask = GENMASK(21, 20),
4416         .vco_val = 0x0,
4417         .alpha_en_mask = BIT(24),
4418 };
4419
4420 static struct clk_hw *gcc_ipq8074_hws[] = {
4421         &gpll0_out_main_div2.hw,
4422         &gpll6_out_main_div2.hw,
4423         &pcnoc_clk_src.hw,
4424         &system_noc_clk_src.hw,
4425         &gcc_xo_div4_clk_src.hw,
4426         &nss_noc_clk_src.hw,
4427         &nss_ppe_cdiv_clk_src.hw,
4428 };
4429
4430 static struct clk_regmap *gcc_ipq8074_clks[] = {
4431         [GPLL0_MAIN] = &gpll0_main.clkr,
4432         [GPLL0] = &gpll0.clkr,
4433         [GPLL2_MAIN] = &gpll2_main.clkr,
4434         [GPLL2] = &gpll2.clkr,
4435         [GPLL4_MAIN] = &gpll4_main.clkr,
4436         [GPLL4] = &gpll4.clkr,
4437         [GPLL6_MAIN] = &gpll6_main.clkr,
4438         [GPLL6] = &gpll6.clkr,
4439         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4440         [UBI32_PLL] = &ubi32_pll.clkr,
4441         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4442         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4443         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4444         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4445         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4446         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4447         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4448         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4449         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4450         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4451         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4452         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4453         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4454         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4455         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4456         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4457         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4458         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4459         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4460         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4461         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4462         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4463         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4464         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4465         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4466         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4467         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4468         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4469         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4470         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4471         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4472         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4473         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4474         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4475         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4476         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4477         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4478         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4479         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4480         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4481         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4482         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4483         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4484         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4485         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4486         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4487         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4488         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4489         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4490         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4491         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4492         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4493         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4494         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4495         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4496         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4497         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4498         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4499         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4500         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4501         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4502         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4503         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4504         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4505         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4506         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4507         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4508         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4509         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4510         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4511         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4512         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4513         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4514         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4515         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4516         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4517         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4518         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4519         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4520         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4521         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4522         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4523         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4524         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4525         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4526         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4527         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4528         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4529         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4530         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4531         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4532         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4533         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4534         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4535         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4536         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4537         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4538         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4539         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4540         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4541         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4542         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4543         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4544         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4545         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4546         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4547         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4548         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4549         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4550         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4551         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4552         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4553         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4554         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4555         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4556         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4557         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4558         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4559         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4560         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4561         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4562         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4563         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4564         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4565         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4566         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4567         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4568         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4569         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4570         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4571         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4572         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4573         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4574         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4575         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4576         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4577         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4578         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4579         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4580         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4581         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4582         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4583         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4584         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4585         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4586         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4587         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4588         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4589         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4590         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4591         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4592         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4593         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4594         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4595         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4596         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4597         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4598         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4599         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4600         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4601         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4602         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4603         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4604         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4605         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4606         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4607         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4608         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4609         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4610         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4611         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4612         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4613         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4614         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4615         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4616         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4617         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4618         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4619         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4620         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4621         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4622         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4623         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4624         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4625         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4626         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4627         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4628         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4629         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4630         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4631         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4632         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4633         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4634         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4635         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4636         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4637         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4638         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4639         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4640         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4641         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4642         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4643         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4644         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4645         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4646         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4647         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4648         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4649         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4650         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4651         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4652         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4653         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4654         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4655         [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4656         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4657         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4658 };
4659
4660 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4661         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4662         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4663         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4664         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4665         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4666         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4667         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4668         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4669         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4670         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4671         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4672         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4673         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4674         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4675         [GCC_SMMU_BCR] = { 0x12000, 0 },
4676         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4677         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4678         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4679         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4680         [GCC_PRNG_BCR] = { 0x13000, 0 },
4681         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4682         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4683         [GCC_WCSS_BCR] = { 0x18000, 0 },
4684         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4685         [GCC_NSS_BCR] = { 0x19000, 0 },
4686         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4687         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4688         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4689         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4690         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4691         [GCC_TCSR_BCR] = { 0x28000, 0 },
4692         [GCC_QDSS_BCR] = { 0x29000, 0 },
4693         [GCC_DCD_BCR] = { 0x2a000, 0 },
4694         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4695         [GCC_MPM_BCR] = { 0x2c000, 0 },
4696         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4697         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4698         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4699         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4700         [GCC_TLMM_BCR] = { 0x34000, 0 },
4701         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4702         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4703         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4704         [GCC_USB0_BCR] = { 0x3e070, 0 },
4705         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4706         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4707         [GCC_USB1_BCR] = { 0x3f070, 0 },
4708         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4709         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4710         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4711         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4712         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4713         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4714         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4715         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4716         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4717         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4718         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4719         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4720         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4721         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4722         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4723         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4724         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4725         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4726         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4727         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4728         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4729         [GCC_QPIC_BCR] = { 0x57018, 0 },
4730         [GCC_MDIO_BCR] = { 0x58000, 0 },
4731         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4732         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4733         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4734         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4735         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4736         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4737         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4738         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4739         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4740         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4741         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4742         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4743         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4744         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4745         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4746         [GCC_DCC_BCR] = { 0x77000, 0 },
4747         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4748         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4749         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4750         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4751         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4752         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4753         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4754         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4755         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4756         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4757         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4758         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4759         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4760         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4761         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4762         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4763         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4764         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4765         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4766         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4767         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4768         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4769         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4770         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4771         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4772         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4773         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4774         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4775         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4776         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4777         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4778         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4779         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4780         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4781         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4782         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4783         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4784         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4785         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4786         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4787         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4788         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4789         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4790         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4791         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4792         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4793 };
4794
4795 static const struct of_device_id gcc_ipq8074_match_table[] = {
4796         { .compatible = "qcom,gcc-ipq8074" },
4797         { }
4798 };
4799 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4800
4801 static const struct regmap_config gcc_ipq8074_regmap_config = {
4802         .reg_bits       = 32,
4803         .reg_stride     = 4,
4804         .val_bits       = 32,
4805         .max_register   = 0x7fffc,
4806         .fast_io        = true,
4807 };
4808
4809 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4810         .config = &gcc_ipq8074_regmap_config,
4811         .clks = gcc_ipq8074_clks,
4812         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4813         .resets = gcc_ipq8074_resets,
4814         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4815         .clk_hws = gcc_ipq8074_hws,
4816         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4817 };
4818
4819 static int gcc_ipq8074_probe(struct platform_device *pdev)
4820 {
4821         struct regmap *regmap;
4822
4823         regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4824         if (IS_ERR(regmap))
4825                 return PTR_ERR(regmap);
4826
4827         /* SW Workaround for UBI32 Huayra PLL */
4828         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4829
4830         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4831         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4832                                 &nss_crypto_pll_config);
4833
4834         return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4835 }
4836
4837 static struct platform_driver gcc_ipq8074_driver = {
4838         .probe = gcc_ipq8074_probe,
4839         .driver = {
4840                 .name   = "qcom,gcc-ipq8074",
4841                 .of_match_table = gcc_ipq8074_match_table,
4842         },
4843 };
4844
4845 static int __init gcc_ipq8074_init(void)
4846 {
4847         return platform_driver_register(&gcc_ipq8074_driver);
4848 }
4849 core_initcall(gcc_ipq8074_init);
4850
4851 static void __exit gcc_ipq8074_exit(void)
4852 {
4853         platform_driver_unregister(&gcc_ipq8074_driver);
4854 }
4855 module_exit(gcc_ipq8074_exit);
4856
4857 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4858 MODULE_LICENSE("GPL v2");
4859 MODULE_ALIAS("platform:gcc-ipq8074");