drivers/clk/qcom/gcc-ipq8074.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  15
  16 #include "common.h"
  17 #include "clk-regmap.h"
  18 #include "clk-pll.h"
  19 #include "clk-rcg.h"
  20 #include "clk-branch.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-regmap-divider.h"
  23 #include "clk-regmap-mux.h"
  24 #include "gdsc.h"
  25 #include "reset.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL0_DIV2,
  31         P_GPLL2,
  32         P_GPLL4,
  33         P_GPLL6,
  34         P_SLEEP_CLK,
  35         P_PCIE20_PHY0_PIPE,
  36         P_PCIE20_PHY1_PIPE,
  37         P_USB3PHY_0_PIPE,
  38         P_USB3PHY_1_PIPE,
  39         P_UBI32_PLL,
  40         P_NSS_CRYPTO_PLL,
  41         P_BIAS_PLL,
  42         P_BIAS_PLL_NSS_NOC,
  43         P_UNIPHY0_RX,
  44         P_UNIPHY0_TX,
  45         P_UNIPHY1_RX,
  46         P_UNIPHY1_TX,
  47         P_UNIPHY2_RX,
  48         P_UNIPHY2_TX,
  49 };
  50
  51 static struct clk_alpha_pll gpll0_main = {
  52         .offset = 0x21000,
  53         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  54         .clkr = {
  55                 .enable_reg = 0x0b000,
  56                 .enable_mask = BIT(0),
  57                 .hw.init = &(struct clk_init_data){
  58                         .name = "gpll0_main",
  59                         .parent_data = &(const struct clk_parent_data){
  60                                 .fw_name = "xo",
  61                                 .name = "xo",
  62                         },
  63                         .num_parents = 1,
  64                         .ops = &clk_alpha_pll_ops,
  65                 },
  66         },
  67 };
  68
  69 static struct clk_fixed_factor gpll0_out_main_div2 = {
  70         .mult = 1,
  71         .div = 2,
  72         .hw.init = &(struct clk_init_data){
  73                 .name = "gpll0_out_main_div2",
  74                 .parent_hws = (const struct clk_hw *[]){
  75                                 &gpll0_main.clkr.hw },
  76                 .num_parents = 1,
  77                 .ops = &clk_fixed_factor_ops,
  78         },
  79 };
  80
  81 static struct clk_alpha_pll_postdiv gpll0 = {
  82         .offset = 0x21000,
  83         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  84         .width = 4,
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll0",
  87                 .parent_hws = (const struct clk_hw *[]){
  88                                 &gpll0_main.clkr.hw },
  89                 .num_parents = 1,
  90                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  91         },
  92 };
  93
  94 static struct clk_alpha_pll gpll2_main = {
  95         .offset = 0x4a000,
  96         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  97         .clkr = {
  98                 .enable_reg = 0x0b000,
  99                 .enable_mask = BIT(2),
 100                 .hw.init = &(struct clk_init_data){
 101                         .name = "gpll2_main",
 102                         .parent_data = &(const struct clk_parent_data){
 103                                 .fw_name = "xo",
 104                                 .name = "xo",
 105                         },
 106                         .num_parents = 1,
 107                         .ops = &clk_alpha_pll_ops,
 108                         .flags = CLK_IS_CRITICAL,
 109                 },
 110         },
 111 };
 112
 113 static struct clk_alpha_pll_postdiv gpll2 = {
 114         .offset = 0x4a000,
 115         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 116         .width = 4,
 117         .clkr.hw.init = &(struct clk_init_data){
 118                 .name = "gpll2",
 119                 .parent_hws = (const struct clk_hw *[]){
 120                                 &gpll2_main.clkr.hw },
 121                 .num_parents = 1,
 122                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 123         },
 124 };
 125
 126 static struct clk_alpha_pll gpll4_main = {
 127         .offset = 0x24000,
 128         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 129         .clkr = {
 130                 .enable_reg = 0x0b000,
 131                 .enable_mask = BIT(5),
 132                 .hw.init = &(struct clk_init_data){
 133                         .name = "gpll4_main",
 134                         .parent_data = &(const struct clk_parent_data){
 135                                 .fw_name = "xo",
 136                                 .name = "xo",
 137                         },
 138                         .num_parents = 1,
 139                         .ops = &clk_alpha_pll_ops,
 140                         .flags = CLK_IS_CRITICAL,
 141                 },
 142         },
 143 };
 144
 145 static struct clk_alpha_pll_postdiv gpll4 = {
 146         .offset = 0x24000,
 147         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 148         .width = 4,
 149         .clkr.hw.init = &(struct clk_init_data){
 150                 .name = "gpll4",
 151                 .parent_hws = (const struct clk_hw *[]){
 152                                 &gpll4_main.clkr.hw },
 153                 .num_parents = 1,
 154                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 155         },
 156 };
 157
 158 static struct clk_alpha_pll gpll6_main = {
 159         .offset = 0x37000,
 160         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 161         .flags = SUPPORTS_DYNAMIC_UPDATE,
 162         .clkr = {
 163                 .enable_reg = 0x0b000,
 164                 .enable_mask = BIT(7),
 165                 .hw.init = &(struct clk_init_data){
 166                         .name = "gpll6_main",
 167                         .parent_data = &(const struct clk_parent_data){
 168                                 .fw_name = "xo",
 169                                 .name = "xo",
 170                         },
 171                         .num_parents = 1,
 172                         .ops = &clk_alpha_pll_ops,
 173                         .flags = CLK_IS_CRITICAL,
 174                 },
 175         },
 176 };
 177
 178 static struct clk_alpha_pll_postdiv gpll6 = {
 179         .offset = 0x37000,
 180         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 181         .width = 2,
 182         .clkr.hw.init = &(struct clk_init_data){
 183                 .name = "gpll6",
 184                 .parent_hws = (const struct clk_hw *[]){
 185                                 &gpll6_main.clkr.hw },
 186                 .num_parents = 1,
 187                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 188         },
 189 };
 190
 191 static struct clk_fixed_factor gpll6_out_main_div2 = {
 192         .mult = 1,
 193         .div = 2,
 194         .hw.init = &(struct clk_init_data){
 195                 .name = "gpll6_out_main_div2",
 196                 .parent_hws = (const struct clk_hw *[]){
 197                                 &gpll6_main.clkr.hw },
 198                 .num_parents = 1,
 199                 .ops = &clk_fixed_factor_ops,
 200         },
 201 };
 202
 203 static struct clk_alpha_pll ubi32_pll_main = {
 204         .offset = 0x25000,
 205         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 206         .flags = SUPPORTS_DYNAMIC_UPDATE,
 207         .clkr = {
 208                 .enable_reg = 0x0b000,
 209                 .enable_mask = BIT(6),
 210                 .hw.init = &(struct clk_init_data){
 211                         .name = "ubi32_pll_main",
 212                         .parent_data = &(const struct clk_parent_data){
 213                                 .fw_name = "xo",
 214                                 .name = "xo",
 215                         },
 216                         .num_parents = 1,
 217                         .ops = &clk_alpha_pll_huayra_ops,
 218                 },
 219         },
 220 };
 221
 222 static struct clk_alpha_pll_postdiv ubi32_pll = {
 223         .offset = 0x25000,
 224         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 225         .width = 2,
 226         .clkr.hw.init = &(struct clk_init_data){
 227                 .name = "ubi32_pll",
 228                 .parent_hws = (const struct clk_hw *[]){
 229                                 &ubi32_pll_main.clkr.hw },
 230                 .num_parents = 1,
 231                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 232                 .flags = CLK_SET_RATE_PARENT,
 233         },
 234 };
 235
 236 static struct clk_alpha_pll nss_crypto_pll_main = {
 237         .offset = 0x22000,
 238         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 239         .clkr = {
 240                 .enable_reg = 0x0b000,
 241                 .enable_mask = BIT(4),
 242                 .hw.init = &(struct clk_init_data){
 243                         .name = "nss_crypto_pll_main",
 244                         .parent_data = &(const struct clk_parent_data){
 245                                 .fw_name = "xo",
 246                                 .name = "xo",
 247                         },
 248                         .num_parents = 1,
 249                         .ops = &clk_alpha_pll_ops,
 250                 },
 251         },
 252 };
 253
 254 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 255         .offset = 0x22000,
 256         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 257         .width = 4,
 258         .clkr.hw.init = &(struct clk_init_data){
 259                 .name = "nss_crypto_pll",
 260                 .parent_hws = (const struct clk_hw *[]){
 261                                 &nss_crypto_pll_main.clkr.hw },
 262                 .num_parents = 1,
 263                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 264         },
 265 };
 266
 267 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 268         F(19200000, P_XO, 1, 0, 0),
 269         F(50000000, P_GPLL0, 16, 0, 0),
 270         F(100000000, P_GPLL0, 8, 0, 0),
 271         { }
 272 };
 273
 274 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 275         { .fw_name = "xo", .name = "xo" },
 276         { .hw = &gpll0.clkr.hw},
 277         { .hw = &gpll0_out_main_div2.hw},
 278 };
 279
 280 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 281         { P_XO, 0 },
 282         { P_GPLL0, 1 },
 283         { P_GPLL0_DIV2, 4 },
 284 };
 285
 286 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 287         .cmd_rcgr = 0x27000,
 288         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 289         .hid_width = 5,
 290         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 291         .clkr.hw.init = &(struct clk_init_data){
 292                 .name = "pcnoc_bfdcd_clk_src",
 293                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 294                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 295                 .ops = &clk_rcg2_ops,
 296                 .flags = CLK_IS_CRITICAL,
 297         },
 298 };
 299
 300 static struct clk_fixed_factor pcnoc_clk_src = {
 301         .mult = 1,
 302         .div = 1,
 303         .hw.init = &(struct clk_init_data){
 304                 .name = "pcnoc_clk_src",
 305                 .parent_hws = (const struct clk_hw *[]){
 306                                 &pcnoc_bfdcd_clk_src.clkr.hw },
 307                 .num_parents = 1,
 308                 .ops = &clk_fixed_factor_ops,
 309                 .flags = CLK_SET_RATE_PARENT,
 310         },
 311 };
 312
 313 static struct clk_branch gcc_sleep_clk_src = {
 314         .halt_reg = 0x30000,
 315         .clkr = {
 316                 .enable_reg = 0x30000,
 317                 .enable_mask = BIT(1),
 318                 .hw.init = &(struct clk_init_data){
 319                         .name = "gcc_sleep_clk_src",
 320                         .parent_data = &(const struct clk_parent_data){
 321                                 .fw_name = "sleep_clk",
 322                                 .name = "sleep_clk",
 323                         },
 324                         .num_parents = 1,
 325                         .ops = &clk_branch2_ops,
 326                         .flags = CLK_IS_CRITICAL,
 327                 },
 328         },
 329 };
 330
 331 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 332         F(19200000, P_XO, 1, 0, 0),
 333         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 334         F(50000000, P_GPLL0, 16, 0, 0),
 335         { }
 336 };
 337
 338 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 339         .cmd_rcgr = 0x0200c,
 340         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 341         .hid_width = 5,
 342         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 343         .clkr.hw.init = &(struct clk_init_data){
 344                 .name = "blsp1_qup1_i2c_apps_clk_src",
 345                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 346                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 347                 .ops = &clk_rcg2_ops,
 348         },
 349 };
 350
 351 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 352         F(960000, P_XO, 10, 1, 2),
 353         F(4800000, P_XO, 4, 0, 0),
 354         F(9600000, P_XO, 2, 0, 0),
 355         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 356         F(16000000, P_GPLL0, 10, 1, 5),
 357         F(19200000, P_XO, 1, 0, 0),
 358         F(25000000, P_GPLL0, 16, 1, 2),
 359         F(50000000, P_GPLL0, 16, 0, 0),
 360         { }
 361 };
 362
 363 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 364         .cmd_rcgr = 0x02024,
 365         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 366         .mnd_width = 8,
 367         .hid_width = 5,
 368         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 369         .clkr.hw.init = &(struct clk_init_data){
 370                 .name = "blsp1_qup1_spi_apps_clk_src",
 371                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 372                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 373                 .ops = &clk_rcg2_ops,
 374         },
 375 };
 376
 377 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 378         .cmd_rcgr = 0x03000,
 379         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 380         .hid_width = 5,
 381         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 382         .clkr.hw.init = &(struct clk_init_data){
 383                 .name = "blsp1_qup2_i2c_apps_clk_src",
 384                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 385                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 386                 .ops = &clk_rcg2_ops,
 387         },
 388 };
 389
 390 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 391         .cmd_rcgr = 0x03014,
 392         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 393         .mnd_width = 8,
 394         .hid_width = 5,
 395         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 396         .clkr.hw.init = &(struct clk_init_data){
 397                 .name = "blsp1_qup2_spi_apps_clk_src",
 398                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 399                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 400                 .ops = &clk_rcg2_ops,
 401         },
 402 };
 403
 404 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 405         .cmd_rcgr = 0x04000,
 406         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 407         .hid_width = 5,
 408         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 409         .clkr.hw.init = &(struct clk_init_data){
 410                 .name = "blsp1_qup3_i2c_apps_clk_src",
 411                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 412                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 413                 .ops = &clk_rcg2_ops,
 414         },
 415 };
 416
 417 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 418         .cmd_rcgr = 0x04014,
 419         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 420         .mnd_width = 8,
 421         .hid_width = 5,
 422         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 423         .clkr.hw.init = &(struct clk_init_data){
 424                 .name = "blsp1_qup3_spi_apps_clk_src",
 425                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 426                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 427                 .ops = &clk_rcg2_ops,
 428         },
 429 };
 430
 431 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 432         .cmd_rcgr = 0x05000,
 433         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 434         .hid_width = 5,
 435         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 436         .clkr.hw.init = &(struct clk_init_data){
 437                 .name = "blsp1_qup4_i2c_apps_clk_src",
 438                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 439                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 440                 .ops = &clk_rcg2_ops,
 441         },
 442 };
 443
 444 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 445         .cmd_rcgr = 0x05014,
 446         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 447         .mnd_width = 8,
 448         .hid_width = 5,
 449         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 450         .clkr.hw.init = &(struct clk_init_data){
 451                 .name = "blsp1_qup4_spi_apps_clk_src",
 452                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 453                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 454                 .ops = &clk_rcg2_ops,
 455         },
 456 };
 457
 458 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 459         .cmd_rcgr = 0x06000,
 460         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 461         .hid_width = 5,
 462         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 463         .clkr.hw.init = &(struct clk_init_data){
 464                 .name = "blsp1_qup5_i2c_apps_clk_src",
 465                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 466                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 467                 .ops = &clk_rcg2_ops,
 468         },
 469 };
 470
 471 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 472         .cmd_rcgr = 0x06014,
 473         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 474         .mnd_width = 8,
 475         .hid_width = 5,
 476         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 477         .clkr.hw.init = &(struct clk_init_data){
 478                 .name = "blsp1_qup5_spi_apps_clk_src",
 479                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 480                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 481                 .ops = &clk_rcg2_ops,
 482         },
 483 };
 484
 485 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 486         .cmd_rcgr = 0x07000,
 487         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 488         .hid_width = 5,
 489         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 490         .clkr.hw.init = &(struct clk_init_data){
 491                 .name = "blsp1_qup6_i2c_apps_clk_src",
 492                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 493                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 494                 .ops = &clk_rcg2_ops,
 495         },
 496 };
 497
 498 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 499         .cmd_rcgr = 0x07014,
 500         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 501         .mnd_width = 8,
 502         .hid_width = 5,
 503         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 504         .clkr.hw.init = &(struct clk_init_data){
 505                 .name = "blsp1_qup6_spi_apps_clk_src",
 506                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 507                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 513         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 514         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 515         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 516         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 517         F(19200000, P_XO, 1, 0, 0),
 518         F(24000000, P_GPLL0, 1, 3, 100),
 519         F(25000000, P_GPLL0, 16, 1, 2),
 520         F(32000000, P_GPLL0, 1, 1, 25),
 521         F(40000000, P_GPLL0, 1, 1, 20),
 522         F(46400000, P_GPLL0, 1, 29, 500),
 523         F(48000000, P_GPLL0, 1, 3, 50),
 524         F(51200000, P_GPLL0, 1, 8, 125),
 525         F(56000000, P_GPLL0, 1, 7, 100),
 526         F(58982400, P_GPLL0, 1, 1152, 15625),
 527         F(60000000, P_GPLL0, 1, 3, 40),
 528         F(64000000, P_GPLL0, 12.5, 1, 1),
 529         { }
 530 };
 531
 532 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 533         .cmd_rcgr = 0x02044,
 534         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 535         .mnd_width = 16,
 536         .hid_width = 5,
 537         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 538         .clkr.hw.init = &(struct clk_init_data){
 539                 .name = "blsp1_uart1_apps_clk_src",
 540                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 541                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 542                 .ops = &clk_rcg2_ops,
 543         },
 544 };
 545
 546 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 547         .cmd_rcgr = 0x03034,
 548         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 549         .mnd_width = 16,
 550         .hid_width = 5,
 551         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 552         .clkr.hw.init = &(struct clk_init_data){
 553                 .name = "blsp1_uart2_apps_clk_src",
 554                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 555                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 556                 .ops = &clk_rcg2_ops,
 557         },
 558 };
 559
 560 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 561         .cmd_rcgr = 0x04034,
 562         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 563         .mnd_width = 16,
 564         .hid_width = 5,
 565         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 566         .clkr.hw.init = &(struct clk_init_data){
 567                 .name = "blsp1_uart3_apps_clk_src",
 568                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 569                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 570                 .ops = &clk_rcg2_ops,
 571         },
 572 };
 573
 574 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 575         .cmd_rcgr = 0x05034,
 576         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 577         .mnd_width = 16,
 578         .hid_width = 5,
 579         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 580         .clkr.hw.init = &(struct clk_init_data){
 581                 .name = "blsp1_uart4_apps_clk_src",
 582                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 583                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 584                 .ops = &clk_rcg2_ops,
 585         },
 586 };
 587
 588 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 589         .cmd_rcgr = 0x06034,
 590         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 591         .mnd_width = 16,
 592         .hid_width = 5,
 593         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 594         .clkr.hw.init = &(struct clk_init_data){
 595                 .name = "blsp1_uart5_apps_clk_src",
 596                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 597                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 603         .cmd_rcgr = 0x07034,
 604         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 605         .mnd_width = 16,
 606         .hid_width = 5,
 607         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 608         .clkr.hw.init = &(struct clk_init_data){
 609                 .name = "blsp1_uart6_apps_clk_src",
 610                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 611                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 612                 .ops = &clk_rcg2_ops,
 613         },
 614 };
 615
 616 static const struct clk_parent_data gcc_xo_gpll0[] = {
 617         { .fw_name = "xo" },
 618         { .hw = &gpll0.clkr.hw },
 619 };
 620
 621 static const struct parent_map gcc_xo_gpll0_map[] = {
 622         { P_XO, 0 },
 623         { P_GPLL0, 1 },
 624 };
 625
 626 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 627         F(19200000, P_XO, 1, 0, 0),
 628         F(200000000, P_GPLL0, 4, 0, 0),
 629         { }
 630 };
 631
 632 static struct clk_rcg2 pcie0_axi_clk_src = {
 633         .cmd_rcgr = 0x75054,
 634         .freq_tbl = ftbl_pcie_axi_clk_src,
 635         .hid_width = 5,
 636         .parent_map = gcc_xo_gpll0_map,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "pcie0_axi_clk_src",
 639                 .parent_data = gcc_xo_gpll0,
 640                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 641                 .ops = &clk_rcg2_ops,
 642         },
 643 };
 644
 645 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 646         F(19200000, P_XO, 1, 0, 0),
 647 };
 648
 649 static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
 650         { .fw_name = "xo", .name = "xo" },
 651         { .hw = &gpll0.clkr.hw },
 652         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 653 };
 654
 655 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
 656         { P_XO, 0 },
 657         { P_GPLL0, 2 },
 658         { P_SLEEP_CLK, 6 },
 659 };
 660
 661 static struct clk_rcg2 pcie0_aux_clk_src = {
 662         .cmd_rcgr = 0x75024,
 663         .freq_tbl = ftbl_pcie_aux_clk_src,
 664         .mnd_width = 16,
 665         .hid_width = 5,
 666         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 667         .clkr.hw.init = &(struct clk_init_data){
 668                 .name = "pcie0_aux_clk_src",
 669                 .parent_data = gcc_xo_gpll0_sleep_clk,
 670                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 671                 .ops = &clk_rcg2_ops,
 672         },
 673 };
 674
 675 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
 676         { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
 677         { .fw_name = "xo", .name = "xo" },
 678 };
 679
 680 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 681         { P_PCIE20_PHY0_PIPE, 0 },
 682         { P_XO, 2 },
 683 };
 684
 685 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 686         .reg = 0x7501c,
 687         .shift = 8,
 688         .width = 2,
 689         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 690         .clkr = {
 691                 .hw.init = &(struct clk_init_data){
 692                         .name = "pcie0_pipe_clk_src",
 693                         .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
 694                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
 695                         .ops = &clk_regmap_mux_closest_ops,
 696                         .flags = CLK_SET_RATE_PARENT,
 697                 },
 698         },
 699 };
 700
 701 static struct clk_rcg2 pcie1_axi_clk_src = {
 702         .cmd_rcgr = 0x76054,
 703         .freq_tbl = ftbl_pcie_axi_clk_src,
 704         .hid_width = 5,
 705         .parent_map = gcc_xo_gpll0_map,
 706         .clkr.hw.init = &(struct clk_init_data){
 707                 .name = "pcie1_axi_clk_src",
 708                 .parent_data = gcc_xo_gpll0,
 709                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 710                 .ops = &clk_rcg2_ops,
 711         },
 712 };
 713
 714 static struct clk_rcg2 pcie1_aux_clk_src = {
 715         .cmd_rcgr = 0x76024,
 716         .freq_tbl = ftbl_pcie_aux_clk_src,
 717         .mnd_width = 16,
 718         .hid_width = 5,
 719         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 720         .clkr.hw.init = &(struct clk_init_data){
 721                 .name = "pcie1_aux_clk_src",
 722                 .parent_data = gcc_xo_gpll0_sleep_clk,
 723                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 724                 .ops = &clk_rcg2_ops,
 725         },
 726 };
 727
 728 static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
 729         { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
 730         { .fw_name = "xo", .name = "xo" },
 731 };
 732
 733 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 734         { P_PCIE20_PHY1_PIPE, 0 },
 735         { P_XO, 2 },
 736 };
 737
 738 static struct clk_regmap_mux pcie1_pipe_clk_src = {
 739         .reg = 0x7601c,
 740         .shift = 8,
 741         .width = 2,
 742         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
 743         .clkr = {
 744                 .hw.init = &(struct clk_init_data){
 745                         .name = "pcie1_pipe_clk_src",
 746                         .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
 747                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
 748                         .ops = &clk_regmap_mux_closest_ops,
 749                         .flags = CLK_SET_RATE_PARENT,
 750                 },
 751         },
 752 };
 753
 754 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 755         F(144000, P_XO, 16, 3, 25),
 756         F(400000, P_XO, 12, 1, 4),
 757         F(24000000, P_GPLL2, 12, 1, 4),
 758         F(48000000, P_GPLL2, 12, 1, 2),
 759         F(96000000, P_GPLL2, 12, 0, 0),
 760         F(177777778, P_GPLL0, 4.5, 0, 0),
 761         F(192000000, P_GPLL2, 6, 0, 0),
 762         F(384000000, P_GPLL2, 3, 0, 0),
 763         { }
 764 };
 765
 766 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 767         { .fw_name = "xo", .name = "xo" },
 768         { .hw = &gpll0.clkr.hw },
 769         { .hw = &gpll2.clkr.hw },
 770         { .hw = &gpll0_out_main_div2.hw },
 771 };
 772
 773 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 774         { P_XO, 0 },
 775         { P_GPLL0, 1 },
 776         { P_GPLL2, 2 },
 777         { P_GPLL0_DIV2, 4 },
 778 };
 779
 780 static struct clk_rcg2 sdcc1_apps_clk_src = {
 781         .cmd_rcgr = 0x42004,
 782         .freq_tbl = ftbl_sdcc_apps_clk_src,
 783         .mnd_width = 8,
 784         .hid_width = 5,
 785         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 786         .clkr.hw.init = &(struct clk_init_data){
 787                 .name = "sdcc1_apps_clk_src",
 788                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 789                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 790                 .ops = &clk_rcg2_floor_ops,
 791         },
 792 };
 793
 794 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
 795         F(19200000, P_XO, 1, 0, 0),
 796         F(160000000, P_GPLL0, 5, 0, 0),
 797         F(308570000, P_GPLL6, 3.5, 0, 0),
 798 };
 799
 800 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 801         { .fw_name = "xo", .name = "xo" },
 802         { .hw = &gpll0.clkr.hw },
 803         { .hw = &gpll6.clkr.hw },
 804         { .hw = &gpll0_out_main_div2.hw },
 805 };
 806
 807 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 808         { P_XO, 0 },
 809         { P_GPLL0, 1 },
 810         { P_GPLL6, 2 },
 811         { P_GPLL0_DIV2, 4 },
 812 };
 813
 814 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 815         .cmd_rcgr = 0x5d000,
 816         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
 817         .mnd_width = 8,
 818         .hid_width = 5,
 819         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
 820         .clkr.hw.init = &(struct clk_init_data){
 821                 .name = "sdcc1_ice_core_clk_src",
 822                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
 823                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
 824                 .ops = &clk_rcg2_ops,
 825         },
 826 };
 827
 828 static struct clk_rcg2 sdcc2_apps_clk_src = {
 829         .cmd_rcgr = 0x43004,
 830         .freq_tbl = ftbl_sdcc_apps_clk_src,
 831         .mnd_width = 8,
 832         .hid_width = 5,
 833         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 834         .clkr.hw.init = &(struct clk_init_data){
 835                 .name = "sdcc2_apps_clk_src",
 836                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 837                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 838                 .ops = &clk_rcg2_floor_ops,
 839         },
 840 };
 841
 842 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
 843         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 844         F(100000000, P_GPLL0, 8, 0, 0),
 845         F(133330000, P_GPLL0, 6, 0, 0),
 846         { }
 847 };
 848
 849 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 850         { .fw_name = "xo", .name = "xo" },
 851         { .hw = &gpll0_out_main_div2.hw },
 852         { .hw = &gpll0.clkr.hw },
 853 };
 854
 855 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 856         { P_XO, 0 },
 857         { P_GPLL0_DIV2, 2 },
 858         { P_GPLL0, 1 },
 859 };
 860
 861 static struct clk_rcg2 usb0_master_clk_src = {
 862         .cmd_rcgr = 0x3e00c,
 863         .freq_tbl = ftbl_usb_master_clk_src,
 864         .mnd_width = 8,
 865         .hid_width = 5,
 866         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 867         .clkr.hw.init = &(struct clk_init_data){
 868                 .name = "usb0_master_clk_src",
 869                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 870                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 871                 .ops = &clk_rcg2_ops,
 872         },
 873 };
 874
 875 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
 876         F(19200000, P_XO, 1, 0, 0),
 877         { }
 878 };
 879
 880 static struct clk_rcg2 usb0_aux_clk_src = {
 881         .cmd_rcgr = 0x3e05c,
 882         .freq_tbl = ftbl_usb_aux_clk_src,
 883         .mnd_width = 16,
 884         .hid_width = 5,
 885         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 886         .clkr.hw.init = &(struct clk_init_data){
 887                 .name = "usb0_aux_clk_src",
 888                 .parent_data = gcc_xo_gpll0_sleep_clk,
 889                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 890                 .ops = &clk_rcg2_ops,
 891         },
 892 };
 893
 894 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
 895         F(19200000, P_XO, 1, 0, 0),
 896         F(20000000, P_GPLL6, 6, 1, 9),
 897         F(60000000, P_GPLL6, 6, 1, 3),
 898         { }
 899 };
 900
 901 static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 902         { .fw_name = "xo", .name = "xo" },
 903         { .hw = &gpll6.clkr.hw },
 904         { .hw = &gpll0.clkr.hw },
 905         { .hw = &gpll0_out_main_div2.hw },
 906 };
 907
 908 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 909         { P_XO, 0 },
 910         { P_GPLL6, 1 },
 911         { P_GPLL0, 3 },
 912         { P_GPLL0_DIV2, 4 },
 913 };
 914
 915 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
 916         .cmd_rcgr = 0x3e020,
 917         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 921         .clkr.hw.init = &(struct clk_init_data){
 922                 .name = "usb0_mock_utmi_clk_src",
 923                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 924                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
 925                 .ops = &clk_rcg2_ops,
 926         },
 927 };
 928
 929 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 930         { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
 931         { .fw_name = "xo", .name = "xo" },
 932 };
 933
 934 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 935         { P_USB3PHY_0_PIPE, 0 },
 936         { P_XO, 2 },
 937 };
 938
 939 static struct clk_regmap_mux usb0_pipe_clk_src = {
 940         .reg = 0x3e048,
 941         .shift = 8,
 942         .width = 2,
 943         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
 944         .clkr = {
 945                 .hw.init = &(struct clk_init_data){
 946                         .name = "usb0_pipe_clk_src",
 947                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
 948                         .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
 949                         .ops = &clk_regmap_mux_closest_ops,
 950                         .flags = CLK_SET_RATE_PARENT,
 951                 },
 952         },
 953 };
 954
 955 static struct clk_rcg2 usb1_master_clk_src = {
 956         .cmd_rcgr = 0x3f00c,
 957         .freq_tbl = ftbl_usb_master_clk_src,
 958         .mnd_width = 8,
 959         .hid_width = 5,
 960         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 961         .clkr.hw.init = &(struct clk_init_data){
 962                 .name = "usb1_master_clk_src",
 963                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 964                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 965                 .ops = &clk_rcg2_ops,
 966         },
 967 };
 968
 969 static struct clk_rcg2 usb1_aux_clk_src = {
 970         .cmd_rcgr = 0x3f05c,
 971         .freq_tbl = ftbl_usb_aux_clk_src,
 972         .mnd_width = 16,
 973         .hid_width = 5,
 974         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 975         .clkr.hw.init = &(struct clk_init_data){
 976                 .name = "usb1_aux_clk_src",
 977                 .parent_data = gcc_xo_gpll0_sleep_clk,
 978                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 979                 .ops = &clk_rcg2_ops,
 980         },
 981 };
 982
 983 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
 984         .cmd_rcgr = 0x3f020,
 985         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
 986         .mnd_width = 8,
 987         .hid_width = 5,
 988         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 989         .clkr.hw.init = &(struct clk_init_data){
 990                 .name = "usb1_mock_utmi_clk_src",
 991                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 992                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
 993                 .ops = &clk_rcg2_ops,
 994         },
 995 };
 996
 997 static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 998         { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
 999         { .fw_name = "xo", .name = "xo" },
1000 };
1001
1002 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
1003         { P_USB3PHY_1_PIPE, 0 },
1004         { P_XO, 2 },
1005 };
1006
1007 static struct clk_regmap_mux usb1_pipe_clk_src = {
1008         .reg = 0x3f048,
1009         .shift = 8,
1010         .width = 2,
1011         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1012         .clkr = {
1013                 .hw.init = &(struct clk_init_data){
1014                         .name = "usb1_pipe_clk_src",
1015                         .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
1016                         .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
1017                         .ops = &clk_regmap_mux_closest_ops,
1018                         .flags = CLK_SET_RATE_PARENT,
1019                 },
1020         },
1021 };
1022
1023 static struct clk_branch gcc_xo_clk_src = {
1024         .halt_reg = 0x30018,
1025         .clkr = {
1026                 .enable_reg = 0x30018,
1027                 .enable_mask = BIT(1),
1028                 .hw.init = &(struct clk_init_data){
1029                         .name = "gcc_xo_clk_src",
1030                         .parent_data = &(const struct clk_parent_data){
1031                                 .fw_name = "xo",
1032                                 .name = "xo",
1033                         },
1034                         .num_parents = 1,
1035                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1036                         .ops = &clk_branch2_ops,
1037                 },
1038         },
1039 };
1040
1041 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1042         .mult = 1,
1043         .div = 4,
1044         .hw.init = &(struct clk_init_data){
1045                 .name = "gcc_xo_div4_clk_src",
1046                 .parent_hws = (const struct clk_hw *[]){
1047                                 &gcc_xo_clk_src.clkr.hw },
1048                 .num_parents = 1,
1049                 .ops = &clk_fixed_factor_ops,
1050                 .flags = CLK_SET_RATE_PARENT,
1051         },
1052 };
1053
1054 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1055         F(19200000, P_XO, 1, 0, 0),
1056         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1057         F(100000000, P_GPLL0, 8, 0, 0),
1058         F(133333333, P_GPLL0, 6, 0, 0),
1059         F(160000000, P_GPLL0, 5, 0, 0),
1060         F(200000000, P_GPLL0, 4, 0, 0),
1061         F(266666667, P_GPLL0, 3, 0, 0),
1062         { }
1063 };
1064
1065 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
1066         { .fw_name = "xo", .name = "xo" },
1067         { .hw = &gpll0.clkr.hw },
1068         { .hw = &gpll6.clkr.hw },
1069         { .hw = &gpll0_out_main_div2.hw },
1070 };
1071
1072 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
1073         { P_XO, 0 },
1074         { P_GPLL0, 1 },
1075         { P_GPLL6, 2 },
1076         { P_GPLL0_DIV2, 3 },
1077 };
1078
1079 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1080         .cmd_rcgr = 0x26004,
1081         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1082         .hid_width = 5,
1083         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1084         .clkr.hw.init = &(struct clk_init_data){
1085                 .name = "system_noc_bfdcd_clk_src",
1086                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1087                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
1088                 .ops = &clk_rcg2_ops,
1089                 .flags = CLK_IS_CRITICAL,
1090         },
1091 };
1092
1093 static struct clk_fixed_factor system_noc_clk_src = {
1094         .mult = 1,
1095         .div = 1,
1096         .hw.init = &(struct clk_init_data){
1097                 .name = "system_noc_clk_src",
1098                 .parent_hws = (const struct clk_hw *[]){
1099                                 &system_noc_bfdcd_clk_src.clkr.hw },
1100                 .num_parents = 1,
1101                 .ops = &clk_fixed_factor_ops,
1102                 .flags = CLK_SET_RATE_PARENT,
1103         },
1104 };
1105
1106 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1107         F(19200000, P_XO, 1, 0, 0),
1108         F(200000000, P_GPLL0, 4, 0, 0),
1109         { }
1110 };
1111
1112 static struct clk_rcg2 nss_ce_clk_src = {
1113         .cmd_rcgr = 0x68098,
1114         .freq_tbl = ftbl_nss_ce_clk_src,
1115         .hid_width = 5,
1116         .parent_map = gcc_xo_gpll0_map,
1117         .clkr.hw.init = &(struct clk_init_data){
1118                 .name = "nss_ce_clk_src",
1119                 .parent_data = gcc_xo_gpll0,
1120                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1121                 .ops = &clk_rcg2_ops,
1122         },
1123 };
1124
1125 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1126         F(19200000, P_XO, 1, 0, 0),
1127         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1128         { }
1129 };
1130
1131 static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
1132         { .fw_name = "xo", .name = "xo" },
1133         { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
1134         { .hw = &gpll0.clkr.hw },
1135         { .hw = &gpll2.clkr.hw },
1136 };
1137
1138 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
1139         { P_XO, 0 },
1140         { P_BIAS_PLL_NSS_NOC, 1 },
1141         { P_GPLL0, 2 },
1142         { P_GPLL2, 3 },
1143 };
1144
1145 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1146         .cmd_rcgr = 0x68088,
1147         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1148         .hid_width = 5,
1149         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1150         .clkr.hw.init = &(struct clk_init_data){
1151                 .name = "nss_noc_bfdcd_clk_src",
1152                 .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1153                 .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
1154                 .ops = &clk_rcg2_ops,
1155         },
1156 };
1157
1158 static struct clk_fixed_factor nss_noc_clk_src = {
1159         .mult = 1,
1160         .div = 1,
1161         .hw.init = &(struct clk_init_data){
1162                 .name = "nss_noc_clk_src",
1163                 .parent_hws = (const struct clk_hw *[]){
1164                                 &nss_noc_bfdcd_clk_src.clkr.hw },
1165                 .num_parents = 1,
1166                 .ops = &clk_fixed_factor_ops,
1167                 .flags = CLK_SET_RATE_PARENT,
1168         },
1169 };
1170
1171 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1172         F(19200000, P_XO, 1, 0, 0),
1173         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1174         { }
1175 };
1176
1177 static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
1178         { .fw_name = "xo", .name = "xo" },
1179         { .hw = &nss_crypto_pll.clkr.hw },
1180         { .hw = &gpll0.clkr.hw },
1181 };
1182
1183 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
1184         { P_XO, 0 },
1185         { P_NSS_CRYPTO_PLL, 1 },
1186         { P_GPLL0, 2 },
1187 };
1188
1189 static struct clk_rcg2 nss_crypto_clk_src = {
1190         .cmd_rcgr = 0x68144,
1191         .freq_tbl = ftbl_nss_crypto_clk_src,
1192         .mnd_width = 16,
1193         .hid_width = 5,
1194         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1195         .clkr.hw.init = &(struct clk_init_data){
1196                 .name = "nss_crypto_clk_src",
1197                 .parent_data = gcc_xo_nss_crypto_pll_gpll0,
1198                 .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
1199                 .ops = &clk_rcg2_ops,
1200         },
1201 };
1202
1203 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1204         F(19200000, P_XO, 1, 0, 0),
1205         F(187200000, P_UBI32_PLL, 8, 0, 0),
1206         F(748800000, P_UBI32_PLL, 2, 0, 0),
1207         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1208         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1209         { }
1210 };
1211
1212 static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1213         { .fw_name = "xo", .name = "xo" },
1214         { .hw = &ubi32_pll.clkr.hw },
1215         { .hw = &gpll0.clkr.hw },
1216         { .hw = &gpll2.clkr.hw },
1217         { .hw = &gpll4.clkr.hw },
1218         { .hw = &gpll6.clkr.hw },
1219 };
1220
1221 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1222         { P_XO, 0 },
1223         { P_UBI32_PLL, 1 },
1224         { P_GPLL0, 2 },
1225         { P_GPLL2, 3 },
1226         { P_GPLL4, 4 },
1227         { P_GPLL6, 5 },
1228 };
1229
1230 static struct clk_rcg2 nss_ubi0_clk_src = {
1231         .cmd_rcgr = 0x68104,
1232         .freq_tbl = ftbl_nss_ubi_clk_src,
1233         .hid_width = 5,
1234         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1235         .clkr.hw.init = &(struct clk_init_data){
1236                 .name = "nss_ubi0_clk_src",
1237                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1238                 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1239                 .ops = &clk_rcg2_ops,
1240                 .flags = CLK_SET_RATE_PARENT,
1241         },
1242 };
1243
1244 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1245         .reg = 0x68118,
1246         .shift = 0,
1247         .width = 4,
1248         .clkr = {
1249                 .hw.init = &(struct clk_init_data){
1250                         .name = "nss_ubi0_div_clk_src",
1251                         .parent_hws = (const struct clk_hw *[]){
1252                                 &nss_ubi0_clk_src.clkr.hw },
1253                         .num_parents = 1,
1254                         .ops = &clk_regmap_div_ro_ops,
1255                         .flags = CLK_SET_RATE_PARENT,
1256                 },
1257         },
1258 };
1259
1260 static struct clk_rcg2 nss_ubi1_clk_src = {
1261         .cmd_rcgr = 0x68124,
1262         .freq_tbl = ftbl_nss_ubi_clk_src,
1263         .hid_width = 5,
1264         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1265         .clkr.hw.init = &(struct clk_init_data){
1266                 .name = "nss_ubi1_clk_src",
1267                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1268                 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1269                 .ops = &clk_rcg2_ops,
1270                 .flags = CLK_SET_RATE_PARENT,
1271         },
1272 };
1273
1274 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1275         .reg = 0x68138,
1276         .shift = 0,
1277         .width = 4,
1278         .clkr = {
1279                 .hw.init = &(struct clk_init_data){
1280                         .name = "nss_ubi1_div_clk_src",
1281                         .parent_hws = (const struct clk_hw *[]){
1282                                 &nss_ubi1_clk_src.clkr.hw },
1283                         .num_parents = 1,
1284                         .ops = &clk_regmap_div_ro_ops,
1285                         .flags = CLK_SET_RATE_PARENT,
1286                 },
1287         },
1288 };
1289
1290 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1291         F(19200000, P_XO, 1, 0, 0),
1292         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1293         { }
1294 };
1295
1296 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
1297         { .fw_name = "xo", .name = "xo" },
1298         { .hw = &gpll0_out_main_div2.hw },
1299 };
1300
1301 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
1302         { P_XO, 0 },
1303         { P_GPLL0_DIV2, 1 },
1304 };
1305
1306 static struct clk_rcg2 ubi_mpt_clk_src = {
1307         .cmd_rcgr = 0x68090,
1308         .freq_tbl = ftbl_ubi_mpt_clk_src,
1309         .hid_width = 5,
1310         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1311         .clkr.hw.init = &(struct clk_init_data){
1312                 .name = "ubi_mpt_clk_src",
1313                 .parent_data = gcc_xo_gpll0_out_main_div2,
1314                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
1315                 .ops = &clk_rcg2_ops,
1316         },
1317 };
1318
1319 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1320         F(19200000, P_XO, 1, 0, 0),
1321         F(400000000, P_GPLL0, 2, 0, 0),
1322         { }
1323 };
1324
1325 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1326         { .fw_name = "xo", .name = "xo" },
1327         { .hw = &gpll0.clkr.hw },
1328         { .hw = &gpll4.clkr.hw },
1329 };
1330
1331 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1332         { P_XO, 0 },
1333         { P_GPLL0, 1 },
1334         { P_GPLL4, 2 },
1335 };
1336
1337 static struct clk_rcg2 nss_imem_clk_src = {
1338         .cmd_rcgr = 0x68158,
1339         .freq_tbl = ftbl_nss_imem_clk_src,
1340         .hid_width = 5,
1341         .parent_map = gcc_xo_gpll0_gpll4_map,
1342         .clkr.hw.init = &(struct clk_init_data){
1343                 .name = "nss_imem_clk_src",
1344                 .parent_data = gcc_xo_gpll0_gpll4,
1345                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1346                 .ops = &clk_rcg2_ops,
1347         },
1348 };
1349
1350 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1351         F(19200000, P_XO, 1, 0, 0),
1352         F(300000000, P_BIAS_PLL, 1, 0, 0),
1353         { }
1354 };
1355
1356 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
1357         { .fw_name = "xo", .name = "xo" },
1358         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1359         { .hw = &gpll0.clkr.hw },
1360         { .hw = &gpll4.clkr.hw },
1361         { .hw = &nss_crypto_pll.clkr.hw },
1362         { .hw = &ubi32_pll.clkr.hw },
1363 };
1364
1365 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
1366         { P_XO, 0 },
1367         { P_BIAS_PLL, 1 },
1368         { P_GPLL0, 2 },
1369         { P_GPLL4, 3 },
1370         { P_NSS_CRYPTO_PLL, 4 },
1371         { P_UBI32_PLL, 5 },
1372 };
1373
1374 static struct clk_rcg2 nss_ppe_clk_src = {
1375         .cmd_rcgr = 0x68080,
1376         .freq_tbl = ftbl_nss_ppe_clk_src,
1377         .hid_width = 5,
1378         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1379         .clkr.hw.init = &(struct clk_init_data){
1380                 .name = "nss_ppe_clk_src",
1381                 .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1382                 .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
1383                 .ops = &clk_rcg2_ops,
1384         },
1385 };
1386
1387 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1388         .mult = 1,
1389         .div = 4,
1390         .hw.init = &(struct clk_init_data){
1391                 .name = "nss_ppe_cdiv_clk_src",
1392                 .parent_hws = (const struct clk_hw *[]){
1393                                 &nss_ppe_clk_src.clkr.hw },
1394                 .num_parents = 1,
1395                 .ops = &clk_fixed_factor_ops,
1396                 .flags = CLK_SET_RATE_PARENT,
1397         },
1398 };
1399
1400 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1401         F(19200000, P_XO, 1, 0, 0),
1402         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1403         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1404         { }
1405 };
1406
1407 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
1408         { .fw_name = "xo", .name = "xo" },
1409         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1410         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1411         { .hw = &ubi32_pll.clkr.hw },
1412         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1413 };
1414
1415 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
1416         { P_XO, 0 },
1417         { P_UNIPHY0_RX, 1 },
1418         { P_UNIPHY0_TX, 2 },
1419         { P_UBI32_PLL, 5 },
1420         { P_BIAS_PLL, 6 },
1421 };
1422
1423 static struct clk_rcg2 nss_port1_rx_clk_src = {
1424         .cmd_rcgr = 0x68020,
1425         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1426         .hid_width = 5,
1427         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1428         .clkr.hw.init = &(struct clk_init_data){
1429                 .name = "nss_port1_rx_clk_src",
1430                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1431                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1432                 .ops = &clk_rcg2_ops,
1433         },
1434 };
1435
1436 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1437         .reg = 0x68400,
1438         .shift = 0,
1439         .width = 4,
1440         .clkr = {
1441                 .hw.init = &(struct clk_init_data){
1442                         .name = "nss_port1_rx_div_clk_src",
1443                         .parent_hws = (const struct clk_hw *[]){
1444                                 &nss_port1_rx_clk_src.clkr.hw },
1445                         .num_parents = 1,
1446                         .ops = &clk_regmap_div_ops,
1447                         .flags = CLK_SET_RATE_PARENT,
1448                 },
1449         },
1450 };
1451
1452 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1453         F(19200000, P_XO, 1, 0, 0),
1454         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1455         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1456         { }
1457 };
1458
1459 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
1460         { .fw_name = "xo", .name = "xo" },
1461         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1462         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1463         { .hw = &ubi32_pll.clkr.hw },
1464         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1465 };
1466
1467 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
1468         { P_XO, 0 },
1469         { P_UNIPHY0_TX, 1 },
1470         { P_UNIPHY0_RX, 2 },
1471         { P_UBI32_PLL, 5 },
1472         { P_BIAS_PLL, 6 },
1473 };
1474
1475 static struct clk_rcg2 nss_port1_tx_clk_src = {
1476         .cmd_rcgr = 0x68028,
1477         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1478         .hid_width = 5,
1479         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1480         .clkr.hw.init = &(struct clk_init_data){
1481                 .name = "nss_port1_tx_clk_src",
1482                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1483                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1484                 .ops = &clk_rcg2_ops,
1485         },
1486 };
1487
1488 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1489         .reg = 0x68404,
1490         .shift = 0,
1491         .width = 4,
1492         .clkr = {
1493                 .hw.init = &(struct clk_init_data){
1494                         .name = "nss_port1_tx_div_clk_src",
1495                         .parent_hws = (const struct clk_hw *[]){
1496                                 &nss_port1_tx_clk_src.clkr.hw },
1497                         .num_parents = 1,
1498                         .ops = &clk_regmap_div_ops,
1499                         .flags = CLK_SET_RATE_PARENT,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_rcg2 nss_port2_rx_clk_src = {
1505         .cmd_rcgr = 0x68030,
1506         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1507         .hid_width = 5,
1508         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1509         .clkr.hw.init = &(struct clk_init_data){
1510                 .name = "nss_port2_rx_clk_src",
1511                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1512                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1513                 .ops = &clk_rcg2_ops,
1514         },
1515 };
1516
1517 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1518         .reg = 0x68410,
1519         .shift = 0,
1520         .width = 4,
1521         .clkr = {
1522                 .hw.init = &(struct clk_init_data){
1523                         .name = "nss_port2_rx_div_clk_src",
1524                         .parent_hws = (const struct clk_hw *[]){
1525                                 &nss_port2_rx_clk_src.clkr.hw },
1526                         .num_parents = 1,
1527                         .ops = &clk_regmap_div_ops,
1528                         .flags = CLK_SET_RATE_PARENT,
1529                 },
1530         },
1531 };
1532
1533 static struct clk_rcg2 nss_port2_tx_clk_src = {
1534         .cmd_rcgr = 0x68038,
1535         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1536         .hid_width = 5,
1537         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1538         .clkr.hw.init = &(struct clk_init_data){
1539                 .name = "nss_port2_tx_clk_src",
1540                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1541                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1542                 .ops = &clk_rcg2_ops,
1543         },
1544 };
1545
1546 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1547         .reg = 0x68414,
1548         .shift = 0,
1549         .width = 4,
1550         .clkr = {
1551                 .hw.init = &(struct clk_init_data){
1552                         .name = "nss_port2_tx_div_clk_src",
1553                         .parent_hws = (const struct clk_hw *[]){
1554                                 &nss_port2_tx_clk_src.clkr.hw },
1555                         .num_parents = 1,
1556                         .ops = &clk_regmap_div_ops,
1557                         .flags = CLK_SET_RATE_PARENT,
1558                 },
1559         },
1560 };
1561
1562 static struct clk_rcg2 nss_port3_rx_clk_src = {
1563         .cmd_rcgr = 0x68040,
1564         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1565         .hid_width = 5,
1566         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1567         .clkr.hw.init = &(struct clk_init_data){
1568                 .name = "nss_port3_rx_clk_src",
1569                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1570                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1571                 .ops = &clk_rcg2_ops,
1572         },
1573 };
1574
1575 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1576         .reg = 0x68420,
1577         .shift = 0,
1578         .width = 4,
1579         .clkr = {
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "nss_port3_rx_div_clk_src",
1582                         .parent_hws = (const struct clk_hw *[]){
1583                                 &nss_port3_rx_clk_src.clkr.hw },
1584                         .num_parents = 1,
1585                         .ops = &clk_regmap_div_ops,
1586                         .flags = CLK_SET_RATE_PARENT,
1587                 },
1588         },
1589 };
1590
1591 static struct clk_rcg2 nss_port3_tx_clk_src = {
1592         .cmd_rcgr = 0x68048,
1593         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1594         .hid_width = 5,
1595         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1596         .clkr.hw.init = &(struct clk_init_data){
1597                 .name = "nss_port3_tx_clk_src",
1598                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1599                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1600                 .ops = &clk_rcg2_ops,
1601         },
1602 };
1603
1604 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1605         .reg = 0x68424,
1606         .shift = 0,
1607         .width = 4,
1608         .clkr = {
1609                 .hw.init = &(struct clk_init_data){
1610                         .name = "nss_port3_tx_div_clk_src",
1611                         .parent_hws = (const struct clk_hw *[]){
1612                                 &nss_port3_tx_clk_src.clkr.hw },
1613                         .num_parents = 1,
1614                         .ops = &clk_regmap_div_ops,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_rcg2 nss_port4_rx_clk_src = {
1621         .cmd_rcgr = 0x68050,
1622         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1623         .hid_width = 5,
1624         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1625         .clkr.hw.init = &(struct clk_init_data){
1626                 .name = "nss_port4_rx_clk_src",
1627                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1628                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1629                 .ops = &clk_rcg2_ops,
1630         },
1631 };
1632
1633 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1634         .reg = 0x68430,
1635         .shift = 0,
1636         .width = 4,
1637         .clkr = {
1638                 .hw.init = &(struct clk_init_data){
1639                         .name = "nss_port4_rx_div_clk_src",
1640                         .parent_hws = (const struct clk_hw *[]){
1641                                 &nss_port4_rx_clk_src.clkr.hw },
1642                         .num_parents = 1,
1643                         .ops = &clk_regmap_div_ops,
1644                         .flags = CLK_SET_RATE_PARENT,
1645                 },
1646         },
1647 };
1648
1649 static struct clk_rcg2 nss_port4_tx_clk_src = {
1650         .cmd_rcgr = 0x68058,
1651         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1652         .hid_width = 5,
1653         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1654         .clkr.hw.init = &(struct clk_init_data){
1655                 .name = "nss_port4_tx_clk_src",
1656                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1657                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1658                 .ops = &clk_rcg2_ops,
1659         },
1660 };
1661
1662 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1663         .reg = 0x68434,
1664         .shift = 0,
1665         .width = 4,
1666         .clkr = {
1667                 .hw.init = &(struct clk_init_data){
1668                         .name = "nss_port4_tx_div_clk_src",
1669                         .parent_hws = (const struct clk_hw *[]){
1670                                 &nss_port4_tx_clk_src.clkr.hw },
1671                         .num_parents = 1,
1672                         .ops = &clk_regmap_div_ops,
1673                         .flags = CLK_SET_RATE_PARENT,
1674                 },
1675         },
1676 };
1677
1678 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1679         F(19200000, P_XO, 1, 0, 0),
1680         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1681         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1682         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1683         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1684         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1685         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1686         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1687         { }
1688 };
1689
1690 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
1691         { .fw_name = "xo", .name = "xo" },
1692         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1693         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1694         { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1695         { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1696         { .hw = &ubi32_pll.clkr.hw },
1697         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1698 };
1699
1700 static const struct parent_map
1701 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
1702         { P_XO, 0 },
1703         { P_UNIPHY0_RX, 1 },
1704         { P_UNIPHY0_TX, 2 },
1705         { P_UNIPHY1_RX, 3 },
1706         { P_UNIPHY1_TX, 4 },
1707         { P_UBI32_PLL, 5 },
1708         { P_BIAS_PLL, 6 },
1709 };
1710
1711 static struct clk_rcg2 nss_port5_rx_clk_src = {
1712         .cmd_rcgr = 0x68060,
1713         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1714         .hid_width = 5,
1715         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1716         .clkr.hw.init = &(struct clk_init_data){
1717                 .name = "nss_port5_rx_clk_src",
1718                 .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1719                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1720                 .ops = &clk_rcg2_ops,
1721         },
1722 };
1723
1724 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1725         .reg = 0x68440,
1726         .shift = 0,
1727         .width = 4,
1728         .clkr = {
1729                 .hw.init = &(struct clk_init_data){
1730                         .name = "nss_port5_rx_div_clk_src",
1731                         .parent_hws = (const struct clk_hw *[]){
1732                                 &nss_port5_rx_clk_src.clkr.hw },
1733                         .num_parents = 1,
1734                         .ops = &clk_regmap_div_ops,
1735                         .flags = CLK_SET_RATE_PARENT,
1736                 },
1737         },
1738 };
1739
1740 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1741         F(19200000, P_XO, 1, 0, 0),
1742         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1743         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1744         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1745         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1746         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1747         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1748         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1749         { }
1750 };
1751
1752 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
1753         { .fw_name = "xo", .name = "xo" },
1754         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1755         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1756         { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1757         { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1758         { .hw = &ubi32_pll.clkr.hw },
1759         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1760 };
1761
1762 static const struct parent_map
1763 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
1764         { P_XO, 0 },
1765         { P_UNIPHY0_TX, 1 },
1766         { P_UNIPHY0_RX, 2 },
1767         { P_UNIPHY1_TX, 3 },
1768         { P_UNIPHY1_RX, 4 },
1769         { P_UBI32_PLL, 5 },
1770         { P_BIAS_PLL, 6 },
1771 };
1772
1773 static struct clk_rcg2 nss_port5_tx_clk_src = {
1774         .cmd_rcgr = 0x68068,
1775         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1776         .hid_width = 5,
1777         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1778         .clkr.hw.init = &(struct clk_init_data){
1779                 .name = "nss_port5_tx_clk_src",
1780                 .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1781                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1782                 .ops = &clk_rcg2_ops,
1783         },
1784 };
1785
1786 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1787         .reg = 0x68444,
1788         .shift = 0,
1789         .width = 4,
1790         .clkr = {
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "nss_port5_tx_div_clk_src",
1793                         .parent_hws = (const struct clk_hw *[]){
1794                                 &nss_port5_tx_clk_src.clkr.hw },
1795                         .num_parents = 1,
1796                         .ops = &clk_regmap_div_ops,
1797                         .flags = CLK_SET_RATE_PARENT,
1798                 },
1799         },
1800 };
1801
1802 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1803         F(19200000, P_XO, 1, 0, 0),
1804         F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1805         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1806         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1807         F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1808         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1809         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1810         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1811         { }
1812 };
1813
1814 static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
1815         { .fw_name = "xo", .name = "xo" },
1816         { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1817         { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1818         { .hw = &ubi32_pll.clkr.hw },
1819         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1820 };
1821
1822 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
1823         { P_XO, 0 },
1824         { P_UNIPHY2_RX, 1 },
1825         { P_UNIPHY2_TX, 2 },
1826         { P_UBI32_PLL, 5 },
1827         { P_BIAS_PLL, 6 },
1828 };
1829
1830 static struct clk_rcg2 nss_port6_rx_clk_src = {
1831         .cmd_rcgr = 0x68070,
1832         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1833         .hid_width = 5,
1834         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1835         .clkr.hw.init = &(struct clk_init_data){
1836                 .name = "nss_port6_rx_clk_src",
1837                 .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1838                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1839                 .ops = &clk_rcg2_ops,
1840         },
1841 };
1842
1843 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1844         .reg = 0x68450,
1845         .shift = 0,
1846         .width = 4,
1847         .clkr = {
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "nss_port6_rx_div_clk_src",
1850                         .parent_hws = (const struct clk_hw *[]){
1851                                 &nss_port6_rx_clk_src.clkr.hw },
1852                         .num_parents = 1,
1853                         .ops = &clk_regmap_div_ops,
1854                         .flags = CLK_SET_RATE_PARENT,
1855                 },
1856         },
1857 };
1858
1859 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1860         F(19200000, P_XO, 1, 0, 0),
1861         F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1862         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1863         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1864         F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1865         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1866         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1867         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1868         { }
1869 };
1870
1871 static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
1872         { .fw_name = "xo", .name = "xo" },
1873         { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1874         { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1875         { .hw = &ubi32_pll.clkr.hw },
1876         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1877 };
1878
1879 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
1880         { P_XO, 0 },
1881         { P_UNIPHY2_TX, 1 },
1882         { P_UNIPHY2_RX, 2 },
1883         { P_UBI32_PLL, 5 },
1884         { P_BIAS_PLL, 6 },
1885 };
1886
1887 static struct clk_rcg2 nss_port6_tx_clk_src = {
1888         .cmd_rcgr = 0x68078,
1889         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1890         .hid_width = 5,
1891         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1892         .clkr.hw.init = &(struct clk_init_data){
1893                 .name = "nss_port6_tx_clk_src",
1894                 .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1895                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1896                 .ops = &clk_rcg2_ops,
1897         },
1898 };
1899
1900 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1901         .reg = 0x68454,
1902         .shift = 0,
1903         .width = 4,
1904         .clkr = {
1905                 .hw.init = &(struct clk_init_data){
1906                         .name = "nss_port6_tx_div_clk_src",
1907                         .parent_hws = (const struct clk_hw *[]){
1908                                 &nss_port6_tx_clk_src.clkr.hw },
1909                         .num_parents = 1,
1910                         .ops = &clk_regmap_div_ops,
1911                         .flags = CLK_SET_RATE_PARENT,
1912                 },
1913         },
1914 };
1915
1916 static struct freq_tbl ftbl_crypto_clk_src[] = {
1917         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1918         F(80000000, P_GPLL0, 10, 0, 0),
1919         F(100000000, P_GPLL0, 8, 0, 0),
1920         F(160000000, P_GPLL0, 5, 0, 0),
1921         { }
1922 };
1923
1924 static struct clk_rcg2 crypto_clk_src = {
1925         .cmd_rcgr = 0x16004,
1926         .freq_tbl = ftbl_crypto_clk_src,
1927         .hid_width = 5,
1928         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1929         .clkr.hw.init = &(struct clk_init_data){
1930                 .name = "crypto_clk_src",
1931                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1932                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1933                 .ops = &clk_rcg2_ops,
1934         },
1935 };
1936
1937 static struct freq_tbl ftbl_gp_clk_src[] = {
1938         F(19200000, P_XO, 1, 0, 0),
1939         { }
1940 };
1941
1942 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1943         { .fw_name = "xo", .name = "xo" },
1944         { .hw = &gpll0.clkr.hw },
1945         { .hw = &gpll6.clkr.hw },
1946         { .hw = &gpll0_out_main_div2.hw },
1947         { .fw_name = "sleep_clk", .name = "sleep_clk" },
1948 };
1949
1950 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1951         { P_XO, 0 },
1952         { P_GPLL0, 1 },
1953         { P_GPLL6, 2 },
1954         { P_GPLL0_DIV2, 4 },
1955         { P_SLEEP_CLK, 6 },
1956 };
1957
1958 static struct clk_rcg2 gp1_clk_src = {
1959         .cmd_rcgr = 0x08004,
1960         .freq_tbl = ftbl_gp_clk_src,
1961         .mnd_width = 8,
1962         .hid_width = 5,
1963         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1964         .clkr.hw.init = &(struct clk_init_data){
1965                 .name = "gp1_clk_src",
1966                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1967                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1968                 .ops = &clk_rcg2_ops,
1969         },
1970 };
1971
1972 static struct clk_rcg2 gp2_clk_src = {
1973         .cmd_rcgr = 0x09004,
1974         .freq_tbl = ftbl_gp_clk_src,
1975         .mnd_width = 8,
1976         .hid_width = 5,
1977         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1978         .clkr.hw.init = &(struct clk_init_data){
1979                 .name = "gp2_clk_src",
1980                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1981                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1982                 .ops = &clk_rcg2_ops,
1983         },
1984 };
1985
1986 static struct clk_rcg2 gp3_clk_src = {
1987         .cmd_rcgr = 0x0a004,
1988         .freq_tbl = ftbl_gp_clk_src,
1989         .mnd_width = 8,
1990         .hid_width = 5,
1991         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1992         .clkr.hw.init = &(struct clk_init_data){
1993                 .name = "gp3_clk_src",
1994                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1995                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1996                 .ops = &clk_rcg2_ops,
1997         },
1998 };
1999
2000 static struct clk_branch gcc_blsp1_ahb_clk = {
2001         .halt_reg = 0x01008,
2002         .clkr = {
2003                 .enable_reg = 0x01008,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "gcc_blsp1_ahb_clk",
2007                         .parent_hws = (const struct clk_hw *[]){
2008                                 &pcnoc_clk_src.hw },
2009                         .num_parents = 1,
2010                         .flags = CLK_SET_RATE_PARENT,
2011                         .ops = &clk_branch2_ops,
2012                 },
2013         },
2014 };
2015
2016 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2017         .halt_reg = 0x02008,
2018         .clkr = {
2019                 .enable_reg = 0x02008,
2020                 .enable_mask = BIT(0),
2021                 .hw.init = &(struct clk_init_data){
2022                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2023                         .parent_hws = (const struct clk_hw *[]){
2024                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
2025                         .num_parents = 1,
2026                         .flags = CLK_SET_RATE_PARENT,
2027                         .ops = &clk_branch2_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2033         .halt_reg = 0x02004,
2034         .clkr = {
2035                 .enable_reg = 0x02004,
2036                 .enable_mask = BIT(0),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2039                         .parent_hws = (const struct clk_hw *[]){
2040                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2049         .halt_reg = 0x03010,
2050         .clkr = {
2051                 .enable_reg = 0x03010,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2055                         .parent_hws = (const struct clk_hw *[]){
2056                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2057                         .num_parents = 1,
2058                         .flags = CLK_SET_RATE_PARENT,
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2065         .halt_reg = 0x0300c,
2066         .clkr = {
2067                 .enable_reg = 0x0300c,
2068                 .enable_mask = BIT(0),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2071                         .parent_hws = (const struct clk_hw *[]){
2072                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw },
2073                         .num_parents = 1,
2074                         .flags = CLK_SET_RATE_PARENT,
2075                         .ops = &clk_branch2_ops,
2076                 },
2077         },
2078 };
2079
2080 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2081         .halt_reg = 0x04010,
2082         .clkr = {
2083                 .enable_reg = 0x04010,
2084                 .enable_mask = BIT(0),
2085                 .hw.init = &(struct clk_init_data){
2086                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2087                         .parent_hws = (const struct clk_hw *[]){
2088                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2089                         .num_parents = 1,
2090                         .flags = CLK_SET_RATE_PARENT,
2091                         .ops = &clk_branch2_ops,
2092                 },
2093         },
2094 };
2095
2096 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2097         .halt_reg = 0x0400c,
2098         .clkr = {
2099                 .enable_reg = 0x0400c,
2100                 .enable_mask = BIT(0),
2101                 .hw.init = &(struct clk_init_data){
2102                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2103                         .parent_hws = (const struct clk_hw *[]){
2104                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw },
2105                         .num_parents = 1,
2106                         .flags = CLK_SET_RATE_PARENT,
2107                         .ops = &clk_branch2_ops,
2108                 },
2109         },
2110 };
2111
2112 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2113         .halt_reg = 0x05010,
2114         .clkr = {
2115                 .enable_reg = 0x05010,
2116                 .enable_mask = BIT(0),
2117                 .hw.init = &(struct clk_init_data){
2118                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2119                         .parent_hws = (const struct clk_hw *[]){
2120                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2129         .halt_reg = 0x0500c,
2130         .clkr = {
2131                 .enable_reg = 0x0500c,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2135                         .parent_hws = (const struct clk_hw *[]){
2136                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw },
2137                         .num_parents = 1,
2138                         .flags = CLK_SET_RATE_PARENT,
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2145         .halt_reg = 0x06010,
2146         .clkr = {
2147                 .enable_reg = 0x06010,
2148                 .enable_mask = BIT(0),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2151                         .parent_hws = (const struct clk_hw *[]){
2152                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2153                         .num_parents = 1,
2154                         .flags = CLK_SET_RATE_PARENT,
2155                         .ops = &clk_branch2_ops,
2156                 },
2157         },
2158 };
2159
2160 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2161         .halt_reg = 0x0600c,
2162         .clkr = {
2163                 .enable_reg = 0x0600c,
2164                 .enable_mask = BIT(0),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2167                         .parent_hws = (const struct clk_hw *[]){
2168                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw },
2169                         .num_parents = 1,
2170                         .flags = CLK_SET_RATE_PARENT,
2171                         .ops = &clk_branch2_ops,
2172                 },
2173         },
2174 };
2175
2176 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2177         .halt_reg = 0x07010,
2178         .clkr = {
2179                 .enable_reg = 0x07010,
2180                 .enable_mask = BIT(0),
2181                 .hw.init = &(struct clk_init_data){
2182                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2183                         .parent_hws = (const struct clk_hw *[]){
2184                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2185                         .num_parents = 1,
2186                         .flags = CLK_SET_RATE_PARENT,
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2193         .halt_reg = 0x0700c,
2194         .clkr = {
2195                 .enable_reg = 0x0700c,
2196                 .enable_mask = BIT(0),
2197                 .hw.init = &(struct clk_init_data){
2198                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2199                         .parent_hws = (const struct clk_hw *[]){
2200                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw },
2201                         .num_parents = 1,
2202                         .flags = CLK_SET_RATE_PARENT,
2203                         .ops = &clk_branch2_ops,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2209         .halt_reg = 0x0203c,
2210         .clkr = {
2211                 .enable_reg = 0x0203c,
2212                 .enable_mask = BIT(0),
2213                 .hw.init = &(struct clk_init_data){
2214                         .name = "gcc_blsp1_uart1_apps_clk",
2215                         .parent_hws = (const struct clk_hw *[]){
2216                                 &blsp1_uart1_apps_clk_src.clkr.hw },
2217                         .num_parents = 1,
2218                         .flags = CLK_SET_RATE_PARENT,
2219                         .ops = &clk_branch2_ops,
2220                 },
2221         },
2222 };
2223
2224 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2225         .halt_reg = 0x0302c,
2226         .clkr = {
2227                 .enable_reg = 0x0302c,
2228                 .enable_mask = BIT(0),
2229                 .hw.init = &(struct clk_init_data){
2230                         .name = "gcc_blsp1_uart2_apps_clk",
2231                         .parent_hws = (const struct clk_hw *[]){
2232                                 &blsp1_uart2_apps_clk_src.clkr.hw },
2233                         .num_parents = 1,
2234                         .flags = CLK_SET_RATE_PARENT,
2235                         .ops = &clk_branch2_ops,
2236                 },
2237         },
2238 };
2239
2240 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2241         .halt_reg = 0x0402c,
2242         .clkr = {
2243                 .enable_reg = 0x0402c,
2244                 .enable_mask = BIT(0),
2245                 .hw.init = &(struct clk_init_data){
2246                         .name = "gcc_blsp1_uart3_apps_clk",
2247                         .parent_hws = (const struct clk_hw *[]){
2248                                 &blsp1_uart3_apps_clk_src.clkr.hw },
2249                         .num_parents = 1,
2250                         .flags = CLK_SET_RATE_PARENT,
2251                         .ops = &clk_branch2_ops,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2257         .halt_reg = 0x0502c,
2258         .clkr = {
2259                 .enable_reg = 0x0502c,
2260                 .enable_mask = BIT(0),
2261                 .hw.init = &(struct clk_init_data){
2262                         .name = "gcc_blsp1_uart4_apps_clk",
2263                         .parent_hws = (const struct clk_hw *[]){
2264                                 &blsp1_uart4_apps_clk_src.clkr.hw },
2265                         .num_parents = 1,
2266                         .flags = CLK_SET_RATE_PARENT,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2273         .halt_reg = 0x0602c,
2274         .clkr = {
2275                 .enable_reg = 0x0602c,
2276                 .enable_mask = BIT(0),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "gcc_blsp1_uart5_apps_clk",
2279                         .parent_hws = (const struct clk_hw *[]){
2280                                 &blsp1_uart5_apps_clk_src.clkr.hw },
2281                         .num_parents = 1,
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2289         .halt_reg = 0x0702c,
2290         .clkr = {
2291                 .enable_reg = 0x0702c,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_blsp1_uart6_apps_clk",
2295                         .parent_hws = (const struct clk_hw *[]){
2296                                 &blsp1_uart6_apps_clk_src.clkr.hw },
2297                         .num_parents = 1,
2298                         .flags = CLK_SET_RATE_PARENT,
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_prng_ahb_clk = {
2305         .halt_reg = 0x13004,
2306         .halt_check = BRANCH_HALT_VOTED,
2307         .clkr = {
2308                 .enable_reg = 0x0b004,
2309                 .enable_mask = BIT(8),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_prng_ahb_clk",
2312                         .parent_hws = (const struct clk_hw *[]){
2313                                 &pcnoc_clk_src.hw },
2314                         .num_parents = 1,
2315                         .flags = CLK_SET_RATE_PARENT,
2316                         .ops = &clk_branch2_ops,
2317                 },
2318         },
2319 };
2320
2321 static struct clk_branch gcc_qpic_ahb_clk = {
2322         .halt_reg = 0x57024,
2323         .clkr = {
2324                 .enable_reg = 0x57024,
2325                 .enable_mask = BIT(0),
2326                 .hw.init = &(struct clk_init_data){
2327                         .name = "gcc_qpic_ahb_clk",
2328                         .parent_hws = (const struct clk_hw *[]){
2329                                 &pcnoc_clk_src.hw },
2330                         .num_parents = 1,
2331                         .flags = CLK_SET_RATE_PARENT,
2332                         .ops = &clk_branch2_ops,
2333                 },
2334         },
2335 };
2336
2337 static struct clk_branch gcc_qpic_clk = {
2338         .halt_reg = 0x57020,
2339         .clkr = {
2340                 .enable_reg = 0x57020,
2341                 .enable_mask = BIT(0),
2342                 .hw.init = &(struct clk_init_data){
2343                         .name = "gcc_qpic_clk",
2344                         .parent_hws = (const struct clk_hw *[]){
2345                                 &pcnoc_clk_src.hw },
2346                         .num_parents = 1,
2347                         .flags = CLK_SET_RATE_PARENT,
2348                         .ops = &clk_branch2_ops,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch gcc_pcie0_ahb_clk = {
2354         .halt_reg = 0x75010,
2355         .clkr = {
2356                 .enable_reg = 0x75010,
2357                 .enable_mask = BIT(0),
2358                 .hw.init = &(struct clk_init_data){
2359                         .name = "gcc_pcie0_ahb_clk",
2360                         .parent_hws = (const struct clk_hw *[]){
2361                                 &pcnoc_clk_src.hw },
2362                         .num_parents = 1,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_pcie0_aux_clk = {
2370         .halt_reg = 0x75014,
2371         .clkr = {
2372                 .enable_reg = 0x75014,
2373                 .enable_mask = BIT(0),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gcc_pcie0_aux_clk",
2376                         .parent_hws = (const struct clk_hw *[]){
2377                                 &pcie0_aux_clk_src.clkr.hw },
2378                         .num_parents = 1,
2379                         .flags = CLK_SET_RATE_PARENT,
2380                         .ops = &clk_branch2_ops,
2381                 },
2382         },
2383 };
2384
2385 static struct clk_branch gcc_pcie0_axi_m_clk = {
2386         .halt_reg = 0x75008,
2387         .clkr = {
2388                 .enable_reg = 0x75008,
2389                 .enable_mask = BIT(0),
2390                 .hw.init = &(struct clk_init_data){
2391                         .name = "gcc_pcie0_axi_m_clk",
2392                         .parent_hws = (const struct clk_hw *[]){
2393                                 &pcie0_axi_clk_src.clkr.hw },
2394                         .num_parents = 1,
2395                         .flags = CLK_SET_RATE_PARENT,
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_pcie0_axi_s_clk = {
2402         .halt_reg = 0x7500c,
2403         .clkr = {
2404                 .enable_reg = 0x7500c,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_pcie0_axi_s_clk",
2408                         .parent_hws = (const struct clk_hw *[]){
2409                                 &pcie0_axi_clk_src.clkr.hw },
2410                         .num_parents = 1,
2411                         .flags = CLK_SET_RATE_PARENT,
2412                         .ops = &clk_branch2_ops,
2413                 },
2414         },
2415 };
2416
2417 static struct clk_branch gcc_pcie0_pipe_clk = {
2418         .halt_reg = 0x75018,
2419         .halt_check = BRANCH_HALT_DELAY,
2420         .clkr = {
2421                 .enable_reg = 0x75018,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(struct clk_init_data){
2424                         .name = "gcc_pcie0_pipe_clk",
2425                         .parent_hws = (const struct clk_hw *[]){
2426                                 &pcie0_pipe_clk_src.clkr.hw },
2427                         .num_parents = 1,
2428                         .flags = CLK_SET_RATE_PARENT,
2429                         .ops = &clk_branch2_ops,
2430                 },
2431         },
2432 };
2433
2434 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2435         .halt_reg = 0x26048,
2436         .clkr = {
2437                 .enable_reg = 0x26048,
2438                 .enable_mask = BIT(0),
2439                 .hw.init = &(struct clk_init_data){
2440                         .name = "gcc_sys_noc_pcie0_axi_clk",
2441                         .parent_hws = (const struct clk_hw *[]){
2442                                 &pcie0_axi_clk_src.clkr.hw },
2443                         .num_parents = 1,
2444                         .flags = CLK_SET_RATE_PARENT,
2445                         .ops = &clk_branch2_ops,
2446                 },
2447         },
2448 };
2449
2450 static struct clk_branch gcc_pcie1_ahb_clk = {
2451         .halt_reg = 0x76010,
2452         .clkr = {
2453                 .enable_reg = 0x76010,
2454                 .enable_mask = BIT(0),
2455                 .hw.init = &(struct clk_init_data){
2456                         .name = "gcc_pcie1_ahb_clk",
2457                         .parent_hws = (const struct clk_hw *[]){
2458                                 &pcnoc_clk_src.hw },
2459                         .num_parents = 1,
2460                         .flags = CLK_SET_RATE_PARENT,
2461                         .ops = &clk_branch2_ops,
2462                 },
2463         },
2464 };
2465
2466 static struct clk_branch gcc_pcie1_aux_clk = {
2467         .halt_reg = 0x76014,
2468         .clkr = {
2469                 .enable_reg = 0x76014,
2470                 .enable_mask = BIT(0),
2471                 .hw.init = &(struct clk_init_data){
2472                         .name = "gcc_pcie1_aux_clk",
2473                         .parent_hws = (const struct clk_hw *[]){
2474                                 &pcie1_aux_clk_src.clkr.hw },
2475                         .num_parents = 1,
2476                         .flags = CLK_SET_RATE_PARENT,
2477                         .ops = &clk_branch2_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch gcc_pcie1_axi_m_clk = {
2483         .halt_reg = 0x76008,
2484         .clkr = {
2485                 .enable_reg = 0x76008,
2486                 .enable_mask = BIT(0),
2487                 .hw.init = &(struct clk_init_data){
2488                         .name = "gcc_pcie1_axi_m_clk",
2489                         .parent_hws = (const struct clk_hw *[]){
2490                                 &pcie1_axi_clk_src.clkr.hw },
2491                         .num_parents = 1,
2492                         .flags = CLK_SET_RATE_PARENT,
2493                         .ops = &clk_branch2_ops,
2494                 },
2495         },
2496 };
2497
2498 static struct clk_branch gcc_pcie1_axi_s_clk = {
2499         .halt_reg = 0x7600c,
2500         .clkr = {
2501                 .enable_reg = 0x7600c,
2502                 .enable_mask = BIT(0),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gcc_pcie1_axi_s_clk",
2505                         .parent_hws = (const struct clk_hw *[]){
2506                                 &pcie1_axi_clk_src.clkr.hw },
2507                         .num_parents = 1,
2508                         .flags = CLK_SET_RATE_PARENT,
2509                         .ops = &clk_branch2_ops,
2510                 },
2511         },
2512 };
2513
2514 static struct clk_branch gcc_pcie1_pipe_clk = {
2515         .halt_reg = 0x76018,
2516         .halt_check = BRANCH_HALT_DELAY,
2517         .clkr = {
2518                 .enable_reg = 0x76018,
2519                 .enable_mask = BIT(0),
2520                 .hw.init = &(struct clk_init_data){
2521                         .name = "gcc_pcie1_pipe_clk",
2522                         .parent_hws = (const struct clk_hw *[]){
2523                                 &pcie1_pipe_clk_src.clkr.hw },
2524                         .num_parents = 1,
2525                         .flags = CLK_SET_RATE_PARENT,
2526                         .ops = &clk_branch2_ops,
2527                 },
2528         },
2529 };
2530
2531 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2532         .halt_reg = 0x2604c,
2533         .clkr = {
2534                 .enable_reg = 0x2604c,
2535                 .enable_mask = BIT(0),
2536                 .hw.init = &(struct clk_init_data){
2537                         .name = "gcc_sys_noc_pcie1_axi_clk",
2538                         .parent_hws = (const struct clk_hw *[]){
2539                                 &pcie1_axi_clk_src.clkr.hw },
2540                         .num_parents = 1,
2541                         .flags = CLK_SET_RATE_PARENT,
2542                         .ops = &clk_branch2_ops,
2543                 },
2544         },
2545 };
2546
2547 static struct clk_branch gcc_usb0_aux_clk = {
2548         .halt_reg = 0x3e044,
2549         .clkr = {
2550                 .enable_reg = 0x3e044,
2551                 .enable_mask = BIT(0),
2552                 .hw.init = &(struct clk_init_data){
2553                         .name = "gcc_usb0_aux_clk",
2554                         .parent_hws = (const struct clk_hw *[]){
2555                                 &usb0_aux_clk_src.clkr.hw },
2556                         .num_parents = 1,
2557                         .flags = CLK_SET_RATE_PARENT,
2558                         .ops = &clk_branch2_ops,
2559                 },
2560         },
2561 };
2562
2563 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2564         .halt_reg = 0x26040,
2565         .clkr = {
2566                 .enable_reg = 0x26040,
2567                 .enable_mask = BIT(0),
2568                 .hw.init = &(struct clk_init_data){
2569                         .name = "gcc_sys_noc_usb0_axi_clk",
2570                         .parent_hws = (const struct clk_hw *[]){
2571                                 &usb0_master_clk_src.clkr.hw },
2572                         .num_parents = 1,
2573                         .flags = CLK_SET_RATE_PARENT,
2574                         .ops = &clk_branch2_ops,
2575                 },
2576         },
2577 };
2578
2579 static struct clk_branch gcc_usb0_master_clk = {
2580         .halt_reg = 0x3e000,
2581         .clkr = {
2582                 .enable_reg = 0x3e000,
2583                 .enable_mask = BIT(0),
2584                 .hw.init = &(struct clk_init_data){
2585                         .name = "gcc_usb0_master_clk",
2586                         .parent_hws = (const struct clk_hw *[]){
2587                                 &usb0_master_clk_src.clkr.hw },
2588                         .num_parents = 1,
2589                         .flags = CLK_SET_RATE_PARENT,
2590                         .ops = &clk_branch2_ops,
2591                 },
2592         },
2593 };
2594
2595 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2596         .halt_reg = 0x3e008,
2597         .clkr = {
2598                 .enable_reg = 0x3e008,
2599                 .enable_mask = BIT(0),
2600                 .hw.init = &(struct clk_init_data){
2601                         .name = "gcc_usb0_mock_utmi_clk",
2602                         .parent_hws = (const struct clk_hw *[]){
2603                                 &usb0_mock_utmi_clk_src.clkr.hw },
2604                         .num_parents = 1,
2605                         .flags = CLK_SET_RATE_PARENT,
2606                         .ops = &clk_branch2_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2612         .halt_reg = 0x3e080,
2613         .clkr = {
2614                 .enable_reg = 0x3e080,
2615                 .enable_mask = BIT(0),
2616                 .hw.init = &(struct clk_init_data){
2617                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2618                         .parent_hws = (const struct clk_hw *[]){
2619                                 &pcnoc_clk_src.hw },
2620                         .num_parents = 1,
2621                         .flags = CLK_SET_RATE_PARENT,
2622                         .ops = &clk_branch2_ops,
2623                 },
2624         },
2625 };
2626
2627 static struct clk_branch gcc_usb0_pipe_clk = {
2628         .halt_reg = 0x3e040,
2629         .halt_check = BRANCH_HALT_DELAY,
2630         .clkr = {
2631                 .enable_reg = 0x3e040,
2632                 .enable_mask = BIT(0),
2633                 .hw.init = &(struct clk_init_data){
2634                         .name = "gcc_usb0_pipe_clk",
2635                         .parent_hws = (const struct clk_hw *[]){
2636                                 &usb0_pipe_clk_src.clkr.hw },
2637                         .num_parents = 1,
2638                         .flags = CLK_SET_RATE_PARENT,
2639                         .ops = &clk_branch2_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch gcc_usb0_sleep_clk = {
2645         .halt_reg = 0x3e004,
2646         .clkr = {
2647                 .enable_reg = 0x3e004,
2648                 .enable_mask = BIT(0),
2649                 .hw.init = &(struct clk_init_data){
2650                         .name = "gcc_usb0_sleep_clk",
2651                         .parent_hws = (const struct clk_hw *[]){
2652                                 &gcc_sleep_clk_src.clkr.hw },
2653                         .num_parents = 1,
2654                         .flags = CLK_SET_RATE_PARENT,
2655                         .ops = &clk_branch2_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch gcc_usb1_aux_clk = {
2661         .halt_reg = 0x3f044,
2662         .clkr = {
2663                 .enable_reg = 0x3f044,
2664                 .enable_mask = BIT(0),
2665                 .hw.init = &(struct clk_init_data){
2666                         .name = "gcc_usb1_aux_clk",
2667                         .parent_hws = (const struct clk_hw *[]){
2668                                 &usb1_aux_clk_src.clkr.hw },
2669                         .num_parents = 1,
2670                         .flags = CLK_SET_RATE_PARENT,
2671                         .ops = &clk_branch2_ops,
2672                 },
2673         },
2674 };
2675
2676 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2677         .halt_reg = 0x26044,
2678         .clkr = {
2679                 .enable_reg = 0x26044,
2680                 .enable_mask = BIT(0),
2681                 .hw.init = &(struct clk_init_data){
2682                         .name = "gcc_sys_noc_usb1_axi_clk",
2683                         .parent_hws = (const struct clk_hw *[]){
2684                                 &usb1_master_clk_src.clkr.hw },
2685                         .num_parents = 1,
2686                         .flags = CLK_SET_RATE_PARENT,
2687                         .ops = &clk_branch2_ops,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch gcc_usb1_master_clk = {
2693         .halt_reg = 0x3f000,
2694         .clkr = {
2695                 .enable_reg = 0x3f000,
2696                 .enable_mask = BIT(0),
2697                 .hw.init = &(struct clk_init_data){
2698                         .name = "gcc_usb1_master_clk",
2699                         .parent_hws = (const struct clk_hw *[]){
2700                                 &usb1_master_clk_src.clkr.hw },
2701                         .num_parents = 1,
2702                         .flags = CLK_SET_RATE_PARENT,
2703                         .ops = &clk_branch2_ops,
2704                 },
2705         },
2706 };
2707
2708 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2709         .halt_reg = 0x3f008,
2710         .clkr = {
2711                 .enable_reg = 0x3f008,
2712                 .enable_mask = BIT(0),
2713                 .hw.init = &(struct clk_init_data){
2714                         .name = "gcc_usb1_mock_utmi_clk",
2715                         .parent_hws = (const struct clk_hw *[]){
2716                                 &usb1_mock_utmi_clk_src.clkr.hw },
2717                         .num_parents = 1,
2718                         .flags = CLK_SET_RATE_PARENT,
2719                         .ops = &clk_branch2_ops,
2720                 },
2721         },
2722 };
2723
2724 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2725         .halt_reg = 0x3f080,
2726         .clkr = {
2727                 .enable_reg = 0x3f080,
2728                 .enable_mask = BIT(0),
2729                 .hw.init = &(struct clk_init_data){
2730                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2731                         .parent_hws = (const struct clk_hw *[]){
2732                                 &pcnoc_clk_src.hw },
2733                         .num_parents = 1,
2734                         .flags = CLK_SET_RATE_PARENT,
2735                         .ops = &clk_branch2_ops,
2736                 },
2737         },
2738 };
2739
2740 static struct clk_branch gcc_usb1_pipe_clk = {
2741         .halt_reg = 0x3f040,
2742         .halt_check = BRANCH_HALT_DELAY,
2743         .clkr = {
2744                 .enable_reg = 0x3f040,
2745                 .enable_mask = BIT(0),
2746                 .hw.init = &(struct clk_init_data){
2747                         .name = "gcc_usb1_pipe_clk",
2748                         .parent_hws = (const struct clk_hw *[]){
2749                                 &usb1_pipe_clk_src.clkr.hw },
2750                         .num_parents = 1,
2751                         .flags = CLK_SET_RATE_PARENT,
2752                         .ops = &clk_branch2_ops,
2753                 },
2754         },
2755 };
2756
2757 static struct clk_branch gcc_usb1_sleep_clk = {
2758         .halt_reg = 0x3f004,
2759         .clkr = {
2760                 .enable_reg = 0x3f004,
2761                 .enable_mask = BIT(0),
2762                 .hw.init = &(struct clk_init_data){
2763                         .name = "gcc_usb1_sleep_clk",
2764                         .parent_hws = (const struct clk_hw *[]){
2765                                 &gcc_sleep_clk_src.clkr.hw },
2766                         .num_parents = 1,
2767                         .flags = CLK_SET_RATE_PARENT,
2768                         .ops = &clk_branch2_ops,
2769                 },
2770         },
2771 };
2772
2773 static struct clk_branch gcc_sdcc1_ahb_clk = {
2774         .halt_reg = 0x4201c,
2775         .clkr = {
2776                 .enable_reg = 0x4201c,
2777                 .enable_mask = BIT(0),
2778                 .hw.init = &(struct clk_init_data){
2779                         .name = "gcc_sdcc1_ahb_clk",
2780                         .parent_hws = (const struct clk_hw *[]){
2781                                 &pcnoc_clk_src.hw },
2782                         .num_parents = 1,
2783                         .flags = CLK_SET_RATE_PARENT,
2784                         .ops = &clk_branch2_ops,
2785                 },
2786         },
2787 };
2788
2789 static struct clk_branch gcc_sdcc1_apps_clk = {
2790         .halt_reg = 0x42018,
2791         .clkr = {
2792                 .enable_reg = 0x42018,
2793                 .enable_mask = BIT(0),
2794                 .hw.init = &(struct clk_init_data){
2795                         .name = "gcc_sdcc1_apps_clk",
2796                         .parent_hws = (const struct clk_hw *[]){
2797                                 &sdcc1_apps_clk_src.clkr.hw },
2798                         .num_parents = 1,
2799                         .flags = CLK_SET_RATE_PARENT,
2800                         .ops = &clk_branch2_ops,
2801                 },
2802         },
2803 };
2804
2805 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2806         .halt_reg = 0x5d014,
2807         .clkr = {
2808                 .enable_reg = 0x5d014,
2809                 .enable_mask = BIT(0),
2810                 .hw.init = &(struct clk_init_data){
2811                         .name = "gcc_sdcc1_ice_core_clk",
2812                         .parent_hws = (const struct clk_hw *[]){
2813                                 &sdcc1_ice_core_clk_src.clkr.hw },
2814                         .num_parents = 1,
2815                         .flags = CLK_SET_RATE_PARENT,
2816                         .ops = &clk_branch2_ops,
2817                 },
2818         },
2819 };
2820
2821 static struct clk_branch gcc_sdcc2_ahb_clk = {
2822         .halt_reg = 0x4301c,
2823         .clkr = {
2824                 .enable_reg = 0x4301c,
2825                 .enable_mask = BIT(0),
2826                 .hw.init = &(struct clk_init_data){
2827                         .name = "gcc_sdcc2_ahb_clk",
2828                         .parent_hws = (const struct clk_hw *[]){
2829                                 &pcnoc_clk_src.hw },
2830                         .num_parents = 1,
2831                         .flags = CLK_SET_RATE_PARENT,
2832                         .ops = &clk_branch2_ops,
2833                 },
2834         },
2835 };
2836
2837 static struct clk_branch gcc_sdcc2_apps_clk = {
2838         .halt_reg = 0x43018,
2839         .clkr = {
2840                 .enable_reg = 0x43018,
2841                 .enable_mask = BIT(0),
2842                 .hw.init = &(struct clk_init_data){
2843                         .name = "gcc_sdcc2_apps_clk",
2844                         .parent_hws = (const struct clk_hw *[]){
2845                                 &sdcc2_apps_clk_src.clkr.hw },
2846                         .num_parents = 1,
2847                         .flags = CLK_SET_RATE_PARENT,
2848                         .ops = &clk_branch2_ops,
2849                 },
2850         },
2851 };
2852
2853 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2854         .halt_reg = 0x1d03c,
2855         .clkr = {
2856                 .enable_reg = 0x1d03c,
2857                 .enable_mask = BIT(0),
2858                 .hw.init = &(struct clk_init_data){
2859                         .name = "gcc_mem_noc_nss_axi_clk",
2860                         .parent_hws = (const struct clk_hw *[]){
2861                                 &nss_noc_clk_src.hw },
2862                         .num_parents = 1,
2863                         .flags = CLK_SET_RATE_PARENT,
2864                         .ops = &clk_branch2_ops,
2865                 },
2866         },
2867 };
2868
2869 static struct clk_branch gcc_nss_ce_apb_clk = {
2870         .halt_reg = 0x68174,
2871         .clkr = {
2872                 .enable_reg = 0x68174,
2873                 .enable_mask = BIT(0),
2874                 .hw.init = &(struct clk_init_data){
2875                         .name = "gcc_nss_ce_apb_clk",
2876                         .parent_hws = (const struct clk_hw *[]){
2877                                 &nss_ce_clk_src.clkr.hw },
2878                         .num_parents = 1,
2879                         .flags = CLK_SET_RATE_PARENT,
2880                         .ops = &clk_branch2_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch gcc_nss_ce_axi_clk = {
2886         .halt_reg = 0x68170,
2887         .clkr = {
2888                 .enable_reg = 0x68170,
2889                 .enable_mask = BIT(0),
2890                 .hw.init = &(struct clk_init_data){
2891                         .name = "gcc_nss_ce_axi_clk",
2892                         .parent_hws = (const struct clk_hw *[]){
2893                                 &nss_ce_clk_src.clkr.hw },
2894                         .num_parents = 1,
2895                         .flags = CLK_SET_RATE_PARENT,
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch gcc_nss_cfg_clk = {
2902         .halt_reg = 0x68160,
2903         .clkr = {
2904                 .enable_reg = 0x68160,
2905                 .enable_mask = BIT(0),
2906                 .hw.init = &(struct clk_init_data){
2907                         .name = "gcc_nss_cfg_clk",
2908                         .parent_hws = (const struct clk_hw *[]){
2909                                 &pcnoc_clk_src.hw },
2910                         .num_parents = 1,
2911                         .flags = CLK_SET_RATE_PARENT,
2912                         .ops = &clk_branch2_ops,
2913                 },
2914         },
2915 };
2916
2917 static struct clk_branch gcc_nss_crypto_clk = {
2918         .halt_reg = 0x68164,
2919         .clkr = {
2920                 .enable_reg = 0x68164,
2921                 .enable_mask = BIT(0),
2922                 .hw.init = &(struct clk_init_data){
2923                         .name = "gcc_nss_crypto_clk",
2924                         .parent_hws = (const struct clk_hw *[]){
2925                                 &nss_crypto_clk_src.clkr.hw },
2926                         .num_parents = 1,
2927                         .flags = CLK_SET_RATE_PARENT,
2928                         .ops = &clk_branch2_ops,
2929                 },
2930         },
2931 };
2932
2933 static struct clk_branch gcc_nss_csr_clk = {
2934         .halt_reg = 0x68318,
2935         .clkr = {
2936                 .enable_reg = 0x68318,
2937                 .enable_mask = BIT(0),
2938                 .hw.init = &(struct clk_init_data){
2939                         .name = "gcc_nss_csr_clk",
2940                         .parent_hws = (const struct clk_hw *[]){
2941                                 &nss_ce_clk_src.clkr.hw },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_nss_edma_cfg_clk = {
2950         .halt_reg = 0x6819c,
2951         .clkr = {
2952                 .enable_reg = 0x6819c,
2953                 .enable_mask = BIT(0),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "gcc_nss_edma_cfg_clk",
2956                         .parent_hws = (const struct clk_hw *[]){
2957                                 &nss_ppe_clk_src.clkr.hw },
2958                         .num_parents = 1,
2959                         .flags = CLK_SET_RATE_PARENT,
2960                         .ops = &clk_branch2_ops,
2961                 },
2962         },
2963 };
2964
2965 static struct clk_branch gcc_nss_edma_clk = {
2966         .halt_reg = 0x68198,
2967         .clkr = {
2968                 .enable_reg = 0x68198,
2969                 .enable_mask = BIT(0),
2970                 .hw.init = &(struct clk_init_data){
2971                         .name = "gcc_nss_edma_clk",
2972                         .parent_hws = (const struct clk_hw *[]){
2973                                 &nss_ppe_clk_src.clkr.hw },
2974                         .num_parents = 1,
2975                         .flags = CLK_SET_RATE_PARENT,
2976                         .ops = &clk_branch2_ops,
2977                 },
2978         },
2979 };
2980
2981 static struct clk_branch gcc_nss_imem_clk = {
2982         .halt_reg = 0x68178,
2983         .clkr = {
2984                 .enable_reg = 0x68178,
2985                 .enable_mask = BIT(0),
2986                 .hw.init = &(struct clk_init_data){
2987                         .name = "gcc_nss_imem_clk",
2988                         .parent_hws = (const struct clk_hw *[]){
2989                                 &nss_imem_clk_src.clkr.hw },
2990                         .num_parents = 1,
2991                         .flags = CLK_SET_RATE_PARENT,
2992                         .ops = &clk_branch2_ops,
2993                 },
2994         },
2995 };
2996
2997 static struct clk_branch gcc_nss_noc_clk = {
2998         .halt_reg = 0x68168,
2999         .clkr = {
3000                 .enable_reg = 0x68168,
3001                 .enable_mask = BIT(0),
3002                 .hw.init = &(struct clk_init_data){
3003                         .name = "gcc_nss_noc_clk",
3004                         .parent_hws = (const struct clk_hw *[]){
3005                                 &nss_noc_clk_src.hw },
3006                         .num_parents = 1,
3007                         .flags = CLK_SET_RATE_PARENT,
3008                         .ops = &clk_branch2_ops,
3009                 },
3010         },
3011 };
3012
3013 static struct clk_branch gcc_nss_ppe_btq_clk = {
3014         .halt_reg = 0x6833c,
3015         .clkr = {
3016                 .enable_reg = 0x6833c,
3017                 .enable_mask = BIT(0),
3018                 .hw.init = &(struct clk_init_data){
3019                         .name = "gcc_nss_ppe_btq_clk",
3020                         .parent_hws = (const struct clk_hw *[]){
3021                                 &nss_ppe_clk_src.clkr.hw },
3022                         .num_parents = 1,
3023                         .flags = CLK_SET_RATE_PARENT,
3024                         .ops = &clk_branch2_ops,
3025                 },
3026         },
3027 };
3028
3029 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3030         .halt_reg = 0x68194,
3031         .clkr = {
3032                 .enable_reg = 0x68194,
3033                 .enable_mask = BIT(0),
3034                 .hw.init = &(struct clk_init_data){
3035                         .name = "gcc_nss_ppe_cfg_clk",
3036                         .parent_hws = (const struct clk_hw *[]){
3037                                 &nss_ppe_clk_src.clkr.hw },
3038                         .num_parents = 1,
3039                         .flags = CLK_SET_RATE_PARENT,
3040                         .ops = &clk_branch2_ops,
3041                 },
3042         },
3043 };
3044
3045 static struct clk_branch gcc_nss_ppe_clk = {
3046         .halt_reg = 0x68190,
3047         .clkr = {
3048                 .enable_reg = 0x68190,
3049                 .enable_mask = BIT(0),
3050                 .hw.init = &(struct clk_init_data){
3051                         .name = "gcc_nss_ppe_clk",
3052                         .parent_hws = (const struct clk_hw *[]){
3053                                 &nss_ppe_clk_src.clkr.hw },
3054                         .num_parents = 1,
3055                         .flags = CLK_SET_RATE_PARENT,
3056                         .ops = &clk_branch2_ops,
3057                 },
3058         },
3059 };
3060
3061 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3062         .halt_reg = 0x68338,
3063         .clkr = {
3064                 .enable_reg = 0x68338,
3065                 .enable_mask = BIT(0),
3066                 .hw.init = &(struct clk_init_data){
3067                         .name = "gcc_nss_ppe_ipe_clk",
3068                         .parent_hws = (const struct clk_hw *[]){
3069                                 &nss_ppe_clk_src.clkr.hw },
3070                         .num_parents = 1,
3071                         .flags = CLK_SET_RATE_PARENT,
3072                         .ops = &clk_branch2_ops,
3073                 },
3074         },
3075 };
3076
3077 static struct clk_branch gcc_nss_ptp_ref_clk = {
3078         .halt_reg = 0x6816c,
3079         .clkr = {
3080                 .enable_reg = 0x6816c,
3081                 .enable_mask = BIT(0),
3082                 .hw.init = &(struct clk_init_data){
3083                         .name = "gcc_nss_ptp_ref_clk",
3084                         .parent_hws = (const struct clk_hw *[]){
3085                                 &nss_ppe_cdiv_clk_src.hw },
3086                         .num_parents = 1,
3087                         .flags = CLK_SET_RATE_PARENT,
3088                         .ops = &clk_branch2_ops,
3089                 },
3090         },
3091 };
3092
3093 static struct clk_branch gcc_crypto_ppe_clk = {
3094         .halt_reg = 0x68310,
3095         .halt_bit = 31,
3096         .clkr = {
3097                 .enable_reg = 0x68310,
3098                 .enable_mask = BIT(0),
3099                 .hw.init = &(struct clk_init_data){
3100                         .name = "gcc_crypto_ppe_clk",
3101                         .parent_hws = (const struct clk_hw *[]){
3102                                 &nss_ppe_clk_src.clkr.hw },
3103                         .num_parents = 1,
3104                         .flags = CLK_SET_RATE_PARENT,
3105                         .ops = &clk_branch2_ops,
3106                 },
3107         },
3108 };
3109
3110 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3111         .halt_reg = 0x6830c,
3112         .clkr = {
3113                 .enable_reg = 0x6830c,
3114                 .enable_mask = BIT(0),
3115                 .hw.init = &(struct clk_init_data){
3116                         .name = "gcc_nssnoc_ce_apb_clk",
3117                         .parent_hws = (const struct clk_hw *[]){
3118                                 &nss_ce_clk_src.clkr.hw },
3119                         .num_parents = 1,
3120                         .flags = CLK_SET_RATE_PARENT,
3121                         .ops = &clk_branch2_ops,
3122                 },
3123         },
3124 };
3125
3126 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3127         .halt_reg = 0x68308,
3128         .clkr = {
3129                 .enable_reg = 0x68308,
3130                 .enable_mask = BIT(0),
3131                 .hw.init = &(struct clk_init_data){
3132                         .name = "gcc_nssnoc_ce_axi_clk",
3133                         .parent_hws = (const struct clk_hw *[]){
3134                                 &nss_ce_clk_src.clkr.hw },
3135                         .num_parents = 1,
3136                         .flags = CLK_SET_RATE_PARENT,
3137                         .ops = &clk_branch2_ops,
3138                 },
3139         },
3140 };
3141
3142 static struct clk_branch gcc_nssnoc_crypto_clk = {
3143         .halt_reg = 0x68314,
3144         .clkr = {
3145                 .enable_reg = 0x68314,
3146                 .enable_mask = BIT(0),
3147                 .hw.init = &(struct clk_init_data){
3148                         .name = "gcc_nssnoc_crypto_clk",
3149                         .parent_hws = (const struct clk_hw *[]){
3150                                 &nss_crypto_clk_src.clkr.hw },
3151                         .num_parents = 1,
3152                         .flags = CLK_SET_RATE_PARENT,
3153                         .ops = &clk_branch2_ops,
3154                 },
3155         },
3156 };
3157
3158 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3159         .halt_reg = 0x68304,
3160         .clkr = {
3161                 .enable_reg = 0x68304,
3162                 .enable_mask = BIT(0),
3163                 .hw.init = &(struct clk_init_data){
3164                         .name = "gcc_nssnoc_ppe_cfg_clk",
3165                         .parent_hws = (const struct clk_hw *[]){
3166                                 &nss_ppe_clk_src.clkr.hw },
3167                         .num_parents = 1,
3168                         .flags = CLK_SET_RATE_PARENT,
3169                         .ops = &clk_branch2_ops,
3170                 },
3171         },
3172 };
3173
3174 static struct clk_branch gcc_nssnoc_ppe_clk = {
3175         .halt_reg = 0x68300,
3176         .clkr = {
3177                 .enable_reg = 0x68300,
3178                 .enable_mask = BIT(0),
3179                 .hw.init = &(struct clk_init_data){
3180                         .name = "gcc_nssnoc_ppe_clk",
3181                         .parent_hws = (const struct clk_hw *[]){
3182                                 &nss_ppe_clk_src.clkr.hw },
3183                         .num_parents = 1,
3184                         .flags = CLK_SET_RATE_PARENT,
3185                         .ops = &clk_branch2_ops,
3186                 },
3187         },
3188 };
3189
3190 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3191         .halt_reg = 0x68180,
3192         .clkr = {
3193                 .enable_reg = 0x68180,
3194                 .enable_mask = BIT(0),
3195                 .hw.init = &(struct clk_init_data){
3196                         .name = "gcc_nssnoc_qosgen_ref_clk",
3197                         .parent_hws = (const struct clk_hw *[]){
3198                                 &gcc_xo_clk_src.clkr.hw },
3199                         .num_parents = 1,
3200                         .flags = CLK_SET_RATE_PARENT,
3201                         .ops = &clk_branch2_ops,
3202                 },
3203         },
3204 };
3205
3206 static struct clk_branch gcc_nssnoc_snoc_clk = {
3207         .halt_reg = 0x68188,
3208         .clkr = {
3209                 .enable_reg = 0x68188,
3210                 .enable_mask = BIT(0),
3211                 .hw.init = &(struct clk_init_data){
3212                         .name = "gcc_nssnoc_snoc_clk",
3213                         .parent_hws = (const struct clk_hw *[]){
3214                                 &system_noc_clk_src.hw },
3215                         .num_parents = 1,
3216                         .flags = CLK_SET_RATE_PARENT,
3217                         .ops = &clk_branch2_ops,
3218                 },
3219         },
3220 };
3221
3222 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3223         .halt_reg = 0x68184,
3224         .clkr = {
3225                 .enable_reg = 0x68184,
3226                 .enable_mask = BIT(0),
3227                 .hw.init = &(struct clk_init_data){
3228                         .name = "gcc_nssnoc_timeout_ref_clk",
3229                         .parent_hws = (const struct clk_hw *[]){
3230                                 &gcc_xo_div4_clk_src.hw },
3231                         .num_parents = 1,
3232                         .flags = CLK_SET_RATE_PARENT,
3233                         .ops = &clk_branch2_ops,
3234                 },
3235         },
3236 };
3237
3238 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3239         .halt_reg = 0x68270,
3240         .clkr = {
3241                 .enable_reg = 0x68270,
3242                 .enable_mask = BIT(0),
3243                 .hw.init = &(struct clk_init_data){
3244                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3245                         .parent_hws = (const struct clk_hw *[]){
3246                                 &nss_ce_clk_src.clkr.hw },
3247                         .num_parents = 1,
3248                         .flags = CLK_SET_RATE_PARENT,
3249                         .ops = &clk_branch2_ops,
3250                 },
3251         },
3252 };
3253
3254 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3255         .halt_reg = 0x68274,
3256         .clkr = {
3257                 .enable_reg = 0x68274,
3258                 .enable_mask = BIT(0),
3259                 .hw.init = &(struct clk_init_data){
3260                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3261                         .parent_hws = (const struct clk_hw *[]){
3262                                 &nss_ce_clk_src.clkr.hw },
3263                         .num_parents = 1,
3264                         .flags = CLK_SET_RATE_PARENT,
3265                         .ops = &clk_branch2_ops,
3266                 },
3267         },
3268 };
3269
3270 static struct clk_branch gcc_ubi0_ahb_clk = {
3271         .halt_reg = 0x6820c,
3272         .halt_check = BRANCH_HALT_DELAY,
3273         .clkr = {
3274                 .enable_reg = 0x6820c,
3275                 .enable_mask = BIT(0),
3276                 .hw.init = &(struct clk_init_data){
3277                         .name = "gcc_ubi0_ahb_clk",
3278                         .parent_hws = (const struct clk_hw *[]){
3279                                 &nss_ce_clk_src.clkr.hw },
3280                         .num_parents = 1,
3281                         .flags = CLK_SET_RATE_PARENT,
3282                         .ops = &clk_branch2_ops,
3283                 },
3284         },
3285 };
3286
3287 static struct clk_branch gcc_ubi0_axi_clk = {
3288         .halt_reg = 0x68200,
3289         .halt_check = BRANCH_HALT_DELAY,
3290         .clkr = {
3291                 .enable_reg = 0x68200,
3292                 .enable_mask = BIT(0),
3293                 .hw.init = &(struct clk_init_data){
3294                         .name = "gcc_ubi0_axi_clk",
3295                         .parent_hws = (const struct clk_hw *[]){
3296                                 &nss_noc_clk_src.hw },
3297                         .num_parents = 1,
3298                         .flags = CLK_SET_RATE_PARENT,
3299                         .ops = &clk_branch2_ops,
3300                 },
3301         },
3302 };
3303
3304 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3305         .halt_reg = 0x68204,
3306         .halt_check = BRANCH_HALT_DELAY,
3307         .clkr = {
3308                 .enable_reg = 0x68204,
3309                 .enable_mask = BIT(0),
3310                 .hw.init = &(struct clk_init_data){
3311                         .name = "gcc_ubi0_nc_axi_clk",
3312                         .parent_hws = (const struct clk_hw *[]){
3313                                 &nss_noc_clk_src.hw },
3314                         .num_parents = 1,
3315                         .flags = CLK_SET_RATE_PARENT,
3316                         .ops = &clk_branch2_ops,
3317                 },
3318         },
3319 };
3320
3321 static struct clk_branch gcc_ubi0_core_clk = {
3322         .halt_reg = 0x68210,
3323         .halt_check = BRANCH_HALT_DELAY,
3324         .clkr = {
3325                 .enable_reg = 0x68210,
3326                 .enable_mask = BIT(0),
3327                 .hw.init = &(struct clk_init_data){
3328                         .name = "gcc_ubi0_core_clk",
3329                         .parent_hws = (const struct clk_hw *[]){
3330                                 &nss_ubi0_div_clk_src.clkr.hw },
3331                         .num_parents = 1,
3332                         .flags = CLK_SET_RATE_PARENT,
3333                         .ops = &clk_branch2_ops,
3334                 },
3335         },
3336 };
3337
3338 static struct clk_branch gcc_ubi0_mpt_clk = {
3339         .halt_reg = 0x68208,
3340         .halt_check = BRANCH_HALT_DELAY,
3341         .clkr = {
3342                 .enable_reg = 0x68208,
3343                 .enable_mask = BIT(0),
3344                 .hw.init = &(struct clk_init_data){
3345                         .name = "gcc_ubi0_mpt_clk",
3346                         .parent_hws = (const struct clk_hw *[]){
3347                                 &ubi_mpt_clk_src.clkr.hw },
3348                         .num_parents = 1,
3349                         .flags = CLK_SET_RATE_PARENT,
3350                         .ops = &clk_branch2_ops,
3351                 },
3352         },
3353 };
3354
3355 static struct clk_branch gcc_ubi1_ahb_clk = {
3356         .halt_reg = 0x6822c,
3357         .halt_check = BRANCH_HALT_DELAY,
3358         .clkr = {
3359                 .enable_reg = 0x6822c,
3360                 .enable_mask = BIT(0),
3361                 .hw.init = &(struct clk_init_data){
3362                         .name = "gcc_ubi1_ahb_clk",
3363                         .parent_hws = (const struct clk_hw *[]){
3364                                 &nss_ce_clk_src.clkr.hw },
3365                         .num_parents = 1,
3366                         .flags = CLK_SET_RATE_PARENT,
3367                         .ops = &clk_branch2_ops,
3368                 },
3369         },
3370 };
3371
3372 static struct clk_branch gcc_ubi1_axi_clk = {
3373         .halt_reg = 0x68220,
3374         .halt_check = BRANCH_HALT_DELAY,
3375         .clkr = {
3376                 .enable_reg = 0x68220,
3377                 .enable_mask = BIT(0),
3378                 .hw.init = &(struct clk_init_data){
3379                         .name = "gcc_ubi1_axi_clk",
3380                         .parent_hws = (const struct clk_hw *[]){
3381                                 &nss_noc_clk_src.hw },
3382                         .num_parents = 1,
3383                         .flags = CLK_SET_RATE_PARENT,
3384                         .ops = &clk_branch2_ops,
3385                 },
3386         },
3387 };
3388
3389 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3390         .halt_reg = 0x68224,
3391         .halt_check = BRANCH_HALT_DELAY,
3392         .clkr = {
3393                 .enable_reg = 0x68224,
3394                 .enable_mask = BIT(0),
3395                 .hw.init = &(struct clk_init_data){
3396                         .name = "gcc_ubi1_nc_axi_clk",
3397                         .parent_hws = (const struct clk_hw *[]){
3398                                 &nss_noc_clk_src.hw },
3399                         .num_parents = 1,
3400                         .flags = CLK_SET_RATE_PARENT,
3401                         .ops = &clk_branch2_ops,
3402                 },
3403         },
3404 };
3405
3406 static struct clk_branch gcc_ubi1_core_clk = {
3407         .halt_reg = 0x68230,
3408         .halt_check = BRANCH_HALT_DELAY,
3409         .clkr = {
3410                 .enable_reg = 0x68230,
3411                 .enable_mask = BIT(0),
3412                 .hw.init = &(struct clk_init_data){
3413                         .name = "gcc_ubi1_core_clk",
3414                         .parent_hws = (const struct clk_hw *[]){
3415                                 &nss_ubi1_div_clk_src.clkr.hw },
3416                         .num_parents = 1,
3417                         .flags = CLK_SET_RATE_PARENT,
3418                         .ops = &clk_branch2_ops,
3419                 },
3420         },
3421 };
3422
3423 static struct clk_branch gcc_ubi1_mpt_clk = {
3424         .halt_reg = 0x68228,
3425         .halt_check = BRANCH_HALT_DELAY,
3426         .clkr = {
3427                 .enable_reg = 0x68228,
3428                 .enable_mask = BIT(0),
3429                 .hw.init = &(struct clk_init_data){
3430                         .name = "gcc_ubi1_mpt_clk",
3431                         .parent_hws = (const struct clk_hw *[]){
3432                                 &ubi_mpt_clk_src.clkr.hw },
3433                         .num_parents = 1,
3434                         .flags = CLK_SET_RATE_PARENT,
3435                         .ops = &clk_branch2_ops,
3436                 },
3437         },
3438 };
3439
3440 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3441         .halt_reg = 0x56308,
3442         .clkr = {
3443                 .enable_reg = 0x56308,
3444                 .enable_mask = BIT(0),
3445                 .hw.init = &(struct clk_init_data){
3446                         .name = "gcc_cmn_12gpll_ahb_clk",
3447                         .parent_hws = (const struct clk_hw *[]){
3448                                 &pcnoc_clk_src.hw },
3449                         .num_parents = 1,
3450                         .flags = CLK_SET_RATE_PARENT,
3451                         .ops = &clk_branch2_ops,
3452                 },
3453         },
3454 };
3455
3456 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3457         .halt_reg = 0x5630c,
3458         .clkr = {
3459                 .enable_reg = 0x5630c,
3460                 .enable_mask = BIT(0),
3461                 .hw.init = &(struct clk_init_data){
3462                         .name = "gcc_cmn_12gpll_sys_clk",
3463                         .parent_hws = (const struct clk_hw *[]){
3464                                 &gcc_xo_clk_src.clkr.hw },
3465                         .num_parents = 1,
3466                         .flags = CLK_SET_RATE_PARENT,
3467                         .ops = &clk_branch2_ops,
3468                 },
3469         },
3470 };
3471
3472 static struct clk_branch gcc_mdio_ahb_clk = {
3473         .halt_reg = 0x58004,
3474         .clkr = {
3475                 .enable_reg = 0x58004,
3476                 .enable_mask = BIT(0),
3477                 .hw.init = &(struct clk_init_data){
3478                         .name = "gcc_mdio_ahb_clk",
3479                         .parent_hws = (const struct clk_hw *[]){
3480                                 &pcnoc_clk_src.hw },
3481                         .num_parents = 1,
3482                         .flags = CLK_SET_RATE_PARENT,
3483                         .ops = &clk_branch2_ops,
3484                 },
3485         },
3486 };
3487
3488 static struct clk_branch gcc_uniphy0_ahb_clk = {
3489         .halt_reg = 0x56008,
3490         .clkr = {
3491                 .enable_reg = 0x56008,
3492                 .enable_mask = BIT(0),
3493                 .hw.init = &(struct clk_init_data){
3494                         .name = "gcc_uniphy0_ahb_clk",
3495                         .parent_hws = (const struct clk_hw *[]){
3496                                 &pcnoc_clk_src.hw },
3497                         .num_parents = 1,
3498                         .flags = CLK_SET_RATE_PARENT,
3499                         .ops = &clk_branch2_ops,
3500                 },
3501         },
3502 };
3503
3504 static struct clk_branch gcc_uniphy0_sys_clk = {
3505         .halt_reg = 0x5600c,
3506         .clkr = {
3507                 .enable_reg = 0x5600c,
3508                 .enable_mask = BIT(0),
3509                 .hw.init = &(struct clk_init_data){
3510                         .name = "gcc_uniphy0_sys_clk",
3511                         .parent_hws = (const struct clk_hw *[]){
3512                                 &gcc_xo_clk_src.clkr.hw },
3513                         .num_parents = 1,
3514                         .flags = CLK_SET_RATE_PARENT,
3515                         .ops = &clk_branch2_ops,
3516                 },
3517         },
3518 };
3519
3520 static struct clk_branch gcc_uniphy1_ahb_clk = {
3521         .halt_reg = 0x56108,
3522         .clkr = {
3523                 .enable_reg = 0x56108,
3524                 .enable_mask = BIT(0),
3525                 .hw.init = &(struct clk_init_data){
3526                         .name = "gcc_uniphy1_ahb_clk",
3527                         .parent_hws = (const struct clk_hw *[]){
3528                                 &pcnoc_clk_src.hw },
3529                         .num_parents = 1,
3530                         .flags = CLK_SET_RATE_PARENT,
3531                         .ops = &clk_branch2_ops,
3532                 },
3533         },
3534 };
3535
3536 static struct clk_branch gcc_uniphy1_sys_clk = {
3537         .halt_reg = 0x5610c,
3538         .clkr = {
3539                 .enable_reg = 0x5610c,
3540                 .enable_mask = BIT(0),
3541                 .hw.init = &(struct clk_init_data){
3542                         .name = "gcc_uniphy1_sys_clk",
3543                         .parent_hws = (const struct clk_hw *[]){
3544                                 &gcc_xo_clk_src.clkr.hw },
3545                         .num_parents = 1,
3546                         .flags = CLK_SET_RATE_PARENT,
3547                         .ops = &clk_branch2_ops,
3548                 },
3549         },
3550 };
3551
3552 static struct clk_branch gcc_uniphy2_ahb_clk = {
3553         .halt_reg = 0x56208,
3554         .clkr = {
3555                 .enable_reg = 0x56208,
3556                 .enable_mask = BIT(0),
3557                 .hw.init = &(struct clk_init_data){
3558                         .name = "gcc_uniphy2_ahb_clk",
3559                         .parent_hws = (const struct clk_hw *[]){
3560                                 &pcnoc_clk_src.hw },
3561                         .num_parents = 1,
3562                         .flags = CLK_SET_RATE_PARENT,
3563                         .ops = &clk_branch2_ops,
3564                 },
3565         },
3566 };
3567
3568 static struct clk_branch gcc_uniphy2_sys_clk = {
3569         .halt_reg = 0x5620c,
3570         .clkr = {
3571                 .enable_reg = 0x5620c,
3572                 .enable_mask = BIT(0),
3573                 .hw.init = &(struct clk_init_data){
3574                         .name = "gcc_uniphy2_sys_clk",
3575                         .parent_hws = (const struct clk_hw *[]){
3576                                 &gcc_xo_clk_src.clkr.hw },
3577                         .num_parents = 1,
3578                         .flags = CLK_SET_RATE_PARENT,
3579                         .ops = &clk_branch2_ops,
3580                 },
3581         },
3582 };
3583
3584 static struct clk_branch gcc_nss_port1_rx_clk = {
3585         .halt_reg = 0x68240,
3586         .clkr = {
3587                 .enable_reg = 0x68240,
3588                 .enable_mask = BIT(0),
3589                 .hw.init = &(struct clk_init_data){
3590                         .name = "gcc_nss_port1_rx_clk",
3591                         .parent_hws = (const struct clk_hw *[]){
3592                                 &nss_port1_rx_div_clk_src.clkr.hw },
3593                         .num_parents = 1,
3594                         .flags = CLK_SET_RATE_PARENT,
3595                         .ops = &clk_branch2_ops,
3596                 },
3597         },
3598 };
3599
3600 static struct clk_branch gcc_nss_port1_tx_clk = {
3601         .halt_reg = 0x68244,
3602         .clkr = {
3603                 .enable_reg = 0x68244,
3604                 .enable_mask = BIT(0),
3605                 .hw.init = &(struct clk_init_data){
3606                         .name = "gcc_nss_port1_tx_clk",
3607                         .parent_hws = (const struct clk_hw *[]){
3608                                 &nss_port1_tx_div_clk_src.clkr.hw },
3609                         .num_parents = 1,
3610                         .flags = CLK_SET_RATE_PARENT,
3611                         .ops = &clk_branch2_ops,
3612                 },
3613         },
3614 };
3615
3616 static struct clk_branch gcc_nss_port2_rx_clk = {
3617         .halt_reg = 0x68248,
3618         .clkr = {
3619                 .enable_reg = 0x68248,
3620                 .enable_mask = BIT(0),
3621                 .hw.init = &(struct clk_init_data){
3622                         .name = "gcc_nss_port2_rx_clk",
3623                         .parent_hws = (const struct clk_hw *[]){
3624                                 &nss_port2_rx_div_clk_src.clkr.hw },
3625                         .num_parents = 1,
3626                         .flags = CLK_SET_RATE_PARENT,
3627                         .ops = &clk_branch2_ops,
3628                 },
3629         },
3630 };
3631
3632 static struct clk_branch gcc_nss_port2_tx_clk = {
3633         .halt_reg = 0x6824c,
3634         .clkr = {
3635                 .enable_reg = 0x6824c,
3636                 .enable_mask = BIT(0),
3637                 .hw.init = &(struct clk_init_data){
3638                         .name = "gcc_nss_port2_tx_clk",
3639                         .parent_hws = (const struct clk_hw *[]){
3640                                 &nss_port2_tx_div_clk_src.clkr.hw },
3641                         .num_parents = 1,
3642                         .flags = CLK_SET_RATE_PARENT,
3643                         .ops = &clk_branch2_ops,
3644                 },
3645         },
3646 };
3647
3648 static struct clk_branch gcc_nss_port3_rx_clk = {
3649         .halt_reg = 0x68250,
3650         .clkr = {
3651                 .enable_reg = 0x68250,
3652                 .enable_mask = BIT(0),
3653                 .hw.init = &(struct clk_init_data){
3654                         .name = "gcc_nss_port3_rx_clk",
3655                         .parent_hws = (const struct clk_hw *[]){
3656                                 &nss_port3_rx_div_clk_src.clkr.hw },
3657                         .num_parents = 1,
3658                         .flags = CLK_SET_RATE_PARENT,
3659                         .ops = &clk_branch2_ops,
3660                 },
3661         },
3662 };
3663
3664 static struct clk_branch gcc_nss_port3_tx_clk = {
3665         .halt_reg = 0x68254,
3666         .clkr = {
3667                 .enable_reg = 0x68254,
3668                 .enable_mask = BIT(0),
3669                 .hw.init = &(struct clk_init_data){
3670                         .name = "gcc_nss_port3_tx_clk",
3671                         .parent_hws = (const struct clk_hw *[]){
3672                                 &nss_port3_tx_div_clk_src.clkr.hw },
3673                         .num_parents = 1,
3674                         .flags = CLK_SET_RATE_PARENT,
3675                         .ops = &clk_branch2_ops,
3676                 },
3677         },
3678 };
3679
3680 static struct clk_branch gcc_nss_port4_rx_clk = {
3681         .halt_reg = 0x68258,
3682         .clkr = {
3683                 .enable_reg = 0x68258,
3684                 .enable_mask = BIT(0),
3685                 .hw.init = &(struct clk_init_data){
3686                         .name = "gcc_nss_port4_rx_clk",
3687                         .parent_hws = (const struct clk_hw *[]){
3688                                 &nss_port4_rx_div_clk_src.clkr.hw },
3689                         .num_parents = 1,
3690                         .flags = CLK_SET_RATE_PARENT,
3691                         .ops = &clk_branch2_ops,
3692                 },
3693         },
3694 };
3695
3696 static struct clk_branch gcc_nss_port4_tx_clk = {
3697         .halt_reg = 0x6825c,
3698         .clkr = {
3699                 .enable_reg = 0x6825c,
3700                 .enable_mask = BIT(0),
3701                 .hw.init = &(struct clk_init_data){
3702                         .name = "gcc_nss_port4_tx_clk",
3703                         .parent_hws = (const struct clk_hw *[]){
3704                                 &nss_port4_tx_div_clk_src.clkr.hw },
3705                         .num_parents = 1,
3706                         .flags = CLK_SET_RATE_PARENT,
3707                         .ops = &clk_branch2_ops,
3708                 },
3709         },
3710 };
3711
3712 static struct clk_branch gcc_nss_port5_rx_clk = {
3713         .halt_reg = 0x68260,
3714         .clkr = {
3715                 .enable_reg = 0x68260,
3716                 .enable_mask = BIT(0),
3717                 .hw.init = &(struct clk_init_data){
3718                         .name = "gcc_nss_port5_rx_clk",
3719                         .parent_hws = (const struct clk_hw *[]){
3720                                 &nss_port5_rx_div_clk_src.clkr.hw },
3721                         .num_parents = 1,
3722                         .flags = CLK_SET_RATE_PARENT,
3723                         .ops = &clk_branch2_ops,
3724                 },
3725         },
3726 };
3727
3728 static struct clk_branch gcc_nss_port5_tx_clk = {
3729         .halt_reg = 0x68264,
3730         .clkr = {
3731                 .enable_reg = 0x68264,
3732                 .enable_mask = BIT(0),
3733                 .hw.init = &(struct clk_init_data){
3734                         .name = "gcc_nss_port5_tx_clk",
3735                         .parent_hws = (const struct clk_hw *[]){
3736                                 &nss_port5_tx_div_clk_src.clkr.hw },
3737                         .num_parents = 1,
3738                         .flags = CLK_SET_RATE_PARENT,
3739                         .ops = &clk_branch2_ops,
3740                 },
3741         },
3742 };
3743
3744 static struct clk_branch gcc_nss_port6_rx_clk = {
3745         .halt_reg = 0x68268,
3746         .clkr = {
3747                 .enable_reg = 0x68268,
3748                 .enable_mask = BIT(0),
3749                 .hw.init = &(struct clk_init_data){
3750                         .name = "gcc_nss_port6_rx_clk",
3751                         .parent_hws = (const struct clk_hw *[]){
3752                                 &nss_port6_rx_div_clk_src.clkr.hw },
3753                         .num_parents = 1,
3754                         .flags = CLK_SET_RATE_PARENT,
3755                         .ops = &clk_branch2_ops,
3756                 },
3757         },
3758 };
3759
3760 static struct clk_branch gcc_nss_port6_tx_clk = {
3761         .halt_reg = 0x6826c,
3762         .clkr = {
3763                 .enable_reg = 0x6826c,
3764                 .enable_mask = BIT(0),
3765                 .hw.init = &(struct clk_init_data){
3766                         .name = "gcc_nss_port6_tx_clk",
3767                         .parent_hws = (const struct clk_hw *[]){
3768                                 &nss_port6_tx_div_clk_src.clkr.hw },
3769                         .num_parents = 1,
3770                         .flags = CLK_SET_RATE_PARENT,
3771                         .ops = &clk_branch2_ops,
3772                 },
3773         },
3774 };
3775
3776 static struct clk_branch gcc_port1_mac_clk = {
3777         .halt_reg = 0x68320,
3778         .clkr = {
3779                 .enable_reg = 0x68320,
3780                 .enable_mask = BIT(0),
3781                 .hw.init = &(struct clk_init_data){
3782                         .name = "gcc_port1_mac_clk",
3783                         .parent_hws = (const struct clk_hw *[]){
3784                                 &nss_ppe_clk_src.clkr.hw },
3785                         .num_parents = 1,
3786                         .flags = CLK_SET_RATE_PARENT,
3787                         .ops = &clk_branch2_ops,
3788                 },
3789         },
3790 };
3791
3792 static struct clk_branch gcc_port2_mac_clk = {
3793         .halt_reg = 0x68324,
3794         .clkr = {
3795                 .enable_reg = 0x68324,
3796                 .enable_mask = BIT(0),
3797                 .hw.init = &(struct clk_init_data){
3798                         .name = "gcc_port2_mac_clk",
3799                         .parent_hws = (const struct clk_hw *[]){
3800                                 &nss_ppe_clk_src.clkr.hw },
3801                         .num_parents = 1,
3802                         .flags = CLK_SET_RATE_PARENT,
3803                         .ops = &clk_branch2_ops,
3804                 },
3805         },
3806 };
3807
3808 static struct clk_branch gcc_port3_mac_clk = {
3809         .halt_reg = 0x68328,
3810         .clkr = {
3811                 .enable_reg = 0x68328,
3812                 .enable_mask = BIT(0),
3813                 .hw.init = &(struct clk_init_data){
3814                         .name = "gcc_port3_mac_clk",
3815                         .parent_hws = (const struct clk_hw *[]){
3816                                 &nss_ppe_clk_src.clkr.hw },
3817                         .num_parents = 1,
3818                         .flags = CLK_SET_RATE_PARENT,
3819                         .ops = &clk_branch2_ops,
3820                 },
3821         },
3822 };
3823
3824 static struct clk_branch gcc_port4_mac_clk = {
3825         .halt_reg = 0x6832c,
3826         .clkr = {
3827                 .enable_reg = 0x6832c,
3828                 .enable_mask = BIT(0),
3829                 .hw.init = &(struct clk_init_data){
3830                         .name = "gcc_port4_mac_clk",
3831                         .parent_hws = (const struct clk_hw *[]){
3832                                 &nss_ppe_clk_src.clkr.hw },
3833                         .num_parents = 1,
3834                         .flags = CLK_SET_RATE_PARENT,
3835                         .ops = &clk_branch2_ops,
3836                 },
3837         },
3838 };
3839
3840 static struct clk_branch gcc_port5_mac_clk = {
3841         .halt_reg = 0x68330,
3842         .clkr = {
3843                 .enable_reg = 0x68330,
3844                 .enable_mask = BIT(0),
3845                 .hw.init = &(struct clk_init_data){
3846                         .name = "gcc_port5_mac_clk",
3847                         .parent_hws = (const struct clk_hw *[]){
3848                                 &nss_ppe_clk_src.clkr.hw },
3849                         .num_parents = 1,
3850                         .flags = CLK_SET_RATE_PARENT,
3851                         .ops = &clk_branch2_ops,
3852                 },
3853         },
3854 };
3855
3856 static struct clk_branch gcc_port6_mac_clk = {
3857         .halt_reg = 0x68334,
3858         .clkr = {
3859                 .enable_reg = 0x68334,
3860                 .enable_mask = BIT(0),
3861                 .hw.init = &(struct clk_init_data){
3862                         .name = "gcc_port6_mac_clk",
3863                         .parent_hws = (const struct clk_hw *[]){
3864                                 &nss_ppe_clk_src.clkr.hw },
3865                         .num_parents = 1,
3866                         .flags = CLK_SET_RATE_PARENT,
3867                         .ops = &clk_branch2_ops,
3868                 },
3869         },
3870 };
3871
3872 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3873         .halt_reg = 0x56010,
3874         .clkr = {
3875                 .enable_reg = 0x56010,
3876                 .enable_mask = BIT(0),
3877                 .hw.init = &(struct clk_init_data){
3878                         .name = "gcc_uniphy0_port1_rx_clk",
3879                         .parent_hws = (const struct clk_hw *[]){
3880                                 &nss_port1_rx_div_clk_src.clkr.hw },
3881                         .num_parents = 1,
3882                         .flags = CLK_SET_RATE_PARENT,
3883                         .ops = &clk_branch2_ops,
3884                 },
3885         },
3886 };
3887
3888 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3889         .halt_reg = 0x56014,
3890         .clkr = {
3891                 .enable_reg = 0x56014,
3892                 .enable_mask = BIT(0),
3893                 .hw.init = &(struct clk_init_data){
3894                         .name = "gcc_uniphy0_port1_tx_clk",
3895                         .parent_hws = (const struct clk_hw *[]){
3896                                 &nss_port1_tx_div_clk_src.clkr.hw },
3897                         .num_parents = 1,
3898                         .flags = CLK_SET_RATE_PARENT,
3899                         .ops = &clk_branch2_ops,
3900                 },
3901         },
3902 };
3903
3904 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3905         .halt_reg = 0x56018,
3906         .clkr = {
3907                 .enable_reg = 0x56018,
3908                 .enable_mask = BIT(0),
3909                 .hw.init = &(struct clk_init_data){
3910                         .name = "gcc_uniphy0_port2_rx_clk",
3911                         .parent_hws = (const struct clk_hw *[]){
3912                                 &nss_port2_rx_div_clk_src.clkr.hw },
3913                         .num_parents = 1,
3914                         .flags = CLK_SET_RATE_PARENT,
3915                         .ops = &clk_branch2_ops,
3916                 },
3917         },
3918 };
3919
3920 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3921         .halt_reg = 0x5601c,
3922         .clkr = {
3923                 .enable_reg = 0x5601c,
3924                 .enable_mask = BIT(0),
3925                 .hw.init = &(struct clk_init_data){
3926                         .name = "gcc_uniphy0_port2_tx_clk",
3927                         .parent_hws = (const struct clk_hw *[]){
3928                                 &nss_port2_tx_div_clk_src.clkr.hw },
3929                         .num_parents = 1,
3930                         .flags = CLK_SET_RATE_PARENT,
3931                         .ops = &clk_branch2_ops,
3932                 },
3933         },
3934 };
3935
3936 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3937         .halt_reg = 0x56020,
3938         .clkr = {
3939                 .enable_reg = 0x56020,
3940                 .enable_mask = BIT(0),
3941                 .hw.init = &(struct clk_init_data){
3942                         .name = "gcc_uniphy0_port3_rx_clk",
3943                         .parent_hws = (const struct clk_hw *[]){
3944                                 &nss_port3_rx_div_clk_src.clkr.hw },
3945                         .num_parents = 1,
3946                         .flags = CLK_SET_RATE_PARENT,
3947                         .ops = &clk_branch2_ops,
3948                 },
3949         },
3950 };
3951
3952 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3953         .halt_reg = 0x56024,
3954         .clkr = {
3955                 .enable_reg = 0x56024,
3956                 .enable_mask = BIT(0),
3957                 .hw.init = &(struct clk_init_data){
3958                         .name = "gcc_uniphy0_port3_tx_clk",
3959                         .parent_hws = (const struct clk_hw *[]){
3960                                 &nss_port3_tx_div_clk_src.clkr.hw },
3961                         .num_parents = 1,
3962                         .flags = CLK_SET_RATE_PARENT,
3963                         .ops = &clk_branch2_ops,
3964                 },
3965         },
3966 };
3967
3968 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3969         .halt_reg = 0x56028,
3970         .clkr = {
3971                 .enable_reg = 0x56028,
3972                 .enable_mask = BIT(0),
3973                 .hw.init = &(struct clk_init_data){
3974                         .name = "gcc_uniphy0_port4_rx_clk",
3975                         .parent_hws = (const struct clk_hw *[]){
3976                                 &nss_port4_rx_div_clk_src.clkr.hw },
3977                         .num_parents = 1,
3978                         .flags = CLK_SET_RATE_PARENT,
3979                         .ops = &clk_branch2_ops,
3980                 },
3981         },
3982 };
3983
3984 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3985         .halt_reg = 0x5602c,
3986         .clkr = {
3987                 .enable_reg = 0x5602c,
3988                 .enable_mask = BIT(0),
3989                 .hw.init = &(struct clk_init_data){
3990                         .name = "gcc_uniphy0_port4_tx_clk",
3991                         .parent_hws = (const struct clk_hw *[]){
3992                                 &nss_port4_tx_div_clk_src.clkr.hw },
3993                         .num_parents = 1,
3994                         .flags = CLK_SET_RATE_PARENT,
3995                         .ops = &clk_branch2_ops,
3996                 },
3997         },
3998 };
3999
4000 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4001         .halt_reg = 0x56030,
4002         .clkr = {
4003                 .enable_reg = 0x56030,
4004                 .enable_mask = BIT(0),
4005                 .hw.init = &(struct clk_init_data){
4006                         .name = "gcc_uniphy0_port5_rx_clk",
4007                         .parent_hws = (const struct clk_hw *[]){
4008                                 &nss_port5_rx_div_clk_src.clkr.hw },
4009                         .num_parents = 1,
4010                         .flags = CLK_SET_RATE_PARENT,
4011                         .ops = &clk_branch2_ops,
4012                 },
4013         },
4014 };
4015
4016 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4017         .halt_reg = 0x56034,
4018         .clkr = {
4019                 .enable_reg = 0x56034,
4020                 .enable_mask = BIT(0),
4021                 .hw.init = &(struct clk_init_data){
4022                         .name = "gcc_uniphy0_port5_tx_clk",
4023                         .parent_hws = (const struct clk_hw *[]){
4024                                 &nss_port5_tx_div_clk_src.clkr.hw },
4025                         .num_parents = 1,
4026                         .flags = CLK_SET_RATE_PARENT,
4027                         .ops = &clk_branch2_ops,
4028                 },
4029         },
4030 };
4031
4032 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4033         .halt_reg = 0x56110,
4034         .clkr = {
4035                 .enable_reg = 0x56110,
4036                 .enable_mask = BIT(0),
4037                 .hw.init = &(struct clk_init_data){
4038                         .name = "gcc_uniphy1_port5_rx_clk",
4039                         .parent_hws = (const struct clk_hw *[]){
4040                                 &nss_port5_rx_div_clk_src.clkr.hw },
4041                         .num_parents = 1,
4042                         .flags = CLK_SET_RATE_PARENT,
4043                         .ops = &clk_branch2_ops,
4044                 },
4045         },
4046 };
4047
4048 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4049         .halt_reg = 0x56114,
4050         .clkr = {
4051                 .enable_reg = 0x56114,
4052                 .enable_mask = BIT(0),
4053                 .hw.init = &(struct clk_init_data){
4054                         .name = "gcc_uniphy1_port5_tx_clk",
4055                         .parent_hws = (const struct clk_hw *[]){
4056                                 &nss_port5_tx_div_clk_src.clkr.hw },
4057                         .num_parents = 1,
4058                         .flags = CLK_SET_RATE_PARENT,
4059                         .ops = &clk_branch2_ops,
4060                 },
4061         },
4062 };
4063
4064 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4065         .halt_reg = 0x56210,
4066         .clkr = {
4067                 .enable_reg = 0x56210,
4068                 .enable_mask = BIT(0),
4069                 .hw.init = &(struct clk_init_data){
4070                         .name = "gcc_uniphy2_port6_rx_clk",
4071                         .parent_hws = (const struct clk_hw *[]){
4072                                 &nss_port6_rx_div_clk_src.clkr.hw },
4073                         .num_parents = 1,
4074                         .flags = CLK_SET_RATE_PARENT,
4075                         .ops = &clk_branch2_ops,
4076                 },
4077         },
4078 };
4079
4080 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4081         .halt_reg = 0x56214,
4082         .clkr = {
4083                 .enable_reg = 0x56214,
4084                 .enable_mask = BIT(0),
4085                 .hw.init = &(struct clk_init_data){
4086                         .name = "gcc_uniphy2_port6_tx_clk",
4087                         .parent_hws = (const struct clk_hw *[]){
4088                                 &nss_port6_tx_div_clk_src.clkr.hw },
4089                         .num_parents = 1,
4090                         .flags = CLK_SET_RATE_PARENT,
4091                         .ops = &clk_branch2_ops,
4092                 },
4093         },
4094 };
4095
4096 static struct clk_branch gcc_crypto_ahb_clk = {
4097         .halt_reg = 0x16024,
4098         .halt_check = BRANCH_HALT_VOTED,
4099         .clkr = {
4100                 .enable_reg = 0x0b004,
4101                 .enable_mask = BIT(0),
4102                 .hw.init = &(struct clk_init_data){
4103                         .name = "gcc_crypto_ahb_clk",
4104                         .parent_hws = (const struct clk_hw *[]){
4105                                 &pcnoc_clk_src.hw },
4106                         .num_parents = 1,
4107                         .flags = CLK_SET_RATE_PARENT,
4108                         .ops = &clk_branch2_ops,
4109                 },
4110         },
4111 };
4112
4113 static struct clk_branch gcc_crypto_axi_clk = {
4114         .halt_reg = 0x16020,
4115         .halt_check = BRANCH_HALT_VOTED,
4116         .clkr = {
4117                 .enable_reg = 0x0b004,
4118                 .enable_mask = BIT(1),
4119                 .hw.init = &(struct clk_init_data){
4120                         .name = "gcc_crypto_axi_clk",
4121                         .parent_hws = (const struct clk_hw *[]){
4122                                 &pcnoc_clk_src.hw },
4123                         .num_parents = 1,
4124                         .flags = CLK_SET_RATE_PARENT,
4125                         .ops = &clk_branch2_ops,
4126                 },
4127         },
4128 };
4129
4130 static struct clk_branch gcc_crypto_clk = {
4131         .halt_reg = 0x1601c,
4132         .halt_check = BRANCH_HALT_VOTED,
4133         .clkr = {
4134                 .enable_reg = 0x0b004,
4135                 .enable_mask = BIT(2),
4136                 .hw.init = &(struct clk_init_data){
4137                         .name = "gcc_crypto_clk",
4138                         .parent_hws = (const struct clk_hw *[]){
4139                                 &crypto_clk_src.clkr.hw },
4140                         .num_parents = 1,
4141                         .flags = CLK_SET_RATE_PARENT,
4142                         .ops = &clk_branch2_ops,
4143                 },
4144         },
4145 };
4146
4147 static struct clk_branch gcc_gp1_clk = {
4148         .halt_reg = 0x08000,
4149         .clkr = {
4150                 .enable_reg = 0x08000,
4151                 .enable_mask = BIT(0),
4152                 .hw.init = &(struct clk_init_data){
4153                         .name = "gcc_gp1_clk",
4154                         .parent_hws = (const struct clk_hw *[]){
4155                                 &gp1_clk_src.clkr.hw },
4156                         .num_parents = 1,
4157                         .flags = CLK_SET_RATE_PARENT,
4158                         .ops = &clk_branch2_ops,
4159                 },
4160         },
4161 };
4162
4163 static struct clk_branch gcc_gp2_clk = {
4164         .halt_reg = 0x09000,
4165         .clkr = {
4166                 .enable_reg = 0x09000,
4167                 .enable_mask = BIT(0),
4168                 .hw.init = &(struct clk_init_data){
4169                         .name = "gcc_gp2_clk",
4170                         .parent_hws = (const struct clk_hw *[]){
4171                                 &gp2_clk_src.clkr.hw },
4172                         .num_parents = 1,
4173                         .flags = CLK_SET_RATE_PARENT,
4174                         .ops = &clk_branch2_ops,
4175                 },
4176         },
4177 };
4178
4179 static struct clk_branch gcc_gp3_clk = {
4180         .halt_reg = 0x0a000,
4181         .clkr = {
4182                 .enable_reg = 0x0a000,
4183                 .enable_mask = BIT(0),
4184                 .hw.init = &(struct clk_init_data){
4185                         .name = "gcc_gp3_clk",
4186                         .parent_hws = (const struct clk_hw *[]){
4187                                 &gp3_clk_src.clkr.hw },
4188                         .num_parents = 1,
4189                         .flags = CLK_SET_RATE_PARENT,
4190                         .ops = &clk_branch2_ops,
4191                 },
4192         },
4193 };
4194
4195 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
4196         F(19200000, P_XO, 1, 0, 0),
4197         F(100000000, P_GPLL0, 8, 0, 0),
4198         { }
4199 };
4200
4201 static struct clk_rcg2 pcie0_rchng_clk_src = {
4202         .cmd_rcgr = 0x75070,
4203         .freq_tbl = ftbl_pcie_rchng_clk_src,
4204         .hid_width = 5,
4205         .parent_map = gcc_xo_gpll0_map,
4206         .clkr.hw.init = &(struct clk_init_data){
4207                 .name = "pcie0_rchng_clk_src",
4208                 .parent_data = gcc_xo_gpll0,
4209                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
4210                 .ops = &clk_rcg2_ops,
4211         },
4212 };
4213
4214 static struct clk_branch gcc_pcie0_rchng_clk = {
4215         .halt_reg = 0x75070,
4216         .halt_bit = 31,
4217         .clkr = {
4218                 .enable_reg = 0x75070,
4219                 .enable_mask = BIT(1),
4220                 .hw.init = &(struct clk_init_data){
4221                         .name = "gcc_pcie0_rchng_clk",
4222                         .parent_hws = (const struct clk_hw *[]){
4223                                 &pcie0_rchng_clk_src.clkr.hw,
4224                         },
4225                         .num_parents = 1,
4226                         .flags = CLK_SET_RATE_PARENT,
4227                         .ops = &clk_branch2_ops,
4228                 },
4229         },
4230 };
4231
4232 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
4233         .halt_reg = 0x75048,
4234         .halt_bit = 31,
4235         .clkr = {
4236                 .enable_reg = 0x75048,
4237                 .enable_mask = BIT(0),
4238                 .hw.init = &(struct clk_init_data){
4239                         .name = "gcc_pcie0_axi_s_bridge_clk",
4240                         .parent_hws = (const struct clk_hw *[]){
4241                                 &pcie0_axi_clk_src.clkr.hw,
4242                         },
4243                         .num_parents = 1,
4244                         .flags = CLK_SET_RATE_PARENT,
4245                         .ops = &clk_branch2_ops,
4246                 },
4247         },
4248 };
4249
4250 static struct gdsc usb0_gdsc = {
4251         .gdscr = 0x3e078,
4252         .pd = {
4253                 .name = "usb0_gdsc",
4254         },
4255         .pwrsts = PWRSTS_OFF_ON,
4256 };
4257
4258 static struct gdsc usb1_gdsc = {
4259         .gdscr = 0x3f078,
4260         .pd = {
4261                 .name = "usb1_gdsc",
4262         },
4263         .pwrsts = PWRSTS_OFF_ON,
4264 };
4265
4266 static const struct alpha_pll_config ubi32_pll_config = {
4267         .l = 0x4e,
4268         .config_ctl_val = 0x200d4aa8,
4269         .config_ctl_hi_val = 0x3c2,
4270         .main_output_mask = BIT(0),
4271         .aux_output_mask = BIT(1),
4272         .pre_div_val = 0x0,
4273         .pre_div_mask = BIT(12),
4274         .post_div_val = 0x0,
4275         .post_div_mask = GENMASK(9, 8),
4276 };
4277
4278 static const struct alpha_pll_config nss_crypto_pll_config = {
4279         .l = 0x3e,
4280         .alpha = 0x0,
4281         .alpha_hi = 0x80,
4282         .config_ctl_val = 0x4001055b,
4283         .main_output_mask = BIT(0),
4284         .pre_div_val = 0x0,
4285         .pre_div_mask = GENMASK(14, 12),
4286         .post_div_val = 0x1 << 8,
4287         .post_div_mask = GENMASK(11, 8),
4288         .vco_mask = GENMASK(21, 20),
4289         .vco_val = 0x0,
4290         .alpha_en_mask = BIT(24),
4291 };
4292
4293 static struct clk_hw *gcc_ipq8074_hws[] = {
4294         &gpll0_out_main_div2.hw,
4295         &gpll6_out_main_div2.hw,
4296         &pcnoc_clk_src.hw,
4297         &system_noc_clk_src.hw,
4298         &gcc_xo_div4_clk_src.hw,
4299         &nss_noc_clk_src.hw,
4300         &nss_ppe_cdiv_clk_src.hw,
4301 };
4302
4303 static struct clk_regmap *gcc_ipq8074_clks[] = {
4304         [GPLL0_MAIN] = &gpll0_main.clkr,
4305         [GPLL0] = &gpll0.clkr,
4306         [GPLL2_MAIN] = &gpll2_main.clkr,
4307         [GPLL2] = &gpll2.clkr,
4308         [GPLL4_MAIN] = &gpll4_main.clkr,
4309         [GPLL4] = &gpll4.clkr,
4310         [GPLL6_MAIN] = &gpll6_main.clkr,
4311         [GPLL6] = &gpll6.clkr,
4312         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4313         [UBI32_PLL] = &ubi32_pll.clkr,
4314         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4315         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4316         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4317         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4318         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4319         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4320         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4321         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4322         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4323         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4324         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4325         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4326         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4327         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4328         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4329         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4330         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4331         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4332         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4333         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4334         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4335         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4336         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4337         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4338         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4339         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4340         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4341         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4342         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4343         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4344         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4345         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4346         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4347         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4348         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4349         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4350         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4351         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4352         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4353         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4354         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4355         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4356         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4357         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4358         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4359         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4360         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4361         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4362         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4363         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4364         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4365         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4366         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4367         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4368         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4369         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4370         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4371         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4372         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4373         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4374         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4375         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4376         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4377         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4378         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4379         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4380         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4381         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4382         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4383         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4384         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4385         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4386         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4387         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4388         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4389         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4390         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4391         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4392         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4393         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4394         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4395         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4396         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4397         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4398         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4399         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4400         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4401         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4402         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4403         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4404         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4405         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4406         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4407         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4408         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4409         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4410         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4411         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4412         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4413         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4414         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4415         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4416         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4417         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4418         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4419         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4420         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4421         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4422         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4423         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4424         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4425         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4426         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4427         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4428         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4429         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4430         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4431         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4432         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4433         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4434         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4435         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4436         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4437         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4438         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4439         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4440         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4441         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4442         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4443         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4444         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4445         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4446         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4447         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4448         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4449         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4450         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4451         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4452         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4453         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4454         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4455         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4456         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4457         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4458         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4459         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4460         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4461         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4462         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4463         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4464         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4465         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4466         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4467         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4468         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4469         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4470         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4471         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4472         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4473         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4474         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4475         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4476         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4477         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4478         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4479         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4480         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4481         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4482         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4483         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4484         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4485         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4486         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4487         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4488         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4489         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4490         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4491         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4492         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4493         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4494         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4495         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4496         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4497         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4498         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4499         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4500         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4501         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4502         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4503         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4504         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4505         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4506         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4507         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4508         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4509         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4510         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4511         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4512         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4513         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4514         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4515         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4516         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4517         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4518         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4519         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4520         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4521         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4522         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4523         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4524         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4525         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4526         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4527         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4528         [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4529         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4530         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4531         [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4532 };
4533
4534 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4535         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4536         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4537         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4538         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4539         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4540         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4541         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4542         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4543         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4544         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4545         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4546         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4547         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4548         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4549         [GCC_SMMU_BCR] = { 0x12000, 0 },
4550         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4551         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4552         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4553         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4554         [GCC_PRNG_BCR] = { 0x13000, 0 },
4555         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4556         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4557         [GCC_WCSS_BCR] = { 0x18000, 0 },
4558         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4559         [GCC_NSS_BCR] = { 0x19000, 0 },
4560         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4561         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4562         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4563         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4564         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4565         [GCC_TCSR_BCR] = { 0x28000, 0 },
4566         [GCC_QDSS_BCR] = { 0x29000, 0 },
4567         [GCC_DCD_BCR] = { 0x2a000, 0 },
4568         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4569         [GCC_MPM_BCR] = { 0x2c000, 0 },
4570         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4571         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4572         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4573         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4574         [GCC_TLMM_BCR] = { 0x34000, 0 },
4575         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4576         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4577         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4578         [GCC_USB0_BCR] = { 0x3e070, 0 },
4579         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4580         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4581         [GCC_USB1_BCR] = { 0x3f070, 0 },
4582         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4583         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4584         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4585         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4586         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4587         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4588         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4589         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4590         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4591         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4592         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4593         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4594         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4595         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4596         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4597         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4598         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4599         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4600         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4601         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4602         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4603         [GCC_QPIC_BCR] = { 0x57018, 0 },
4604         [GCC_MDIO_BCR] = { 0x58000, 0 },
4605         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4606         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4607         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4608         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4609         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4610         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4611         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4612         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4613         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4614         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4615         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4616         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4617         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4618         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4619         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4620         [GCC_DCC_BCR] = { 0x77000, 0 },
4621         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4622         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4623         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4624         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4625         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4626         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4627         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4628         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4629         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4630         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4631         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4632         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4633         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4634         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4635         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4636         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4637         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4638         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4639         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4640         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4641         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4642         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4643         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4644         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4645         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4646         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4647         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4648         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4649         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4650         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4651         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4652         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4653         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4654         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4655         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4656         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4657         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4658         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4659         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4660         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4661         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4662         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4663         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4664         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4665         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4666         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4667         [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
4668         [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4669         [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4670         [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4671         [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4672         [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4673         [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
4674         [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
4675         [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4676         [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
4677         [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
4678         [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
4679         [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
4680         [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
4681 };
4682
4683 static struct gdsc *gcc_ipq8074_gdscs[] = {
4684         [USB0_GDSC] = &usb0_gdsc,
4685         [USB1_GDSC] = &usb1_gdsc,
4686 };
4687
4688 static const struct of_device_id gcc_ipq8074_match_table[] = {
4689         { .compatible = "qcom,gcc-ipq8074" },
4690         { }
4691 };
4692 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4693
4694 static const struct regmap_config gcc_ipq8074_regmap_config = {
4695         .reg_bits       = 32,
4696         .reg_stride     = 4,
4697         .val_bits       = 32,
4698         .max_register   = 0x7fffc,
4699         .fast_io        = true,
4700 };
4701
4702 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4703         .config = &gcc_ipq8074_regmap_config,
4704         .clks = gcc_ipq8074_clks,
4705         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4706         .resets = gcc_ipq8074_resets,
4707         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4708         .clk_hws = gcc_ipq8074_hws,
4709         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4710         .gdscs = gcc_ipq8074_gdscs,
4711         .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
4712 };
4713
4714 static int gcc_ipq8074_probe(struct platform_device *pdev)
4715 {
4716         struct regmap *regmap;
4717
4718         regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4719         if (IS_ERR(regmap))
4720                 return PTR_ERR(regmap);
4721
4722         /* SW Workaround for UBI32 Huayra PLL */
4723         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4724
4725         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4726         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4727                                 &nss_crypto_pll_config);
4728
4729         return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4730 }
4731
4732 static struct platform_driver gcc_ipq8074_driver = {
4733         .probe = gcc_ipq8074_probe,
4734         .driver = {
4735                 .name   = "qcom,gcc-ipq8074",
4736                 .of_match_table = gcc_ipq8074_match_table,
4737         },
4738 };
4739
4740 static int __init gcc_ipq8074_init(void)
4741 {
4742         return platform_driver_register(&gcc_ipq8074_driver);
4743 }
4744 core_initcall(gcc_ipq8074_init);
4745
4746 static void __exit gcc_ipq8074_exit(void)
4747 {
4748         platform_driver_unregister(&gcc_ipq8074_driver);
4749 }
4750 module_exit(gcc_ipq8074_exit);
4751
4752 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4753 MODULE_LICENSE("GPL v2");
4754 MODULE_ALIAS("platform:gcc-ipq8074");