drivers/clk/qcom/gcc-ipq8074.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "clk-alpha-pll.h"
  31 #include "reset.h"
  32
  33 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  34
  35 enum {
  36         P_XO,
  37         P_GPLL0,
  38         P_GPLL0_DIV2,
  39 };
  40
  41 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  42         "xo",
  43         "gpll0",
  44         "gpll0_out_main_div2",
  45 };
  46
  47 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  48         { P_XO, 0 },
  49         { P_GPLL0, 1 },
  50         { P_GPLL0_DIV2, 4 },
  51 };
  52
  53 static struct clk_alpha_pll gpll0_main = {
  54         .offset = 0x21000,
  55         .clkr = {
  56                 .enable_reg = 0x0b000,
  57                 .enable_mask = BIT(0),
  58                 .hw.init = &(struct clk_init_data){
  59                         .name = "gpll0_main",
  60                         .parent_names = (const char *[]){
  61                                 "xo"
  62                         },
  63                         .num_parents = 1,
  64                         .ops = &clk_alpha_pll_ops,
  65                 },
  66         },
  67 };
  68
  69 static struct clk_fixed_factor gpll0_out_main_div2 = {
  70         .mult = 1,
  71         .div = 2,
  72         .hw.init = &(struct clk_init_data){
  73                 .name = "gpll0_out_main_div2",
  74                 .parent_names = (const char *[]){
  75                         "gpll0_main"
  76                 },
  77                 .num_parents = 1,
  78                 .ops = &clk_fixed_factor_ops,
  79                 .flags = CLK_SET_RATE_PARENT,
  80         },
  81 };
  82
  83 static struct clk_alpha_pll_postdiv gpll0 = {
  84         .offset = 0x21000,
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll0",
  87                 .parent_names = (const char *[]){
  88                         "gpll0_main"
  89                 },
  90                 .num_parents = 1,
  91                 .ops = &clk_alpha_pll_postdiv_ops,
  92         },
  93 };
  94
  95 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
  96         F(19200000, P_XO, 1, 0, 0),
  97         F(50000000, P_GPLL0, 16, 0, 0),
  98         F(100000000, P_GPLL0, 8, 0, 0),
  99         { }
 100 };
 101
 102 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 103         .cmd_rcgr = 0x27000,
 104         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 105         .hid_width = 5,
 106         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 107         .clkr.hw.init = &(struct clk_init_data){
 108                 .name = "pcnoc_bfdcd_clk_src",
 109                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 110                 .num_parents = 3,
 111                 .ops = &clk_rcg2_ops,
 112                 .flags = CLK_IS_CRITICAL,
 113         },
 114 };
 115
 116 static struct clk_fixed_factor pcnoc_clk_src = {
 117         .mult = 1,
 118         .div = 1,
 119         .hw.init = &(struct clk_init_data){
 120                 .name = "pcnoc_clk_src",
 121                 .parent_names = (const char *[]){
 122                         "pcnoc_bfdcd_clk_src"
 123                 },
 124                 .num_parents = 1,
 125                 .ops = &clk_fixed_factor_ops,
 126                 .flags = CLK_SET_RATE_PARENT,
 127         },
 128 };
 129
 130 static struct clk_branch gcc_sleep_clk_src = {
 131         .halt_reg = 0x30000,
 132         .clkr = {
 133                 .enable_reg = 0x30000,
 134                 .enable_mask = BIT(1),
 135                 .hw.init = &(struct clk_init_data){
 136                         .name = "gcc_sleep_clk_src",
 137                         .parent_names = (const char *[]){
 138                                 "sleep_clk"
 139                         },
 140                         .num_parents = 1,
 141                         .ops = &clk_branch2_ops,
 142                         .flags = CLK_IS_CRITICAL,
 143                 },
 144         },
 145 };
 146
 147 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 148         F(19200000, P_XO, 1, 0, 0),
 149         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 150         F(50000000, P_GPLL0, 16, 0, 0),
 151         { }
 152 };
 153
 154 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 155         .cmd_rcgr = 0x0200c,
 156         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 157         .hid_width = 5,
 158         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 159         .clkr.hw.init = &(struct clk_init_data){
 160                 .name = "blsp1_qup1_i2c_apps_clk_src",
 161                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 162                 .num_parents = 3,
 163                 .ops = &clk_rcg2_ops,
 164         },
 165 };
 166
 167 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 168         F(960000, P_XO, 10, 1, 2),
 169         F(4800000, P_XO, 4, 0, 0),
 170         F(9600000, P_XO, 2, 0, 0),
 171         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 172         F(16000000, P_GPLL0, 10, 1, 5),
 173         F(19200000, P_XO, 1, 0, 0),
 174         F(25000000, P_GPLL0, 16, 1, 2),
 175         F(50000000, P_GPLL0, 16, 0, 0),
 176         { }
 177 };
 178
 179 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 180         .cmd_rcgr = 0x02024,
 181         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 182         .mnd_width = 8,
 183         .hid_width = 5,
 184         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "blsp1_qup1_spi_apps_clk_src",
 187                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 188                 .num_parents = 3,
 189                 .ops = &clk_rcg2_ops,
 190         },
 191 };
 192
 193 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 194         .cmd_rcgr = 0x03000,
 195         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 196         .hid_width = 5,
 197         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .name = "blsp1_qup2_i2c_apps_clk_src",
 200                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 201                 .num_parents = 3,
 202                 .ops = &clk_rcg2_ops,
 203         },
 204 };
 205
 206 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 207         .cmd_rcgr = 0x03014,
 208         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 209         .mnd_width = 8,
 210         .hid_width = 5,
 211         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 212         .clkr.hw.init = &(struct clk_init_data){
 213                 .name = "blsp1_qup2_spi_apps_clk_src",
 214                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 215                 .num_parents = 3,
 216                 .ops = &clk_rcg2_ops,
 217         },
 218 };
 219
 220 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 221         .cmd_rcgr = 0x04000,
 222         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 223         .hid_width = 5,
 224         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 225         .clkr.hw.init = &(struct clk_init_data){
 226                 .name = "blsp1_qup3_i2c_apps_clk_src",
 227                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 228                 .num_parents = 3,
 229                 .ops = &clk_rcg2_ops,
 230         },
 231 };
 232
 233 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 234         .cmd_rcgr = 0x04014,
 235         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 236         .mnd_width = 8,
 237         .hid_width = 5,
 238         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "blsp1_qup3_spi_apps_clk_src",
 241                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 242                 .num_parents = 3,
 243                 .ops = &clk_rcg2_ops,
 244         },
 245 };
 246
 247 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 248         .cmd_rcgr = 0x05000,
 249         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 250         .hid_width = 5,
 251         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 252         .clkr.hw.init = &(struct clk_init_data){
 253                 .name = "blsp1_qup4_i2c_apps_clk_src",
 254                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 255                 .num_parents = 3,
 256                 .ops = &clk_rcg2_ops,
 257         },
 258 };
 259
 260 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 261         .cmd_rcgr = 0x05014,
 262         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 263         .mnd_width = 8,
 264         .hid_width = 5,
 265         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 266         .clkr.hw.init = &(struct clk_init_data){
 267                 .name = "blsp1_qup4_spi_apps_clk_src",
 268                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 269                 .num_parents = 3,
 270                 .ops = &clk_rcg2_ops,
 271         },
 272 };
 273
 274 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 275         .cmd_rcgr = 0x06000,
 276         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 277         .hid_width = 5,
 278         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 279         .clkr.hw.init = &(struct clk_init_data){
 280                 .name = "blsp1_qup5_i2c_apps_clk_src",
 281                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 282                 .num_parents = 3,
 283                 .ops = &clk_rcg2_ops,
 284         },
 285 };
 286
 287 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 288         .cmd_rcgr = 0x06014,
 289         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 290         .mnd_width = 8,
 291         .hid_width = 5,
 292         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 293         .clkr.hw.init = &(struct clk_init_data){
 294                 .name = "blsp1_qup5_spi_apps_clk_src",
 295                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 296                 .num_parents = 3,
 297                 .ops = &clk_rcg2_ops,
 298         },
 299 };
 300
 301 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 302         .cmd_rcgr = 0x07000,
 303         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 304         .hid_width = 5,
 305         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 306         .clkr.hw.init = &(struct clk_init_data){
 307                 .name = "blsp1_qup6_i2c_apps_clk_src",
 308                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 309                 .num_parents = 3,
 310                 .ops = &clk_rcg2_ops,
 311         },
 312 };
 313
 314 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 315         .cmd_rcgr = 0x07014,
 316         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 317         .mnd_width = 8,
 318         .hid_width = 5,
 319         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 320         .clkr.hw.init = &(struct clk_init_data){
 321                 .name = "blsp1_qup6_spi_apps_clk_src",
 322                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 323                 .num_parents = 3,
 324                 .ops = &clk_rcg2_ops,
 325         },
 326 };
 327
 328 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 329         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 330         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 331         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 332         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 333         F(19200000, P_XO, 1, 0, 0),
 334         F(24000000, P_GPLL0, 1, 3, 100),
 335         F(25000000, P_GPLL0, 16, 1, 2),
 336         F(32000000, P_GPLL0, 1, 1, 25),
 337         F(40000000, P_GPLL0, 1, 1, 20),
 338         F(46400000, P_GPLL0, 1, 29, 500),
 339         F(48000000, P_GPLL0, 1, 3, 50),
 340         F(51200000, P_GPLL0, 1, 8, 125),
 341         F(56000000, P_GPLL0, 1, 7, 100),
 342         F(58982400, P_GPLL0, 1, 1152, 15625),
 343         F(60000000, P_GPLL0, 1, 3, 40),
 344         F(64000000, P_GPLL0, 12.5, 1, 1),
 345         { }
 346 };
 347
 348 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 349         .cmd_rcgr = 0x02044,
 350         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 351         .mnd_width = 16,
 352         .hid_width = 5,
 353         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 354         .clkr.hw.init = &(struct clk_init_data){
 355                 .name = "blsp1_uart1_apps_clk_src",
 356                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 357                 .num_parents = 3,
 358                 .ops = &clk_rcg2_ops,
 359         },
 360 };
 361
 362 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 363         .cmd_rcgr = 0x03034,
 364         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 365         .mnd_width = 16,
 366         .hid_width = 5,
 367         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 368         .clkr.hw.init = &(struct clk_init_data){
 369                 .name = "blsp1_uart2_apps_clk_src",
 370                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 371                 .num_parents = 3,
 372                 .ops = &clk_rcg2_ops,
 373         },
 374 };
 375
 376 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 377         .cmd_rcgr = 0x04034,
 378         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 379         .mnd_width = 16,
 380         .hid_width = 5,
 381         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 382         .clkr.hw.init = &(struct clk_init_data){
 383                 .name = "blsp1_uart3_apps_clk_src",
 384                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 385                 .num_parents = 3,
 386                 .ops = &clk_rcg2_ops,
 387         },
 388 };
 389
 390 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 391         .cmd_rcgr = 0x05034,
 392         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 393         .mnd_width = 16,
 394         .hid_width = 5,
 395         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 396         .clkr.hw.init = &(struct clk_init_data){
 397                 .name = "blsp1_uart4_apps_clk_src",
 398                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 399                 .num_parents = 3,
 400                 .ops = &clk_rcg2_ops,
 401         },
 402 };
 403
 404 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 405         .cmd_rcgr = 0x06034,
 406         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 407         .mnd_width = 16,
 408         .hid_width = 5,
 409         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 410         .clkr.hw.init = &(struct clk_init_data){
 411                 .name = "blsp1_uart5_apps_clk_src",
 412                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 413                 .num_parents = 3,
 414                 .ops = &clk_rcg2_ops,
 415         },
 416 };
 417
 418 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 419         .cmd_rcgr = 0x07034,
 420         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 421         .mnd_width = 16,
 422         .hid_width = 5,
 423         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "blsp1_uart6_apps_clk_src",
 426                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 427                 .num_parents = 3,
 428                 .ops = &clk_rcg2_ops,
 429         },
 430 };
 431
 432 static struct clk_branch gcc_blsp1_ahb_clk = {
 433         .halt_reg = 0x01008,
 434         .clkr = {
 435                 .enable_reg = 0x01008,
 436                 .enable_mask = BIT(0),
 437                 .hw.init = &(struct clk_init_data){
 438                         .name = "gcc_blsp1_ahb_clk",
 439                         .parent_names = (const char *[]){
 440                                 "pcnoc_clk_src"
 441                         },
 442                         .num_parents = 1,
 443                         .flags = CLK_SET_RATE_PARENT,
 444                         .ops = &clk_branch2_ops,
 445                 },
 446         },
 447 };
 448
 449 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 450         .halt_reg = 0x02008,
 451         .clkr = {
 452                 .enable_reg = 0x02008,
 453                 .enable_mask = BIT(0),
 454                 .hw.init = &(struct clk_init_data){
 455                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 456                         .parent_names = (const char *[]){
 457                                 "blsp1_qup1_i2c_apps_clk_src"
 458                         },
 459                         .num_parents = 1,
 460                         .flags = CLK_SET_RATE_PARENT,
 461                         .ops = &clk_branch2_ops,
 462                 },
 463         },
 464 };
 465
 466 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 467         .halt_reg = 0x02004,
 468         .clkr = {
 469                 .enable_reg = 0x02004,
 470                 .enable_mask = BIT(0),
 471                 .hw.init = &(struct clk_init_data){
 472                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 473                         .parent_names = (const char *[]){
 474                                 "blsp1_qup1_spi_apps_clk_src"
 475                         },
 476                         .num_parents = 1,
 477                         .flags = CLK_SET_RATE_PARENT,
 478                         .ops = &clk_branch2_ops,
 479                 },
 480         },
 481 };
 482
 483 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 484         .halt_reg = 0x03010,
 485         .clkr = {
 486                 .enable_reg = 0x03010,
 487                 .enable_mask = BIT(0),
 488                 .hw.init = &(struct clk_init_data){
 489                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 490                         .parent_names = (const char *[]){
 491                                 "blsp1_qup2_i2c_apps_clk_src"
 492                         },
 493                         .num_parents = 1,
 494                         .flags = CLK_SET_RATE_PARENT,
 495                         .ops = &clk_branch2_ops,
 496                 },
 497         },
 498 };
 499
 500 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 501         .halt_reg = 0x0300c,
 502         .clkr = {
 503                 .enable_reg = 0x0300c,
 504                 .enable_mask = BIT(0),
 505                 .hw.init = &(struct clk_init_data){
 506                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 507                         .parent_names = (const char *[]){
 508                                 "blsp1_qup2_spi_apps_clk_src"
 509                         },
 510                         .num_parents = 1,
 511                         .flags = CLK_SET_RATE_PARENT,
 512                         .ops = &clk_branch2_ops,
 513                 },
 514         },
 515 };
 516
 517 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 518         .halt_reg = 0x04010,
 519         .clkr = {
 520                 .enable_reg = 0x04010,
 521                 .enable_mask = BIT(0),
 522                 .hw.init = &(struct clk_init_data){
 523                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
 524                         .parent_names = (const char *[]){
 525                                 "blsp1_qup3_i2c_apps_clk_src"
 526                         },
 527                         .num_parents = 1,
 528                         .flags = CLK_SET_RATE_PARENT,
 529                         .ops = &clk_branch2_ops,
 530                 },
 531         },
 532 };
 533
 534 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 535         .halt_reg = 0x0400c,
 536         .clkr = {
 537                 .enable_reg = 0x0400c,
 538                 .enable_mask = BIT(0),
 539                 .hw.init = &(struct clk_init_data){
 540                         .name = "gcc_blsp1_qup3_spi_apps_clk",
 541                         .parent_names = (const char *[]){
 542                                 "blsp1_qup3_spi_apps_clk_src"
 543                         },
 544                         .num_parents = 1,
 545                         .flags = CLK_SET_RATE_PARENT,
 546                         .ops = &clk_branch2_ops,
 547                 },
 548         },
 549 };
 550
 551 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 552         .halt_reg = 0x05010,
 553         .clkr = {
 554                 .enable_reg = 0x05010,
 555                 .enable_mask = BIT(0),
 556                 .hw.init = &(struct clk_init_data){
 557                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
 558                         .parent_names = (const char *[]){
 559                                 "blsp1_qup4_i2c_apps_clk_src"
 560                         },
 561                         .num_parents = 1,
 562                         .flags = CLK_SET_RATE_PARENT,
 563                         .ops = &clk_branch2_ops,
 564                 },
 565         },
 566 };
 567
 568 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 569         .halt_reg = 0x0500c,
 570         .clkr = {
 571                 .enable_reg = 0x0500c,
 572                 .enable_mask = BIT(0),
 573                 .hw.init = &(struct clk_init_data){
 574                         .name = "gcc_blsp1_qup4_spi_apps_clk",
 575                         .parent_names = (const char *[]){
 576                                 "blsp1_qup4_spi_apps_clk_src"
 577                         },
 578                         .num_parents = 1,
 579                         .flags = CLK_SET_RATE_PARENT,
 580                         .ops = &clk_branch2_ops,
 581                 },
 582         },
 583 };
 584
 585 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 586         .halt_reg = 0x06010,
 587         .clkr = {
 588                 .enable_reg = 0x06010,
 589                 .enable_mask = BIT(0),
 590                 .hw.init = &(struct clk_init_data){
 591                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
 592                         .parent_names = (const char *[]){
 593                                 "blsp1_qup5_i2c_apps_clk_src"
 594                         },
 595                         .num_parents = 1,
 596                         .flags = CLK_SET_RATE_PARENT,
 597                         .ops = &clk_branch2_ops,
 598                 },
 599         },
 600 };
 601
 602 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 603         .halt_reg = 0x0600c,
 604         .clkr = {
 605                 .enable_reg = 0x0600c,
 606                 .enable_mask = BIT(0),
 607                 .hw.init = &(struct clk_init_data){
 608                         .name = "gcc_blsp1_qup5_spi_apps_clk",
 609                         .parent_names = (const char *[]){
 610                                 "blsp1_qup5_spi_apps_clk_src"
 611                         },
 612                         .num_parents = 1,
 613                         .flags = CLK_SET_RATE_PARENT,
 614                         .ops = &clk_branch2_ops,
 615                 },
 616         },
 617 };
 618
 619 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 620         .halt_reg = 0x07010,
 621         .clkr = {
 622                 .enable_reg = 0x07010,
 623                 .enable_mask = BIT(0),
 624                 .hw.init = &(struct clk_init_data){
 625                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
 626                         .parent_names = (const char *[]){
 627                                 "blsp1_qup6_i2c_apps_clk_src"
 628                         },
 629                         .num_parents = 1,
 630                         .flags = CLK_SET_RATE_PARENT,
 631                         .ops = &clk_branch2_ops,
 632                 },
 633         },
 634 };
 635
 636 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 637         .halt_reg = 0x0700c,
 638         .clkr = {
 639                 .enable_reg = 0x0700c,
 640                 .enable_mask = BIT(0),
 641                 .hw.init = &(struct clk_init_data){
 642                         .name = "gcc_blsp1_qup6_spi_apps_clk",
 643                         .parent_names = (const char *[]){
 644                                 "blsp1_qup6_spi_apps_clk_src"
 645                         },
 646                         .num_parents = 1,
 647                         .flags = CLK_SET_RATE_PARENT,
 648                         .ops = &clk_branch2_ops,
 649                 },
 650         },
 651 };
 652
 653 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 654         .halt_reg = 0x0203c,
 655         .clkr = {
 656                 .enable_reg = 0x0203c,
 657                 .enable_mask = BIT(0),
 658                 .hw.init = &(struct clk_init_data){
 659                         .name = "gcc_blsp1_uart1_apps_clk",
 660                         .parent_names = (const char *[]){
 661                                 "blsp1_uart1_apps_clk_src"
 662                         },
 663                         .num_parents = 1,
 664                         .flags = CLK_SET_RATE_PARENT,
 665                         .ops = &clk_branch2_ops,
 666                 },
 667         },
 668 };
 669
 670 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 671         .halt_reg = 0x0302c,
 672         .clkr = {
 673                 .enable_reg = 0x0302c,
 674                 .enable_mask = BIT(0),
 675                 .hw.init = &(struct clk_init_data){
 676                         .name = "gcc_blsp1_uart2_apps_clk",
 677                         .parent_names = (const char *[]){
 678                                 "blsp1_uart2_apps_clk_src"
 679                         },
 680                         .num_parents = 1,
 681                         .flags = CLK_SET_RATE_PARENT,
 682                         .ops = &clk_branch2_ops,
 683                 },
 684         },
 685 };
 686
 687 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
 688         .halt_reg = 0x0402c,
 689         .clkr = {
 690                 .enable_reg = 0x0402c,
 691                 .enable_mask = BIT(0),
 692                 .hw.init = &(struct clk_init_data){
 693                         .name = "gcc_blsp1_uart3_apps_clk",
 694                         .parent_names = (const char *[]){
 695                                 "blsp1_uart3_apps_clk_src"
 696                         },
 697                         .num_parents = 1,
 698                         .flags = CLK_SET_RATE_PARENT,
 699                         .ops = &clk_branch2_ops,
 700                 },
 701         },
 702 };
 703
 704 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
 705         .halt_reg = 0x0502c,
 706         .clkr = {
 707                 .enable_reg = 0x0502c,
 708                 .enable_mask = BIT(0),
 709                 .hw.init = &(struct clk_init_data){
 710                         .name = "gcc_blsp1_uart4_apps_clk",
 711                         .parent_names = (const char *[]){
 712                                 "blsp1_uart4_apps_clk_src"
 713                         },
 714                         .num_parents = 1,
 715                         .flags = CLK_SET_RATE_PARENT,
 716                         .ops = &clk_branch2_ops,
 717                 },
 718         },
 719 };
 720
 721 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
 722         .halt_reg = 0x0602c,
 723         .clkr = {
 724                 .enable_reg = 0x0602c,
 725                 .enable_mask = BIT(0),
 726                 .hw.init = &(struct clk_init_data){
 727                         .name = "gcc_blsp1_uart5_apps_clk",
 728                         .parent_names = (const char *[]){
 729                                 "blsp1_uart5_apps_clk_src"
 730                         },
 731                         .num_parents = 1,
 732                         .flags = CLK_SET_RATE_PARENT,
 733                         .ops = &clk_branch2_ops,
 734                 },
 735         },
 736 };
 737
 738 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
 739         .halt_reg = 0x0702c,
 740         .clkr = {
 741                 .enable_reg = 0x0702c,
 742                 .enable_mask = BIT(0),
 743                 .hw.init = &(struct clk_init_data){
 744                         .name = "gcc_blsp1_uart6_apps_clk",
 745                         .parent_names = (const char *[]){
 746                                 "blsp1_uart6_apps_clk_src"
 747                         },
 748                         .num_parents = 1,
 749                         .flags = CLK_SET_RATE_PARENT,
 750                         .ops = &clk_branch2_ops,
 751                 },
 752         },
 753 };
 754
 755 static struct clk_branch gcc_prng_ahb_clk = {
 756         .halt_reg = 0x13004,
 757         .halt_check = BRANCH_HALT_VOTED,
 758         .clkr = {
 759                 .enable_reg = 0x0b004,
 760                 .enable_mask = BIT(8),
 761                 .hw.init = &(struct clk_init_data){
 762                         .name = "gcc_prng_ahb_clk",
 763                         .parent_names = (const char *[]){
 764                                 "pcnoc_clk_src"
 765                         },
 766                         .num_parents = 1,
 767                         .flags = CLK_SET_RATE_PARENT,
 768                         .ops = &clk_branch2_ops,
 769                 },
 770         },
 771 };
 772
 773 static struct clk_branch gcc_qpic_ahb_clk = {
 774         .halt_reg = 0x57024,
 775         .clkr = {
 776                 .enable_reg = 0x57024,
 777                 .enable_mask = BIT(0),
 778                 .hw.init = &(struct clk_init_data){
 779                         .name = "gcc_qpic_ahb_clk",
 780                         .parent_names = (const char *[]){
 781                                 "pcnoc_clk_src"
 782                         },
 783                         .num_parents = 1,
 784                         .flags = CLK_SET_RATE_PARENT,
 785                         .ops = &clk_branch2_ops,
 786                 },
 787         },
 788 };
 789
 790 static struct clk_branch gcc_qpic_clk = {
 791         .halt_reg = 0x57020,
 792         .clkr = {
 793                 .enable_reg = 0x57020,
 794                 .enable_mask = BIT(0),
 795                 .hw.init = &(struct clk_init_data){
 796                         .name = "gcc_qpic_clk",
 797                         .parent_names = (const char *[]){
 798                                 "pcnoc_clk_src"
 799                         },
 800                         .num_parents = 1,
 801                         .flags = CLK_SET_RATE_PARENT,
 802                         .ops = &clk_branch2_ops,
 803                 },
 804         },
 805 };
 806
 807 static struct clk_hw *gcc_ipq8074_hws[] = {
 808         &gpll0_out_main_div2.hw,
 809         &pcnoc_clk_src.hw,
 810 };
 811
 812 static struct clk_regmap *gcc_ipq8074_clks[] = {
 813         [GPLL0_MAIN] = &gpll0_main.clkr,
 814         [GPLL0] = &gpll0.clkr,
 815         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
 816         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
 817         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
 818         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
 819         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
 820         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
 821         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
 822         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
 823         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
 824         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
 825         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
 826         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
 827         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
 828         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
 829         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
 830         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
 831         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
 832         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
 833         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
 834         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
 835         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
 836         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
 837         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
 838         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
 839         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
 840         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
 841         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
 842         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
 843         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
 844         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
 845         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
 846         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
 847         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
 848         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
 849         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
 850         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
 851         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
 852         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
 853         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
 854         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
 855         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
 856         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
 857 };
 858
 859 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
 860         [GCC_BLSP1_BCR] = { 0x01000, 0 },
 861         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
 862         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
 863         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
 864         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
 865         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
 866         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
 867         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
 868         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
 869         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
 870         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
 871         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
 872         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
 873         [GCC_IMEM_BCR] = { 0x0e000, 0 },
 874         [GCC_SMMU_BCR] = { 0x12000, 0 },
 875         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
 876         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
 877         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
 878         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
 879         [GCC_PRNG_BCR] = { 0x13000, 0 },
 880         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
 881         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
 882         [GCC_WCSS_BCR] = { 0x18000, 0 },
 883         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
 884         [GCC_NSS_BCR] = { 0x19000, 0 },
 885         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
 886         [GCC_ADSS_BCR] = { 0x1c000, 0 },
 887         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
 888         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
 889         [GCC_PCNOC_BCR] = { 0x27018, 0 },
 890         [GCC_TCSR_BCR] = { 0x28000, 0 },
 891         [GCC_QDSS_BCR] = { 0x29000, 0 },
 892         [GCC_DCD_BCR] = { 0x2a000, 0 },
 893         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
 894         [GCC_MPM_BCR] = { 0x2c000, 0 },
 895         [GCC_SPMI_BCR] = { 0x2e000, 0 },
 896         [GCC_SPDM_BCR] = { 0x2f000, 0 },
 897         [GCC_RBCPR_BCR] = { 0x33000, 0 },
 898         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
 899         [GCC_TLMM_BCR] = { 0x34000, 0 },
 900         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
 901         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
 902         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
 903         [GCC_USB0_BCR] = { 0x3e070, 0 },
 904         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
 905         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
 906         [GCC_USB1_BCR] = { 0x3f070, 0 },
 907         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
 908         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
 909         [GCC_SDCC1_BCR] = { 0x42000, 0 },
 910         [GCC_SDCC2_BCR] = { 0x43000, 0 },
 911         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
 912         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
 913         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
 914         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
 915         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
 916         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
 917         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
 918         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
 919         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
 920         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
 921         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
 922         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
 923         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
 924         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
 925         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
 926         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
 927         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
 928         [GCC_QPIC_BCR] = { 0x57018, 0 },
 929         [GCC_MDIO_BCR] = { 0x58000, 0 },
 930         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
 931         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
 932         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
 933         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
 934         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
 935         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
 936         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
 937         [GCC_PCIE0_BCR] = { 0x75004, 0 },
 938         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
 939         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
 940         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
 941         [GCC_PCIE1_BCR] = { 0x76004, 0 },
 942         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
 943         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
 944         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
 945         [GCC_DCC_BCR] = { 0x77000, 0 },
 946         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
 947         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
 948         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
 949 };
 950
 951 static const struct of_device_id gcc_ipq8074_match_table[] = {
 952         { .compatible = "qcom,gcc-ipq8074" },
 953         { }
 954 };
 955 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
 956
 957 static const struct regmap_config gcc_ipq8074_regmap_config = {
 958         .reg_bits       = 32,
 959         .reg_stride     = 4,
 960         .val_bits       = 32,
 961         .max_register   = 0x7fffc,
 962         .fast_io        = true,
 963 };
 964
 965 static const struct qcom_cc_desc gcc_ipq8074_desc = {
 966         .config = &gcc_ipq8074_regmap_config,
 967         .clks = gcc_ipq8074_clks,
 968         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
 969         .resets = gcc_ipq8074_resets,
 970         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
 971 };
 972
 973 static int gcc_ipq8074_probe(struct platform_device *pdev)
 974 {
 975         int ret, i;
 976
 977         for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
 978                 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
 979                 if (ret)
 980                         return ret;
 981         }
 982
 983         return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
 984 }
 985
 986 static struct platform_driver gcc_ipq8074_driver = {
 987         .probe = gcc_ipq8074_probe,
 988         .driver = {
 989                 .name   = "qcom,gcc-ipq8074",
 990                 .of_match_table = gcc_ipq8074_match_table,
 991         },
 992 };
 993
 994 static int __init gcc_ipq8074_init(void)
 995 {
 996         return platform_driver_register(&gcc_ipq8074_driver);
 997 }
 998 core_initcall(gcc_ipq8074_init);
 999
1000 static void __exit gcc_ipq8074_exit(void)
1001 {
1002         platform_driver_unregister(&gcc_ipq8074_driver);
1003 }
1004 module_exit(gcc_ipq8074_exit);
1005
1006 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
1007 MODULE_LICENSE("GPL v2");
1008 MODULE_ALIAS("platform:gcc-ipq8074");