drivers/clk/qcom/gcc-ipq8074.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "clk-alpha-pll.h"
  31 #include "clk-regmap-divider.h"
  32 #include "clk-regmap-mux.h"
  33 #include "reset.h"
  34
  35 enum {
  36         P_XO,
  37         P_GPLL0,
  38         P_GPLL0_DIV2,
  39         P_GPLL2,
  40         P_GPLL4,
  41         P_GPLL6,
  42         P_SLEEP_CLK,
  43         P_PCIE20_PHY0_PIPE,
  44         P_PCIE20_PHY1_PIPE,
  45         P_USB3PHY_0_PIPE,
  46         P_USB3PHY_1_PIPE,
  47         P_UBI32_PLL,
  48         P_NSS_CRYPTO_PLL,
  49         P_BIAS_PLL,
  50         P_BIAS_PLL_NSS_NOC,
  51         P_UNIPHY0_RX,
  52         P_UNIPHY0_TX,
  53         P_UNIPHY1_RX,
  54         P_UNIPHY1_TX,
  55         P_UNIPHY2_RX,
  56         P_UNIPHY2_TX,
  57 };
  58
  59 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  60         "xo",
  61         "gpll0",
  62         "gpll0_out_main_div2",
  63 };
  64
  65 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  66         { P_XO, 0 },
  67         { P_GPLL0, 1 },
  68         { P_GPLL0_DIV2, 4 },
  69 };
  70
  71 static const char * const gcc_xo_gpll0[] = {
  72         "xo",
  73         "gpll0",
  74 };
  75
  76 static const struct parent_map gcc_xo_gpll0_map[] = {
  77         { P_XO, 0 },
  78         { P_GPLL0, 1 },
  79 };
  80
  81 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  82         "xo",
  83         "gpll0",
  84         "gpll2",
  85         "gpll0_out_main_div2",
  86 };
  87
  88 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  89         { P_XO, 0 },
  90         { P_GPLL0, 1 },
  91         { P_GPLL2, 2 },
  92         { P_GPLL0_DIV2, 4 },
  93 };
  94
  95 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  96         "xo",
  97         "gpll0",
  98         "sleep_clk",
  99 };
 100
 101 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
 102         { P_XO, 0 },
 103         { P_GPLL0, 2 },
 104         { P_SLEEP_CLK, 6 },
 105 };
 106
 107 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 108         "xo",
 109         "gpll6",
 110         "gpll0",
 111         "gpll0_out_main_div2",
 112 };
 113
 114 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 115         { P_XO, 0 },
 116         { P_GPLL6, 1 },
 117         { P_GPLL0, 3 },
 118         { P_GPLL0_DIV2, 4 },
 119 };
 120
 121 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 122         "xo",
 123         "gpll0_out_main_div2",
 124         "gpll0",
 125 };
 126
 127 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 128         { P_XO, 0 },
 129         { P_GPLL0_DIV2, 2 },
 130         { P_GPLL0, 1 },
 131 };
 132
 133 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 134         "usb3phy_0_cc_pipe_clk",
 135         "xo",
 136 };
 137
 138 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 139         { P_USB3PHY_0_PIPE, 0 },
 140         { P_XO, 2 },
 141 };
 142
 143 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 144         "usb3phy_1_cc_pipe_clk",
 145         "xo",
 146 };
 147
 148 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 149         { P_USB3PHY_1_PIPE, 0 },
 150         { P_XO, 2 },
 151 };
 152
 153 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 154         "pcie20_phy0_pipe_clk",
 155         "xo",
 156 };
 157
 158 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 159         { P_PCIE20_PHY0_PIPE, 0 },
 160         { P_XO, 2 },
 161 };
 162
 163 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 164         "pcie20_phy1_pipe_clk",
 165         "xo",
 166 };
 167
 168 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 169         { P_PCIE20_PHY1_PIPE, 0 },
 170         { P_XO, 2 },
 171 };
 172
 173 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 174         "xo",
 175         "gpll0",
 176         "gpll6",
 177         "gpll0_out_main_div2",
 178 };
 179
 180 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 181         { P_XO, 0 },
 182         { P_GPLL0, 1 },
 183         { P_GPLL6, 2 },
 184         { P_GPLL0_DIV2, 4 },
 185 };
 186
 187 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 188         "xo",
 189         "gpll0",
 190         "gpll6",
 191         "gpll0_out_main_div2",
 192 };
 193
 194 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 195         { P_XO, 0 },
 196         { P_GPLL0, 1 },
 197         { P_GPLL6, 2 },
 198         { P_GPLL0_DIV2, 3 },
 199 };
 200
 201 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 202         "xo",
 203         "bias_pll_nss_noc_clk",
 204         "gpll0",
 205         "gpll2",
 206 };
 207
 208 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 209         { P_XO, 0 },
 210         { P_BIAS_PLL_NSS_NOC, 1 },
 211         { P_GPLL0, 2 },
 212         { P_GPLL2, 3 },
 213 };
 214
 215 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 216         "xo",
 217         "nss_crypto_pll",
 218         "gpll0",
 219 };
 220
 221 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 222         { P_XO, 0 },
 223         { P_NSS_CRYPTO_PLL, 1 },
 224         { P_GPLL0, 2 },
 225 };
 226
 227 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 228         "xo",
 229         "ubi32_pll",
 230         "gpll0",
 231         "gpll2",
 232         "gpll4",
 233         "gpll6",
 234 };
 235
 236 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 237         { P_XO, 0 },
 238         { P_UBI32_PLL, 1 },
 239         { P_GPLL0, 2 },
 240         { P_GPLL2, 3 },
 241         { P_GPLL4, 4 },
 242         { P_GPLL6, 5 },
 243 };
 244
 245 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 246         "xo",
 247         "gpll0_out_main_div2",
 248 };
 249
 250 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 251         { P_XO, 0 },
 252         { P_GPLL0_DIV2, 1 },
 253 };
 254
 255 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 256         "xo",
 257         "bias_pll_cc_clk",
 258         "gpll0",
 259         "gpll4",
 260         "nss_crypto_pll",
 261         "ubi32_pll",
 262 };
 263
 264 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 265         { P_XO, 0 },
 266         { P_BIAS_PLL, 1 },
 267         { P_GPLL0, 2 },
 268         { P_GPLL4, 3 },
 269         { P_NSS_CRYPTO_PLL, 4 },
 270         { P_UBI32_PLL, 5 },
 271 };
 272
 273 static const char * const gcc_xo_gpll0_gpll4[] = {
 274         "xo",
 275         "gpll0",
 276         "gpll4",
 277 };
 278
 279 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 280         { P_XO, 0 },
 281         { P_GPLL0, 1 },
 282         { P_GPLL4, 2 },
 283 };
 284
 285 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 286         "xo",
 287         "uniphy0_gcc_rx_clk",
 288         "uniphy0_gcc_tx_clk",
 289         "ubi32_pll",
 290         "bias_pll_cc_clk",
 291 };
 292
 293 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 294         { P_XO, 0 },
 295         { P_UNIPHY0_RX, 1 },
 296         { P_UNIPHY0_TX, 2 },
 297         { P_UBI32_PLL, 5 },
 298         { P_BIAS_PLL, 6 },
 299 };
 300
 301 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 302         "xo",
 303         "uniphy0_gcc_tx_clk",
 304         "uniphy0_gcc_rx_clk",
 305         "ubi32_pll",
 306         "bias_pll_cc_clk",
 307 };
 308
 309 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 310         { P_XO, 0 },
 311         { P_UNIPHY0_TX, 1 },
 312         { P_UNIPHY0_RX, 2 },
 313         { P_UBI32_PLL, 5 },
 314         { P_BIAS_PLL, 6 },
 315 };
 316
 317 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 318         "xo",
 319         "uniphy0_gcc_rx_clk",
 320         "uniphy0_gcc_tx_clk",
 321         "uniphy1_gcc_rx_clk",
 322         "uniphy1_gcc_tx_clk",
 323         "ubi32_pll",
 324         "bias_pll_cc_clk",
 325 };
 326
 327 static const struct parent_map
 328 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 329         { P_XO, 0 },
 330         { P_UNIPHY0_RX, 1 },
 331         { P_UNIPHY0_TX, 2 },
 332         { P_UNIPHY1_RX, 3 },
 333         { P_UNIPHY1_TX, 4 },
 334         { P_UBI32_PLL, 5 },
 335         { P_BIAS_PLL, 6 },
 336 };
 337
 338 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 339         "xo",
 340         "uniphy0_gcc_tx_clk",
 341         "uniphy0_gcc_rx_clk",
 342         "uniphy1_gcc_tx_clk",
 343         "uniphy1_gcc_rx_clk",
 344         "ubi32_pll",
 345         "bias_pll_cc_clk",
 346 };
 347
 348 static const struct parent_map
 349 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 350         { P_XO, 0 },
 351         { P_UNIPHY0_TX, 1 },
 352         { P_UNIPHY0_RX, 2 },
 353         { P_UNIPHY1_TX, 3 },
 354         { P_UNIPHY1_RX, 4 },
 355         { P_UBI32_PLL, 5 },
 356         { P_BIAS_PLL, 6 },
 357 };
 358
 359 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 360         "xo",
 361         "uniphy2_gcc_rx_clk",
 362         "uniphy2_gcc_tx_clk",
 363         "ubi32_pll",
 364         "bias_pll_cc_clk",
 365 };
 366
 367 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
 368         { P_XO, 0 },
 369         { P_UNIPHY2_RX, 1 },
 370         { P_UNIPHY2_TX, 2 },
 371         { P_UBI32_PLL, 5 },
 372         { P_BIAS_PLL, 6 },
 373 };
 374
 375 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 376         "xo",
 377         "uniphy2_gcc_tx_clk",
 378         "uniphy2_gcc_rx_clk",
 379         "ubi32_pll",
 380         "bias_pll_cc_clk",
 381 };
 382
 383 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
 384         { P_XO, 0 },
 385         { P_UNIPHY2_TX, 1 },
 386         { P_UNIPHY2_RX, 2 },
 387         { P_UBI32_PLL, 5 },
 388         { P_BIAS_PLL, 6 },
 389 };
 390
 391 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
 392         "xo",
 393         "gpll0",
 394         "gpll6",
 395         "gpll0_out_main_div2",
 396         "sleep_clk",
 397 };
 398
 399 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
 400         { P_XO, 0 },
 401         { P_GPLL0, 1 },
 402         { P_GPLL6, 2 },
 403         { P_GPLL0_DIV2, 4 },
 404         { P_SLEEP_CLK, 6 },
 405 };
 406
 407 static struct clk_alpha_pll gpll0_main = {
 408         .offset = 0x21000,
 409         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 410         .clkr = {
 411                 .enable_reg = 0x0b000,
 412                 .enable_mask = BIT(0),
 413                 .hw.init = &(struct clk_init_data){
 414                         .name = "gpll0_main",
 415                         .parent_names = (const char *[]){
 416                                 "xo"
 417                         },
 418                         .num_parents = 1,
 419                         .ops = &clk_alpha_pll_ops,
 420                 },
 421         },
 422 };
 423
 424 static struct clk_fixed_factor gpll0_out_main_div2 = {
 425         .mult = 1,
 426         .div = 2,
 427         .hw.init = &(struct clk_init_data){
 428                 .name = "gpll0_out_main_div2",
 429                 .parent_names = (const char *[]){
 430                         "gpll0_main"
 431                 },
 432                 .num_parents = 1,
 433                 .ops = &clk_fixed_factor_ops,
 434                 .flags = CLK_SET_RATE_PARENT,
 435         },
 436 };
 437
 438 static struct clk_alpha_pll_postdiv gpll0 = {
 439         .offset = 0x21000,
 440         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 441         .width = 4,
 442         .clkr.hw.init = &(struct clk_init_data){
 443                 .name = "gpll0",
 444                 .parent_names = (const char *[]){
 445                         "gpll0_main"
 446                 },
 447                 .num_parents = 1,
 448                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 449         },
 450 };
 451
 452 static struct clk_alpha_pll gpll2_main = {
 453         .offset = 0x4a000,
 454         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 455         .clkr = {
 456                 .enable_reg = 0x0b000,
 457                 .enable_mask = BIT(2),
 458                 .hw.init = &(struct clk_init_data){
 459                         .name = "gpll2_main",
 460                         .parent_names = (const char *[]){
 461                                 "xo"
 462                         },
 463                         .num_parents = 1,
 464                         .ops = &clk_alpha_pll_ops,
 465                         .flags = CLK_IS_CRITICAL,
 466                 },
 467         },
 468 };
 469
 470 static struct clk_alpha_pll_postdiv gpll2 = {
 471         .offset = 0x4a000,
 472         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 473         .width = 4,
 474         .clkr.hw.init = &(struct clk_init_data){
 475                 .name = "gpll2",
 476                 .parent_names = (const char *[]){
 477                         "gpll2_main"
 478                 },
 479                 .num_parents = 1,
 480                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 481                 .flags = CLK_SET_RATE_PARENT,
 482         },
 483 };
 484
 485 static struct clk_alpha_pll gpll4_main = {
 486         .offset = 0x24000,
 487         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 488         .clkr = {
 489                 .enable_reg = 0x0b000,
 490                 .enable_mask = BIT(5),
 491                 .hw.init = &(struct clk_init_data){
 492                         .name = "gpll4_main",
 493                         .parent_names = (const char *[]){
 494                                 "xo"
 495                         },
 496                         .num_parents = 1,
 497                         .ops = &clk_alpha_pll_ops,
 498                         .flags = CLK_IS_CRITICAL,
 499                 },
 500         },
 501 };
 502
 503 static struct clk_alpha_pll_postdiv gpll4 = {
 504         .offset = 0x24000,
 505         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 506         .width = 4,
 507         .clkr.hw.init = &(struct clk_init_data){
 508                 .name = "gpll4",
 509                 .parent_names = (const char *[]){
 510                         "gpll4_main"
 511                 },
 512                 .num_parents = 1,
 513                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 514                 .flags = CLK_SET_RATE_PARENT,
 515         },
 516 };
 517
 518 static struct clk_alpha_pll gpll6_main = {
 519         .offset = 0x37000,
 520         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 521         .flags = SUPPORTS_DYNAMIC_UPDATE,
 522         .clkr = {
 523                 .enable_reg = 0x0b000,
 524                 .enable_mask = BIT(7),
 525                 .hw.init = &(struct clk_init_data){
 526                         .name = "gpll6_main",
 527                         .parent_names = (const char *[]){
 528                                 "xo"
 529                         },
 530                         .num_parents = 1,
 531                         .ops = &clk_alpha_pll_ops,
 532                         .flags = CLK_IS_CRITICAL,
 533                 },
 534         },
 535 };
 536
 537 static struct clk_alpha_pll_postdiv gpll6 = {
 538         .offset = 0x37000,
 539         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 540         .width = 2,
 541         .clkr.hw.init = &(struct clk_init_data){
 542                 .name = "gpll6",
 543                 .parent_names = (const char *[]){
 544                         "gpll6_main"
 545                 },
 546                 .num_parents = 1,
 547                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 548                 .flags = CLK_SET_RATE_PARENT,
 549         },
 550 };
 551
 552 static struct clk_fixed_factor gpll6_out_main_div2 = {
 553         .mult = 1,
 554         .div = 2,
 555         .hw.init = &(struct clk_init_data){
 556                 .name = "gpll6_out_main_div2",
 557                 .parent_names = (const char *[]){
 558                         "gpll6_main"
 559                 },
 560                 .num_parents = 1,
 561                 .ops = &clk_fixed_factor_ops,
 562                 .flags = CLK_SET_RATE_PARENT,
 563         },
 564 };
 565
 566 static struct clk_alpha_pll ubi32_pll_main = {
 567         .offset = 0x25000,
 568         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 569         .flags = SUPPORTS_DYNAMIC_UPDATE,
 570         .clkr = {
 571                 .enable_reg = 0x0b000,
 572                 .enable_mask = BIT(6),
 573                 .hw.init = &(struct clk_init_data){
 574                         .name = "ubi32_pll_main",
 575                         .parent_names = (const char *[]){
 576                                 "xo"
 577                         },
 578                         .num_parents = 1,
 579                         .ops = &clk_alpha_pll_huayra_ops,
 580                 },
 581         },
 582 };
 583
 584 static struct clk_alpha_pll_postdiv ubi32_pll = {
 585         .offset = 0x25000,
 586         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 587         .width = 2,
 588         .clkr.hw.init = &(struct clk_init_data){
 589                 .name = "ubi32_pll",
 590                 .parent_names = (const char *[]){
 591                         "ubi32_pll_main"
 592                 },
 593                 .num_parents = 1,
 594                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 595                 .flags = CLK_SET_RATE_PARENT,
 596         },
 597 };
 598
 599 static struct clk_alpha_pll nss_crypto_pll_main = {
 600         .offset = 0x22000,
 601         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 602         .clkr = {
 603                 .enable_reg = 0x0b000,
 604                 .enable_mask = BIT(4),
 605                 .hw.init = &(struct clk_init_data){
 606                         .name = "nss_crypto_pll_main",
 607                         .parent_names = (const char *[]){
 608                                 "xo"
 609                         },
 610                         .num_parents = 1,
 611                         .ops = &clk_alpha_pll_ops,
 612                 },
 613         },
 614 };
 615
 616 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 617         .offset = 0x22000,
 618         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 619         .width = 4,
 620         .clkr.hw.init = &(struct clk_init_data){
 621                 .name = "nss_crypto_pll",
 622                 .parent_names = (const char *[]){
 623                         "nss_crypto_pll_main"
 624                 },
 625                 .num_parents = 1,
 626                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 627                 .flags = CLK_SET_RATE_PARENT,
 628         },
 629 };
 630
 631 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 632         F(19200000, P_XO, 1, 0, 0),
 633         F(50000000, P_GPLL0, 16, 0, 0),
 634         F(100000000, P_GPLL0, 8, 0, 0),
 635         { }
 636 };
 637
 638 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 639         .cmd_rcgr = 0x27000,
 640         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 641         .hid_width = 5,
 642         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 643         .clkr.hw.init = &(struct clk_init_data){
 644                 .name = "pcnoc_bfdcd_clk_src",
 645                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 646                 .num_parents = 3,
 647                 .ops = &clk_rcg2_ops,
 648                 .flags = CLK_IS_CRITICAL,
 649         },
 650 };
 651
 652 static struct clk_fixed_factor pcnoc_clk_src = {
 653         .mult = 1,
 654         .div = 1,
 655         .hw.init = &(struct clk_init_data){
 656                 .name = "pcnoc_clk_src",
 657                 .parent_names = (const char *[]){
 658                         "pcnoc_bfdcd_clk_src"
 659                 },
 660                 .num_parents = 1,
 661                 .ops = &clk_fixed_factor_ops,
 662                 .flags = CLK_SET_RATE_PARENT,
 663         },
 664 };
 665
 666 static struct clk_branch gcc_sleep_clk_src = {
 667         .halt_reg = 0x30000,
 668         .clkr = {
 669                 .enable_reg = 0x30000,
 670                 .enable_mask = BIT(1),
 671                 .hw.init = &(struct clk_init_data){
 672                         .name = "gcc_sleep_clk_src",
 673                         .parent_names = (const char *[]){
 674                                 "sleep_clk"
 675                         },
 676                         .num_parents = 1,
 677                         .ops = &clk_branch2_ops,
 678                 },
 679         },
 680 };
 681
 682 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 683         F(19200000, P_XO, 1, 0, 0),
 684         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 685         F(50000000, P_GPLL0, 16, 0, 0),
 686         { }
 687 };
 688
 689 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 690         .cmd_rcgr = 0x0200c,
 691         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 692         .hid_width = 5,
 693         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 694         .clkr.hw.init = &(struct clk_init_data){
 695                 .name = "blsp1_qup1_i2c_apps_clk_src",
 696                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 697                 .num_parents = 3,
 698                 .ops = &clk_rcg2_ops,
 699         },
 700 };
 701
 702 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 703         F(960000, P_XO, 10, 1, 2),
 704         F(4800000, P_XO, 4, 0, 0),
 705         F(9600000, P_XO, 2, 0, 0),
 706         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 707         F(16000000, P_GPLL0, 10, 1, 5),
 708         F(19200000, P_XO, 1, 0, 0),
 709         F(25000000, P_GPLL0, 16, 1, 2),
 710         F(50000000, P_GPLL0, 16, 0, 0),
 711         { }
 712 };
 713
 714 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 715         .cmd_rcgr = 0x02024,
 716         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 717         .mnd_width = 8,
 718         .hid_width = 5,
 719         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 720         .clkr.hw.init = &(struct clk_init_data){
 721                 .name = "blsp1_qup1_spi_apps_clk_src",
 722                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 723                 .num_parents = 3,
 724                 .ops = &clk_rcg2_ops,
 725         },
 726 };
 727
 728 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 729         .cmd_rcgr = 0x03000,
 730         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 731         .hid_width = 5,
 732         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 733         .clkr.hw.init = &(struct clk_init_data){
 734                 .name = "blsp1_qup2_i2c_apps_clk_src",
 735                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 736                 .num_parents = 3,
 737                 .ops = &clk_rcg2_ops,
 738         },
 739 };
 740
 741 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 742         .cmd_rcgr = 0x03014,
 743         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 744         .mnd_width = 8,
 745         .hid_width = 5,
 746         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 747         .clkr.hw.init = &(struct clk_init_data){
 748                 .name = "blsp1_qup2_spi_apps_clk_src",
 749                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 750                 .num_parents = 3,
 751                 .ops = &clk_rcg2_ops,
 752         },
 753 };
 754
 755 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 756         .cmd_rcgr = 0x04000,
 757         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 758         .hid_width = 5,
 759         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "blsp1_qup3_i2c_apps_clk_src",
 762                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 763                 .num_parents = 3,
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 769         .cmd_rcgr = 0x04014,
 770         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 771         .mnd_width = 8,
 772         .hid_width = 5,
 773         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "blsp1_qup3_spi_apps_clk_src",
 776                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 777                 .num_parents = 3,
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 783         .cmd_rcgr = 0x05000,
 784         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 785         .hid_width = 5,
 786         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 787         .clkr.hw.init = &(struct clk_init_data){
 788                 .name = "blsp1_qup4_i2c_apps_clk_src",
 789                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 790                 .num_parents = 3,
 791                 .ops = &clk_rcg2_ops,
 792         },
 793 };
 794
 795 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 796         .cmd_rcgr = 0x05014,
 797         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 798         .mnd_width = 8,
 799         .hid_width = 5,
 800         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup4_spi_apps_clk_src",
 803                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 804                 .num_parents = 3,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 810         .cmd_rcgr = 0x06000,
 811         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 812         .hid_width = 5,
 813         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "blsp1_qup5_i2c_apps_clk_src",
 816                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 817                 .num_parents = 3,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 823         .cmd_rcgr = 0x06014,
 824         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 825         .mnd_width = 8,
 826         .hid_width = 5,
 827         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 828         .clkr.hw.init = &(struct clk_init_data){
 829                 .name = "blsp1_qup5_spi_apps_clk_src",
 830                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 831                 .num_parents = 3,
 832                 .ops = &clk_rcg2_ops,
 833         },
 834 };
 835
 836 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 837         .cmd_rcgr = 0x07000,
 838         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 839         .hid_width = 5,
 840         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 841         .clkr.hw.init = &(struct clk_init_data){
 842                 .name = "blsp1_qup6_i2c_apps_clk_src",
 843                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 844                 .num_parents = 3,
 845                 .ops = &clk_rcg2_ops,
 846         },
 847 };
 848
 849 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 850         .cmd_rcgr = 0x07014,
 851         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 852         .mnd_width = 8,
 853         .hid_width = 5,
 854         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 855         .clkr.hw.init = &(struct clk_init_data){
 856                 .name = "blsp1_qup6_spi_apps_clk_src",
 857                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 858                 .num_parents = 3,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 864         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 865         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 866         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 867         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 868         F(19200000, P_XO, 1, 0, 0),
 869         F(24000000, P_GPLL0, 1, 3, 100),
 870         F(25000000, P_GPLL0, 16, 1, 2),
 871         F(32000000, P_GPLL0, 1, 1, 25),
 872         F(40000000, P_GPLL0, 1, 1, 20),
 873         F(46400000, P_GPLL0, 1, 29, 500),
 874         F(48000000, P_GPLL0, 1, 3, 50),
 875         F(51200000, P_GPLL0, 1, 8, 125),
 876         F(56000000, P_GPLL0, 1, 7, 100),
 877         F(58982400, P_GPLL0, 1, 1152, 15625),
 878         F(60000000, P_GPLL0, 1, 3, 40),
 879         F(64000000, P_GPLL0, 12.5, 1, 1),
 880         { }
 881 };
 882
 883 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 884         .cmd_rcgr = 0x02044,
 885         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 886         .mnd_width = 16,
 887         .hid_width = 5,
 888         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 889         .clkr.hw.init = &(struct clk_init_data){
 890                 .name = "blsp1_uart1_apps_clk_src",
 891                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 892                 .num_parents = 3,
 893                 .ops = &clk_rcg2_ops,
 894         },
 895 };
 896
 897 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 898         .cmd_rcgr = 0x03034,
 899         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 900         .mnd_width = 16,
 901         .hid_width = 5,
 902         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 903         .clkr.hw.init = &(struct clk_init_data){
 904                 .name = "blsp1_uart2_apps_clk_src",
 905                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 906                 .num_parents = 3,
 907                 .ops = &clk_rcg2_ops,
 908         },
 909 };
 910
 911 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 912         .cmd_rcgr = 0x04034,
 913         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 914         .mnd_width = 16,
 915         .hid_width = 5,
 916         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 917         .clkr.hw.init = &(struct clk_init_data){
 918                 .name = "blsp1_uart3_apps_clk_src",
 919                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 920                 .num_parents = 3,
 921                 .ops = &clk_rcg2_ops,
 922         },
 923 };
 924
 925 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 926         .cmd_rcgr = 0x05034,
 927         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 928         .mnd_width = 16,
 929         .hid_width = 5,
 930         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 931         .clkr.hw.init = &(struct clk_init_data){
 932                 .name = "blsp1_uart4_apps_clk_src",
 933                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 934                 .num_parents = 3,
 935                 .ops = &clk_rcg2_ops,
 936         },
 937 };
 938
 939 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 940         .cmd_rcgr = 0x06034,
 941         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 942         .mnd_width = 16,
 943         .hid_width = 5,
 944         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 945         .clkr.hw.init = &(struct clk_init_data){
 946                 .name = "blsp1_uart5_apps_clk_src",
 947                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 948                 .num_parents = 3,
 949                 .ops = &clk_rcg2_ops,
 950         },
 951 };
 952
 953 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 954         .cmd_rcgr = 0x07034,
 955         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 956         .mnd_width = 16,
 957         .hid_width = 5,
 958         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 959         .clkr.hw.init = &(struct clk_init_data){
 960                 .name = "blsp1_uart6_apps_clk_src",
 961                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 962                 .num_parents = 3,
 963                 .ops = &clk_rcg2_ops,
 964         },
 965 };
 966
 967 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 968         F(19200000, P_XO, 1, 0, 0),
 969         F(200000000, P_GPLL0, 4, 0, 0),
 970         { }
 971 };
 972
 973 static struct clk_rcg2 pcie0_axi_clk_src = {
 974         .cmd_rcgr = 0x75054,
 975         .freq_tbl = ftbl_pcie_axi_clk_src,
 976         .hid_width = 5,
 977         .parent_map = gcc_xo_gpll0_map,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "pcie0_axi_clk_src",
 980                 .parent_names = gcc_xo_gpll0,
 981                 .num_parents = 2,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 987         F(19200000, P_XO, 1, 0, 0),
 988 };
 989
 990 static struct clk_rcg2 pcie0_aux_clk_src = {
 991         .cmd_rcgr = 0x75024,
 992         .freq_tbl = ftbl_pcie_aux_clk_src,
 993         .mnd_width = 16,
 994         .hid_width = 5,
 995         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 996         .clkr.hw.init = &(struct clk_init_data){
 997                 .name = "pcie0_aux_clk_src",
 998                 .parent_names = gcc_xo_gpll0_sleep_clk,
 999                 .num_parents = 3,
1000                 .ops = &clk_rcg2_ops,
1001         },
1002 };
1003
1004 static struct clk_regmap_mux pcie0_pipe_clk_src = {
1005         .reg = 0x7501c,
1006         .shift = 8,
1007         .width = 2,
1008         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1009         .clkr = {
1010                 .hw.init = &(struct clk_init_data){
1011                         .name = "pcie0_pipe_clk_src",
1012                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1013                         .num_parents = 2,
1014                         .ops = &clk_regmap_mux_closest_ops,
1015                         .flags = CLK_SET_RATE_PARENT,
1016                 },
1017         },
1018 };
1019
1020 static struct clk_rcg2 pcie1_axi_clk_src = {
1021         .cmd_rcgr = 0x76054,
1022         .freq_tbl = ftbl_pcie_axi_clk_src,
1023         .hid_width = 5,
1024         .parent_map = gcc_xo_gpll0_map,
1025         .clkr.hw.init = &(struct clk_init_data){
1026                 .name = "pcie1_axi_clk_src",
1027                 .parent_names = gcc_xo_gpll0,
1028                 .num_parents = 2,
1029                 .ops = &clk_rcg2_ops,
1030         },
1031 };
1032
1033 static struct clk_rcg2 pcie1_aux_clk_src = {
1034         .cmd_rcgr = 0x76024,
1035         .freq_tbl = ftbl_pcie_aux_clk_src,
1036         .mnd_width = 16,
1037         .hid_width = 5,
1038         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1039         .clkr.hw.init = &(struct clk_init_data){
1040                 .name = "pcie1_aux_clk_src",
1041                 .parent_names = gcc_xo_gpll0_sleep_clk,
1042                 .num_parents = 3,
1043                 .ops = &clk_rcg2_ops,
1044         },
1045 };
1046
1047 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1048         .reg = 0x7601c,
1049         .shift = 8,
1050         .width = 2,
1051         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1052         .clkr = {
1053                 .hw.init = &(struct clk_init_data){
1054                         .name = "pcie1_pipe_clk_src",
1055                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1056                         .num_parents = 2,
1057                         .ops = &clk_regmap_mux_closest_ops,
1058                         .flags = CLK_SET_RATE_PARENT,
1059                 },
1060         },
1061 };
1062
1063 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1064         F(144000, P_XO, 16, 3, 25),
1065         F(400000, P_XO, 12, 1, 4),
1066         F(24000000, P_GPLL2, 12, 1, 4),
1067         F(48000000, P_GPLL2, 12, 1, 2),
1068         F(96000000, P_GPLL2, 12, 0, 0),
1069         F(177777778, P_GPLL0, 4.5, 0, 0),
1070         F(192000000, P_GPLL2, 6, 0, 0),
1071         F(384000000, P_GPLL2, 3, 0, 0),
1072         { }
1073 };
1074
1075 static struct clk_rcg2 sdcc1_apps_clk_src = {
1076         .cmd_rcgr = 0x42004,
1077         .freq_tbl = ftbl_sdcc_apps_clk_src,
1078         .mnd_width = 8,
1079         .hid_width = 5,
1080         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1081         .clkr.hw.init = &(struct clk_init_data){
1082                 .name = "sdcc1_apps_clk_src",
1083                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1084                 .num_parents = 4,
1085                 .ops = &clk_rcg2_floor_ops,
1086         },
1087 };
1088
1089 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1090         F(19200000, P_XO, 1, 0, 0),
1091         F(160000000, P_GPLL0, 5, 0, 0),
1092         F(308570000, P_GPLL6, 3.5, 0, 0),
1093 };
1094
1095 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1096         .cmd_rcgr = 0x5d000,
1097         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1098         .mnd_width = 8,
1099         .hid_width = 5,
1100         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1101         .clkr.hw.init = &(struct clk_init_data){
1102                 .name = "sdcc1_ice_core_clk_src",
1103                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1104                 .num_parents = 4,
1105                 .ops = &clk_rcg2_ops,
1106         },
1107 };
1108
1109 static struct clk_rcg2 sdcc2_apps_clk_src = {
1110         .cmd_rcgr = 0x43004,
1111         .freq_tbl = ftbl_sdcc_apps_clk_src,
1112         .mnd_width = 8,
1113         .hid_width = 5,
1114         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1115         .clkr.hw.init = &(struct clk_init_data){
1116                 .name = "sdcc2_apps_clk_src",
1117                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1118                 .num_parents = 4,
1119                 .ops = &clk_rcg2_ops,
1120         },
1121 };
1122
1123 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1124         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1125         F(100000000, P_GPLL0, 8, 0, 0),
1126         F(133330000, P_GPLL0, 6, 0, 0),
1127         { }
1128 };
1129
1130 static struct clk_rcg2 usb0_master_clk_src = {
1131         .cmd_rcgr = 0x3e00c,
1132         .freq_tbl = ftbl_usb_master_clk_src,
1133         .mnd_width = 8,
1134         .hid_width = 5,
1135         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1136         .clkr.hw.init = &(struct clk_init_data){
1137                 .name = "usb0_master_clk_src",
1138                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1139                 .num_parents = 3,
1140                 .ops = &clk_rcg2_ops,
1141         },
1142 };
1143
1144 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1145         F(19200000, P_XO, 1, 0, 0),
1146         { }
1147 };
1148
1149 static struct clk_rcg2 usb0_aux_clk_src = {
1150         .cmd_rcgr = 0x3e05c,
1151         .freq_tbl = ftbl_usb_aux_clk_src,
1152         .mnd_width = 16,
1153         .hid_width = 5,
1154         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1155         .clkr.hw.init = &(struct clk_init_data){
1156                 .name = "usb0_aux_clk_src",
1157                 .parent_names = gcc_xo_gpll0_sleep_clk,
1158                 .num_parents = 3,
1159                 .ops = &clk_rcg2_ops,
1160         },
1161 };
1162
1163 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1164         F(19200000, P_XO, 1, 0, 0),
1165         F(20000000, P_GPLL6, 6, 1, 9),
1166         F(60000000, P_GPLL6, 6, 1, 3),
1167         { }
1168 };
1169
1170 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1171         .cmd_rcgr = 0x3e020,
1172         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1173         .mnd_width = 8,
1174         .hid_width = 5,
1175         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1176         .clkr.hw.init = &(struct clk_init_data){
1177                 .name = "usb0_mock_utmi_clk_src",
1178                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1179                 .num_parents = 4,
1180                 .ops = &clk_rcg2_ops,
1181         },
1182 };
1183
1184 static struct clk_regmap_mux usb0_pipe_clk_src = {
1185         .reg = 0x3e048,
1186         .shift = 8,
1187         .width = 2,
1188         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1189         .clkr = {
1190                 .hw.init = &(struct clk_init_data){
1191                         .name = "usb0_pipe_clk_src",
1192                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1193                         .num_parents = 2,
1194                         .ops = &clk_regmap_mux_closest_ops,
1195                         .flags = CLK_SET_RATE_PARENT,
1196                 },
1197         },
1198 };
1199
1200 static struct clk_rcg2 usb1_master_clk_src = {
1201         .cmd_rcgr = 0x3f00c,
1202         .freq_tbl = ftbl_usb_master_clk_src,
1203         .mnd_width = 8,
1204         .hid_width = 5,
1205         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1206         .clkr.hw.init = &(struct clk_init_data){
1207                 .name = "usb1_master_clk_src",
1208                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1209                 .num_parents = 3,
1210                 .ops = &clk_rcg2_ops,
1211         },
1212 };
1213
1214 static struct clk_rcg2 usb1_aux_clk_src = {
1215         .cmd_rcgr = 0x3f05c,
1216         .freq_tbl = ftbl_usb_aux_clk_src,
1217         .mnd_width = 16,
1218         .hid_width = 5,
1219         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1220         .clkr.hw.init = &(struct clk_init_data){
1221                 .name = "usb1_aux_clk_src",
1222                 .parent_names = gcc_xo_gpll0_sleep_clk,
1223                 .num_parents = 3,
1224                 .ops = &clk_rcg2_ops,
1225         },
1226 };
1227
1228 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1229         .cmd_rcgr = 0x3f020,
1230         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1231         .mnd_width = 8,
1232         .hid_width = 5,
1233         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1234         .clkr.hw.init = &(struct clk_init_data){
1235                 .name = "usb1_mock_utmi_clk_src",
1236                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1237                 .num_parents = 4,
1238                 .ops = &clk_rcg2_ops,
1239         },
1240 };
1241
1242 static struct clk_regmap_mux usb1_pipe_clk_src = {
1243         .reg = 0x3f048,
1244         .shift = 8,
1245         .width = 2,
1246         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1247         .clkr = {
1248                 .hw.init = &(struct clk_init_data){
1249                         .name = "usb1_pipe_clk_src",
1250                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1251                         .num_parents = 2,
1252                         .ops = &clk_regmap_mux_closest_ops,
1253                         .flags = CLK_SET_RATE_PARENT,
1254                 },
1255         },
1256 };
1257
1258 static struct clk_branch gcc_xo_clk_src = {
1259         .halt_reg = 0x30018,
1260         .clkr = {
1261                 .enable_reg = 0x30018,
1262                 .enable_mask = BIT(1),
1263                 .hw.init = &(struct clk_init_data){
1264                         .name = "gcc_xo_clk_src",
1265                         .parent_names = (const char *[]){
1266                                 "xo"
1267                         },
1268                         .num_parents = 1,
1269                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1270                         .ops = &clk_branch2_ops,
1271                 },
1272         },
1273 };
1274
1275 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1276         .mult = 1,
1277         .div = 4,
1278         .hw.init = &(struct clk_init_data){
1279                 .name = "gcc_xo_div4_clk_src",
1280                 .parent_names = (const char *[]){
1281                         "gcc_xo_clk_src"
1282                 },
1283                 .num_parents = 1,
1284                 .ops = &clk_fixed_factor_ops,
1285                 .flags = CLK_SET_RATE_PARENT,
1286         },
1287 };
1288
1289 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1290         F(19200000, P_XO, 1, 0, 0),
1291         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1292         F(100000000, P_GPLL0, 8, 0, 0),
1293         F(133333333, P_GPLL0, 6, 0, 0),
1294         F(160000000, P_GPLL0, 5, 0, 0),
1295         F(200000000, P_GPLL0, 4, 0, 0),
1296         F(266666667, P_GPLL0, 3, 0, 0),
1297         { }
1298 };
1299
1300 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1301         .cmd_rcgr = 0x26004,
1302         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1303         .hid_width = 5,
1304         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1305         .clkr.hw.init = &(struct clk_init_data){
1306                 .name = "system_noc_bfdcd_clk_src",
1307                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1308                 .num_parents = 4,
1309                 .ops = &clk_rcg2_ops,
1310                 .flags = CLK_IS_CRITICAL,
1311         },
1312 };
1313
1314 static struct clk_fixed_factor system_noc_clk_src = {
1315         .mult = 1,
1316         .div = 1,
1317         .hw.init = &(struct clk_init_data){
1318                 .name = "system_noc_clk_src",
1319                 .parent_names = (const char *[]){
1320                         "system_noc_bfdcd_clk_src"
1321                 },
1322                 .num_parents = 1,
1323                 .ops = &clk_fixed_factor_ops,
1324                 .flags = CLK_SET_RATE_PARENT,
1325         },
1326 };
1327
1328 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1329         F(19200000, P_XO, 1, 0, 0),
1330         F(200000000, P_GPLL0, 4, 0, 0),
1331         { }
1332 };
1333
1334 static struct clk_rcg2 nss_ce_clk_src = {
1335         .cmd_rcgr = 0x68098,
1336         .freq_tbl = ftbl_nss_ce_clk_src,
1337         .hid_width = 5,
1338         .parent_map = gcc_xo_gpll0_map,
1339         .clkr.hw.init = &(struct clk_init_data){
1340                 .name = "nss_ce_clk_src",
1341                 .parent_names = gcc_xo_gpll0,
1342                 .num_parents = 2,
1343                 .ops = &clk_rcg2_ops,
1344         },
1345 };
1346
1347 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1348         F(19200000, P_XO, 1, 0, 0),
1349         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1350         { }
1351 };
1352
1353 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1354         .cmd_rcgr = 0x68088,
1355         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1356         .hid_width = 5,
1357         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1358         .clkr.hw.init = &(struct clk_init_data){
1359                 .name = "nss_noc_bfdcd_clk_src",
1360                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1361                 .num_parents = 4,
1362                 .ops = &clk_rcg2_ops,
1363         },
1364 };
1365
1366 static struct clk_fixed_factor nss_noc_clk_src = {
1367         .mult = 1,
1368         .div = 1,
1369         .hw.init = &(struct clk_init_data){
1370                 .name = "nss_noc_clk_src",
1371                 .parent_names = (const char *[]){
1372                         "nss_noc_bfdcd_clk_src"
1373                 },
1374                 .num_parents = 1,
1375                 .ops = &clk_fixed_factor_ops,
1376                 .flags = CLK_SET_RATE_PARENT,
1377         },
1378 };
1379
1380 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1381         F(19200000, P_XO, 1, 0, 0),
1382         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1383         { }
1384 };
1385
1386 static struct clk_rcg2 nss_crypto_clk_src = {
1387         .cmd_rcgr = 0x68144,
1388         .freq_tbl = ftbl_nss_crypto_clk_src,
1389         .mnd_width = 16,
1390         .hid_width = 5,
1391         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1392         .clkr.hw.init = &(struct clk_init_data){
1393                 .name = "nss_crypto_clk_src",
1394                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1395                 .num_parents = 3,
1396                 .ops = &clk_rcg2_ops,
1397         },
1398 };
1399
1400 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1401         F(19200000, P_XO, 1, 0, 0),
1402         F(187200000, P_UBI32_PLL, 8, 0, 0),
1403         F(748800000, P_UBI32_PLL, 2, 0, 0),
1404         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1405         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1406         { }
1407 };
1408
1409 static struct clk_rcg2 nss_ubi0_clk_src = {
1410         .cmd_rcgr = 0x68104,
1411         .freq_tbl = ftbl_nss_ubi_clk_src,
1412         .hid_width = 5,
1413         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1414         .clkr.hw.init = &(struct clk_init_data){
1415                 .name = "nss_ubi0_clk_src",
1416                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1417                 .num_parents = 6,
1418                 .ops = &clk_rcg2_ops,
1419                 .flags = CLK_SET_RATE_PARENT,
1420         },
1421 };
1422
1423 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1424         .reg = 0x68118,
1425         .shift = 0,
1426         .width = 4,
1427         .clkr = {
1428                 .hw.init = &(struct clk_init_data){
1429                         .name = "nss_ubi0_div_clk_src",
1430                         .parent_names = (const char *[]){
1431                                 "nss_ubi0_clk_src"
1432                         },
1433                         .num_parents = 1,
1434                         .ops = &clk_regmap_div_ro_ops,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                 },
1437         },
1438 };
1439
1440 static struct clk_rcg2 nss_ubi1_clk_src = {
1441         .cmd_rcgr = 0x68124,
1442         .freq_tbl = ftbl_nss_ubi_clk_src,
1443         .hid_width = 5,
1444         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1445         .clkr.hw.init = &(struct clk_init_data){
1446                 .name = "nss_ubi1_clk_src",
1447                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1448                 .num_parents = 6,
1449                 .ops = &clk_rcg2_ops,
1450                 .flags = CLK_SET_RATE_PARENT,
1451         },
1452 };
1453
1454 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1455         .reg = 0x68138,
1456         .shift = 0,
1457         .width = 4,
1458         .clkr = {
1459                 .hw.init = &(struct clk_init_data){
1460                         .name = "nss_ubi1_div_clk_src",
1461                         .parent_names = (const char *[]){
1462                                 "nss_ubi1_clk_src"
1463                         },
1464                         .num_parents = 1,
1465                         .ops = &clk_regmap_div_ro_ops,
1466                         .flags = CLK_SET_RATE_PARENT,
1467                 },
1468         },
1469 };
1470
1471 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1472         F(19200000, P_XO, 1, 0, 0),
1473         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1474         { }
1475 };
1476
1477 static struct clk_rcg2 ubi_mpt_clk_src = {
1478         .cmd_rcgr = 0x68090,
1479         .freq_tbl = ftbl_ubi_mpt_clk_src,
1480         .hid_width = 5,
1481         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1482         .clkr.hw.init = &(struct clk_init_data){
1483                 .name = "ubi_mpt_clk_src",
1484                 .parent_names = gcc_xo_gpll0_out_main_div2,
1485                 .num_parents = 2,
1486                 .ops = &clk_rcg2_ops,
1487         },
1488 };
1489
1490 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1491         F(19200000, P_XO, 1, 0, 0),
1492         F(400000000, P_GPLL0, 2, 0, 0),
1493         { }
1494 };
1495
1496 static struct clk_rcg2 nss_imem_clk_src = {
1497         .cmd_rcgr = 0x68158,
1498         .freq_tbl = ftbl_nss_imem_clk_src,
1499         .hid_width = 5,
1500         .parent_map = gcc_xo_gpll0_gpll4_map,
1501         .clkr.hw.init = &(struct clk_init_data){
1502                 .name = "nss_imem_clk_src",
1503                 .parent_names = gcc_xo_gpll0_gpll4,
1504                 .num_parents = 3,
1505                 .ops = &clk_rcg2_ops,
1506         },
1507 };
1508
1509 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1510         F(19200000, P_XO, 1, 0, 0),
1511         F(300000000, P_BIAS_PLL, 1, 0, 0),
1512         { }
1513 };
1514
1515 static struct clk_rcg2 nss_ppe_clk_src = {
1516         .cmd_rcgr = 0x68080,
1517         .freq_tbl = ftbl_nss_ppe_clk_src,
1518         .hid_width = 5,
1519         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1520         .clkr.hw.init = &(struct clk_init_data){
1521                 .name = "nss_ppe_clk_src",
1522                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1523                 .num_parents = 6,
1524                 .ops = &clk_rcg2_ops,
1525         },
1526 };
1527
1528 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1529         .mult = 1,
1530         .div = 4,
1531         .hw.init = &(struct clk_init_data){
1532                 .name = "nss_ppe_cdiv_clk_src",
1533                 .parent_names = (const char *[]){
1534                         "nss_ppe_clk_src"
1535                 },
1536                 .num_parents = 1,
1537                 .ops = &clk_fixed_factor_ops,
1538                 .flags = CLK_SET_RATE_PARENT,
1539         },
1540 };
1541
1542 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1543         F(19200000, P_XO, 1, 0, 0),
1544         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1545         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1546         { }
1547 };
1548
1549 static struct clk_rcg2 nss_port1_rx_clk_src = {
1550         .cmd_rcgr = 0x68020,
1551         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1552         .hid_width = 5,
1553         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1554         .clkr.hw.init = &(struct clk_init_data){
1555                 .name = "nss_port1_rx_clk_src",
1556                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1557                 .num_parents = 5,
1558                 .ops = &clk_rcg2_ops,
1559         },
1560 };
1561
1562 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1563         .reg = 0x68400,
1564         .shift = 0,
1565         .width = 4,
1566         .clkr = {
1567                 .hw.init = &(struct clk_init_data){
1568                         .name = "nss_port1_rx_div_clk_src",
1569                         .parent_names = (const char *[]){
1570                                 "nss_port1_rx_clk_src"
1571                         },
1572                         .num_parents = 1,
1573                         .ops = &clk_regmap_div_ops,
1574                         .flags = CLK_SET_RATE_PARENT,
1575                 },
1576         },
1577 };
1578
1579 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1580         F(19200000, P_XO, 1, 0, 0),
1581         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1582         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1583         { }
1584 };
1585
1586 static struct clk_rcg2 nss_port1_tx_clk_src = {
1587         .cmd_rcgr = 0x68028,
1588         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1589         .hid_width = 5,
1590         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1591         .clkr.hw.init = &(struct clk_init_data){
1592                 .name = "nss_port1_tx_clk_src",
1593                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1594                 .num_parents = 5,
1595                 .ops = &clk_rcg2_ops,
1596         },
1597 };
1598
1599 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1600         .reg = 0x68404,
1601         .shift = 0,
1602         .width = 4,
1603         .clkr = {
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "nss_port1_tx_div_clk_src",
1606                         .parent_names = (const char *[]){
1607                                 "nss_port1_tx_clk_src"
1608                         },
1609                         .num_parents = 1,
1610                         .ops = &clk_regmap_div_ops,
1611                         .flags = CLK_SET_RATE_PARENT,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_rcg2 nss_port2_rx_clk_src = {
1617         .cmd_rcgr = 0x68030,
1618         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1619         .hid_width = 5,
1620         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1621         .clkr.hw.init = &(struct clk_init_data){
1622                 .name = "nss_port2_rx_clk_src",
1623                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1624                 .num_parents = 5,
1625                 .ops = &clk_rcg2_ops,
1626         },
1627 };
1628
1629 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1630         .reg = 0x68410,
1631         .shift = 0,
1632         .width = 4,
1633         .clkr = {
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "nss_port2_rx_div_clk_src",
1636                         .parent_names = (const char *[]){
1637                                 "nss_port2_rx_clk_src"
1638                         },
1639                         .num_parents = 1,
1640                         .ops = &clk_regmap_div_ops,
1641                         .flags = CLK_SET_RATE_PARENT,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_rcg2 nss_port2_tx_clk_src = {
1647         .cmd_rcgr = 0x68038,
1648         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1649         .hid_width = 5,
1650         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1651         .clkr.hw.init = &(struct clk_init_data){
1652                 .name = "nss_port2_tx_clk_src",
1653                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1654                 .num_parents = 5,
1655                 .ops = &clk_rcg2_ops,
1656         },
1657 };
1658
1659 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1660         .reg = 0x68414,
1661         .shift = 0,
1662         .width = 4,
1663         .clkr = {
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "nss_port2_tx_div_clk_src",
1666                         .parent_names = (const char *[]){
1667                                 "nss_port2_tx_clk_src"
1668                         },
1669                         .num_parents = 1,
1670                         .ops = &clk_regmap_div_ops,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                 },
1673         },
1674 };
1675
1676 static struct clk_rcg2 nss_port3_rx_clk_src = {
1677         .cmd_rcgr = 0x68040,
1678         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1679         .hid_width = 5,
1680         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1681         .clkr.hw.init = &(struct clk_init_data){
1682                 .name = "nss_port3_rx_clk_src",
1683                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1684                 .num_parents = 5,
1685                 .ops = &clk_rcg2_ops,
1686         },
1687 };
1688
1689 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1690         .reg = 0x68420,
1691         .shift = 0,
1692         .width = 4,
1693         .clkr = {
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "nss_port3_rx_div_clk_src",
1696                         .parent_names = (const char *[]){
1697                                 "nss_port3_rx_clk_src"
1698                         },
1699                         .num_parents = 1,
1700                         .ops = &clk_regmap_div_ops,
1701                         .flags = CLK_SET_RATE_PARENT,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_rcg2 nss_port3_tx_clk_src = {
1707         .cmd_rcgr = 0x68048,
1708         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1709         .hid_width = 5,
1710         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1711         .clkr.hw.init = &(struct clk_init_data){
1712                 .name = "nss_port3_tx_clk_src",
1713                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1714                 .num_parents = 5,
1715                 .ops = &clk_rcg2_ops,
1716         },
1717 };
1718
1719 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1720         .reg = 0x68424,
1721         .shift = 0,
1722         .width = 4,
1723         .clkr = {
1724                 .hw.init = &(struct clk_init_data){
1725                         .name = "nss_port3_tx_div_clk_src",
1726                         .parent_names = (const char *[]){
1727                                 "nss_port3_tx_clk_src"
1728                         },
1729                         .num_parents = 1,
1730                         .ops = &clk_regmap_div_ops,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_rcg2 nss_port4_rx_clk_src = {
1737         .cmd_rcgr = 0x68050,
1738         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1739         .hid_width = 5,
1740         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1741         .clkr.hw.init = &(struct clk_init_data){
1742                 .name = "nss_port4_rx_clk_src",
1743                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1744                 .num_parents = 5,
1745                 .ops = &clk_rcg2_ops,
1746         },
1747 };
1748
1749 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1750         .reg = 0x68430,
1751         .shift = 0,
1752         .width = 4,
1753         .clkr = {
1754                 .hw.init = &(struct clk_init_data){
1755                         .name = "nss_port4_rx_div_clk_src",
1756                         .parent_names = (const char *[]){
1757                                 "nss_port4_rx_clk_src"
1758                         },
1759                         .num_parents = 1,
1760                         .ops = &clk_regmap_div_ops,
1761                         .flags = CLK_SET_RATE_PARENT,
1762                 },
1763         },
1764 };
1765
1766 static struct clk_rcg2 nss_port4_tx_clk_src = {
1767         .cmd_rcgr = 0x68058,
1768         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1769         .hid_width = 5,
1770         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1771         .clkr.hw.init = &(struct clk_init_data){
1772                 .name = "nss_port4_tx_clk_src",
1773                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1774                 .num_parents = 5,
1775                 .ops = &clk_rcg2_ops,
1776         },
1777 };
1778
1779 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1780         .reg = 0x68434,
1781         .shift = 0,
1782         .width = 4,
1783         .clkr = {
1784                 .hw.init = &(struct clk_init_data){
1785                         .name = "nss_port4_tx_div_clk_src",
1786                         .parent_names = (const char *[]){
1787                                 "nss_port4_tx_clk_src"
1788                         },
1789                         .num_parents = 1,
1790                         .ops = &clk_regmap_div_ops,
1791                         .flags = CLK_SET_RATE_PARENT,
1792                 },
1793         },
1794 };
1795
1796 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1797         F(19200000, P_XO, 1, 0, 0),
1798         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1799         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1800         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1801         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1802         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1803         { }
1804 };
1805
1806 static struct clk_rcg2 nss_port5_rx_clk_src = {
1807         .cmd_rcgr = 0x68060,
1808         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1809         .hid_width = 5,
1810         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1811         .clkr.hw.init = &(struct clk_init_data){
1812                 .name = "nss_port5_rx_clk_src",
1813                 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1814                 .num_parents = 7,
1815                 .ops = &clk_rcg2_ops,
1816         },
1817 };
1818
1819 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1820         .reg = 0x68440,
1821         .shift = 0,
1822         .width = 4,
1823         .clkr = {
1824                 .hw.init = &(struct clk_init_data){
1825                         .name = "nss_port5_rx_div_clk_src",
1826                         .parent_names = (const char *[]){
1827                                 "nss_port5_rx_clk_src"
1828                         },
1829                         .num_parents = 1,
1830                         .ops = &clk_regmap_div_ops,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                 },
1833         },
1834 };
1835
1836 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1837         F(19200000, P_XO, 1, 0, 0),
1838         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1839         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1840         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1841         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1842         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1843         { }
1844 };
1845
1846 static struct clk_rcg2 nss_port5_tx_clk_src = {
1847         .cmd_rcgr = 0x68068,
1848         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1849         .hid_width = 5,
1850         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1851         .clkr.hw.init = &(struct clk_init_data){
1852                 .name = "nss_port5_tx_clk_src",
1853                 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1854                 .num_parents = 7,
1855                 .ops = &clk_rcg2_ops,
1856         },
1857 };
1858
1859 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1860         .reg = 0x68444,
1861         .shift = 0,
1862         .width = 4,
1863         .clkr = {
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "nss_port5_tx_div_clk_src",
1866                         .parent_names = (const char *[]){
1867                                 "nss_port5_tx_clk_src"
1868                         },
1869                         .num_parents = 1,
1870                         .ops = &clk_regmap_div_ops,
1871                         .flags = CLK_SET_RATE_PARENT,
1872                 },
1873         },
1874 };
1875
1876 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1877         F(19200000, P_XO, 1, 0, 0),
1878         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1879         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1880         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1881         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1882         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1883         { }
1884 };
1885
1886 static struct clk_rcg2 nss_port6_rx_clk_src = {
1887         .cmd_rcgr = 0x68070,
1888         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1889         .hid_width = 5,
1890         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1891         .clkr.hw.init = &(struct clk_init_data){
1892                 .name = "nss_port6_rx_clk_src",
1893                 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1894                 .num_parents = 5,
1895                 .ops = &clk_rcg2_ops,
1896         },
1897 };
1898
1899 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1900         .reg = 0x68450,
1901         .shift = 0,
1902         .width = 4,
1903         .clkr = {
1904                 .hw.init = &(struct clk_init_data){
1905                         .name = "nss_port6_rx_div_clk_src",
1906                         .parent_names = (const char *[]){
1907                                 "nss_port6_rx_clk_src"
1908                         },
1909                         .num_parents = 1,
1910                         .ops = &clk_regmap_div_ops,
1911                         .flags = CLK_SET_RATE_PARENT,
1912                 },
1913         },
1914 };
1915
1916 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1917         F(19200000, P_XO, 1, 0, 0),
1918         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1920         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1921         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1922         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1923         { }
1924 };
1925
1926 static struct clk_rcg2 nss_port6_tx_clk_src = {
1927         .cmd_rcgr = 0x68078,
1928         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1929         .hid_width = 5,
1930         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1931         .clkr.hw.init = &(struct clk_init_data){
1932                 .name = "nss_port6_tx_clk_src",
1933                 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1934                 .num_parents = 5,
1935                 .ops = &clk_rcg2_ops,
1936         },
1937 };
1938
1939 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1940         .reg = 0x68454,
1941         .shift = 0,
1942         .width = 4,
1943         .clkr = {
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "nss_port6_tx_div_clk_src",
1946                         .parent_names = (const char *[]){
1947                                 "nss_port6_tx_clk_src"
1948                         },
1949                         .num_parents = 1,
1950                         .ops = &clk_regmap_div_ops,
1951                         .flags = CLK_SET_RATE_PARENT,
1952                 },
1953         },
1954 };
1955
1956 static struct freq_tbl ftbl_crypto_clk_src[] = {
1957         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1958         F(80000000, P_GPLL0, 10, 0, 0),
1959         F(100000000, P_GPLL0, 8, 0, 0),
1960         F(160000000, P_GPLL0, 5, 0, 0),
1961         { }
1962 };
1963
1964 static struct clk_rcg2 crypto_clk_src = {
1965         .cmd_rcgr = 0x16004,
1966         .freq_tbl = ftbl_crypto_clk_src,
1967         .hid_width = 5,
1968         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1969         .clkr.hw.init = &(struct clk_init_data){
1970                 .name = "crypto_clk_src",
1971                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1972                 .num_parents = 3,
1973                 .ops = &clk_rcg2_ops,
1974         },
1975 };
1976
1977 static struct freq_tbl ftbl_gp_clk_src[] = {
1978         F(19200000, P_XO, 1, 0, 0),
1979         { }
1980 };
1981
1982 static struct clk_rcg2 gp1_clk_src = {
1983         .cmd_rcgr = 0x08004,
1984         .freq_tbl = ftbl_gp_clk_src,
1985         .mnd_width = 8,
1986         .hid_width = 5,
1987         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1988         .clkr.hw.init = &(struct clk_init_data){
1989                 .name = "gp1_clk_src",
1990                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1991                 .num_parents = 5,
1992                 .ops = &clk_rcg2_ops,
1993         },
1994 };
1995
1996 static struct clk_rcg2 gp2_clk_src = {
1997         .cmd_rcgr = 0x09004,
1998         .freq_tbl = ftbl_gp_clk_src,
1999         .mnd_width = 8,
2000         .hid_width = 5,
2001         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2002         .clkr.hw.init = &(struct clk_init_data){
2003                 .name = "gp2_clk_src",
2004                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2005                 .num_parents = 5,
2006                 .ops = &clk_rcg2_ops,
2007         },
2008 };
2009
2010 static struct clk_rcg2 gp3_clk_src = {
2011         .cmd_rcgr = 0x0a004,
2012         .freq_tbl = ftbl_gp_clk_src,
2013         .mnd_width = 8,
2014         .hid_width = 5,
2015         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2016         .clkr.hw.init = &(struct clk_init_data){
2017                 .name = "gp3_clk_src",
2018                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2019                 .num_parents = 5,
2020                 .ops = &clk_rcg2_ops,
2021         },
2022 };
2023
2024 static struct clk_branch gcc_blsp1_ahb_clk = {
2025         .halt_reg = 0x01008,
2026         .clkr = {
2027                 .enable_reg = 0x01008,
2028                 .enable_mask = BIT(0),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "gcc_blsp1_ahb_clk",
2031                         .parent_names = (const char *[]){
2032                                 "pcnoc_clk_src"
2033                         },
2034                         .num_parents = 1,
2035                         .flags = CLK_SET_RATE_PARENT,
2036                         .ops = &clk_branch2_ops,
2037                 },
2038         },
2039 };
2040
2041 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2042         .halt_reg = 0x02008,
2043         .clkr = {
2044                 .enable_reg = 0x02008,
2045                 .enable_mask = BIT(0),
2046                 .hw.init = &(struct clk_init_data){
2047                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2048                         .parent_names = (const char *[]){
2049                                 "blsp1_qup1_i2c_apps_clk_src"
2050                         },
2051                         .num_parents = 1,
2052                         .flags = CLK_SET_RATE_PARENT,
2053                         .ops = &clk_branch2_ops,
2054                 },
2055         },
2056 };
2057
2058 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2059         .halt_reg = 0x02004,
2060         .clkr = {
2061                 .enable_reg = 0x02004,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(struct clk_init_data){
2064                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2065                         .parent_names = (const char *[]){
2066                                 "blsp1_qup1_spi_apps_clk_src"
2067                         },
2068                         .num_parents = 1,
2069                         .flags = CLK_SET_RATE_PARENT,
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2076         .halt_reg = 0x03010,
2077         .clkr = {
2078                 .enable_reg = 0x03010,
2079                 .enable_mask = BIT(0),
2080                 .hw.init = &(struct clk_init_data){
2081                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2082                         .parent_names = (const char *[]){
2083                                 "blsp1_qup2_i2c_apps_clk_src"
2084                         },
2085                         .num_parents = 1,
2086                         .flags = CLK_SET_RATE_PARENT,
2087                         .ops = &clk_branch2_ops,
2088                 },
2089         },
2090 };
2091
2092 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2093         .halt_reg = 0x0300c,
2094         .clkr = {
2095                 .enable_reg = 0x0300c,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data){
2098                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2099                         .parent_names = (const char *[]){
2100                                 "blsp1_qup2_spi_apps_clk_src"
2101                         },
2102                         .num_parents = 1,
2103                         .flags = CLK_SET_RATE_PARENT,
2104                         .ops = &clk_branch2_ops,
2105                 },
2106         },
2107 };
2108
2109 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2110         .halt_reg = 0x04010,
2111         .clkr = {
2112                 .enable_reg = 0x04010,
2113                 .enable_mask = BIT(0),
2114                 .hw.init = &(struct clk_init_data){
2115                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2116                         .parent_names = (const char *[]){
2117                                 "blsp1_qup3_i2c_apps_clk_src"
2118                         },
2119                         .num_parents = 1,
2120                         .flags = CLK_SET_RATE_PARENT,
2121                         .ops = &clk_branch2_ops,
2122                 },
2123         },
2124 };
2125
2126 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2127         .halt_reg = 0x0400c,
2128         .clkr = {
2129                 .enable_reg = 0x0400c,
2130                 .enable_mask = BIT(0),
2131                 .hw.init = &(struct clk_init_data){
2132                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2133                         .parent_names = (const char *[]){
2134                                 "blsp1_qup3_spi_apps_clk_src"
2135                         },
2136                         .num_parents = 1,
2137                         .flags = CLK_SET_RATE_PARENT,
2138                         .ops = &clk_branch2_ops,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2144         .halt_reg = 0x05010,
2145         .clkr = {
2146                 .enable_reg = 0x05010,
2147                 .enable_mask = BIT(0),
2148                 .hw.init = &(struct clk_init_data){
2149                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2150                         .parent_names = (const char *[]){
2151                                 "blsp1_qup4_i2c_apps_clk_src"
2152                         },
2153                         .num_parents = 1,
2154                         .flags = CLK_SET_RATE_PARENT,
2155                         .ops = &clk_branch2_ops,
2156                 },
2157         },
2158 };
2159
2160 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2161         .halt_reg = 0x0500c,
2162         .clkr = {
2163                 .enable_reg = 0x0500c,
2164                 .enable_mask = BIT(0),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2167                         .parent_names = (const char *[]){
2168                                 "blsp1_qup4_spi_apps_clk_src"
2169                         },
2170                         .num_parents = 1,
2171                         .flags = CLK_SET_RATE_PARENT,
2172                         .ops = &clk_branch2_ops,
2173                 },
2174         },
2175 };
2176
2177 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2178         .halt_reg = 0x06010,
2179         .clkr = {
2180                 .enable_reg = 0x06010,
2181                 .enable_mask = BIT(0),
2182                 .hw.init = &(struct clk_init_data){
2183                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2184                         .parent_names = (const char *[]){
2185                                 "blsp1_qup5_i2c_apps_clk_src"
2186                         },
2187                         .num_parents = 1,
2188                         .flags = CLK_SET_RATE_PARENT,
2189                         .ops = &clk_branch2_ops,
2190                 },
2191         },
2192 };
2193
2194 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2195         .halt_reg = 0x0600c,
2196         .clkr = {
2197                 .enable_reg = 0x0600c,
2198                 .enable_mask = BIT(0),
2199                 .hw.init = &(struct clk_init_data){
2200                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2201                         .parent_names = (const char *[]){
2202                                 "blsp1_qup5_spi_apps_clk_src"
2203                         },
2204                         .num_parents = 1,
2205                         .flags = CLK_SET_RATE_PARENT,
2206                         .ops = &clk_branch2_ops,
2207                 },
2208         },
2209 };
2210
2211 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2212         .halt_reg = 0x07010,
2213         .clkr = {
2214                 .enable_reg = 0x07010,
2215                 .enable_mask = BIT(0),
2216                 .hw.init = &(struct clk_init_data){
2217                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2218                         .parent_names = (const char *[]){
2219                                 "blsp1_qup6_i2c_apps_clk_src"
2220                         },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2229         .halt_reg = 0x0700c,
2230         .clkr = {
2231                 .enable_reg = 0x0700c,
2232                 .enable_mask = BIT(0),
2233                 .hw.init = &(struct clk_init_data){
2234                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2235                         .parent_names = (const char *[]){
2236                                 "blsp1_qup6_spi_apps_clk_src"
2237                         },
2238                         .num_parents = 1,
2239                         .flags = CLK_SET_RATE_PARENT,
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2246         .halt_reg = 0x0203c,
2247         .clkr = {
2248                 .enable_reg = 0x0203c,
2249                 .enable_mask = BIT(0),
2250                 .hw.init = &(struct clk_init_data){
2251                         .name = "gcc_blsp1_uart1_apps_clk",
2252                         .parent_names = (const char *[]){
2253                                 "blsp1_uart1_apps_clk_src"
2254                         },
2255                         .num_parents = 1,
2256                         .flags = CLK_SET_RATE_PARENT,
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2263         .halt_reg = 0x0302c,
2264         .clkr = {
2265                 .enable_reg = 0x0302c,
2266                 .enable_mask = BIT(0),
2267                 .hw.init = &(struct clk_init_data){
2268                         .name = "gcc_blsp1_uart2_apps_clk",
2269                         .parent_names = (const char *[]){
2270                                 "blsp1_uart2_apps_clk_src"
2271                         },
2272                         .num_parents = 1,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                         .ops = &clk_branch2_ops,
2275                 },
2276         },
2277 };
2278
2279 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2280         .halt_reg = 0x0402c,
2281         .clkr = {
2282                 .enable_reg = 0x0402c,
2283                 .enable_mask = BIT(0),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "gcc_blsp1_uart3_apps_clk",
2286                         .parent_names = (const char *[]){
2287                                 "blsp1_uart3_apps_clk_src"
2288                         },
2289                         .num_parents = 1,
2290                         .flags = CLK_SET_RATE_PARENT,
2291                         .ops = &clk_branch2_ops,
2292                 },
2293         },
2294 };
2295
2296 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2297         .halt_reg = 0x0502c,
2298         .clkr = {
2299                 .enable_reg = 0x0502c,
2300                 .enable_mask = BIT(0),
2301                 .hw.init = &(struct clk_init_data){
2302                         .name = "gcc_blsp1_uart4_apps_clk",
2303                         .parent_names = (const char *[]){
2304                                 "blsp1_uart4_apps_clk_src"
2305                         },
2306                         .num_parents = 1,
2307                         .flags = CLK_SET_RATE_PARENT,
2308                         .ops = &clk_branch2_ops,
2309                 },
2310         },
2311 };
2312
2313 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2314         .halt_reg = 0x0602c,
2315         .clkr = {
2316                 .enable_reg = 0x0602c,
2317                 .enable_mask = BIT(0),
2318                 .hw.init = &(struct clk_init_data){
2319                         .name = "gcc_blsp1_uart5_apps_clk",
2320                         .parent_names = (const char *[]){
2321                                 "blsp1_uart5_apps_clk_src"
2322                         },
2323                         .num_parents = 1,
2324                         .flags = CLK_SET_RATE_PARENT,
2325                         .ops = &clk_branch2_ops,
2326                 },
2327         },
2328 };
2329
2330 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2331         .halt_reg = 0x0702c,
2332         .clkr = {
2333                 .enable_reg = 0x0702c,
2334                 .enable_mask = BIT(0),
2335                 .hw.init = &(struct clk_init_data){
2336                         .name = "gcc_blsp1_uart6_apps_clk",
2337                         .parent_names = (const char *[]){
2338                                 "blsp1_uart6_apps_clk_src"
2339                         },
2340                         .num_parents = 1,
2341                         .flags = CLK_SET_RATE_PARENT,
2342                         .ops = &clk_branch2_ops,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch gcc_prng_ahb_clk = {
2348         .halt_reg = 0x13004,
2349         .halt_check = BRANCH_HALT_VOTED,
2350         .clkr = {
2351                 .enable_reg = 0x0b004,
2352                 .enable_mask = BIT(8),
2353                 .hw.init = &(struct clk_init_data){
2354                         .name = "gcc_prng_ahb_clk",
2355                         .parent_names = (const char *[]){
2356                                 "pcnoc_clk_src"
2357                         },
2358                         .num_parents = 1,
2359                         .flags = CLK_SET_RATE_PARENT,
2360                         .ops = &clk_branch2_ops,
2361                 },
2362         },
2363 };
2364
2365 static struct clk_branch gcc_qpic_ahb_clk = {
2366         .halt_reg = 0x57024,
2367         .clkr = {
2368                 .enable_reg = 0x57024,
2369                 .enable_mask = BIT(0),
2370                 .hw.init = &(struct clk_init_data){
2371                         .name = "gcc_qpic_ahb_clk",
2372                         .parent_names = (const char *[]){
2373                                 "pcnoc_clk_src"
2374                         },
2375                         .num_parents = 1,
2376                         .flags = CLK_SET_RATE_PARENT,
2377                         .ops = &clk_branch2_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gcc_qpic_clk = {
2383         .halt_reg = 0x57020,
2384         .clkr = {
2385                 .enable_reg = 0x57020,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(struct clk_init_data){
2388                         .name = "gcc_qpic_clk",
2389                         .parent_names = (const char *[]){
2390                                 "pcnoc_clk_src"
2391                         },
2392                         .num_parents = 1,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                         .ops = &clk_branch2_ops,
2395                 },
2396         },
2397 };
2398
2399 static struct clk_branch gcc_pcie0_ahb_clk = {
2400         .halt_reg = 0x75010,
2401         .clkr = {
2402                 .enable_reg = 0x75010,
2403                 .enable_mask = BIT(0),
2404                 .hw.init = &(struct clk_init_data){
2405                         .name = "gcc_pcie0_ahb_clk",
2406                         .parent_names = (const char *[]){
2407                                 "pcnoc_clk_src"
2408                         },
2409                         .num_parents = 1,
2410                         .flags = CLK_SET_RATE_PARENT,
2411                         .ops = &clk_branch2_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gcc_pcie0_aux_clk = {
2417         .halt_reg = 0x75014,
2418         .clkr = {
2419                 .enable_reg = 0x75014,
2420                 .enable_mask = BIT(0),
2421                 .hw.init = &(struct clk_init_data){
2422                         .name = "gcc_pcie0_aux_clk",
2423                         .parent_names = (const char *[]){
2424                                 "pcie0_aux_clk_src"
2425                         },
2426                         .num_parents = 1,
2427                         .flags = CLK_SET_RATE_PARENT,
2428                         .ops = &clk_branch2_ops,
2429                 },
2430         },
2431 };
2432
2433 static struct clk_branch gcc_pcie0_axi_m_clk = {
2434         .halt_reg = 0x75008,
2435         .clkr = {
2436                 .enable_reg = 0x75008,
2437                 .enable_mask = BIT(0),
2438                 .hw.init = &(struct clk_init_data){
2439                         .name = "gcc_pcie0_axi_m_clk",
2440                         .parent_names = (const char *[]){
2441                                 "pcie0_axi_clk_src"
2442                         },
2443                         .num_parents = 1,
2444                         .flags = CLK_SET_RATE_PARENT,
2445                         .ops = &clk_branch2_ops,
2446                 },
2447         },
2448 };
2449
2450 static struct clk_branch gcc_pcie0_axi_s_clk = {
2451         .halt_reg = 0x7500c,
2452         .clkr = {
2453                 .enable_reg = 0x7500c,
2454                 .enable_mask = BIT(0),
2455                 .hw.init = &(struct clk_init_data){
2456                         .name = "gcc_pcie0_axi_s_clk",
2457                         .parent_names = (const char *[]){
2458                                 "pcie0_axi_clk_src"
2459                         },
2460                         .num_parents = 1,
2461                         .flags = CLK_SET_RATE_PARENT,
2462                         .ops = &clk_branch2_ops,
2463                 },
2464         },
2465 };
2466
2467 static struct clk_branch gcc_pcie0_pipe_clk = {
2468         .halt_reg = 0x75018,
2469         .halt_check = BRANCH_HALT_DELAY,
2470         .clkr = {
2471                 .enable_reg = 0x75018,
2472                 .enable_mask = BIT(0),
2473                 .hw.init = &(struct clk_init_data){
2474                         .name = "gcc_pcie0_pipe_clk",
2475                         .parent_names = (const char *[]){
2476                                 "pcie0_pipe_clk_src"
2477                         },
2478                         .num_parents = 1,
2479                         .flags = CLK_SET_RATE_PARENT,
2480                         .ops = &clk_branch2_ops,
2481                 },
2482         },
2483 };
2484
2485 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2486         .halt_reg = 0x26048,
2487         .clkr = {
2488                 .enable_reg = 0x26048,
2489                 .enable_mask = BIT(0),
2490                 .hw.init = &(struct clk_init_data){
2491                         .name = "gcc_sys_noc_pcie0_axi_clk",
2492                         .parent_names = (const char *[]){
2493                                 "pcie0_axi_clk_src"
2494                         },
2495                         .num_parents = 1,
2496                         .flags = CLK_SET_RATE_PARENT,
2497                         .ops = &clk_branch2_ops,
2498                 },
2499         },
2500 };
2501
2502 static struct clk_branch gcc_pcie1_ahb_clk = {
2503         .halt_reg = 0x76010,
2504         .clkr = {
2505                 .enable_reg = 0x76010,
2506                 .enable_mask = BIT(0),
2507                 .hw.init = &(struct clk_init_data){
2508                         .name = "gcc_pcie1_ahb_clk",
2509                         .parent_names = (const char *[]){
2510                                 "pcnoc_clk_src"
2511                         },
2512                         .num_parents = 1,
2513                         .flags = CLK_SET_RATE_PARENT,
2514                         .ops = &clk_branch2_ops,
2515                 },
2516         },
2517 };
2518
2519 static struct clk_branch gcc_pcie1_aux_clk = {
2520         .halt_reg = 0x76014,
2521         .clkr = {
2522                 .enable_reg = 0x76014,
2523                 .enable_mask = BIT(0),
2524                 .hw.init = &(struct clk_init_data){
2525                         .name = "gcc_pcie1_aux_clk",
2526                         .parent_names = (const char *[]){
2527                                 "pcie1_aux_clk_src"
2528                         },
2529                         .num_parents = 1,
2530                         .flags = CLK_SET_RATE_PARENT,
2531                         .ops = &clk_branch2_ops,
2532                 },
2533         },
2534 };
2535
2536 static struct clk_branch gcc_pcie1_axi_m_clk = {
2537         .halt_reg = 0x76008,
2538         .clkr = {
2539                 .enable_reg = 0x76008,
2540                 .enable_mask = BIT(0),
2541                 .hw.init = &(struct clk_init_data){
2542                         .name = "gcc_pcie1_axi_m_clk",
2543                         .parent_names = (const char *[]){
2544                                 "pcie1_axi_clk_src"
2545                         },
2546                         .num_parents = 1,
2547                         .flags = CLK_SET_RATE_PARENT,
2548                         .ops = &clk_branch2_ops,
2549                 },
2550         },
2551 };
2552
2553 static struct clk_branch gcc_pcie1_axi_s_clk = {
2554         .halt_reg = 0x7600c,
2555         .clkr = {
2556                 .enable_reg = 0x7600c,
2557                 .enable_mask = BIT(0),
2558                 .hw.init = &(struct clk_init_data){
2559                         .name = "gcc_pcie1_axi_s_clk",
2560                         .parent_names = (const char *[]){
2561                                 "pcie1_axi_clk_src"
2562                         },
2563                         .num_parents = 1,
2564                         .flags = CLK_SET_RATE_PARENT,
2565                         .ops = &clk_branch2_ops,
2566                 },
2567         },
2568 };
2569
2570 static struct clk_branch gcc_pcie1_pipe_clk = {
2571         .halt_reg = 0x76018,
2572         .halt_check = BRANCH_HALT_DELAY,
2573         .clkr = {
2574                 .enable_reg = 0x76018,
2575                 .enable_mask = BIT(0),
2576                 .hw.init = &(struct clk_init_data){
2577                         .name = "gcc_pcie1_pipe_clk",
2578                         .parent_names = (const char *[]){
2579                                 "pcie1_pipe_clk_src"
2580                         },
2581                         .num_parents = 1,
2582                         .flags = CLK_SET_RATE_PARENT,
2583                         .ops = &clk_branch2_ops,
2584                 },
2585         },
2586 };
2587
2588 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2589         .halt_reg = 0x2604c,
2590         .clkr = {
2591                 .enable_reg = 0x2604c,
2592                 .enable_mask = BIT(0),
2593                 .hw.init = &(struct clk_init_data){
2594                         .name = "gcc_sys_noc_pcie1_axi_clk",
2595                         .parent_names = (const char *[]){
2596                                 "pcie1_axi_clk_src"
2597                         },
2598                         .num_parents = 1,
2599                         .flags = CLK_SET_RATE_PARENT,
2600                         .ops = &clk_branch2_ops,
2601                 },
2602         },
2603 };
2604
2605 static struct clk_branch gcc_usb0_aux_clk = {
2606         .halt_reg = 0x3e044,
2607         .clkr = {
2608                 .enable_reg = 0x3e044,
2609                 .enable_mask = BIT(0),
2610                 .hw.init = &(struct clk_init_data){
2611                         .name = "gcc_usb0_aux_clk",
2612                         .parent_names = (const char *[]){
2613                                 "usb0_aux_clk_src"
2614                         },
2615                         .num_parents = 1,
2616                         .flags = CLK_SET_RATE_PARENT,
2617                         .ops = &clk_branch2_ops,
2618                 },
2619         },
2620 };
2621
2622 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2623         .halt_reg = 0x26040,
2624         .clkr = {
2625                 .enable_reg = 0x26040,
2626                 .enable_mask = BIT(0),
2627                 .hw.init = &(struct clk_init_data){
2628                         .name = "gcc_sys_noc_usb0_axi_clk",
2629                         .parent_names = (const char *[]){
2630                                 "usb0_master_clk_src"
2631                         },
2632                         .num_parents = 1,
2633                         .flags = CLK_SET_RATE_PARENT,
2634                         .ops = &clk_branch2_ops,
2635                 },
2636         },
2637 };
2638
2639 static struct clk_branch gcc_usb0_master_clk = {
2640         .halt_reg = 0x3e000,
2641         .clkr = {
2642                 .enable_reg = 0x3e000,
2643                 .enable_mask = BIT(0),
2644                 .hw.init = &(struct clk_init_data){
2645                         .name = "gcc_usb0_master_clk",
2646                         .parent_names = (const char *[]){
2647                                 "usb0_master_clk_src"
2648                         },
2649                         .num_parents = 1,
2650                         .flags = CLK_SET_RATE_PARENT,
2651                         .ops = &clk_branch2_ops,
2652                 },
2653         },
2654 };
2655
2656 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2657         .halt_reg = 0x3e008,
2658         .clkr = {
2659                 .enable_reg = 0x3e008,
2660                 .enable_mask = BIT(0),
2661                 .hw.init = &(struct clk_init_data){
2662                         .name = "gcc_usb0_mock_utmi_clk",
2663                         .parent_names = (const char *[]){
2664                                 "usb0_mock_utmi_clk_src"
2665                         },
2666                         .num_parents = 1,
2667                         .flags = CLK_SET_RATE_PARENT,
2668                         .ops = &clk_branch2_ops,
2669                 },
2670         },
2671 };
2672
2673 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2674         .halt_reg = 0x3e080,
2675         .clkr = {
2676                 .enable_reg = 0x3e080,
2677                 .enable_mask = BIT(0),
2678                 .hw.init = &(struct clk_init_data){
2679                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2680                         .parent_names = (const char *[]){
2681                                 "pcnoc_clk_src"
2682                         },
2683                         .num_parents = 1,
2684                         .flags = CLK_SET_RATE_PARENT,
2685                         .ops = &clk_branch2_ops,
2686                 },
2687         },
2688 };
2689
2690 static struct clk_branch gcc_usb0_pipe_clk = {
2691         .halt_reg = 0x3e040,
2692         .halt_check = BRANCH_HALT_DELAY,
2693         .clkr = {
2694                 .enable_reg = 0x3e040,
2695                 .enable_mask = BIT(0),
2696                 .hw.init = &(struct clk_init_data){
2697                         .name = "gcc_usb0_pipe_clk",
2698                         .parent_names = (const char *[]){
2699                                 "usb0_pipe_clk_src"
2700                         },
2701                         .num_parents = 1,
2702                         .flags = CLK_SET_RATE_PARENT,
2703                         .ops = &clk_branch2_ops,
2704                 },
2705         },
2706 };
2707
2708 static struct clk_branch gcc_usb0_sleep_clk = {
2709         .halt_reg = 0x3e004,
2710         .clkr = {
2711                 .enable_reg = 0x3e004,
2712                 .enable_mask = BIT(0),
2713                 .hw.init = &(struct clk_init_data){
2714                         .name = "gcc_usb0_sleep_clk",
2715                         .parent_names = (const char *[]){
2716                                 "gcc_sleep_clk_src"
2717                         },
2718                         .num_parents = 1,
2719                         .flags = CLK_SET_RATE_PARENT,
2720                         .ops = &clk_branch2_ops,
2721                 },
2722         },
2723 };
2724
2725 static struct clk_branch gcc_usb1_aux_clk = {
2726         .halt_reg = 0x3f044,
2727         .clkr = {
2728                 .enable_reg = 0x3f044,
2729                 .enable_mask = BIT(0),
2730                 .hw.init = &(struct clk_init_data){
2731                         .name = "gcc_usb1_aux_clk",
2732                         .parent_names = (const char *[]){
2733                                 "usb1_aux_clk_src"
2734                         },
2735                         .num_parents = 1,
2736                         .flags = CLK_SET_RATE_PARENT,
2737                         .ops = &clk_branch2_ops,
2738                 },
2739         },
2740 };
2741
2742 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2743         .halt_reg = 0x26044,
2744         .clkr = {
2745                 .enable_reg = 0x26044,
2746                 .enable_mask = BIT(0),
2747                 .hw.init = &(struct clk_init_data){
2748                         .name = "gcc_sys_noc_usb1_axi_clk",
2749                         .parent_names = (const char *[]){
2750                                 "usb1_master_clk_src"
2751                         },
2752                         .num_parents = 1,
2753                         .flags = CLK_SET_RATE_PARENT,
2754                         .ops = &clk_branch2_ops,
2755                 },
2756         },
2757 };
2758
2759 static struct clk_branch gcc_usb1_master_clk = {
2760         .halt_reg = 0x3f000,
2761         .clkr = {
2762                 .enable_reg = 0x3f000,
2763                 .enable_mask = BIT(0),
2764                 .hw.init = &(struct clk_init_data){
2765                         .name = "gcc_usb1_master_clk",
2766                         .parent_names = (const char *[]){
2767                                 "usb1_master_clk_src"
2768                         },
2769                         .num_parents = 1,
2770                         .flags = CLK_SET_RATE_PARENT,
2771                         .ops = &clk_branch2_ops,
2772                 },
2773         },
2774 };
2775
2776 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2777         .halt_reg = 0x3f008,
2778         .clkr = {
2779                 .enable_reg = 0x3f008,
2780                 .enable_mask = BIT(0),
2781                 .hw.init = &(struct clk_init_data){
2782                         .name = "gcc_usb1_mock_utmi_clk",
2783                         .parent_names = (const char *[]){
2784                                 "usb1_mock_utmi_clk_src"
2785                         },
2786                         .num_parents = 1,
2787                         .flags = CLK_SET_RATE_PARENT,
2788                         .ops = &clk_branch2_ops,
2789                 },
2790         },
2791 };
2792
2793 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2794         .halt_reg = 0x3f080,
2795         .clkr = {
2796                 .enable_reg = 0x3f080,
2797                 .enable_mask = BIT(0),
2798                 .hw.init = &(struct clk_init_data){
2799                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2800                         .parent_names = (const char *[]){
2801                                 "pcnoc_clk_src"
2802                         },
2803                         .num_parents = 1,
2804                         .flags = CLK_SET_RATE_PARENT,
2805                         .ops = &clk_branch2_ops,
2806                 },
2807         },
2808 };
2809
2810 static struct clk_branch gcc_usb1_pipe_clk = {
2811         .halt_reg = 0x3f040,
2812         .halt_check = BRANCH_HALT_DELAY,
2813         .clkr = {
2814                 .enable_reg = 0x3f040,
2815                 .enable_mask = BIT(0),
2816                 .hw.init = &(struct clk_init_data){
2817                         .name = "gcc_usb1_pipe_clk",
2818                         .parent_names = (const char *[]){
2819                                 "usb1_pipe_clk_src"
2820                         },
2821                         .num_parents = 1,
2822                         .flags = CLK_SET_RATE_PARENT,
2823                         .ops = &clk_branch2_ops,
2824                 },
2825         },
2826 };
2827
2828 static struct clk_branch gcc_usb1_sleep_clk = {
2829         .halt_reg = 0x3f004,
2830         .clkr = {
2831                 .enable_reg = 0x3f004,
2832                 .enable_mask = BIT(0),
2833                 .hw.init = &(struct clk_init_data){
2834                         .name = "gcc_usb1_sleep_clk",
2835                         .parent_names = (const char *[]){
2836                                 "gcc_sleep_clk_src"
2837                         },
2838                         .num_parents = 1,
2839                         .flags = CLK_SET_RATE_PARENT,
2840                         .ops = &clk_branch2_ops,
2841                 },
2842         },
2843 };
2844
2845 static struct clk_branch gcc_sdcc1_ahb_clk = {
2846         .halt_reg = 0x4201c,
2847         .clkr = {
2848                 .enable_reg = 0x4201c,
2849                 .enable_mask = BIT(0),
2850                 .hw.init = &(struct clk_init_data){
2851                         .name = "gcc_sdcc1_ahb_clk",
2852                         .parent_names = (const char *[]){
2853                                 "pcnoc_clk_src"
2854                         },
2855                         .num_parents = 1,
2856                         .flags = CLK_SET_RATE_PARENT,
2857                         .ops = &clk_branch2_ops,
2858                 },
2859         },
2860 };
2861
2862 static struct clk_branch gcc_sdcc1_apps_clk = {
2863         .halt_reg = 0x42018,
2864         .clkr = {
2865                 .enable_reg = 0x42018,
2866                 .enable_mask = BIT(0),
2867                 .hw.init = &(struct clk_init_data){
2868                         .name = "gcc_sdcc1_apps_clk",
2869                         .parent_names = (const char *[]){
2870                                 "sdcc1_apps_clk_src"
2871                         },
2872                         .num_parents = 1,
2873                         .flags = CLK_SET_RATE_PARENT,
2874                         .ops = &clk_branch2_ops,
2875                 },
2876         },
2877 };
2878
2879 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2880         .halt_reg = 0x5d014,
2881         .clkr = {
2882                 .enable_reg = 0x5d014,
2883                 .enable_mask = BIT(0),
2884                 .hw.init = &(struct clk_init_data){
2885                         .name = "gcc_sdcc1_ice_core_clk",
2886                         .parent_names = (const char *[]){
2887                                 "sdcc1_ice_core_clk_src"
2888                         },
2889                         .num_parents = 1,
2890                         .flags = CLK_SET_RATE_PARENT,
2891                         .ops = &clk_branch2_ops,
2892                 },
2893         },
2894 };
2895
2896 static struct clk_branch gcc_sdcc2_ahb_clk = {
2897         .halt_reg = 0x4301c,
2898         .clkr = {
2899                 .enable_reg = 0x4301c,
2900                 .enable_mask = BIT(0),
2901                 .hw.init = &(struct clk_init_data){
2902                         .name = "gcc_sdcc2_ahb_clk",
2903                         .parent_names = (const char *[]){
2904                                 "pcnoc_clk_src"
2905                         },
2906                         .num_parents = 1,
2907                         .flags = CLK_SET_RATE_PARENT,
2908                         .ops = &clk_branch2_ops,
2909                 },
2910         },
2911 };
2912
2913 static struct clk_branch gcc_sdcc2_apps_clk = {
2914         .halt_reg = 0x43018,
2915         .clkr = {
2916                 .enable_reg = 0x43018,
2917                 .enable_mask = BIT(0),
2918                 .hw.init = &(struct clk_init_data){
2919                         .name = "gcc_sdcc2_apps_clk",
2920                         .parent_names = (const char *[]){
2921                                 "sdcc2_apps_clk_src"
2922                         },
2923                         .num_parents = 1,
2924                         .flags = CLK_SET_RATE_PARENT,
2925                         .ops = &clk_branch2_ops,
2926                 },
2927         },
2928 };
2929
2930 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2931         .halt_reg = 0x1d03c,
2932         .clkr = {
2933                 .enable_reg = 0x1d03c,
2934                 .enable_mask = BIT(0),
2935                 .hw.init = &(struct clk_init_data){
2936                         .name = "gcc_mem_noc_nss_axi_clk",
2937                         .parent_names = (const char *[]){
2938                                 "nss_noc_clk_src"
2939                         },
2940                         .num_parents = 1,
2941                         .flags = CLK_SET_RATE_PARENT,
2942                         .ops = &clk_branch2_ops,
2943                 },
2944         },
2945 };
2946
2947 static struct clk_branch gcc_nss_ce_apb_clk = {
2948         .halt_reg = 0x68174,
2949         .clkr = {
2950                 .enable_reg = 0x68174,
2951                 .enable_mask = BIT(0),
2952                 .hw.init = &(struct clk_init_data){
2953                         .name = "gcc_nss_ce_apb_clk",
2954                         .parent_names = (const char *[]){
2955                                 "nss_ce_clk_src"
2956                         },
2957                         .num_parents = 1,
2958                         .flags = CLK_SET_RATE_PARENT,
2959                         .ops = &clk_branch2_ops,
2960                 },
2961         },
2962 };
2963
2964 static struct clk_branch gcc_nss_ce_axi_clk = {
2965         .halt_reg = 0x68170,
2966         .clkr = {
2967                 .enable_reg = 0x68170,
2968                 .enable_mask = BIT(0),
2969                 .hw.init = &(struct clk_init_data){
2970                         .name = "gcc_nss_ce_axi_clk",
2971                         .parent_names = (const char *[]){
2972                                 "nss_ce_clk_src"
2973                         },
2974                         .num_parents = 1,
2975                         .flags = CLK_SET_RATE_PARENT,
2976                         .ops = &clk_branch2_ops,
2977                 },
2978         },
2979 };
2980
2981 static struct clk_branch gcc_nss_cfg_clk = {
2982         .halt_reg = 0x68160,
2983         .clkr = {
2984                 .enable_reg = 0x68160,
2985                 .enable_mask = BIT(0),
2986                 .hw.init = &(struct clk_init_data){
2987                         .name = "gcc_nss_cfg_clk",
2988                         .parent_names = (const char *[]){
2989                                 "pcnoc_clk_src"
2990                         },
2991                         .num_parents = 1,
2992                         .flags = CLK_SET_RATE_PARENT,
2993                         .ops = &clk_branch2_ops,
2994                 },
2995         },
2996 };
2997
2998 static struct clk_branch gcc_nss_crypto_clk = {
2999         .halt_reg = 0x68164,
3000         .clkr = {
3001                 .enable_reg = 0x68164,
3002                 .enable_mask = BIT(0),
3003                 .hw.init = &(struct clk_init_data){
3004                         .name = "gcc_nss_crypto_clk",
3005                         .parent_names = (const char *[]){
3006                                 "nss_crypto_clk_src"
3007                         },
3008                         .num_parents = 1,
3009                         .flags = CLK_SET_RATE_PARENT,
3010                         .ops = &clk_branch2_ops,
3011                 },
3012         },
3013 };
3014
3015 static struct clk_branch gcc_nss_csr_clk = {
3016         .halt_reg = 0x68318,
3017         .clkr = {
3018                 .enable_reg = 0x68318,
3019                 .enable_mask = BIT(0),
3020                 .hw.init = &(struct clk_init_data){
3021                         .name = "gcc_nss_csr_clk",
3022                         .parent_names = (const char *[]){
3023                                 "nss_ce_clk_src"
3024                         },
3025                         .num_parents = 1,
3026                         .flags = CLK_SET_RATE_PARENT,
3027                         .ops = &clk_branch2_ops,
3028                 },
3029         },
3030 };
3031
3032 static struct clk_branch gcc_nss_edma_cfg_clk = {
3033         .halt_reg = 0x6819c,
3034         .clkr = {
3035                 .enable_reg = 0x6819c,
3036                 .enable_mask = BIT(0),
3037                 .hw.init = &(struct clk_init_data){
3038                         .name = "gcc_nss_edma_cfg_clk",
3039                         .parent_names = (const char *[]){
3040                                 "nss_ppe_clk_src"
3041                         },
3042                         .num_parents = 1,
3043                         .flags = CLK_SET_RATE_PARENT,
3044                         .ops = &clk_branch2_ops,
3045                 },
3046         },
3047 };
3048
3049 static struct clk_branch gcc_nss_edma_clk = {
3050         .halt_reg = 0x68198,
3051         .clkr = {
3052                 .enable_reg = 0x68198,
3053                 .enable_mask = BIT(0),
3054                 .hw.init = &(struct clk_init_data){
3055                         .name = "gcc_nss_edma_clk",
3056                         .parent_names = (const char *[]){
3057                                 "nss_ppe_clk_src"
3058                         },
3059                         .num_parents = 1,
3060                         .flags = CLK_SET_RATE_PARENT,
3061                         .ops = &clk_branch2_ops,
3062                 },
3063         },
3064 };
3065
3066 static struct clk_branch gcc_nss_imem_clk = {
3067         .halt_reg = 0x68178,
3068         .clkr = {
3069                 .enable_reg = 0x68178,
3070                 .enable_mask = BIT(0),
3071                 .hw.init = &(struct clk_init_data){
3072                         .name = "gcc_nss_imem_clk",
3073                         .parent_names = (const char *[]){
3074                                 "nss_imem_clk_src"
3075                         },
3076                         .num_parents = 1,
3077                         .flags = CLK_SET_RATE_PARENT,
3078                         .ops = &clk_branch2_ops,
3079                 },
3080         },
3081 };
3082
3083 static struct clk_branch gcc_nss_noc_clk = {
3084         .halt_reg = 0x68168,
3085         .clkr = {
3086                 .enable_reg = 0x68168,
3087                 .enable_mask = BIT(0),
3088                 .hw.init = &(struct clk_init_data){
3089                         .name = "gcc_nss_noc_clk",
3090                         .parent_names = (const char *[]){
3091                                 "nss_noc_clk_src"
3092                         },
3093                         .num_parents = 1,
3094                         .flags = CLK_SET_RATE_PARENT,
3095                         .ops = &clk_branch2_ops,
3096                 },
3097         },
3098 };
3099
3100 static struct clk_branch gcc_nss_ppe_btq_clk = {
3101         .halt_reg = 0x6833c,
3102         .clkr = {
3103                 .enable_reg = 0x6833c,
3104                 .enable_mask = BIT(0),
3105                 .hw.init = &(struct clk_init_data){
3106                         .name = "gcc_nss_ppe_btq_clk",
3107                         .parent_names = (const char *[]){
3108                                 "nss_ppe_clk_src"
3109                         },
3110                         .num_parents = 1,
3111                         .flags = CLK_SET_RATE_PARENT,
3112                         .ops = &clk_branch2_ops,
3113                 },
3114         },
3115 };
3116
3117 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3118         .halt_reg = 0x68194,
3119         .clkr = {
3120                 .enable_reg = 0x68194,
3121                 .enable_mask = BIT(0),
3122                 .hw.init = &(struct clk_init_data){
3123                         .name = "gcc_nss_ppe_cfg_clk",
3124                         .parent_names = (const char *[]){
3125                                 "nss_ppe_clk_src"
3126                         },
3127                         .num_parents = 1,
3128                         .flags = CLK_SET_RATE_PARENT,
3129                         .ops = &clk_branch2_ops,
3130                 },
3131         },
3132 };
3133
3134 static struct clk_branch gcc_nss_ppe_clk = {
3135         .halt_reg = 0x68190,
3136         .clkr = {
3137                 .enable_reg = 0x68190,
3138                 .enable_mask = BIT(0),
3139                 .hw.init = &(struct clk_init_data){
3140                         .name = "gcc_nss_ppe_clk",
3141                         .parent_names = (const char *[]){
3142                                 "nss_ppe_clk_src"
3143                         },
3144                         .num_parents = 1,
3145                         .flags = CLK_SET_RATE_PARENT,
3146                         .ops = &clk_branch2_ops,
3147                 },
3148         },
3149 };
3150
3151 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3152         .halt_reg = 0x68338,
3153         .clkr = {
3154                 .enable_reg = 0x68338,
3155                 .enable_mask = BIT(0),
3156                 .hw.init = &(struct clk_init_data){
3157                         .name = "gcc_nss_ppe_ipe_clk",
3158                         .parent_names = (const char *[]){
3159                                 "nss_ppe_clk_src"
3160                         },
3161                         .num_parents = 1,
3162                         .flags = CLK_SET_RATE_PARENT,
3163                         .ops = &clk_branch2_ops,
3164                 },
3165         },
3166 };
3167
3168 static struct clk_branch gcc_nss_ptp_ref_clk = {
3169         .halt_reg = 0x6816c,
3170         .clkr = {
3171                 .enable_reg = 0x6816c,
3172                 .enable_mask = BIT(0),
3173                 .hw.init = &(struct clk_init_data){
3174                         .name = "gcc_nss_ptp_ref_clk",
3175                         .parent_names = (const char *[]){
3176                                 "nss_ppe_cdiv_clk_src"
3177                         },
3178                         .num_parents = 1,
3179                         .flags = CLK_SET_RATE_PARENT,
3180                         .ops = &clk_branch2_ops,
3181                 },
3182         },
3183 };
3184
3185 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3186         .halt_reg = 0x6830c,
3187         .clkr = {
3188                 .enable_reg = 0x6830c,
3189                 .enable_mask = BIT(0),
3190                 .hw.init = &(struct clk_init_data){
3191                         .name = "gcc_nssnoc_ce_apb_clk",
3192                         .parent_names = (const char *[]){
3193                                 "nss_ce_clk_src"
3194                         },
3195                         .num_parents = 1,
3196                         .flags = CLK_SET_RATE_PARENT,
3197                         .ops = &clk_branch2_ops,
3198                 },
3199         },
3200 };
3201
3202 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3203         .halt_reg = 0x68308,
3204         .clkr = {
3205                 .enable_reg = 0x68308,
3206                 .enable_mask = BIT(0),
3207                 .hw.init = &(struct clk_init_data){
3208                         .name = "gcc_nssnoc_ce_axi_clk",
3209                         .parent_names = (const char *[]){
3210                                 "nss_ce_clk_src"
3211                         },
3212                         .num_parents = 1,
3213                         .flags = CLK_SET_RATE_PARENT,
3214                         .ops = &clk_branch2_ops,
3215                 },
3216         },
3217 };
3218
3219 static struct clk_branch gcc_nssnoc_crypto_clk = {
3220         .halt_reg = 0x68314,
3221         .clkr = {
3222                 .enable_reg = 0x68314,
3223                 .enable_mask = BIT(0),
3224                 .hw.init = &(struct clk_init_data){
3225                         .name = "gcc_nssnoc_crypto_clk",
3226                         .parent_names = (const char *[]){
3227                                 "nss_crypto_clk_src"
3228                         },
3229                         .num_parents = 1,
3230                         .flags = CLK_SET_RATE_PARENT,
3231                         .ops = &clk_branch2_ops,
3232                 },
3233         },
3234 };
3235
3236 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3237         .halt_reg = 0x68304,
3238         .clkr = {
3239                 .enable_reg = 0x68304,
3240                 .enable_mask = BIT(0),
3241                 .hw.init = &(struct clk_init_data){
3242                         .name = "gcc_nssnoc_ppe_cfg_clk",
3243                         .parent_names = (const char *[]){
3244                                 "nss_ppe_clk_src"
3245                         },
3246                         .num_parents = 1,
3247                         .flags = CLK_SET_RATE_PARENT,
3248                         .ops = &clk_branch2_ops,
3249                 },
3250         },
3251 };
3252
3253 static struct clk_branch gcc_nssnoc_ppe_clk = {
3254         .halt_reg = 0x68300,
3255         .clkr = {
3256                 .enable_reg = 0x68300,
3257                 .enable_mask = BIT(0),
3258                 .hw.init = &(struct clk_init_data){
3259                         .name = "gcc_nssnoc_ppe_clk",
3260                         .parent_names = (const char *[]){
3261                                 "nss_ppe_clk_src"
3262                         },
3263                         .num_parents = 1,
3264                         .flags = CLK_SET_RATE_PARENT,
3265                         .ops = &clk_branch2_ops,
3266                 },
3267         },
3268 };
3269
3270 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3271         .halt_reg = 0x68180,
3272         .clkr = {
3273                 .enable_reg = 0x68180,
3274                 .enable_mask = BIT(0),
3275                 .hw.init = &(struct clk_init_data){
3276                         .name = "gcc_nssnoc_qosgen_ref_clk",
3277                         .parent_names = (const char *[]){
3278                                 "gcc_xo_clk_src"
3279                         },
3280                         .num_parents = 1,
3281                         .flags = CLK_SET_RATE_PARENT,
3282                         .ops = &clk_branch2_ops,
3283                 },
3284         },
3285 };
3286
3287 static struct clk_branch gcc_nssnoc_snoc_clk = {
3288         .halt_reg = 0x68188,
3289         .clkr = {
3290                 .enable_reg = 0x68188,
3291                 .enable_mask = BIT(0),
3292                 .hw.init = &(struct clk_init_data){
3293                         .name = "gcc_nssnoc_snoc_clk",
3294                         .parent_names = (const char *[]){
3295                                 "system_noc_clk_src"
3296                         },
3297                         .num_parents = 1,
3298                         .flags = CLK_SET_RATE_PARENT,
3299                         .ops = &clk_branch2_ops,
3300                 },
3301         },
3302 };
3303
3304 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3305         .halt_reg = 0x68184,
3306         .clkr = {
3307                 .enable_reg = 0x68184,
3308                 .enable_mask = BIT(0),
3309                 .hw.init = &(struct clk_init_data){
3310                         .name = "gcc_nssnoc_timeout_ref_clk",
3311                         .parent_names = (const char *[]){
3312                                 "gcc_xo_div4_clk_src"
3313                         },
3314                         .num_parents = 1,
3315                         .flags = CLK_SET_RATE_PARENT,
3316                         .ops = &clk_branch2_ops,
3317                 },
3318         },
3319 };
3320
3321 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3322         .halt_reg = 0x68270,
3323         .clkr = {
3324                 .enable_reg = 0x68270,
3325                 .enable_mask = BIT(0),
3326                 .hw.init = &(struct clk_init_data){
3327                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3328                         .parent_names = (const char *[]){
3329                                 "nss_ce_clk_src"
3330                         },
3331                         .num_parents = 1,
3332                         .flags = CLK_SET_RATE_PARENT,
3333                         .ops = &clk_branch2_ops,
3334                 },
3335         },
3336 };
3337
3338 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3339         .halt_reg = 0x68274,
3340         .clkr = {
3341                 .enable_reg = 0x68274,
3342                 .enable_mask = BIT(0),
3343                 .hw.init = &(struct clk_init_data){
3344                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3345                         .parent_names = (const char *[]){
3346                                 "nss_ce_clk_src"
3347                         },
3348                         .num_parents = 1,
3349                         .flags = CLK_SET_RATE_PARENT,
3350                         .ops = &clk_branch2_ops,
3351                 },
3352         },
3353 };
3354
3355 static struct clk_branch gcc_ubi0_ahb_clk = {
3356         .halt_reg = 0x6820c,
3357         .clkr = {
3358                 .enable_reg = 0x6820c,
3359                 .enable_mask = BIT(0),
3360                 .hw.init = &(struct clk_init_data){
3361                         .name = "gcc_ubi0_ahb_clk",
3362                         .parent_names = (const char *[]){
3363                                 "nss_ce_clk_src"
3364                         },
3365                         .num_parents = 1,
3366                         .flags = CLK_SET_RATE_PARENT,
3367                         .ops = &clk_branch2_ops,
3368                 },
3369         },
3370 };
3371
3372 static struct clk_branch gcc_ubi0_axi_clk = {
3373         .halt_reg = 0x68200,
3374         .clkr = {
3375                 .enable_reg = 0x68200,
3376                 .enable_mask = BIT(0),
3377                 .hw.init = &(struct clk_init_data){
3378                         .name = "gcc_ubi0_axi_clk",
3379                         .parent_names = (const char *[]){
3380                                 "nss_noc_clk_src"
3381                         },
3382                         .num_parents = 1,
3383                         .flags = CLK_SET_RATE_PARENT,
3384                         .ops = &clk_branch2_ops,
3385                 },
3386         },
3387 };
3388
3389 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3390         .halt_reg = 0x68204,
3391         .clkr = {
3392                 .enable_reg = 0x68204,
3393                 .enable_mask = BIT(0),
3394                 .hw.init = &(struct clk_init_data){
3395                         .name = "gcc_ubi0_nc_axi_clk",
3396                         .parent_names = (const char *[]){
3397                                 "nss_noc_clk_src"
3398                         },
3399                         .num_parents = 1,
3400                         .flags = CLK_SET_RATE_PARENT,
3401                         .ops = &clk_branch2_ops,
3402                 },
3403         },
3404 };
3405
3406 static struct clk_branch gcc_ubi0_core_clk = {
3407         .halt_reg = 0x68210,
3408         .clkr = {
3409                 .enable_reg = 0x68210,
3410                 .enable_mask = BIT(0),
3411                 .hw.init = &(struct clk_init_data){
3412                         .name = "gcc_ubi0_core_clk",
3413                         .parent_names = (const char *[]){
3414                                 "nss_ubi0_div_clk_src"
3415                         },
3416                         .num_parents = 1,
3417                         .flags = CLK_SET_RATE_PARENT,
3418                         .ops = &clk_branch2_ops,
3419                 },
3420         },
3421 };
3422
3423 static struct clk_branch gcc_ubi0_mpt_clk = {
3424         .halt_reg = 0x68208,
3425         .clkr = {
3426                 .enable_reg = 0x68208,
3427                 .enable_mask = BIT(0),
3428                 .hw.init = &(struct clk_init_data){
3429                         .name = "gcc_ubi0_mpt_clk",
3430                         .parent_names = (const char *[]){
3431                                 "ubi_mpt_clk_src"
3432                         },
3433                         .num_parents = 1,
3434                         .flags = CLK_SET_RATE_PARENT,
3435                         .ops = &clk_branch2_ops,
3436                 },
3437         },
3438 };
3439
3440 static struct clk_branch gcc_ubi1_ahb_clk = {
3441         .halt_reg = 0x6822c,
3442         .clkr = {
3443                 .enable_reg = 0x6822c,
3444                 .enable_mask = BIT(0),
3445                 .hw.init = &(struct clk_init_data){
3446                         .name = "gcc_ubi1_ahb_clk",
3447                         .parent_names = (const char *[]){
3448                                 "nss_ce_clk_src"
3449                         },
3450                         .num_parents = 1,
3451                         .flags = CLK_SET_RATE_PARENT,
3452                         .ops = &clk_branch2_ops,
3453                 },
3454         },
3455 };
3456
3457 static struct clk_branch gcc_ubi1_axi_clk = {
3458         .halt_reg = 0x68220,
3459         .clkr = {
3460                 .enable_reg = 0x68220,
3461                 .enable_mask = BIT(0),
3462                 .hw.init = &(struct clk_init_data){
3463                         .name = "gcc_ubi1_axi_clk",
3464                         .parent_names = (const char *[]){
3465                                 "nss_noc_clk_src"
3466                         },
3467                         .num_parents = 1,
3468                         .flags = CLK_SET_RATE_PARENT,
3469                         .ops = &clk_branch2_ops,
3470                 },
3471         },
3472 };
3473
3474 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3475         .halt_reg = 0x68224,
3476         .clkr = {
3477                 .enable_reg = 0x68224,
3478                 .enable_mask = BIT(0),
3479                 .hw.init = &(struct clk_init_data){
3480                         .name = "gcc_ubi1_nc_axi_clk",
3481                         .parent_names = (const char *[]){
3482                                 "nss_noc_clk_src"
3483                         },
3484                         .num_parents = 1,
3485                         .flags = CLK_SET_RATE_PARENT,
3486                         .ops = &clk_branch2_ops,
3487                 },
3488         },
3489 };
3490
3491 static struct clk_branch gcc_ubi1_core_clk = {
3492         .halt_reg = 0x68230,
3493         .clkr = {
3494                 .enable_reg = 0x68230,
3495                 .enable_mask = BIT(0),
3496                 .hw.init = &(struct clk_init_data){
3497                         .name = "gcc_ubi1_core_clk",
3498                         .parent_names = (const char *[]){
3499                                 "nss_ubi1_div_clk_src"
3500                         },
3501                         .num_parents = 1,
3502                         .flags = CLK_SET_RATE_PARENT,
3503                         .ops = &clk_branch2_ops,
3504                 },
3505         },
3506 };
3507
3508 static struct clk_branch gcc_ubi1_mpt_clk = {
3509         .halt_reg = 0x68228,
3510         .clkr = {
3511                 .enable_reg = 0x68228,
3512                 .enable_mask = BIT(0),
3513                 .hw.init = &(struct clk_init_data){
3514                         .name = "gcc_ubi1_mpt_clk",
3515                         .parent_names = (const char *[]){
3516                                 "ubi_mpt_clk_src"
3517                         },
3518                         .num_parents = 1,
3519                         .flags = CLK_SET_RATE_PARENT,
3520                         .ops = &clk_branch2_ops,
3521                 },
3522         },
3523 };
3524
3525 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3526         .halt_reg = 0x56308,
3527         .clkr = {
3528                 .enable_reg = 0x56308,
3529                 .enable_mask = BIT(0),
3530                 .hw.init = &(struct clk_init_data){
3531                         .name = "gcc_cmn_12gpll_ahb_clk",
3532                         .parent_names = (const char *[]){
3533                                 "pcnoc_clk_src"
3534                         },
3535                         .num_parents = 1,
3536                         .flags = CLK_SET_RATE_PARENT,
3537                         .ops = &clk_branch2_ops,
3538                 },
3539         },
3540 };
3541
3542 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3543         .halt_reg = 0x5630c,
3544         .clkr = {
3545                 .enable_reg = 0x5630c,
3546                 .enable_mask = BIT(0),
3547                 .hw.init = &(struct clk_init_data){
3548                         .name = "gcc_cmn_12gpll_sys_clk",
3549                         .parent_names = (const char *[]){
3550                                 "gcc_xo_clk_src"
3551                         },
3552                         .num_parents = 1,
3553                         .flags = CLK_SET_RATE_PARENT,
3554                         .ops = &clk_branch2_ops,
3555                 },
3556         },
3557 };
3558
3559 static struct clk_branch gcc_mdio_ahb_clk = {
3560         .halt_reg = 0x58004,
3561         .clkr = {
3562                 .enable_reg = 0x58004,
3563                 .enable_mask = BIT(0),
3564                 .hw.init = &(struct clk_init_data){
3565                         .name = "gcc_mdio_ahb_clk",
3566                         .parent_names = (const char *[]){
3567                                 "pcnoc_clk_src"
3568                         },
3569                         .num_parents = 1,
3570                         .flags = CLK_SET_RATE_PARENT,
3571                         .ops = &clk_branch2_ops,
3572                 },
3573         },
3574 };
3575
3576 static struct clk_branch gcc_uniphy0_ahb_clk = {
3577         .halt_reg = 0x56008,
3578         .clkr = {
3579                 .enable_reg = 0x56008,
3580                 .enable_mask = BIT(0),
3581                 .hw.init = &(struct clk_init_data){
3582                         .name = "gcc_uniphy0_ahb_clk",
3583                         .parent_names = (const char *[]){
3584                                 "pcnoc_clk_src"
3585                         },
3586                         .num_parents = 1,
3587                         .flags = CLK_SET_RATE_PARENT,
3588                         .ops = &clk_branch2_ops,
3589                 },
3590         },
3591 };
3592
3593 static struct clk_branch gcc_uniphy0_sys_clk = {
3594         .halt_reg = 0x5600c,
3595         .clkr = {
3596                 .enable_reg = 0x5600c,
3597                 .enable_mask = BIT(0),
3598                 .hw.init = &(struct clk_init_data){
3599                         .name = "gcc_uniphy0_sys_clk",
3600                         .parent_names = (const char *[]){
3601                                 "gcc_xo_clk_src"
3602                         },
3603                         .num_parents = 1,
3604                         .flags = CLK_SET_RATE_PARENT,
3605                         .ops = &clk_branch2_ops,
3606                 },
3607         },
3608 };
3609
3610 static struct clk_branch gcc_uniphy1_ahb_clk = {
3611         .halt_reg = 0x56108,
3612         .clkr = {
3613                 .enable_reg = 0x56108,
3614                 .enable_mask = BIT(0),
3615                 .hw.init = &(struct clk_init_data){
3616                         .name = "gcc_uniphy1_ahb_clk",
3617                         .parent_names = (const char *[]){
3618                                 "pcnoc_clk_src"
3619                         },
3620                         .num_parents = 1,
3621                         .flags = CLK_SET_RATE_PARENT,
3622                         .ops = &clk_branch2_ops,
3623                 },
3624         },
3625 };
3626
3627 static struct clk_branch gcc_uniphy1_sys_clk = {
3628         .halt_reg = 0x5610c,
3629         .clkr = {
3630                 .enable_reg = 0x5610c,
3631                 .enable_mask = BIT(0),
3632                 .hw.init = &(struct clk_init_data){
3633                         .name = "gcc_uniphy1_sys_clk",
3634                         .parent_names = (const char *[]){
3635                                 "gcc_xo_clk_src"
3636                         },
3637                         .num_parents = 1,
3638                         .flags = CLK_SET_RATE_PARENT,
3639                         .ops = &clk_branch2_ops,
3640                 },
3641         },
3642 };
3643
3644 static struct clk_branch gcc_uniphy2_ahb_clk = {
3645         .halt_reg = 0x56208,
3646         .clkr = {
3647                 .enable_reg = 0x56208,
3648                 .enable_mask = BIT(0),
3649                 .hw.init = &(struct clk_init_data){
3650                         .name = "gcc_uniphy2_ahb_clk",
3651                         .parent_names = (const char *[]){
3652                                 "pcnoc_clk_src"
3653                         },
3654                         .num_parents = 1,
3655                         .flags = CLK_SET_RATE_PARENT,
3656                         .ops = &clk_branch2_ops,
3657                 },
3658         },
3659 };
3660
3661 static struct clk_branch gcc_uniphy2_sys_clk = {
3662         .halt_reg = 0x5620c,
3663         .clkr = {
3664                 .enable_reg = 0x5620c,
3665                 .enable_mask = BIT(0),
3666                 .hw.init = &(struct clk_init_data){
3667                         .name = "gcc_uniphy2_sys_clk",
3668                         .parent_names = (const char *[]){
3669                                 "gcc_xo_clk_src"
3670                         },
3671                         .num_parents = 1,
3672                         .flags = CLK_SET_RATE_PARENT,
3673                         .ops = &clk_branch2_ops,
3674                 },
3675         },
3676 };
3677
3678 static struct clk_branch gcc_nss_port1_rx_clk = {
3679         .halt_reg = 0x68240,
3680         .clkr = {
3681                 .enable_reg = 0x68240,
3682                 .enable_mask = BIT(0),
3683                 .hw.init = &(struct clk_init_data){
3684                         .name = "gcc_nss_port1_rx_clk",
3685                         .parent_names = (const char *[]){
3686                                 "nss_port1_rx_div_clk_src"
3687                         },
3688                         .num_parents = 1,
3689                         .flags = CLK_SET_RATE_PARENT,
3690                         .ops = &clk_branch2_ops,
3691                 },
3692         },
3693 };
3694
3695 static struct clk_branch gcc_nss_port1_tx_clk = {
3696         .halt_reg = 0x68244,
3697         .clkr = {
3698                 .enable_reg = 0x68244,
3699                 .enable_mask = BIT(0),
3700                 .hw.init = &(struct clk_init_data){
3701                         .name = "gcc_nss_port1_tx_clk",
3702                         .parent_names = (const char *[]){
3703                                 "nss_port1_tx_div_clk_src"
3704                         },
3705                         .num_parents = 1,
3706                         .flags = CLK_SET_RATE_PARENT,
3707                         .ops = &clk_branch2_ops,
3708                 },
3709         },
3710 };
3711
3712 static struct clk_branch gcc_nss_port2_rx_clk = {
3713         .halt_reg = 0x68248,
3714         .clkr = {
3715                 .enable_reg = 0x68248,
3716                 .enable_mask = BIT(0),
3717                 .hw.init = &(struct clk_init_data){
3718                         .name = "gcc_nss_port2_rx_clk",
3719                         .parent_names = (const char *[]){
3720                                 "nss_port2_rx_div_clk_src"
3721                         },
3722                         .num_parents = 1,
3723                         .flags = CLK_SET_RATE_PARENT,
3724                         .ops = &clk_branch2_ops,
3725                 },
3726         },
3727 };
3728
3729 static struct clk_branch gcc_nss_port2_tx_clk = {
3730         .halt_reg = 0x6824c,
3731         .clkr = {
3732                 .enable_reg = 0x6824c,
3733                 .enable_mask = BIT(0),
3734                 .hw.init = &(struct clk_init_data){
3735                         .name = "gcc_nss_port2_tx_clk",
3736                         .parent_names = (const char *[]){
3737                                 "nss_port2_tx_div_clk_src"
3738                         },
3739                         .num_parents = 1,
3740                         .flags = CLK_SET_RATE_PARENT,
3741                         .ops = &clk_branch2_ops,
3742                 },
3743         },
3744 };
3745
3746 static struct clk_branch gcc_nss_port3_rx_clk = {
3747         .halt_reg = 0x68250,
3748         .clkr = {
3749                 .enable_reg = 0x68250,
3750                 .enable_mask = BIT(0),
3751                 .hw.init = &(struct clk_init_data){
3752                         .name = "gcc_nss_port3_rx_clk",
3753                         .parent_names = (const char *[]){
3754                                 "nss_port3_rx_div_clk_src"
3755                         },
3756                         .num_parents = 1,
3757                         .flags = CLK_SET_RATE_PARENT,
3758                         .ops = &clk_branch2_ops,
3759                 },
3760         },
3761 };
3762
3763 static struct clk_branch gcc_nss_port3_tx_clk = {
3764         .halt_reg = 0x68254,
3765         .clkr = {
3766                 .enable_reg = 0x68254,
3767                 .enable_mask = BIT(0),
3768                 .hw.init = &(struct clk_init_data){
3769                         .name = "gcc_nss_port3_tx_clk",
3770                         .parent_names = (const char *[]){
3771                                 "nss_port3_tx_div_clk_src"
3772                         },
3773                         .num_parents = 1,
3774                         .flags = CLK_SET_RATE_PARENT,
3775                         .ops = &clk_branch2_ops,
3776                 },
3777         },
3778 };
3779
3780 static struct clk_branch gcc_nss_port4_rx_clk = {
3781         .halt_reg = 0x68258,
3782         .clkr = {
3783                 .enable_reg = 0x68258,
3784                 .enable_mask = BIT(0),
3785                 .hw.init = &(struct clk_init_data){
3786                         .name = "gcc_nss_port4_rx_clk",
3787                         .parent_names = (const char *[]){
3788                                 "nss_port4_rx_div_clk_src"
3789                         },
3790                         .num_parents = 1,
3791                         .flags = CLK_SET_RATE_PARENT,
3792                         .ops = &clk_branch2_ops,
3793                 },
3794         },
3795 };
3796
3797 static struct clk_branch gcc_nss_port4_tx_clk = {
3798         .halt_reg = 0x6825c,
3799         .clkr = {
3800                 .enable_reg = 0x6825c,
3801                 .enable_mask = BIT(0),
3802                 .hw.init = &(struct clk_init_data){
3803                         .name = "gcc_nss_port4_tx_clk",
3804                         .parent_names = (const char *[]){
3805                                 "nss_port4_tx_div_clk_src"
3806                         },
3807                         .num_parents = 1,
3808                         .flags = CLK_SET_RATE_PARENT,
3809                         .ops = &clk_branch2_ops,
3810                 },
3811         },
3812 };
3813
3814 static struct clk_branch gcc_nss_port5_rx_clk = {
3815         .halt_reg = 0x68260,
3816         .clkr = {
3817                 .enable_reg = 0x68260,
3818                 .enable_mask = BIT(0),
3819                 .hw.init = &(struct clk_init_data){
3820                         .name = "gcc_nss_port5_rx_clk",
3821                         .parent_names = (const char *[]){
3822                                 "nss_port5_rx_div_clk_src"
3823                         },
3824                         .num_parents = 1,
3825                         .flags = CLK_SET_RATE_PARENT,
3826                         .ops = &clk_branch2_ops,
3827                 },
3828         },
3829 };
3830
3831 static struct clk_branch gcc_nss_port5_tx_clk = {
3832         .halt_reg = 0x68264,
3833         .clkr = {
3834                 .enable_reg = 0x68264,
3835                 .enable_mask = BIT(0),
3836                 .hw.init = &(struct clk_init_data){
3837                         .name = "gcc_nss_port5_tx_clk",
3838                         .parent_names = (const char *[]){
3839                                 "nss_port5_tx_div_clk_src"
3840                         },
3841                         .num_parents = 1,
3842                         .flags = CLK_SET_RATE_PARENT,
3843                         .ops = &clk_branch2_ops,
3844                 },
3845         },
3846 };
3847
3848 static struct clk_branch gcc_nss_port6_rx_clk = {
3849         .halt_reg = 0x68268,
3850         .clkr = {
3851                 .enable_reg = 0x68268,
3852                 .enable_mask = BIT(0),
3853                 .hw.init = &(struct clk_init_data){
3854                         .name = "gcc_nss_port6_rx_clk",
3855                         .parent_names = (const char *[]){
3856                                 "nss_port6_rx_div_clk_src"
3857                         },
3858                         .num_parents = 1,
3859                         .flags = CLK_SET_RATE_PARENT,
3860                         .ops = &clk_branch2_ops,
3861                 },
3862         },
3863 };
3864
3865 static struct clk_branch gcc_nss_port6_tx_clk = {
3866         .halt_reg = 0x6826c,
3867         .clkr = {
3868                 .enable_reg = 0x6826c,
3869                 .enable_mask = BIT(0),
3870                 .hw.init = &(struct clk_init_data){
3871                         .name = "gcc_nss_port6_tx_clk",
3872                         .parent_names = (const char *[]){
3873                                 "nss_port6_tx_div_clk_src"
3874                         },
3875                         .num_parents = 1,
3876                         .flags = CLK_SET_RATE_PARENT,
3877                         .ops = &clk_branch2_ops,
3878                 },
3879         },
3880 };
3881
3882 static struct clk_branch gcc_port1_mac_clk = {
3883         .halt_reg = 0x68320,
3884         .clkr = {
3885                 .enable_reg = 0x68320,
3886                 .enable_mask = BIT(0),
3887                 .hw.init = &(struct clk_init_data){
3888                         .name = "gcc_port1_mac_clk",
3889                         .parent_names = (const char *[]){
3890                                 "nss_ppe_clk_src"
3891                         },
3892                         .num_parents = 1,
3893                         .flags = CLK_SET_RATE_PARENT,
3894                         .ops = &clk_branch2_ops,
3895                 },
3896         },
3897 };
3898
3899 static struct clk_branch gcc_port2_mac_clk = {
3900         .halt_reg = 0x68324,
3901         .clkr = {
3902                 .enable_reg = 0x68324,
3903                 .enable_mask = BIT(0),
3904                 .hw.init = &(struct clk_init_data){
3905                         .name = "gcc_port2_mac_clk",
3906                         .parent_names = (const char *[]){
3907                                 "nss_ppe_clk_src"
3908                         },
3909                         .num_parents = 1,
3910                         .flags = CLK_SET_RATE_PARENT,
3911                         .ops = &clk_branch2_ops,
3912                 },
3913         },
3914 };
3915
3916 static struct clk_branch gcc_port3_mac_clk = {
3917         .halt_reg = 0x68328,
3918         .clkr = {
3919                 .enable_reg = 0x68328,
3920                 .enable_mask = BIT(0),
3921                 .hw.init = &(struct clk_init_data){
3922                         .name = "gcc_port3_mac_clk",
3923                         .parent_names = (const char *[]){
3924                                 "nss_ppe_clk_src"
3925                         },
3926                         .num_parents = 1,
3927                         .flags = CLK_SET_RATE_PARENT,
3928                         .ops = &clk_branch2_ops,
3929                 },
3930         },
3931 };
3932
3933 static struct clk_branch gcc_port4_mac_clk = {
3934         .halt_reg = 0x6832c,
3935         .clkr = {
3936                 .enable_reg = 0x6832c,
3937                 .enable_mask = BIT(0),
3938                 .hw.init = &(struct clk_init_data){
3939                         .name = "gcc_port4_mac_clk",
3940                         .parent_names = (const char *[]){
3941                                 "nss_ppe_clk_src"
3942                         },
3943                         .num_parents = 1,
3944                         .flags = CLK_SET_RATE_PARENT,
3945                         .ops = &clk_branch2_ops,
3946                 },
3947         },
3948 };
3949
3950 static struct clk_branch gcc_port5_mac_clk = {
3951         .halt_reg = 0x68330,
3952         .clkr = {
3953                 .enable_reg = 0x68330,
3954                 .enable_mask = BIT(0),
3955                 .hw.init = &(struct clk_init_data){
3956                         .name = "gcc_port5_mac_clk",
3957                         .parent_names = (const char *[]){
3958                                 "nss_ppe_clk_src"
3959                         },
3960                         .num_parents = 1,
3961                         .flags = CLK_SET_RATE_PARENT,
3962                         .ops = &clk_branch2_ops,
3963                 },
3964         },
3965 };
3966
3967 static struct clk_branch gcc_port6_mac_clk = {
3968         .halt_reg = 0x68334,
3969         .clkr = {
3970                 .enable_reg = 0x68334,
3971                 .enable_mask = BIT(0),
3972                 .hw.init = &(struct clk_init_data){
3973                         .name = "gcc_port6_mac_clk",
3974                         .parent_names = (const char *[]){
3975                                 "nss_ppe_clk_src"
3976                         },
3977                         .num_parents = 1,
3978                         .flags = CLK_SET_RATE_PARENT,
3979                         .ops = &clk_branch2_ops,
3980                 },
3981         },
3982 };
3983
3984 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3985         .halt_reg = 0x56010,
3986         .clkr = {
3987                 .enable_reg = 0x56010,
3988                 .enable_mask = BIT(0),
3989                 .hw.init = &(struct clk_init_data){
3990                         .name = "gcc_uniphy0_port1_rx_clk",
3991                         .parent_names = (const char *[]){
3992                                 "nss_port1_rx_div_clk_src"
3993                         },
3994                         .num_parents = 1,
3995                         .flags = CLK_SET_RATE_PARENT,
3996                         .ops = &clk_branch2_ops,
3997                 },
3998         },
3999 };
4000
4001 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
4002         .halt_reg = 0x56014,
4003         .clkr = {
4004                 .enable_reg = 0x56014,
4005                 .enable_mask = BIT(0),
4006                 .hw.init = &(struct clk_init_data){
4007                         .name = "gcc_uniphy0_port1_tx_clk",
4008                         .parent_names = (const char *[]){
4009                                 "nss_port1_tx_div_clk_src"
4010                         },
4011                         .num_parents = 1,
4012                         .flags = CLK_SET_RATE_PARENT,
4013                         .ops = &clk_branch2_ops,
4014                 },
4015         },
4016 };
4017
4018 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4019         .halt_reg = 0x56018,
4020         .clkr = {
4021                 .enable_reg = 0x56018,
4022                 .enable_mask = BIT(0),
4023                 .hw.init = &(struct clk_init_data){
4024                         .name = "gcc_uniphy0_port2_rx_clk",
4025                         .parent_names = (const char *[]){
4026                                 "nss_port2_rx_div_clk_src"
4027                         },
4028                         .num_parents = 1,
4029                         .flags = CLK_SET_RATE_PARENT,
4030                         .ops = &clk_branch2_ops,
4031                 },
4032         },
4033 };
4034
4035 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4036         .halt_reg = 0x5601c,
4037         .clkr = {
4038                 .enable_reg = 0x5601c,
4039                 .enable_mask = BIT(0),
4040                 .hw.init = &(struct clk_init_data){
4041                         .name = "gcc_uniphy0_port2_tx_clk",
4042                         .parent_names = (const char *[]){
4043                                 "nss_port2_tx_div_clk_src"
4044                         },
4045                         .num_parents = 1,
4046                         .flags = CLK_SET_RATE_PARENT,
4047                         .ops = &clk_branch2_ops,
4048                 },
4049         },
4050 };
4051
4052 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4053         .halt_reg = 0x56020,
4054         .clkr = {
4055                 .enable_reg = 0x56020,
4056                 .enable_mask = BIT(0),
4057                 .hw.init = &(struct clk_init_data){
4058                         .name = "gcc_uniphy0_port3_rx_clk",
4059                         .parent_names = (const char *[]){
4060                                 "nss_port3_rx_div_clk_src"
4061                         },
4062                         .num_parents = 1,
4063                         .flags = CLK_SET_RATE_PARENT,
4064                         .ops = &clk_branch2_ops,
4065                 },
4066         },
4067 };
4068
4069 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4070         .halt_reg = 0x56024,
4071         .clkr = {
4072                 .enable_reg = 0x56024,
4073                 .enable_mask = BIT(0),
4074                 .hw.init = &(struct clk_init_data){
4075                         .name = "gcc_uniphy0_port3_tx_clk",
4076                         .parent_names = (const char *[]){
4077                                 "nss_port3_tx_div_clk_src"
4078                         },
4079                         .num_parents = 1,
4080                         .flags = CLK_SET_RATE_PARENT,
4081                         .ops = &clk_branch2_ops,
4082                 },
4083         },
4084 };
4085
4086 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4087         .halt_reg = 0x56028,
4088         .clkr = {
4089                 .enable_reg = 0x56028,
4090                 .enable_mask = BIT(0),
4091                 .hw.init = &(struct clk_init_data){
4092                         .name = "gcc_uniphy0_port4_rx_clk",
4093                         .parent_names = (const char *[]){
4094                                 "nss_port4_rx_div_clk_src"
4095                         },
4096                         .num_parents = 1,
4097                         .flags = CLK_SET_RATE_PARENT,
4098                         .ops = &clk_branch2_ops,
4099                 },
4100         },
4101 };
4102
4103 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4104         .halt_reg = 0x5602c,
4105         .clkr = {
4106                 .enable_reg = 0x5602c,
4107                 .enable_mask = BIT(0),
4108                 .hw.init = &(struct clk_init_data){
4109                         .name = "gcc_uniphy0_port4_tx_clk",
4110                         .parent_names = (const char *[]){
4111                                 "nss_port4_tx_div_clk_src"
4112                         },
4113                         .num_parents = 1,
4114                         .flags = CLK_SET_RATE_PARENT,
4115                         .ops = &clk_branch2_ops,
4116                 },
4117         },
4118 };
4119
4120 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4121         .halt_reg = 0x56030,
4122         .clkr = {
4123                 .enable_reg = 0x56030,
4124                 .enable_mask = BIT(0),
4125                 .hw.init = &(struct clk_init_data){
4126                         .name = "gcc_uniphy0_port5_rx_clk",
4127                         .parent_names = (const char *[]){
4128                                 "nss_port5_rx_div_clk_src"
4129                         },
4130                         .num_parents = 1,
4131                         .flags = CLK_SET_RATE_PARENT,
4132                         .ops = &clk_branch2_ops,
4133                 },
4134         },
4135 };
4136
4137 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4138         .halt_reg = 0x56034,
4139         .clkr = {
4140                 .enable_reg = 0x56034,
4141                 .enable_mask = BIT(0),
4142                 .hw.init = &(struct clk_init_data){
4143                         .name = "gcc_uniphy0_port5_tx_clk",
4144                         .parent_names = (const char *[]){
4145                                 "nss_port5_tx_div_clk_src"
4146                         },
4147                         .num_parents = 1,
4148                         .flags = CLK_SET_RATE_PARENT,
4149                         .ops = &clk_branch2_ops,
4150                 },
4151         },
4152 };
4153
4154 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4155         .halt_reg = 0x56110,
4156         .clkr = {
4157                 .enable_reg = 0x56110,
4158                 .enable_mask = BIT(0),
4159                 .hw.init = &(struct clk_init_data){
4160                         .name = "gcc_uniphy1_port5_rx_clk",
4161                         .parent_names = (const char *[]){
4162                                 "nss_port5_rx_div_clk_src"
4163                         },
4164                         .num_parents = 1,
4165                         .flags = CLK_SET_RATE_PARENT,
4166                         .ops = &clk_branch2_ops,
4167                 },
4168         },
4169 };
4170
4171 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4172         .halt_reg = 0x56114,
4173         .clkr = {
4174                 .enable_reg = 0x56114,
4175                 .enable_mask = BIT(0),
4176                 .hw.init = &(struct clk_init_data){
4177                         .name = "gcc_uniphy1_port5_tx_clk",
4178                         .parent_names = (const char *[]){
4179                                 "nss_port5_tx_div_clk_src"
4180                         },
4181                         .num_parents = 1,
4182                         .flags = CLK_SET_RATE_PARENT,
4183                         .ops = &clk_branch2_ops,
4184                 },
4185         },
4186 };
4187
4188 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4189         .halt_reg = 0x56210,
4190         .clkr = {
4191                 .enable_reg = 0x56210,
4192                 .enable_mask = BIT(0),
4193                 .hw.init = &(struct clk_init_data){
4194                         .name = "gcc_uniphy2_port6_rx_clk",
4195                         .parent_names = (const char *[]){
4196                                 "nss_port6_rx_div_clk_src"
4197                         },
4198                         .num_parents = 1,
4199                         .flags = CLK_SET_RATE_PARENT,
4200                         .ops = &clk_branch2_ops,
4201                 },
4202         },
4203 };
4204
4205 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4206         .halt_reg = 0x56214,
4207         .clkr = {
4208                 .enable_reg = 0x56214,
4209                 .enable_mask = BIT(0),
4210                 .hw.init = &(struct clk_init_data){
4211                         .name = "gcc_uniphy2_port6_tx_clk",
4212                         .parent_names = (const char *[]){
4213                                 "nss_port6_tx_div_clk_src"
4214                         },
4215                         .num_parents = 1,
4216                         .flags = CLK_SET_RATE_PARENT,
4217                         .ops = &clk_branch2_ops,
4218                 },
4219         },
4220 };
4221
4222 static struct clk_branch gcc_crypto_ahb_clk = {
4223         .halt_reg = 0x16024,
4224         .halt_check = BRANCH_HALT_VOTED,
4225         .clkr = {
4226                 .enable_reg = 0x0b004,
4227                 .enable_mask = BIT(0),
4228                 .hw.init = &(struct clk_init_data){
4229                         .name = "gcc_crypto_ahb_clk",
4230                         .parent_names = (const char *[]){
4231                                 "pcnoc_clk_src"
4232                         },
4233                         .num_parents = 1,
4234                         .flags = CLK_SET_RATE_PARENT,
4235                         .ops = &clk_branch2_ops,
4236                 },
4237         },
4238 };
4239
4240 static struct clk_branch gcc_crypto_axi_clk = {
4241         .halt_reg = 0x16020,
4242         .halt_check = BRANCH_HALT_VOTED,
4243         .clkr = {
4244                 .enable_reg = 0x0b004,
4245                 .enable_mask = BIT(1),
4246                 .hw.init = &(struct clk_init_data){
4247                         .name = "gcc_crypto_axi_clk",
4248                         .parent_names = (const char *[]){
4249                                 "pcnoc_clk_src"
4250                         },
4251                         .num_parents = 1,
4252                         .flags = CLK_SET_RATE_PARENT,
4253                         .ops = &clk_branch2_ops,
4254                 },
4255         },
4256 };
4257
4258 static struct clk_branch gcc_crypto_clk = {
4259         .halt_reg = 0x1601c,
4260         .halt_check = BRANCH_HALT_VOTED,
4261         .clkr = {
4262                 .enable_reg = 0x0b004,
4263                 .enable_mask = BIT(2),
4264                 .hw.init = &(struct clk_init_data){
4265                         .name = "gcc_crypto_clk",
4266                         .parent_names = (const char *[]){
4267                                 "crypto_clk_src"
4268                         },
4269                         .num_parents = 1,
4270                         .flags = CLK_SET_RATE_PARENT,
4271                         .ops = &clk_branch2_ops,
4272                 },
4273         },
4274 };
4275
4276 static struct clk_branch gcc_gp1_clk = {
4277         .halt_reg = 0x08000,
4278         .clkr = {
4279                 .enable_reg = 0x08000,
4280                 .enable_mask = BIT(0),
4281                 .hw.init = &(struct clk_init_data){
4282                         .name = "gcc_gp1_clk",
4283                         .parent_names = (const char *[]){
4284                                 "gp1_clk_src"
4285                         },
4286                         .num_parents = 1,
4287                         .flags = CLK_SET_RATE_PARENT,
4288                         .ops = &clk_branch2_ops,
4289                 },
4290         },
4291 };
4292
4293 static struct clk_branch gcc_gp2_clk = {
4294         .halt_reg = 0x09000,
4295         .clkr = {
4296                 .enable_reg = 0x09000,
4297                 .enable_mask = BIT(0),
4298                 .hw.init = &(struct clk_init_data){
4299                         .name = "gcc_gp2_clk",
4300                         .parent_names = (const char *[]){
4301                                 "gp2_clk_src"
4302                         },
4303                         .num_parents = 1,
4304                         .flags = CLK_SET_RATE_PARENT,
4305                         .ops = &clk_branch2_ops,
4306                 },
4307         },
4308 };
4309
4310 static struct clk_branch gcc_gp3_clk = {
4311         .halt_reg = 0x0a000,
4312         .clkr = {
4313                 .enable_reg = 0x0a000,
4314                 .enable_mask = BIT(0),
4315                 .hw.init = &(struct clk_init_data){
4316                         .name = "gcc_gp3_clk",
4317                         .parent_names = (const char *[]){
4318                                 "gp3_clk_src"
4319                         },
4320                         .num_parents = 1,
4321                         .flags = CLK_SET_RATE_PARENT,
4322                         .ops = &clk_branch2_ops,
4323                 },
4324         },
4325 };
4326
4327 static struct clk_hw *gcc_ipq8074_hws[] = {
4328         &gpll0_out_main_div2.hw,
4329         &gpll6_out_main_div2.hw,
4330         &pcnoc_clk_src.hw,
4331         &system_noc_clk_src.hw,
4332         &gcc_xo_div4_clk_src.hw,
4333         &nss_noc_clk_src.hw,
4334         &nss_ppe_cdiv_clk_src.hw,
4335 };
4336
4337 static struct clk_regmap *gcc_ipq8074_clks[] = {
4338         [GPLL0_MAIN] = &gpll0_main.clkr,
4339         [GPLL0] = &gpll0.clkr,
4340         [GPLL2_MAIN] = &gpll2_main.clkr,
4341         [GPLL2] = &gpll2.clkr,
4342         [GPLL4_MAIN] = &gpll4_main.clkr,
4343         [GPLL4] = &gpll4.clkr,
4344         [GPLL6_MAIN] = &gpll6_main.clkr,
4345         [GPLL6] = &gpll6.clkr,
4346         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4347         [UBI32_PLL] = &ubi32_pll.clkr,
4348         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4349         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4350         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4351         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4352         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4353         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4354         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4355         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4356         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4357         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4358         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4359         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4360         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4361         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4362         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4363         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4364         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4365         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4366         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4367         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4368         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4369         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4370         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4371         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4372         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4373         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4374         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4375         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4376         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4377         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4378         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4379         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4380         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4381         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4382         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4383         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4384         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4385         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4386         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4387         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4388         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4389         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4390         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4391         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4392         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4393         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4394         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4395         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4396         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4397         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4398         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4399         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4400         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4401         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4402         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4403         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4404         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4405         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4406         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4407         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4408         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4409         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4410         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4411         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4412         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4413         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4414         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4415         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4416         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4417         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4418         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4419         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4420         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4421         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4422         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4423         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4424         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4425         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4426         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4427         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4428         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4429         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4430         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4431         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4432         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4433         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4434         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4435         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4436         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4437         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4438         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4439         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4440         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4441         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4442         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4443         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4444         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4445         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4446         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4447         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4448         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4449         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4450         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4451         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4452         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4453         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4454         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4455         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4456         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4457         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4458         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4459         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4460         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4461         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4462         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4463         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4464         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4465         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4466         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4467         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4468         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4469         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4470         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4471         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4472         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4473         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4474         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4475         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4476         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4477         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4478         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4479         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4480         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4481         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4482         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4483         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4484         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4485         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4486         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4487         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4488         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4489         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4490         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4491         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4492         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4493         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4494         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4495         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4496         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4497         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4498         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4499         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4500         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4501         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4502         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4503         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4504         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4505         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4506         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4507         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4508         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4509         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4510         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4511         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4512         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4513         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4514         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4515         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4516         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4517         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4518         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4519         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4520         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4521         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4522         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4523         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4524         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4525         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4526         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4527         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4528         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4529         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4530         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4531         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4532         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4533         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4534         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4535         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4536         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4537         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4538         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4539         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4540         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4541         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4542         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4543         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4544         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4545         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4546         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4547         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4548         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4549         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4550         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4551         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4552         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4553         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4554         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4555         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4556         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4557         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4558         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4559         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4560         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4561         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4562 };
4563
4564 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4565         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4566         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4567         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4568         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4569         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4570         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4571         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4572         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4573         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4574         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4575         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4576         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4577         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4578         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4579         [GCC_SMMU_BCR] = { 0x12000, 0 },
4580         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4581         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4582         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4583         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4584         [GCC_PRNG_BCR] = { 0x13000, 0 },
4585         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4586         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4587         [GCC_WCSS_BCR] = { 0x18000, 0 },
4588         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4589         [GCC_NSS_BCR] = { 0x19000, 0 },
4590         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4591         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4592         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4593         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4594         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4595         [GCC_TCSR_BCR] = { 0x28000, 0 },
4596         [GCC_QDSS_BCR] = { 0x29000, 0 },
4597         [GCC_DCD_BCR] = { 0x2a000, 0 },
4598         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4599         [GCC_MPM_BCR] = { 0x2c000, 0 },
4600         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4601         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4602         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4603         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4604         [GCC_TLMM_BCR] = { 0x34000, 0 },
4605         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4606         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4607         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4608         [GCC_USB0_BCR] = { 0x3e070, 0 },
4609         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4610         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4611         [GCC_USB1_BCR] = { 0x3f070, 0 },
4612         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4613         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4614         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4615         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4616         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4617         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4618         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4619         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4620         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4621         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4622         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4623         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4624         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4625         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4626         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4627         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4628         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4629         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4630         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4631         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4632         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4633         [GCC_QPIC_BCR] = { 0x57018, 0 },
4634         [GCC_MDIO_BCR] = { 0x58000, 0 },
4635         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4636         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4637         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4638         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4639         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4640         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4641         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4642         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4643         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4644         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4645         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4646         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4647         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4648         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4649         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4650         [GCC_DCC_BCR] = { 0x77000, 0 },
4651         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4652         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4653         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4654         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4655         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4656         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4657         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4658         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4659         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4660         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4661         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4662         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4663         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4664         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4665         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4666         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4667         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4668         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4669         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4670         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4671         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4672         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4673         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4674         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4675         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4676         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4677         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4678         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4679         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4680         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4681         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4682         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4683         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4684         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4685         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4686         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4687         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4688         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4689         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4690         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4691         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4692         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4693         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4694         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4695         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4696 };
4697
4698 static const struct of_device_id gcc_ipq8074_match_table[] = {
4699         { .compatible = "qcom,gcc-ipq8074" },
4700         { }
4701 };
4702 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4703
4704 static const struct regmap_config gcc_ipq8074_regmap_config = {
4705         .reg_bits       = 32,
4706         .reg_stride     = 4,
4707         .val_bits       = 32,
4708         .max_register   = 0x7fffc,
4709         .fast_io        = true,
4710 };
4711
4712 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4713         .config = &gcc_ipq8074_regmap_config,
4714         .clks = gcc_ipq8074_clks,
4715         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4716         .resets = gcc_ipq8074_resets,
4717         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4718 };
4719
4720 static int gcc_ipq8074_probe(struct platform_device *pdev)
4721 {
4722         int ret, i;
4723
4724         for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
4725                 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
4726                 if (ret)
4727                         return ret;
4728         }
4729
4730         return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
4731 }
4732
4733 static struct platform_driver gcc_ipq8074_driver = {
4734         .probe = gcc_ipq8074_probe,
4735         .driver = {
4736                 .name   = "qcom,gcc-ipq8074",
4737                 .of_match_table = gcc_ipq8074_match_table,
4738         },
4739 };
4740
4741 static int __init gcc_ipq8074_init(void)
4742 {
4743         return platform_driver_register(&gcc_ipq8074_driver);
4744 }
4745 core_initcall(gcc_ipq8074_init);
4746
4747 static void __exit gcc_ipq8074_exit(void)
4748 {
4749         platform_driver_unregister(&gcc_ipq8074_driver);
4750 }
4751 module_exit(gcc_ipq8074_exit);
4752
4753 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4754 MODULE_LICENSE("GPL v2");
4755 MODULE_ALIAS("platform:gcc-ipq8074");