drivers/clk/qcom/gcc-ipq8074.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  16
  17 #include "common.h"
  18 #include "clk-regmap.h"
  19 #include "clk-pll.h"
  20 #include "clk-rcg.h"
  21 #include "clk-branch.h"
  22 #include "clk-alpha-pll.h"
  23 #include "clk-regmap-divider.h"
  24 #include "clk-regmap-mux.h"
  25 #include "gdsc.h"
  26 #include "reset.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_DIV2,
  32         P_GPLL2,
  33         P_GPLL4,
  34         P_GPLL6,
  35         P_SLEEP_CLK,
  36         P_PCIE20_PHY0_PIPE,
  37         P_PCIE20_PHY1_PIPE,
  38         P_USB3PHY_0_PIPE,
  39         P_USB3PHY_1_PIPE,
  40         P_UBI32_PLL,
  41         P_NSS_CRYPTO_PLL,
  42         P_BIAS_PLL,
  43         P_BIAS_PLL_NSS_NOC,
  44         P_UNIPHY0_RX,
  45         P_UNIPHY0_TX,
  46         P_UNIPHY1_RX,
  47         P_UNIPHY1_TX,
  48         P_UNIPHY2_RX,
  49         P_UNIPHY2_TX,
  50 };
  51
  52 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  53         "xo",
  54         "gpll0",
  55         "gpll0_out_main_div2",
  56 };
  57
  58 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  59         { P_XO, 0 },
  60         { P_GPLL0, 1 },
  61         { P_GPLL0_DIV2, 4 },
  62 };
  63
  64 static const struct parent_map gcc_xo_gpll0_map[] = {
  65         { P_XO, 0 },
  66         { P_GPLL0, 1 },
  67 };
  68
  69 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  70         "xo",
  71         "gpll0",
  72         "gpll2",
  73         "gpll0_out_main_div2",
  74 };
  75
  76 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  77         { P_XO, 0 },
  78         { P_GPLL0, 1 },
  79         { P_GPLL2, 2 },
  80         { P_GPLL0_DIV2, 4 },
  81 };
  82
  83 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  84         "xo",
  85         "gpll0",
  86         "sleep_clk",
  87 };
  88
  89 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
  90         { P_XO, 0 },
  91         { P_GPLL0, 2 },
  92         { P_SLEEP_CLK, 6 },
  93 };
  94
  95 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
  96         "xo",
  97         "gpll6",
  98         "gpll0",
  99         "gpll0_out_main_div2",
 100 };
 101
 102 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 103         { P_XO, 0 },
 104         { P_GPLL6, 1 },
 105         { P_GPLL0, 3 },
 106         { P_GPLL0_DIV2, 4 },
 107 };
 108
 109 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 110         "xo",
 111         "gpll0_out_main_div2",
 112         "gpll0",
 113 };
 114
 115 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 116         { P_XO, 0 },
 117         { P_GPLL0_DIV2, 2 },
 118         { P_GPLL0, 1 },
 119 };
 120
 121 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 122         "usb3phy_0_cc_pipe_clk",
 123         "xo",
 124 };
 125
 126 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 127         { P_USB3PHY_0_PIPE, 0 },
 128         { P_XO, 2 },
 129 };
 130
 131 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 132         "usb3phy_1_cc_pipe_clk",
 133         "xo",
 134 };
 135
 136 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 137         { P_USB3PHY_1_PIPE, 0 },
 138         { P_XO, 2 },
 139 };
 140
 141 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 142         "pcie20_phy0_pipe_clk",
 143         "xo",
 144 };
 145
 146 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 147         { P_PCIE20_PHY0_PIPE, 0 },
 148         { P_XO, 2 },
 149 };
 150
 151 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 152         "pcie20_phy1_pipe_clk",
 153         "xo",
 154 };
 155
 156 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 157         { P_PCIE20_PHY1_PIPE, 0 },
 158         { P_XO, 2 },
 159 };
 160
 161 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 162         "xo",
 163         "gpll0",
 164         "gpll6",
 165         "gpll0_out_main_div2",
 166 };
 167
 168 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 169         { P_XO, 0 },
 170         { P_GPLL0, 1 },
 171         { P_GPLL6, 2 },
 172         { P_GPLL0_DIV2, 4 },
 173 };
 174
 175 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 176         "xo",
 177         "gpll0",
 178         "gpll6",
 179         "gpll0_out_main_div2",
 180 };
 181
 182 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 183         { P_XO, 0 },
 184         { P_GPLL0, 1 },
 185         { P_GPLL6, 2 },
 186         { P_GPLL0_DIV2, 3 },
 187 };
 188
 189 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 190         "xo",
 191         "bias_pll_nss_noc_clk",
 192         "gpll0",
 193         "gpll2",
 194 };
 195
 196 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 197         { P_XO, 0 },
 198         { P_BIAS_PLL_NSS_NOC, 1 },
 199         { P_GPLL0, 2 },
 200         { P_GPLL2, 3 },
 201 };
 202
 203 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 204         "xo",
 205         "nss_crypto_pll",
 206         "gpll0",
 207 };
 208
 209 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 210         { P_XO, 0 },
 211         { P_NSS_CRYPTO_PLL, 1 },
 212         { P_GPLL0, 2 },
 213 };
 214
 215 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 216         "xo",
 217         "ubi32_pll",
 218         "gpll0",
 219         "gpll2",
 220         "gpll4",
 221         "gpll6",
 222 };
 223
 224 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 225         { P_XO, 0 },
 226         { P_UBI32_PLL, 1 },
 227         { P_GPLL0, 2 },
 228         { P_GPLL2, 3 },
 229         { P_GPLL4, 4 },
 230         { P_GPLL6, 5 },
 231 };
 232
 233 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 234         "xo",
 235         "gpll0_out_main_div2",
 236 };
 237
 238 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 239         { P_XO, 0 },
 240         { P_GPLL0_DIV2, 1 },
 241 };
 242
 243 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 244         "xo",
 245         "bias_pll_cc_clk",
 246         "gpll0",
 247         "gpll4",
 248         "nss_crypto_pll",
 249         "ubi32_pll",
 250 };
 251
 252 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 253         { P_XO, 0 },
 254         { P_BIAS_PLL, 1 },
 255         { P_GPLL0, 2 },
 256         { P_GPLL4, 3 },
 257         { P_NSS_CRYPTO_PLL, 4 },
 258         { P_UBI32_PLL, 5 },
 259 };
 260
 261 static const char * const gcc_xo_gpll0_gpll4[] = {
 262         "xo",
 263         "gpll0",
 264         "gpll4",
 265 };
 266
 267 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 268         { P_XO, 0 },
 269         { P_GPLL0, 1 },
 270         { P_GPLL4, 2 },
 271 };
 272
 273 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 274         "xo",
 275         "uniphy0_gcc_rx_clk",
 276         "uniphy0_gcc_tx_clk",
 277         "ubi32_pll",
 278         "bias_pll_cc_clk",
 279 };
 280
 281 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 282         { P_XO, 0 },
 283         { P_UNIPHY0_RX, 1 },
 284         { P_UNIPHY0_TX, 2 },
 285         { P_UBI32_PLL, 5 },
 286         { P_BIAS_PLL, 6 },
 287 };
 288
 289 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 290         "xo",
 291         "uniphy0_gcc_tx_clk",
 292         "uniphy0_gcc_rx_clk",
 293         "ubi32_pll",
 294         "bias_pll_cc_clk",
 295 };
 296
 297 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 298         { P_XO, 0 },
 299         { P_UNIPHY0_TX, 1 },
 300         { P_UNIPHY0_RX, 2 },
 301         { P_UBI32_PLL, 5 },
 302         { P_BIAS_PLL, 6 },
 303 };
 304
 305 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 306         "xo",
 307         "uniphy0_gcc_rx_clk",
 308         "uniphy0_gcc_tx_clk",
 309         "uniphy1_gcc_rx_clk",
 310         "uniphy1_gcc_tx_clk",
 311         "ubi32_pll",
 312         "bias_pll_cc_clk",
 313 };
 314
 315 static const struct parent_map
 316 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 317         { P_XO, 0 },
 318         { P_UNIPHY0_RX, 1 },
 319         { P_UNIPHY0_TX, 2 },
 320         { P_UNIPHY1_RX, 3 },
 321         { P_UNIPHY1_TX, 4 },
 322         { P_UBI32_PLL, 5 },
 323         { P_BIAS_PLL, 6 },
 324 };
 325
 326 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 327         "xo",
 328         "uniphy0_gcc_tx_clk",
 329         "uniphy0_gcc_rx_clk",
 330         "uniphy1_gcc_tx_clk",
 331         "uniphy1_gcc_rx_clk",
 332         "ubi32_pll",
 333         "bias_pll_cc_clk",
 334 };
 335
 336 static const struct parent_map
 337 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 338         { P_XO, 0 },
 339         { P_UNIPHY0_TX, 1 },
 340         { P_UNIPHY0_RX, 2 },
 341         { P_UNIPHY1_TX, 3 },
 342         { P_UNIPHY1_RX, 4 },
 343         { P_UBI32_PLL, 5 },
 344         { P_BIAS_PLL, 6 },
 345 };
 346
 347 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 348         "xo",
 349         "uniphy2_gcc_rx_clk",
 350         "uniphy2_gcc_tx_clk",
 351         "ubi32_pll",
 352         "bias_pll_cc_clk",
 353 };
 354
 355 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
 356         { P_XO, 0 },
 357         { P_UNIPHY2_RX, 1 },
 358         { P_UNIPHY2_TX, 2 },
 359         { P_UBI32_PLL, 5 },
 360         { P_BIAS_PLL, 6 },
 361 };
 362
 363 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 364         "xo",
 365         "uniphy2_gcc_tx_clk",
 366         "uniphy2_gcc_rx_clk",
 367         "ubi32_pll",
 368         "bias_pll_cc_clk",
 369 };
 370
 371 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
 372         { P_XO, 0 },
 373         { P_UNIPHY2_TX, 1 },
 374         { P_UNIPHY2_RX, 2 },
 375         { P_UBI32_PLL, 5 },
 376         { P_BIAS_PLL, 6 },
 377 };
 378
 379 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
 380         "xo",
 381         "gpll0",
 382         "gpll6",
 383         "gpll0_out_main_div2",
 384         "sleep_clk",
 385 };
 386
 387 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
 388         { P_XO, 0 },
 389         { P_GPLL0, 1 },
 390         { P_GPLL6, 2 },
 391         { P_GPLL0_DIV2, 4 },
 392         { P_SLEEP_CLK, 6 },
 393 };
 394
 395 static struct clk_alpha_pll gpll0_main = {
 396         .offset = 0x21000,
 397         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 398         .clkr = {
 399                 .enable_reg = 0x0b000,
 400                 .enable_mask = BIT(0),
 401                 .hw.init = &(struct clk_init_data){
 402                         .name = "gpll0_main",
 403                         .parent_names = (const char *[]){
 404                                 "xo"
 405                         },
 406                         .num_parents = 1,
 407                         .ops = &clk_alpha_pll_ops,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_fixed_factor gpll0_out_main_div2 = {
 413         .mult = 1,
 414         .div = 2,
 415         .hw.init = &(struct clk_init_data){
 416                 .name = "gpll0_out_main_div2",
 417                 .parent_names = (const char *[]){
 418                         "gpll0_main"
 419                 },
 420                 .num_parents = 1,
 421                 .ops = &clk_fixed_factor_ops,
 422                 .flags = CLK_SET_RATE_PARENT,
 423         },
 424 };
 425
 426 static struct clk_alpha_pll_postdiv gpll0 = {
 427         .offset = 0x21000,
 428         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 429         .width = 4,
 430         .clkr.hw.init = &(struct clk_init_data){
 431                 .name = "gpll0",
 432                 .parent_names = (const char *[]){
 433                         "gpll0_main"
 434                 },
 435                 .num_parents = 1,
 436                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 437         },
 438 };
 439
 440 static struct clk_alpha_pll gpll2_main = {
 441         .offset = 0x4a000,
 442         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 443         .clkr = {
 444                 .enable_reg = 0x0b000,
 445                 .enable_mask = BIT(2),
 446                 .hw.init = &(struct clk_init_data){
 447                         .name = "gpll2_main",
 448                         .parent_names = (const char *[]){
 449                                 "xo"
 450                         },
 451                         .num_parents = 1,
 452                         .ops = &clk_alpha_pll_ops,
 453                         .flags = CLK_IS_CRITICAL,
 454                 },
 455         },
 456 };
 457
 458 static struct clk_alpha_pll_postdiv gpll2 = {
 459         .offset = 0x4a000,
 460         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 461         .width = 4,
 462         .clkr.hw.init = &(struct clk_init_data){
 463                 .name = "gpll2",
 464                 .parent_names = (const char *[]){
 465                         "gpll2_main"
 466                 },
 467                 .num_parents = 1,
 468                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 469                 .flags = CLK_SET_RATE_PARENT,
 470         },
 471 };
 472
 473 static struct clk_alpha_pll gpll4_main = {
 474         .offset = 0x24000,
 475         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 476         .clkr = {
 477                 .enable_reg = 0x0b000,
 478                 .enable_mask = BIT(5),
 479                 .hw.init = &(struct clk_init_data){
 480                         .name = "gpll4_main",
 481                         .parent_names = (const char *[]){
 482                                 "xo"
 483                         },
 484                         .num_parents = 1,
 485                         .ops = &clk_alpha_pll_ops,
 486                         .flags = CLK_IS_CRITICAL,
 487                 },
 488         },
 489 };
 490
 491 static struct clk_alpha_pll_postdiv gpll4 = {
 492         .offset = 0x24000,
 493         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 494         .width = 4,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "gpll4",
 497                 .parent_names = (const char *[]){
 498                         "gpll4_main"
 499                 },
 500                 .num_parents = 1,
 501                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 502                 .flags = CLK_SET_RATE_PARENT,
 503         },
 504 };
 505
 506 static struct clk_alpha_pll gpll6_main = {
 507         .offset = 0x37000,
 508         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 509         .flags = SUPPORTS_DYNAMIC_UPDATE,
 510         .clkr = {
 511                 .enable_reg = 0x0b000,
 512                 .enable_mask = BIT(7),
 513                 .hw.init = &(struct clk_init_data){
 514                         .name = "gpll6_main",
 515                         .parent_names = (const char *[]){
 516                                 "xo"
 517                         },
 518                         .num_parents = 1,
 519                         .ops = &clk_alpha_pll_ops,
 520                         .flags = CLK_IS_CRITICAL,
 521                 },
 522         },
 523 };
 524
 525 static struct clk_alpha_pll_postdiv gpll6 = {
 526         .offset = 0x37000,
 527         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 528         .width = 2,
 529         .clkr.hw.init = &(struct clk_init_data){
 530                 .name = "gpll6",
 531                 .parent_names = (const char *[]){
 532                         "gpll6_main"
 533                 },
 534                 .num_parents = 1,
 535                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 536                 .flags = CLK_SET_RATE_PARENT,
 537         },
 538 };
 539
 540 static struct clk_fixed_factor gpll6_out_main_div2 = {
 541         .mult = 1,
 542         .div = 2,
 543         .hw.init = &(struct clk_init_data){
 544                 .name = "gpll6_out_main_div2",
 545                 .parent_names = (const char *[]){
 546                         "gpll6_main"
 547                 },
 548                 .num_parents = 1,
 549                 .ops = &clk_fixed_factor_ops,
 550                 .flags = CLK_SET_RATE_PARENT,
 551         },
 552 };
 553
 554 static struct clk_alpha_pll ubi32_pll_main = {
 555         .offset = 0x25000,
 556         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 557         .flags = SUPPORTS_DYNAMIC_UPDATE,
 558         .clkr = {
 559                 .enable_reg = 0x0b000,
 560                 .enable_mask = BIT(6),
 561                 .hw.init = &(struct clk_init_data){
 562                         .name = "ubi32_pll_main",
 563                         .parent_names = (const char *[]){
 564                                 "xo"
 565                         },
 566                         .num_parents = 1,
 567                         .ops = &clk_alpha_pll_huayra_ops,
 568                 },
 569         },
 570 };
 571
 572 static struct clk_alpha_pll_postdiv ubi32_pll = {
 573         .offset = 0x25000,
 574         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 575         .width = 2,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "ubi32_pll",
 578                 .parent_names = (const char *[]){
 579                         "ubi32_pll_main"
 580                 },
 581                 .num_parents = 1,
 582                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 583                 .flags = CLK_SET_RATE_PARENT,
 584         },
 585 };
 586
 587 static struct clk_alpha_pll nss_crypto_pll_main = {
 588         .offset = 0x22000,
 589         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 590         .clkr = {
 591                 .enable_reg = 0x0b000,
 592                 .enable_mask = BIT(4),
 593                 .hw.init = &(struct clk_init_data){
 594                         .name = "nss_crypto_pll_main",
 595                         .parent_names = (const char *[]){
 596                                 "xo"
 597                         },
 598                         .num_parents = 1,
 599                         .ops = &clk_alpha_pll_ops,
 600                 },
 601         },
 602 };
 603
 604 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 605         .offset = 0x22000,
 606         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 607         .width = 4,
 608         .clkr.hw.init = &(struct clk_init_data){
 609                 .name = "nss_crypto_pll",
 610                 .parent_names = (const char *[]){
 611                         "nss_crypto_pll_main"
 612                 },
 613                 .num_parents = 1,
 614                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 615                 .flags = CLK_SET_RATE_PARENT,
 616         },
 617 };
 618
 619 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 620         F(19200000, P_XO, 1, 0, 0),
 621         F(50000000, P_GPLL0, 16, 0, 0),
 622         F(100000000, P_GPLL0, 8, 0, 0),
 623         { }
 624 };
 625
 626 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 627         .cmd_rcgr = 0x27000,
 628         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 629         .hid_width = 5,
 630         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 631         .clkr.hw.init = &(struct clk_init_data){
 632                 .name = "pcnoc_bfdcd_clk_src",
 633                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 634                 .num_parents = 3,
 635                 .ops = &clk_rcg2_ops,
 636                 .flags = CLK_IS_CRITICAL,
 637         },
 638 };
 639
 640 static struct clk_fixed_factor pcnoc_clk_src = {
 641         .mult = 1,
 642         .div = 1,
 643         .hw.init = &(struct clk_init_data){
 644                 .name = "pcnoc_clk_src",
 645                 .parent_names = (const char *[]){
 646                         "pcnoc_bfdcd_clk_src"
 647                 },
 648                 .num_parents = 1,
 649                 .ops = &clk_fixed_factor_ops,
 650                 .flags = CLK_SET_RATE_PARENT,
 651         },
 652 };
 653
 654 static struct clk_branch gcc_sleep_clk_src = {
 655         .halt_reg = 0x30000,
 656         .clkr = {
 657                 .enable_reg = 0x30000,
 658                 .enable_mask = BIT(1),
 659                 .hw.init = &(struct clk_init_data){
 660                         .name = "gcc_sleep_clk_src",
 661                         .parent_names = (const char *[]){
 662                                 "sleep_clk"
 663                         },
 664                         .num_parents = 1,
 665                         .ops = &clk_branch2_ops,
 666                         .flags = CLK_IS_CRITICAL,
 667                 },
 668         },
 669 };
 670
 671 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 672         F(19200000, P_XO, 1, 0, 0),
 673         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 674         F(50000000, P_GPLL0, 16, 0, 0),
 675         { }
 676 };
 677
 678 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 679         .cmd_rcgr = 0x0200c,
 680         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 681         .hid_width = 5,
 682         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 683         .clkr.hw.init = &(struct clk_init_data){
 684                 .name = "blsp1_qup1_i2c_apps_clk_src",
 685                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 686                 .num_parents = 3,
 687                 .ops = &clk_rcg2_ops,
 688         },
 689 };
 690
 691 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 692         F(960000, P_XO, 10, 1, 2),
 693         F(4800000, P_XO, 4, 0, 0),
 694         F(9600000, P_XO, 2, 0, 0),
 695         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 696         F(16000000, P_GPLL0, 10, 1, 5),
 697         F(19200000, P_XO, 1, 0, 0),
 698         F(25000000, P_GPLL0, 16, 1, 2),
 699         F(50000000, P_GPLL0, 16, 0, 0),
 700         { }
 701 };
 702
 703 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 704         .cmd_rcgr = 0x02024,
 705         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 706         .mnd_width = 8,
 707         .hid_width = 5,
 708         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 709         .clkr.hw.init = &(struct clk_init_data){
 710                 .name = "blsp1_qup1_spi_apps_clk_src",
 711                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 712                 .num_parents = 3,
 713                 .ops = &clk_rcg2_ops,
 714         },
 715 };
 716
 717 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 718         .cmd_rcgr = 0x03000,
 719         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 720         .hid_width = 5,
 721         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 722         .clkr.hw.init = &(struct clk_init_data){
 723                 .name = "blsp1_qup2_i2c_apps_clk_src",
 724                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 725                 .num_parents = 3,
 726                 .ops = &clk_rcg2_ops,
 727         },
 728 };
 729
 730 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 731         .cmd_rcgr = 0x03014,
 732         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 733         .mnd_width = 8,
 734         .hid_width = 5,
 735         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 736         .clkr.hw.init = &(struct clk_init_data){
 737                 .name = "blsp1_qup2_spi_apps_clk_src",
 738                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 739                 .num_parents = 3,
 740                 .ops = &clk_rcg2_ops,
 741         },
 742 };
 743
 744 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 745         .cmd_rcgr = 0x04000,
 746         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 747         .hid_width = 5,
 748         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 749         .clkr.hw.init = &(struct clk_init_data){
 750                 .name = "blsp1_qup3_i2c_apps_clk_src",
 751                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 752                 .num_parents = 3,
 753                 .ops = &clk_rcg2_ops,
 754         },
 755 };
 756
 757 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 758         .cmd_rcgr = 0x04014,
 759         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 760         .mnd_width = 8,
 761         .hid_width = 5,
 762         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "blsp1_qup3_spi_apps_clk_src",
 765                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 766                 .num_parents = 3,
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 772         .cmd_rcgr = 0x05000,
 773         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 774         .hid_width = 5,
 775         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 776         .clkr.hw.init = &(struct clk_init_data){
 777                 .name = "blsp1_qup4_i2c_apps_clk_src",
 778                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 779                 .num_parents = 3,
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 785         .cmd_rcgr = 0x05014,
 786         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 787         .mnd_width = 8,
 788         .hid_width = 5,
 789         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 790         .clkr.hw.init = &(struct clk_init_data){
 791                 .name = "blsp1_qup4_spi_apps_clk_src",
 792                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 793                 .num_parents = 3,
 794                 .ops = &clk_rcg2_ops,
 795         },
 796 };
 797
 798 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 799         .cmd_rcgr = 0x06000,
 800         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 801         .hid_width = 5,
 802         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 803         .clkr.hw.init = &(struct clk_init_data){
 804                 .name = "blsp1_qup5_i2c_apps_clk_src",
 805                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 806                 .num_parents = 3,
 807                 .ops = &clk_rcg2_ops,
 808         },
 809 };
 810
 811 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 812         .cmd_rcgr = 0x06014,
 813         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 814         .mnd_width = 8,
 815         .hid_width = 5,
 816         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 817         .clkr.hw.init = &(struct clk_init_data){
 818                 .name = "blsp1_qup5_spi_apps_clk_src",
 819                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 820                 .num_parents = 3,
 821                 .ops = &clk_rcg2_ops,
 822         },
 823 };
 824
 825 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 826         .cmd_rcgr = 0x07000,
 827         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 828         .hid_width = 5,
 829         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 830         .clkr.hw.init = &(struct clk_init_data){
 831                 .name = "blsp1_qup6_i2c_apps_clk_src",
 832                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 833                 .num_parents = 3,
 834                 .ops = &clk_rcg2_ops,
 835         },
 836 };
 837
 838 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 839         .cmd_rcgr = 0x07014,
 840         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 841         .mnd_width = 8,
 842         .hid_width = 5,
 843         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 844         .clkr.hw.init = &(struct clk_init_data){
 845                 .name = "blsp1_qup6_spi_apps_clk_src",
 846                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 847                 .num_parents = 3,
 848                 .ops = &clk_rcg2_ops,
 849         },
 850 };
 851
 852 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 853         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 854         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 855         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 856         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 857         F(19200000, P_XO, 1, 0, 0),
 858         F(24000000, P_GPLL0, 1, 3, 100),
 859         F(25000000, P_GPLL0, 16, 1, 2),
 860         F(32000000, P_GPLL0, 1, 1, 25),
 861         F(40000000, P_GPLL0, 1, 1, 20),
 862         F(46400000, P_GPLL0, 1, 29, 500),
 863         F(48000000, P_GPLL0, 1, 3, 50),
 864         F(51200000, P_GPLL0, 1, 8, 125),
 865         F(56000000, P_GPLL0, 1, 7, 100),
 866         F(58982400, P_GPLL0, 1, 1152, 15625),
 867         F(60000000, P_GPLL0, 1, 3, 40),
 868         F(64000000, P_GPLL0, 12.5, 1, 1),
 869         { }
 870 };
 871
 872 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 873         .cmd_rcgr = 0x02044,
 874         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 875         .mnd_width = 16,
 876         .hid_width = 5,
 877         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 878         .clkr.hw.init = &(struct clk_init_data){
 879                 .name = "blsp1_uart1_apps_clk_src",
 880                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 881                 .num_parents = 3,
 882                 .ops = &clk_rcg2_ops,
 883         },
 884 };
 885
 886 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 887         .cmd_rcgr = 0x03034,
 888         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 889         .mnd_width = 16,
 890         .hid_width = 5,
 891         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 892         .clkr.hw.init = &(struct clk_init_data){
 893                 .name = "blsp1_uart2_apps_clk_src",
 894                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 895                 .num_parents = 3,
 896                 .ops = &clk_rcg2_ops,
 897         },
 898 };
 899
 900 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 901         .cmd_rcgr = 0x04034,
 902         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 903         .mnd_width = 16,
 904         .hid_width = 5,
 905         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 906         .clkr.hw.init = &(struct clk_init_data){
 907                 .name = "blsp1_uart3_apps_clk_src",
 908                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 909                 .num_parents = 3,
 910                 .ops = &clk_rcg2_ops,
 911         },
 912 };
 913
 914 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 915         .cmd_rcgr = 0x05034,
 916         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 917         .mnd_width = 16,
 918         .hid_width = 5,
 919         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 920         .clkr.hw.init = &(struct clk_init_data){
 921                 .name = "blsp1_uart4_apps_clk_src",
 922                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 923                 .num_parents = 3,
 924                 .ops = &clk_rcg2_ops,
 925         },
 926 };
 927
 928 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 929         .cmd_rcgr = 0x06034,
 930         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 931         .mnd_width = 16,
 932         .hid_width = 5,
 933         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 934         .clkr.hw.init = &(struct clk_init_data){
 935                 .name = "blsp1_uart5_apps_clk_src",
 936                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 937                 .num_parents = 3,
 938                 .ops = &clk_rcg2_ops,
 939         },
 940 };
 941
 942 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 943         .cmd_rcgr = 0x07034,
 944         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 945         .mnd_width = 16,
 946         .hid_width = 5,
 947         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 948         .clkr.hw.init = &(struct clk_init_data){
 949                 .name = "blsp1_uart6_apps_clk_src",
 950                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 951                 .num_parents = 3,
 952                 .ops = &clk_rcg2_ops,
 953         },
 954 };
 955
 956 static const struct clk_parent_data gcc_xo_gpll0[] = {
 957         { .fw_name = "xo" },
 958         { .hw = &gpll0.clkr.hw },
 959 };
 960
 961 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 962         F(19200000, P_XO, 1, 0, 0),
 963         F(200000000, P_GPLL0, 4, 0, 0),
 964         { }
 965 };
 966
 967 static struct clk_rcg2 pcie0_axi_clk_src = {
 968         .cmd_rcgr = 0x75054,
 969         .freq_tbl = ftbl_pcie_axi_clk_src,
 970         .hid_width = 5,
 971         .parent_map = gcc_xo_gpll0_map,
 972         .clkr.hw.init = &(struct clk_init_data){
 973                 .name = "pcie0_axi_clk_src",
 974                 .parent_data = gcc_xo_gpll0,
 975                 .num_parents = 2,
 976                 .ops = &clk_rcg2_ops,
 977         },
 978 };
 979
 980 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 981         F(19200000, P_XO, 1, 0, 0),
 982 };
 983
 984 static struct clk_rcg2 pcie0_aux_clk_src = {
 985         .cmd_rcgr = 0x75024,
 986         .freq_tbl = ftbl_pcie_aux_clk_src,
 987         .mnd_width = 16,
 988         .hid_width = 5,
 989         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 990         .clkr.hw.init = &(struct clk_init_data){
 991                 .name = "pcie0_aux_clk_src",
 992                 .parent_names = gcc_xo_gpll0_sleep_clk,
 993                 .num_parents = 3,
 994                 .ops = &clk_rcg2_ops,
 995         },
 996 };
 997
 998 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 999         .reg = 0x7501c,
1000         .shift = 8,
1001         .width = 2,
1002         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1003         .clkr = {
1004                 .hw.init = &(struct clk_init_data){
1005                         .name = "pcie0_pipe_clk_src",
1006                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1007                         .num_parents = 2,
1008                         .ops = &clk_regmap_mux_closest_ops,
1009                         .flags = CLK_SET_RATE_PARENT,
1010                 },
1011         },
1012 };
1013
1014 static struct clk_rcg2 pcie1_axi_clk_src = {
1015         .cmd_rcgr = 0x76054,
1016         .freq_tbl = ftbl_pcie_axi_clk_src,
1017         .hid_width = 5,
1018         .parent_map = gcc_xo_gpll0_map,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "pcie1_axi_clk_src",
1021                 .parent_data = gcc_xo_gpll0,
1022                 .num_parents = 2,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static struct clk_rcg2 pcie1_aux_clk_src = {
1028         .cmd_rcgr = 0x76024,
1029         .freq_tbl = ftbl_pcie_aux_clk_src,
1030         .mnd_width = 16,
1031         .hid_width = 5,
1032         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1033         .clkr.hw.init = &(struct clk_init_data){
1034                 .name = "pcie1_aux_clk_src",
1035                 .parent_names = gcc_xo_gpll0_sleep_clk,
1036                 .num_parents = 3,
1037                 .ops = &clk_rcg2_ops,
1038         },
1039 };
1040
1041 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1042         .reg = 0x7601c,
1043         .shift = 8,
1044         .width = 2,
1045         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1046         .clkr = {
1047                 .hw.init = &(struct clk_init_data){
1048                         .name = "pcie1_pipe_clk_src",
1049                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1050                         .num_parents = 2,
1051                         .ops = &clk_regmap_mux_closest_ops,
1052                         .flags = CLK_SET_RATE_PARENT,
1053                 },
1054         },
1055 };
1056
1057 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1058         F(144000, P_XO, 16, 3, 25),
1059         F(400000, P_XO, 12, 1, 4),
1060         F(24000000, P_GPLL2, 12, 1, 4),
1061         F(48000000, P_GPLL2, 12, 1, 2),
1062         F(96000000, P_GPLL2, 12, 0, 0),
1063         F(177777778, P_GPLL0, 4.5, 0, 0),
1064         F(192000000, P_GPLL2, 6, 0, 0),
1065         F(384000000, P_GPLL2, 3, 0, 0),
1066         { }
1067 };
1068
1069 static struct clk_rcg2 sdcc1_apps_clk_src = {
1070         .cmd_rcgr = 0x42004,
1071         .freq_tbl = ftbl_sdcc_apps_clk_src,
1072         .mnd_width = 8,
1073         .hid_width = 5,
1074         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1075         .clkr.hw.init = &(struct clk_init_data){
1076                 .name = "sdcc1_apps_clk_src",
1077                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1078                 .num_parents = 4,
1079                 .ops = &clk_rcg2_floor_ops,
1080         },
1081 };
1082
1083 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1084         F(19200000, P_XO, 1, 0, 0),
1085         F(160000000, P_GPLL0, 5, 0, 0),
1086         F(308570000, P_GPLL6, 3.5, 0, 0),
1087 };
1088
1089 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1090         .cmd_rcgr = 0x5d000,
1091         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1092         .mnd_width = 8,
1093         .hid_width = 5,
1094         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1095         .clkr.hw.init = &(struct clk_init_data){
1096                 .name = "sdcc1_ice_core_clk_src",
1097                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1098                 .num_parents = 4,
1099                 .ops = &clk_rcg2_ops,
1100         },
1101 };
1102
1103 static struct clk_rcg2 sdcc2_apps_clk_src = {
1104         .cmd_rcgr = 0x43004,
1105         .freq_tbl = ftbl_sdcc_apps_clk_src,
1106         .mnd_width = 8,
1107         .hid_width = 5,
1108         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1109         .clkr.hw.init = &(struct clk_init_data){
1110                 .name = "sdcc2_apps_clk_src",
1111                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1112                 .num_parents = 4,
1113                 .ops = &clk_rcg2_floor_ops,
1114         },
1115 };
1116
1117 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1118         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1119         F(100000000, P_GPLL0, 8, 0, 0),
1120         F(133330000, P_GPLL0, 6, 0, 0),
1121         { }
1122 };
1123
1124 static struct clk_rcg2 usb0_master_clk_src = {
1125         .cmd_rcgr = 0x3e00c,
1126         .freq_tbl = ftbl_usb_master_clk_src,
1127         .mnd_width = 8,
1128         .hid_width = 5,
1129         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1130         .clkr.hw.init = &(struct clk_init_data){
1131                 .name = "usb0_master_clk_src",
1132                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1133                 .num_parents = 3,
1134                 .ops = &clk_rcg2_ops,
1135         },
1136 };
1137
1138 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1139         F(19200000, P_XO, 1, 0, 0),
1140         { }
1141 };
1142
1143 static struct clk_rcg2 usb0_aux_clk_src = {
1144         .cmd_rcgr = 0x3e05c,
1145         .freq_tbl = ftbl_usb_aux_clk_src,
1146         .mnd_width = 16,
1147         .hid_width = 5,
1148         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1149         .clkr.hw.init = &(struct clk_init_data){
1150                 .name = "usb0_aux_clk_src",
1151                 .parent_names = gcc_xo_gpll0_sleep_clk,
1152                 .num_parents = 3,
1153                 .ops = &clk_rcg2_ops,
1154         },
1155 };
1156
1157 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1158         F(19200000, P_XO, 1, 0, 0),
1159         F(20000000, P_GPLL6, 6, 1, 9),
1160         F(60000000, P_GPLL6, 6, 1, 3),
1161         { }
1162 };
1163
1164 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1165         .cmd_rcgr = 0x3e020,
1166         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1167         .mnd_width = 8,
1168         .hid_width = 5,
1169         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1170         .clkr.hw.init = &(struct clk_init_data){
1171                 .name = "usb0_mock_utmi_clk_src",
1172                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1173                 .num_parents = 4,
1174                 .ops = &clk_rcg2_ops,
1175         },
1176 };
1177
1178 static struct clk_regmap_mux usb0_pipe_clk_src = {
1179         .reg = 0x3e048,
1180         .shift = 8,
1181         .width = 2,
1182         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1183         .clkr = {
1184                 .hw.init = &(struct clk_init_data){
1185                         .name = "usb0_pipe_clk_src",
1186                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1187                         .num_parents = 2,
1188                         .ops = &clk_regmap_mux_closest_ops,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                 },
1191         },
1192 };
1193
1194 static struct clk_rcg2 usb1_master_clk_src = {
1195         .cmd_rcgr = 0x3f00c,
1196         .freq_tbl = ftbl_usb_master_clk_src,
1197         .mnd_width = 8,
1198         .hid_width = 5,
1199         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1200         .clkr.hw.init = &(struct clk_init_data){
1201                 .name = "usb1_master_clk_src",
1202                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1203                 .num_parents = 3,
1204                 .ops = &clk_rcg2_ops,
1205         },
1206 };
1207
1208 static struct clk_rcg2 usb1_aux_clk_src = {
1209         .cmd_rcgr = 0x3f05c,
1210         .freq_tbl = ftbl_usb_aux_clk_src,
1211         .mnd_width = 16,
1212         .hid_width = 5,
1213         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1214         .clkr.hw.init = &(struct clk_init_data){
1215                 .name = "usb1_aux_clk_src",
1216                 .parent_names = gcc_xo_gpll0_sleep_clk,
1217                 .num_parents = 3,
1218                 .ops = &clk_rcg2_ops,
1219         },
1220 };
1221
1222 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1223         .cmd_rcgr = 0x3f020,
1224         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1225         .mnd_width = 8,
1226         .hid_width = 5,
1227         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1228         .clkr.hw.init = &(struct clk_init_data){
1229                 .name = "usb1_mock_utmi_clk_src",
1230                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1231                 .num_parents = 4,
1232                 .ops = &clk_rcg2_ops,
1233         },
1234 };
1235
1236 static struct clk_regmap_mux usb1_pipe_clk_src = {
1237         .reg = 0x3f048,
1238         .shift = 8,
1239         .width = 2,
1240         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1241         .clkr = {
1242                 .hw.init = &(struct clk_init_data){
1243                         .name = "usb1_pipe_clk_src",
1244                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1245                         .num_parents = 2,
1246                         .ops = &clk_regmap_mux_closest_ops,
1247                         .flags = CLK_SET_RATE_PARENT,
1248                 },
1249         },
1250 };
1251
1252 static struct clk_branch gcc_xo_clk_src = {
1253         .halt_reg = 0x30018,
1254         .clkr = {
1255                 .enable_reg = 0x30018,
1256                 .enable_mask = BIT(1),
1257                 .hw.init = &(struct clk_init_data){
1258                         .name = "gcc_xo_clk_src",
1259                         .parent_names = (const char *[]){
1260                                 "xo"
1261                         },
1262                         .num_parents = 1,
1263                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1264                         .ops = &clk_branch2_ops,
1265                 },
1266         },
1267 };
1268
1269 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1270         .mult = 1,
1271         .div = 4,
1272         .hw.init = &(struct clk_init_data){
1273                 .name = "gcc_xo_div4_clk_src",
1274                 .parent_names = (const char *[]){
1275                         "gcc_xo_clk_src"
1276                 },
1277                 .num_parents = 1,
1278                 .ops = &clk_fixed_factor_ops,
1279                 .flags = CLK_SET_RATE_PARENT,
1280         },
1281 };
1282
1283 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1284         F(19200000, P_XO, 1, 0, 0),
1285         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1286         F(100000000, P_GPLL0, 8, 0, 0),
1287         F(133333333, P_GPLL0, 6, 0, 0),
1288         F(160000000, P_GPLL0, 5, 0, 0),
1289         F(200000000, P_GPLL0, 4, 0, 0),
1290         F(266666667, P_GPLL0, 3, 0, 0),
1291         { }
1292 };
1293
1294 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1295         .cmd_rcgr = 0x26004,
1296         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1297         .hid_width = 5,
1298         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1299         .clkr.hw.init = &(struct clk_init_data){
1300                 .name = "system_noc_bfdcd_clk_src",
1301                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1302                 .num_parents = 4,
1303                 .ops = &clk_rcg2_ops,
1304                 .flags = CLK_IS_CRITICAL,
1305         },
1306 };
1307
1308 static struct clk_fixed_factor system_noc_clk_src = {
1309         .mult = 1,
1310         .div = 1,
1311         .hw.init = &(struct clk_init_data){
1312                 .name = "system_noc_clk_src",
1313                 .parent_names = (const char *[]){
1314                         "system_noc_bfdcd_clk_src"
1315                 },
1316                 .num_parents = 1,
1317                 .ops = &clk_fixed_factor_ops,
1318                 .flags = CLK_SET_RATE_PARENT,
1319         },
1320 };
1321
1322 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1323         F(19200000, P_XO, 1, 0, 0),
1324         F(200000000, P_GPLL0, 4, 0, 0),
1325         { }
1326 };
1327
1328 static struct clk_rcg2 nss_ce_clk_src = {
1329         .cmd_rcgr = 0x68098,
1330         .freq_tbl = ftbl_nss_ce_clk_src,
1331         .hid_width = 5,
1332         .parent_map = gcc_xo_gpll0_map,
1333         .clkr.hw.init = &(struct clk_init_data){
1334                 .name = "nss_ce_clk_src",
1335                 .parent_data = gcc_xo_gpll0,
1336                 .num_parents = 2,
1337                 .ops = &clk_rcg2_ops,
1338         },
1339 };
1340
1341 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1342         F(19200000, P_XO, 1, 0, 0),
1343         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1344         { }
1345 };
1346
1347 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1348         .cmd_rcgr = 0x68088,
1349         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1350         .hid_width = 5,
1351         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1352         .clkr.hw.init = &(struct clk_init_data){
1353                 .name = "nss_noc_bfdcd_clk_src",
1354                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1355                 .num_parents = 4,
1356                 .ops = &clk_rcg2_ops,
1357         },
1358 };
1359
1360 static struct clk_fixed_factor nss_noc_clk_src = {
1361         .mult = 1,
1362         .div = 1,
1363         .hw.init = &(struct clk_init_data){
1364                 .name = "nss_noc_clk_src",
1365                 .parent_names = (const char *[]){
1366                         "nss_noc_bfdcd_clk_src"
1367                 },
1368                 .num_parents = 1,
1369                 .ops = &clk_fixed_factor_ops,
1370                 .flags = CLK_SET_RATE_PARENT,
1371         },
1372 };
1373
1374 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1375         F(19200000, P_XO, 1, 0, 0),
1376         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1377         { }
1378 };
1379
1380 static struct clk_rcg2 nss_crypto_clk_src = {
1381         .cmd_rcgr = 0x68144,
1382         .freq_tbl = ftbl_nss_crypto_clk_src,
1383         .mnd_width = 16,
1384         .hid_width = 5,
1385         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1386         .clkr.hw.init = &(struct clk_init_data){
1387                 .name = "nss_crypto_clk_src",
1388                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1389                 .num_parents = 3,
1390                 .ops = &clk_rcg2_ops,
1391         },
1392 };
1393
1394 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1395         F(19200000, P_XO, 1, 0, 0),
1396         F(187200000, P_UBI32_PLL, 8, 0, 0),
1397         F(748800000, P_UBI32_PLL, 2, 0, 0),
1398         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1399         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1400         { }
1401 };
1402
1403 static struct clk_rcg2 nss_ubi0_clk_src = {
1404         .cmd_rcgr = 0x68104,
1405         .freq_tbl = ftbl_nss_ubi_clk_src,
1406         .hid_width = 5,
1407         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1408         .clkr.hw.init = &(struct clk_init_data){
1409                 .name = "nss_ubi0_clk_src",
1410                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1411                 .num_parents = 6,
1412                 .ops = &clk_rcg2_ops,
1413                 .flags = CLK_SET_RATE_PARENT,
1414         },
1415 };
1416
1417 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1418         .reg = 0x68118,
1419         .shift = 0,
1420         .width = 4,
1421         .clkr = {
1422                 .hw.init = &(struct clk_init_data){
1423                         .name = "nss_ubi0_div_clk_src",
1424                         .parent_names = (const char *[]){
1425                                 "nss_ubi0_clk_src"
1426                         },
1427                         .num_parents = 1,
1428                         .ops = &clk_regmap_div_ro_ops,
1429                         .flags = CLK_SET_RATE_PARENT,
1430                 },
1431         },
1432 };
1433
1434 static struct clk_rcg2 nss_ubi1_clk_src = {
1435         .cmd_rcgr = 0x68124,
1436         .freq_tbl = ftbl_nss_ubi_clk_src,
1437         .hid_width = 5,
1438         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1439         .clkr.hw.init = &(struct clk_init_data){
1440                 .name = "nss_ubi1_clk_src",
1441                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1442                 .num_parents = 6,
1443                 .ops = &clk_rcg2_ops,
1444                 .flags = CLK_SET_RATE_PARENT,
1445         },
1446 };
1447
1448 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1449         .reg = 0x68138,
1450         .shift = 0,
1451         .width = 4,
1452         .clkr = {
1453                 .hw.init = &(struct clk_init_data){
1454                         .name = "nss_ubi1_div_clk_src",
1455                         .parent_names = (const char *[]){
1456                                 "nss_ubi1_clk_src"
1457                         },
1458                         .num_parents = 1,
1459                         .ops = &clk_regmap_div_ro_ops,
1460                         .flags = CLK_SET_RATE_PARENT,
1461                 },
1462         },
1463 };
1464
1465 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1466         F(19200000, P_XO, 1, 0, 0),
1467         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1468         { }
1469 };
1470
1471 static struct clk_rcg2 ubi_mpt_clk_src = {
1472         .cmd_rcgr = 0x68090,
1473         .freq_tbl = ftbl_ubi_mpt_clk_src,
1474         .hid_width = 5,
1475         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1476         .clkr.hw.init = &(struct clk_init_data){
1477                 .name = "ubi_mpt_clk_src",
1478                 .parent_names = gcc_xo_gpll0_out_main_div2,
1479                 .num_parents = 2,
1480                 .ops = &clk_rcg2_ops,
1481         },
1482 };
1483
1484 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1485         F(19200000, P_XO, 1, 0, 0),
1486         F(400000000, P_GPLL0, 2, 0, 0),
1487         { }
1488 };
1489
1490 static struct clk_rcg2 nss_imem_clk_src = {
1491         .cmd_rcgr = 0x68158,
1492         .freq_tbl = ftbl_nss_imem_clk_src,
1493         .hid_width = 5,
1494         .parent_map = gcc_xo_gpll0_gpll4_map,
1495         .clkr.hw.init = &(struct clk_init_data){
1496                 .name = "nss_imem_clk_src",
1497                 .parent_names = gcc_xo_gpll0_gpll4,
1498                 .num_parents = 3,
1499                 .ops = &clk_rcg2_ops,
1500         },
1501 };
1502
1503 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1504         F(19200000, P_XO, 1, 0, 0),
1505         F(300000000, P_BIAS_PLL, 1, 0, 0),
1506         { }
1507 };
1508
1509 static struct clk_rcg2 nss_ppe_clk_src = {
1510         .cmd_rcgr = 0x68080,
1511         .freq_tbl = ftbl_nss_ppe_clk_src,
1512         .hid_width = 5,
1513         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1514         .clkr.hw.init = &(struct clk_init_data){
1515                 .name = "nss_ppe_clk_src",
1516                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1517                 .num_parents = 6,
1518                 .ops = &clk_rcg2_ops,
1519         },
1520 };
1521
1522 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1523         .mult = 1,
1524         .div = 4,
1525         .hw.init = &(struct clk_init_data){
1526                 .name = "nss_ppe_cdiv_clk_src",
1527                 .parent_names = (const char *[]){
1528                         "nss_ppe_clk_src"
1529                 },
1530                 .num_parents = 1,
1531                 .ops = &clk_fixed_factor_ops,
1532                 .flags = CLK_SET_RATE_PARENT,
1533         },
1534 };
1535
1536 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1537         F(19200000, P_XO, 1, 0, 0),
1538         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1539         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1540         { }
1541 };
1542
1543 static struct clk_rcg2 nss_port1_rx_clk_src = {
1544         .cmd_rcgr = 0x68020,
1545         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1546         .hid_width = 5,
1547         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1548         .clkr.hw.init = &(struct clk_init_data){
1549                 .name = "nss_port1_rx_clk_src",
1550                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1551                 .num_parents = 5,
1552                 .ops = &clk_rcg2_ops,
1553         },
1554 };
1555
1556 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1557         .reg = 0x68400,
1558         .shift = 0,
1559         .width = 4,
1560         .clkr = {
1561                 .hw.init = &(struct clk_init_data){
1562                         .name = "nss_port1_rx_div_clk_src",
1563                         .parent_names = (const char *[]){
1564                                 "nss_port1_rx_clk_src"
1565                         },
1566                         .num_parents = 1,
1567                         .ops = &clk_regmap_div_ops,
1568                         .flags = CLK_SET_RATE_PARENT,
1569                 },
1570         },
1571 };
1572
1573 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1574         F(19200000, P_XO, 1, 0, 0),
1575         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1576         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1577         { }
1578 };
1579
1580 static struct clk_rcg2 nss_port1_tx_clk_src = {
1581         .cmd_rcgr = 0x68028,
1582         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1583         .hid_width = 5,
1584         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1585         .clkr.hw.init = &(struct clk_init_data){
1586                 .name = "nss_port1_tx_clk_src",
1587                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1588                 .num_parents = 5,
1589                 .ops = &clk_rcg2_ops,
1590         },
1591 };
1592
1593 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1594         .reg = 0x68404,
1595         .shift = 0,
1596         .width = 4,
1597         .clkr = {
1598                 .hw.init = &(struct clk_init_data){
1599                         .name = "nss_port1_tx_div_clk_src",
1600                         .parent_names = (const char *[]){
1601                                 "nss_port1_tx_clk_src"
1602                         },
1603                         .num_parents = 1,
1604                         .ops = &clk_regmap_div_ops,
1605                         .flags = CLK_SET_RATE_PARENT,
1606                 },
1607         },
1608 };
1609
1610 static struct clk_rcg2 nss_port2_rx_clk_src = {
1611         .cmd_rcgr = 0x68030,
1612         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1613         .hid_width = 5,
1614         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1615         .clkr.hw.init = &(struct clk_init_data){
1616                 .name = "nss_port2_rx_clk_src",
1617                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1618                 .num_parents = 5,
1619                 .ops = &clk_rcg2_ops,
1620         },
1621 };
1622
1623 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1624         .reg = 0x68410,
1625         .shift = 0,
1626         .width = 4,
1627         .clkr = {
1628                 .hw.init = &(struct clk_init_data){
1629                         .name = "nss_port2_rx_div_clk_src",
1630                         .parent_names = (const char *[]){
1631                                 "nss_port2_rx_clk_src"
1632                         },
1633                         .num_parents = 1,
1634                         .ops = &clk_regmap_div_ops,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_rcg2 nss_port2_tx_clk_src = {
1641         .cmd_rcgr = 0x68038,
1642         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1643         .hid_width = 5,
1644         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1645         .clkr.hw.init = &(struct clk_init_data){
1646                 .name = "nss_port2_tx_clk_src",
1647                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1648                 .num_parents = 5,
1649                 .ops = &clk_rcg2_ops,
1650         },
1651 };
1652
1653 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1654         .reg = 0x68414,
1655         .shift = 0,
1656         .width = 4,
1657         .clkr = {
1658                 .hw.init = &(struct clk_init_data){
1659                         .name = "nss_port2_tx_div_clk_src",
1660                         .parent_names = (const char *[]){
1661                                 "nss_port2_tx_clk_src"
1662                         },
1663                         .num_parents = 1,
1664                         .ops = &clk_regmap_div_ops,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                 },
1667         },
1668 };
1669
1670 static struct clk_rcg2 nss_port3_rx_clk_src = {
1671         .cmd_rcgr = 0x68040,
1672         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1673         .hid_width = 5,
1674         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1675         .clkr.hw.init = &(struct clk_init_data){
1676                 .name = "nss_port3_rx_clk_src",
1677                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1678                 .num_parents = 5,
1679                 .ops = &clk_rcg2_ops,
1680         },
1681 };
1682
1683 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1684         .reg = 0x68420,
1685         .shift = 0,
1686         .width = 4,
1687         .clkr = {
1688                 .hw.init = &(struct clk_init_data){
1689                         .name = "nss_port3_rx_div_clk_src",
1690                         .parent_names = (const char *[]){
1691                                 "nss_port3_rx_clk_src"
1692                         },
1693                         .num_parents = 1,
1694                         .ops = &clk_regmap_div_ops,
1695                         .flags = CLK_SET_RATE_PARENT,
1696                 },
1697         },
1698 };
1699
1700 static struct clk_rcg2 nss_port3_tx_clk_src = {
1701         .cmd_rcgr = 0x68048,
1702         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1703         .hid_width = 5,
1704         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1705         .clkr.hw.init = &(struct clk_init_data){
1706                 .name = "nss_port3_tx_clk_src",
1707                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1708                 .num_parents = 5,
1709                 .ops = &clk_rcg2_ops,
1710         },
1711 };
1712
1713 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1714         .reg = 0x68424,
1715         .shift = 0,
1716         .width = 4,
1717         .clkr = {
1718                 .hw.init = &(struct clk_init_data){
1719                         .name = "nss_port3_tx_div_clk_src",
1720                         .parent_names = (const char *[]){
1721                                 "nss_port3_tx_clk_src"
1722                         },
1723                         .num_parents = 1,
1724                         .ops = &clk_regmap_div_ops,
1725                         .flags = CLK_SET_RATE_PARENT,
1726                 },
1727         },
1728 };
1729
1730 static struct clk_rcg2 nss_port4_rx_clk_src = {
1731         .cmd_rcgr = 0x68050,
1732         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1733         .hid_width = 5,
1734         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1735         .clkr.hw.init = &(struct clk_init_data){
1736                 .name = "nss_port4_rx_clk_src",
1737                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1738                 .num_parents = 5,
1739                 .ops = &clk_rcg2_ops,
1740         },
1741 };
1742
1743 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1744         .reg = 0x68430,
1745         .shift = 0,
1746         .width = 4,
1747         .clkr = {
1748                 .hw.init = &(struct clk_init_data){
1749                         .name = "nss_port4_rx_div_clk_src",
1750                         .parent_names = (const char *[]){
1751                                 "nss_port4_rx_clk_src"
1752                         },
1753                         .num_parents = 1,
1754                         .ops = &clk_regmap_div_ops,
1755                         .flags = CLK_SET_RATE_PARENT,
1756                 },
1757         },
1758 };
1759
1760 static struct clk_rcg2 nss_port4_tx_clk_src = {
1761         .cmd_rcgr = 0x68058,
1762         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1763         .hid_width = 5,
1764         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1765         .clkr.hw.init = &(struct clk_init_data){
1766                 .name = "nss_port4_tx_clk_src",
1767                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1768                 .num_parents = 5,
1769                 .ops = &clk_rcg2_ops,
1770         },
1771 };
1772
1773 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1774         .reg = 0x68434,
1775         .shift = 0,
1776         .width = 4,
1777         .clkr = {
1778                 .hw.init = &(struct clk_init_data){
1779                         .name = "nss_port4_tx_div_clk_src",
1780                         .parent_names = (const char *[]){
1781                                 "nss_port4_tx_clk_src"
1782                         },
1783                         .num_parents = 1,
1784                         .ops = &clk_regmap_div_ops,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                 },
1787         },
1788 };
1789
1790 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1791         F(19200000, P_XO, 1, 0, 0),
1792         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1793         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1794         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1795         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1796         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1797         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1798         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1799         { }
1800 };
1801
1802 static struct clk_rcg2 nss_port5_rx_clk_src = {
1803         .cmd_rcgr = 0x68060,
1804         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1805         .hid_width = 5,
1806         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1807         .clkr.hw.init = &(struct clk_init_data){
1808                 .name = "nss_port5_rx_clk_src",
1809                 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1810                 .num_parents = 7,
1811                 .ops = &clk_rcg2_ops,
1812         },
1813 };
1814
1815 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1816         .reg = 0x68440,
1817         .shift = 0,
1818         .width = 4,
1819         .clkr = {
1820                 .hw.init = &(struct clk_init_data){
1821                         .name = "nss_port5_rx_div_clk_src",
1822                         .parent_names = (const char *[]){
1823                                 "nss_port5_rx_clk_src"
1824                         },
1825                         .num_parents = 1,
1826                         .ops = &clk_regmap_div_ops,
1827                         .flags = CLK_SET_RATE_PARENT,
1828                 },
1829         },
1830 };
1831
1832 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1833         F(19200000, P_XO, 1, 0, 0),
1834         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1835         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1836         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1837         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1838         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1839         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1840         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1841         { }
1842 };
1843
1844 static struct clk_rcg2 nss_port5_tx_clk_src = {
1845         .cmd_rcgr = 0x68068,
1846         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1847         .hid_width = 5,
1848         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1849         .clkr.hw.init = &(struct clk_init_data){
1850                 .name = "nss_port5_tx_clk_src",
1851                 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1852                 .num_parents = 7,
1853                 .ops = &clk_rcg2_ops,
1854         },
1855 };
1856
1857 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1858         .reg = 0x68444,
1859         .shift = 0,
1860         .width = 4,
1861         .clkr = {
1862                 .hw.init = &(struct clk_init_data){
1863                         .name = "nss_port5_tx_div_clk_src",
1864                         .parent_names = (const char *[]){
1865                                 "nss_port5_tx_clk_src"
1866                         },
1867                         .num_parents = 1,
1868                         .ops = &clk_regmap_div_ops,
1869                         .flags = CLK_SET_RATE_PARENT,
1870                 },
1871         },
1872 };
1873
1874 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1875         F(19200000, P_XO, 1, 0, 0),
1876         F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1877         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1878         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1879         F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1880         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1881         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1882         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1883         { }
1884 };
1885
1886 static struct clk_rcg2 nss_port6_rx_clk_src = {
1887         .cmd_rcgr = 0x68070,
1888         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1889         .hid_width = 5,
1890         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1891         .clkr.hw.init = &(struct clk_init_data){
1892                 .name = "nss_port6_rx_clk_src",
1893                 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1894                 .num_parents = 5,
1895                 .ops = &clk_rcg2_ops,
1896         },
1897 };
1898
1899 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1900         .reg = 0x68450,
1901         .shift = 0,
1902         .width = 4,
1903         .clkr = {
1904                 .hw.init = &(struct clk_init_data){
1905                         .name = "nss_port6_rx_div_clk_src",
1906                         .parent_names = (const char *[]){
1907                                 "nss_port6_rx_clk_src"
1908                         },
1909                         .num_parents = 1,
1910                         .ops = &clk_regmap_div_ops,
1911                         .flags = CLK_SET_RATE_PARENT,
1912                 },
1913         },
1914 };
1915
1916 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1917         F(19200000, P_XO, 1, 0, 0),
1918         F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1919         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1920         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1921         F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1922         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1923         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1924         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1925         { }
1926 };
1927
1928 static struct clk_rcg2 nss_port6_tx_clk_src = {
1929         .cmd_rcgr = 0x68078,
1930         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1931         .hid_width = 5,
1932         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1933         .clkr.hw.init = &(struct clk_init_data){
1934                 .name = "nss_port6_tx_clk_src",
1935                 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1936                 .num_parents = 5,
1937                 .ops = &clk_rcg2_ops,
1938         },
1939 };
1940
1941 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1942         .reg = 0x68454,
1943         .shift = 0,
1944         .width = 4,
1945         .clkr = {
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "nss_port6_tx_div_clk_src",
1948                         .parent_names = (const char *[]){
1949                                 "nss_port6_tx_clk_src"
1950                         },
1951                         .num_parents = 1,
1952                         .ops = &clk_regmap_div_ops,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                 },
1955         },
1956 };
1957
1958 static struct freq_tbl ftbl_crypto_clk_src[] = {
1959         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1960         F(80000000, P_GPLL0, 10, 0, 0),
1961         F(100000000, P_GPLL0, 8, 0, 0),
1962         F(160000000, P_GPLL0, 5, 0, 0),
1963         { }
1964 };
1965
1966 static struct clk_rcg2 crypto_clk_src = {
1967         .cmd_rcgr = 0x16004,
1968         .freq_tbl = ftbl_crypto_clk_src,
1969         .hid_width = 5,
1970         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1971         .clkr.hw.init = &(struct clk_init_data){
1972                 .name = "crypto_clk_src",
1973                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1974                 .num_parents = 3,
1975                 .ops = &clk_rcg2_ops,
1976         },
1977 };
1978
1979 static struct freq_tbl ftbl_gp_clk_src[] = {
1980         F(19200000, P_XO, 1, 0, 0),
1981         { }
1982 };
1983
1984 static struct clk_rcg2 gp1_clk_src = {
1985         .cmd_rcgr = 0x08004,
1986         .freq_tbl = ftbl_gp_clk_src,
1987         .mnd_width = 8,
1988         .hid_width = 5,
1989         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1990         .clkr.hw.init = &(struct clk_init_data){
1991                 .name = "gp1_clk_src",
1992                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1993                 .num_parents = 5,
1994                 .ops = &clk_rcg2_ops,
1995         },
1996 };
1997
1998 static struct clk_rcg2 gp2_clk_src = {
1999         .cmd_rcgr = 0x09004,
2000         .freq_tbl = ftbl_gp_clk_src,
2001         .mnd_width = 8,
2002         .hid_width = 5,
2003         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2004         .clkr.hw.init = &(struct clk_init_data){
2005                 .name = "gp2_clk_src",
2006                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2007                 .num_parents = 5,
2008                 .ops = &clk_rcg2_ops,
2009         },
2010 };
2011
2012 static struct clk_rcg2 gp3_clk_src = {
2013         .cmd_rcgr = 0x0a004,
2014         .freq_tbl = ftbl_gp_clk_src,
2015         .mnd_width = 8,
2016         .hid_width = 5,
2017         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2018         .clkr.hw.init = &(struct clk_init_data){
2019                 .name = "gp3_clk_src",
2020                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2021                 .num_parents = 5,
2022                 .ops = &clk_rcg2_ops,
2023         },
2024 };
2025
2026 static struct clk_branch gcc_blsp1_ahb_clk = {
2027         .halt_reg = 0x01008,
2028         .clkr = {
2029                 .enable_reg = 0x01008,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_blsp1_ahb_clk",
2033                         .parent_names = (const char *[]){
2034                                 "pcnoc_clk_src"
2035                         },
2036                         .num_parents = 1,
2037                         .flags = CLK_SET_RATE_PARENT,
2038                         .ops = &clk_branch2_ops,
2039                 },
2040         },
2041 };
2042
2043 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2044         .halt_reg = 0x02008,
2045         .clkr = {
2046                 .enable_reg = 0x02008,
2047                 .enable_mask = BIT(0),
2048                 .hw.init = &(struct clk_init_data){
2049                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2050                         .parent_names = (const char *[]){
2051                                 "blsp1_qup1_i2c_apps_clk_src"
2052                         },
2053                         .num_parents = 1,
2054                         .flags = CLK_SET_RATE_PARENT,
2055                         .ops = &clk_branch2_ops,
2056                 },
2057         },
2058 };
2059
2060 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2061         .halt_reg = 0x02004,
2062         .clkr = {
2063                 .enable_reg = 0x02004,
2064                 .enable_mask = BIT(0),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2067                         .parent_names = (const char *[]){
2068                                 "blsp1_qup1_spi_apps_clk_src"
2069                         },
2070                         .num_parents = 1,
2071                         .flags = CLK_SET_RATE_PARENT,
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2078         .halt_reg = 0x03010,
2079         .clkr = {
2080                 .enable_reg = 0x03010,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2084                         .parent_names = (const char *[]){
2085                                 "blsp1_qup2_i2c_apps_clk_src"
2086                         },
2087                         .num_parents = 1,
2088                         .flags = CLK_SET_RATE_PARENT,
2089                         .ops = &clk_branch2_ops,
2090                 },
2091         },
2092 };
2093
2094 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2095         .halt_reg = 0x0300c,
2096         .clkr = {
2097                 .enable_reg = 0x0300c,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2101                         .parent_names = (const char *[]){
2102                                 "blsp1_qup2_spi_apps_clk_src"
2103                         },
2104                         .num_parents = 1,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                         .ops = &clk_branch2_ops,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2112         .halt_reg = 0x04010,
2113         .clkr = {
2114                 .enable_reg = 0x04010,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2118                         .parent_names = (const char *[]){
2119                                 "blsp1_qup3_i2c_apps_clk_src"
2120                         },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2129         .halt_reg = 0x0400c,
2130         .clkr = {
2131                 .enable_reg = 0x0400c,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2135                         .parent_names = (const char *[]){
2136                                 "blsp1_qup3_spi_apps_clk_src"
2137                         },
2138                         .num_parents = 1,
2139                         .flags = CLK_SET_RATE_PARENT,
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2146         .halt_reg = 0x05010,
2147         .clkr = {
2148                 .enable_reg = 0x05010,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2152                         .parent_names = (const char *[]){
2153                                 "blsp1_qup4_i2c_apps_clk_src"
2154                         },
2155                         .num_parents = 1,
2156                         .flags = CLK_SET_RATE_PARENT,
2157                         .ops = &clk_branch2_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2163         .halt_reg = 0x0500c,
2164         .clkr = {
2165                 .enable_reg = 0x0500c,
2166                 .enable_mask = BIT(0),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2169                         .parent_names = (const char *[]){
2170                                 "blsp1_qup4_spi_apps_clk_src"
2171                         },
2172                         .num_parents = 1,
2173                         .flags = CLK_SET_RATE_PARENT,
2174                         .ops = &clk_branch2_ops,
2175                 },
2176         },
2177 };
2178
2179 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2180         .halt_reg = 0x06010,
2181         .clkr = {
2182                 .enable_reg = 0x06010,
2183                 .enable_mask = BIT(0),
2184                 .hw.init = &(struct clk_init_data){
2185                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2186                         .parent_names = (const char *[]){
2187                                 "blsp1_qup5_i2c_apps_clk_src"
2188                         },
2189                         .num_parents = 1,
2190                         .flags = CLK_SET_RATE_PARENT,
2191                         .ops = &clk_branch2_ops,
2192                 },
2193         },
2194 };
2195
2196 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2197         .halt_reg = 0x0600c,
2198         .clkr = {
2199                 .enable_reg = 0x0600c,
2200                 .enable_mask = BIT(0),
2201                 .hw.init = &(struct clk_init_data){
2202                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2203                         .parent_names = (const char *[]){
2204                                 "blsp1_qup5_spi_apps_clk_src"
2205                         },
2206                         .num_parents = 1,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2214         .halt_reg = 0x07010,
2215         .clkr = {
2216                 .enable_reg = 0x07010,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data){
2219                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2220                         .parent_names = (const char *[]){
2221                                 "blsp1_qup6_i2c_apps_clk_src"
2222                         },
2223                         .num_parents = 1,
2224                         .flags = CLK_SET_RATE_PARENT,
2225                         .ops = &clk_branch2_ops,
2226                 },
2227         },
2228 };
2229
2230 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2231         .halt_reg = 0x0700c,
2232         .clkr = {
2233                 .enable_reg = 0x0700c,
2234                 .enable_mask = BIT(0),
2235                 .hw.init = &(struct clk_init_data){
2236                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2237                         .parent_names = (const char *[]){
2238                                 "blsp1_qup6_spi_apps_clk_src"
2239                         },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2248         .halt_reg = 0x0203c,
2249         .clkr = {
2250                 .enable_reg = 0x0203c,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_blsp1_uart1_apps_clk",
2254                         .parent_names = (const char *[]){
2255                                 "blsp1_uart1_apps_clk_src"
2256                         },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2265         .halt_reg = 0x0302c,
2266         .clkr = {
2267                 .enable_reg = 0x0302c,
2268                 .enable_mask = BIT(0),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_blsp1_uart2_apps_clk",
2271                         .parent_names = (const char *[]){
2272                                 "blsp1_uart2_apps_clk_src"
2273                         },
2274                         .num_parents = 1,
2275                         .flags = CLK_SET_RATE_PARENT,
2276                         .ops = &clk_branch2_ops,
2277                 },
2278         },
2279 };
2280
2281 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2282         .halt_reg = 0x0402c,
2283         .clkr = {
2284                 .enable_reg = 0x0402c,
2285                 .enable_mask = BIT(0),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "gcc_blsp1_uart3_apps_clk",
2288                         .parent_names = (const char *[]){
2289                                 "blsp1_uart3_apps_clk_src"
2290                         },
2291                         .num_parents = 1,
2292                         .flags = CLK_SET_RATE_PARENT,
2293                         .ops = &clk_branch2_ops,
2294                 },
2295         },
2296 };
2297
2298 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2299         .halt_reg = 0x0502c,
2300         .clkr = {
2301                 .enable_reg = 0x0502c,
2302                 .enable_mask = BIT(0),
2303                 .hw.init = &(struct clk_init_data){
2304                         .name = "gcc_blsp1_uart4_apps_clk",
2305                         .parent_names = (const char *[]){
2306                                 "blsp1_uart4_apps_clk_src"
2307                         },
2308                         .num_parents = 1,
2309                         .flags = CLK_SET_RATE_PARENT,
2310                         .ops = &clk_branch2_ops,
2311                 },
2312         },
2313 };
2314
2315 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2316         .halt_reg = 0x0602c,
2317         .clkr = {
2318                 .enable_reg = 0x0602c,
2319                 .enable_mask = BIT(0),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_blsp1_uart5_apps_clk",
2322                         .parent_names = (const char *[]){
2323                                 "blsp1_uart5_apps_clk_src"
2324                         },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2333         .halt_reg = 0x0702c,
2334         .clkr = {
2335                 .enable_reg = 0x0702c,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "gcc_blsp1_uart6_apps_clk",
2339                         .parent_names = (const char *[]){
2340                                 "blsp1_uart6_apps_clk_src"
2341                         },
2342                         .num_parents = 1,
2343                         .flags = CLK_SET_RATE_PARENT,
2344                         .ops = &clk_branch2_ops,
2345                 },
2346         },
2347 };
2348
2349 static struct clk_branch gcc_prng_ahb_clk = {
2350         .halt_reg = 0x13004,
2351         .halt_check = BRANCH_HALT_VOTED,
2352         .clkr = {
2353                 .enable_reg = 0x0b004,
2354                 .enable_mask = BIT(8),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gcc_prng_ahb_clk",
2357                         .parent_names = (const char *[]){
2358                                 "pcnoc_clk_src"
2359                         },
2360                         .num_parents = 1,
2361                         .flags = CLK_SET_RATE_PARENT,
2362                         .ops = &clk_branch2_ops,
2363                 },
2364         },
2365 };
2366
2367 static struct clk_branch gcc_qpic_ahb_clk = {
2368         .halt_reg = 0x57024,
2369         .clkr = {
2370                 .enable_reg = 0x57024,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "gcc_qpic_ahb_clk",
2374                         .parent_names = (const char *[]){
2375                                 "pcnoc_clk_src"
2376                         },
2377                         .num_parents = 1,
2378                         .flags = CLK_SET_RATE_PARENT,
2379                         .ops = &clk_branch2_ops,
2380                 },
2381         },
2382 };
2383
2384 static struct clk_branch gcc_qpic_clk = {
2385         .halt_reg = 0x57020,
2386         .clkr = {
2387                 .enable_reg = 0x57020,
2388                 .enable_mask = BIT(0),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gcc_qpic_clk",
2391                         .parent_names = (const char *[]){
2392                                 "pcnoc_clk_src"
2393                         },
2394                         .num_parents = 1,
2395                         .flags = CLK_SET_RATE_PARENT,
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_pcie0_ahb_clk = {
2402         .halt_reg = 0x75010,
2403         .clkr = {
2404                 .enable_reg = 0x75010,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_pcie0_ahb_clk",
2408                         .parent_names = (const char *[]){
2409                                 "pcnoc_clk_src"
2410                         },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_pcie0_aux_clk = {
2419         .halt_reg = 0x75014,
2420         .clkr = {
2421                 .enable_reg = 0x75014,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(struct clk_init_data){
2424                         .name = "gcc_pcie0_aux_clk",
2425                         .parent_names = (const char *[]){
2426                                 "pcie0_aux_clk_src"
2427                         },
2428                         .num_parents = 1,
2429                         .flags = CLK_SET_RATE_PARENT,
2430                         .ops = &clk_branch2_ops,
2431                 },
2432         },
2433 };
2434
2435 static struct clk_branch gcc_pcie0_axi_m_clk = {
2436         .halt_reg = 0x75008,
2437         .clkr = {
2438                 .enable_reg = 0x75008,
2439                 .enable_mask = BIT(0),
2440                 .hw.init = &(struct clk_init_data){
2441                         .name = "gcc_pcie0_axi_m_clk",
2442                         .parent_names = (const char *[]){
2443                                 "pcie0_axi_clk_src"
2444                         },
2445                         .num_parents = 1,
2446                         .flags = CLK_SET_RATE_PARENT,
2447                         .ops = &clk_branch2_ops,
2448                 },
2449         },
2450 };
2451
2452 static struct clk_branch gcc_pcie0_axi_s_clk = {
2453         .halt_reg = 0x7500c,
2454         .clkr = {
2455                 .enable_reg = 0x7500c,
2456                 .enable_mask = BIT(0),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "gcc_pcie0_axi_s_clk",
2459                         .parent_names = (const char *[]){
2460                                 "pcie0_axi_clk_src"
2461                         },
2462                         .num_parents = 1,
2463                         .flags = CLK_SET_RATE_PARENT,
2464                         .ops = &clk_branch2_ops,
2465                 },
2466         },
2467 };
2468
2469 static struct clk_branch gcc_pcie0_pipe_clk = {
2470         .halt_reg = 0x75018,
2471         .halt_check = BRANCH_HALT_DELAY,
2472         .clkr = {
2473                 .enable_reg = 0x75018,
2474                 .enable_mask = BIT(0),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "gcc_pcie0_pipe_clk",
2477                         .parent_names = (const char *[]){
2478                                 "pcie0_pipe_clk_src"
2479                         },
2480                         .num_parents = 1,
2481                         .flags = CLK_SET_RATE_PARENT,
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2488         .halt_reg = 0x26048,
2489         .clkr = {
2490                 .enable_reg = 0x26048,
2491                 .enable_mask = BIT(0),
2492                 .hw.init = &(struct clk_init_data){
2493                         .name = "gcc_sys_noc_pcie0_axi_clk",
2494                         .parent_names = (const char *[]){
2495                                 "pcie0_axi_clk_src"
2496                         },
2497                         .num_parents = 1,
2498                         .flags = CLK_SET_RATE_PARENT,
2499                         .ops = &clk_branch2_ops,
2500                 },
2501         },
2502 };
2503
2504 static struct clk_branch gcc_pcie1_ahb_clk = {
2505         .halt_reg = 0x76010,
2506         .clkr = {
2507                 .enable_reg = 0x76010,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "gcc_pcie1_ahb_clk",
2511                         .parent_names = (const char *[]){
2512                                 "pcnoc_clk_src"
2513                         },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_pcie1_aux_clk = {
2522         .halt_reg = 0x76014,
2523         .clkr = {
2524                 .enable_reg = 0x76014,
2525                 .enable_mask = BIT(0),
2526                 .hw.init = &(struct clk_init_data){
2527                         .name = "gcc_pcie1_aux_clk",
2528                         .parent_names = (const char *[]){
2529                                 "pcie1_aux_clk_src"
2530                         },
2531                         .num_parents = 1,
2532                         .flags = CLK_SET_RATE_PARENT,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_pcie1_axi_m_clk = {
2539         .halt_reg = 0x76008,
2540         .clkr = {
2541                 .enable_reg = 0x76008,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_pcie1_axi_m_clk",
2545                         .parent_names = (const char *[]){
2546                                 "pcie1_axi_clk_src"
2547                         },
2548                         .num_parents = 1,
2549                         .flags = CLK_SET_RATE_PARENT,
2550                         .ops = &clk_branch2_ops,
2551                 },
2552         },
2553 };
2554
2555 static struct clk_branch gcc_pcie1_axi_s_clk = {
2556         .halt_reg = 0x7600c,
2557         .clkr = {
2558                 .enable_reg = 0x7600c,
2559                 .enable_mask = BIT(0),
2560                 .hw.init = &(struct clk_init_data){
2561                         .name = "gcc_pcie1_axi_s_clk",
2562                         .parent_names = (const char *[]){
2563                                 "pcie1_axi_clk_src"
2564                         },
2565                         .num_parents = 1,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                         .ops = &clk_branch2_ops,
2568                 },
2569         },
2570 };
2571
2572 static struct clk_branch gcc_pcie1_pipe_clk = {
2573         .halt_reg = 0x76018,
2574         .halt_check = BRANCH_HALT_DELAY,
2575         .clkr = {
2576                 .enable_reg = 0x76018,
2577                 .enable_mask = BIT(0),
2578                 .hw.init = &(struct clk_init_data){
2579                         .name = "gcc_pcie1_pipe_clk",
2580                         .parent_names = (const char *[]){
2581                                 "pcie1_pipe_clk_src"
2582                         },
2583                         .num_parents = 1,
2584                         .flags = CLK_SET_RATE_PARENT,
2585                         .ops = &clk_branch2_ops,
2586                 },
2587         },
2588 };
2589
2590 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2591         .halt_reg = 0x2604c,
2592         .clkr = {
2593                 .enable_reg = 0x2604c,
2594                 .enable_mask = BIT(0),
2595                 .hw.init = &(struct clk_init_data){
2596                         .name = "gcc_sys_noc_pcie1_axi_clk",
2597                         .parent_names = (const char *[]){
2598                                 "pcie1_axi_clk_src"
2599                         },
2600                         .num_parents = 1,
2601                         .flags = CLK_SET_RATE_PARENT,
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 static struct clk_branch gcc_usb0_aux_clk = {
2608         .halt_reg = 0x3e044,
2609         .clkr = {
2610                 .enable_reg = 0x3e044,
2611                 .enable_mask = BIT(0),
2612                 .hw.init = &(struct clk_init_data){
2613                         .name = "gcc_usb0_aux_clk",
2614                         .parent_names = (const char *[]){
2615                                 "usb0_aux_clk_src"
2616                         },
2617                         .num_parents = 1,
2618                         .flags = CLK_SET_RATE_PARENT,
2619                         .ops = &clk_branch2_ops,
2620                 },
2621         },
2622 };
2623
2624 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2625         .halt_reg = 0x26040,
2626         .clkr = {
2627                 .enable_reg = 0x26040,
2628                 .enable_mask = BIT(0),
2629                 .hw.init = &(struct clk_init_data){
2630                         .name = "gcc_sys_noc_usb0_axi_clk",
2631                         .parent_names = (const char *[]){
2632                                 "usb0_master_clk_src"
2633                         },
2634                         .num_parents = 1,
2635                         .flags = CLK_SET_RATE_PARENT,
2636                         .ops = &clk_branch2_ops,
2637                 },
2638         },
2639 };
2640
2641 static struct clk_branch gcc_usb0_master_clk = {
2642         .halt_reg = 0x3e000,
2643         .clkr = {
2644                 .enable_reg = 0x3e000,
2645                 .enable_mask = BIT(0),
2646                 .hw.init = &(struct clk_init_data){
2647                         .name = "gcc_usb0_master_clk",
2648                         .parent_names = (const char *[]){
2649                                 "usb0_master_clk_src"
2650                         },
2651                         .num_parents = 1,
2652                         .flags = CLK_SET_RATE_PARENT,
2653                         .ops = &clk_branch2_ops,
2654                 },
2655         },
2656 };
2657
2658 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2659         .halt_reg = 0x3e008,
2660         .clkr = {
2661                 .enable_reg = 0x3e008,
2662                 .enable_mask = BIT(0),
2663                 .hw.init = &(struct clk_init_data){
2664                         .name = "gcc_usb0_mock_utmi_clk",
2665                         .parent_names = (const char *[]){
2666                                 "usb0_mock_utmi_clk_src"
2667                         },
2668                         .num_parents = 1,
2669                         .flags = CLK_SET_RATE_PARENT,
2670                         .ops = &clk_branch2_ops,
2671                 },
2672         },
2673 };
2674
2675 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2676         .halt_reg = 0x3e080,
2677         .clkr = {
2678                 .enable_reg = 0x3e080,
2679                 .enable_mask = BIT(0),
2680                 .hw.init = &(struct clk_init_data){
2681                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2682                         .parent_names = (const char *[]){
2683                                 "pcnoc_clk_src"
2684                         },
2685                         .num_parents = 1,
2686                         .flags = CLK_SET_RATE_PARENT,
2687                         .ops = &clk_branch2_ops,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch gcc_usb0_pipe_clk = {
2693         .halt_reg = 0x3e040,
2694         .halt_check = BRANCH_HALT_DELAY,
2695         .clkr = {
2696                 .enable_reg = 0x3e040,
2697                 .enable_mask = BIT(0),
2698                 .hw.init = &(struct clk_init_data){
2699                         .name = "gcc_usb0_pipe_clk",
2700                         .parent_names = (const char *[]){
2701                                 "usb0_pipe_clk_src"
2702                         },
2703                         .num_parents = 1,
2704                         .flags = CLK_SET_RATE_PARENT,
2705                         .ops = &clk_branch2_ops,
2706                 },
2707         },
2708 };
2709
2710 static struct clk_branch gcc_usb0_sleep_clk = {
2711         .halt_reg = 0x3e004,
2712         .clkr = {
2713                 .enable_reg = 0x3e004,
2714                 .enable_mask = BIT(0),
2715                 .hw.init = &(struct clk_init_data){
2716                         .name = "gcc_usb0_sleep_clk",
2717                         .parent_names = (const char *[]){
2718                                 "gcc_sleep_clk_src"
2719                         },
2720                         .num_parents = 1,
2721                         .flags = CLK_SET_RATE_PARENT,
2722                         .ops = &clk_branch2_ops,
2723                 },
2724         },
2725 };
2726
2727 static struct clk_branch gcc_usb1_aux_clk = {
2728         .halt_reg = 0x3f044,
2729         .clkr = {
2730                 .enable_reg = 0x3f044,
2731                 .enable_mask = BIT(0),
2732                 .hw.init = &(struct clk_init_data){
2733                         .name = "gcc_usb1_aux_clk",
2734                         .parent_names = (const char *[]){
2735                                 "usb1_aux_clk_src"
2736                         },
2737                         .num_parents = 1,
2738                         .flags = CLK_SET_RATE_PARENT,
2739                         .ops = &clk_branch2_ops,
2740                 },
2741         },
2742 };
2743
2744 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2745         .halt_reg = 0x26044,
2746         .clkr = {
2747                 .enable_reg = 0x26044,
2748                 .enable_mask = BIT(0),
2749                 .hw.init = &(struct clk_init_data){
2750                         .name = "gcc_sys_noc_usb1_axi_clk",
2751                         .parent_names = (const char *[]){
2752                                 "usb1_master_clk_src"
2753                         },
2754                         .num_parents = 1,
2755                         .flags = CLK_SET_RATE_PARENT,
2756                         .ops = &clk_branch2_ops,
2757                 },
2758         },
2759 };
2760
2761 static struct clk_branch gcc_usb1_master_clk = {
2762         .halt_reg = 0x3f000,
2763         .clkr = {
2764                 .enable_reg = 0x3f000,
2765                 .enable_mask = BIT(0),
2766                 .hw.init = &(struct clk_init_data){
2767                         .name = "gcc_usb1_master_clk",
2768                         .parent_names = (const char *[]){
2769                                 "usb1_master_clk_src"
2770                         },
2771                         .num_parents = 1,
2772                         .flags = CLK_SET_RATE_PARENT,
2773                         .ops = &clk_branch2_ops,
2774                 },
2775         },
2776 };
2777
2778 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2779         .halt_reg = 0x3f008,
2780         .clkr = {
2781                 .enable_reg = 0x3f008,
2782                 .enable_mask = BIT(0),
2783                 .hw.init = &(struct clk_init_data){
2784                         .name = "gcc_usb1_mock_utmi_clk",
2785                         .parent_names = (const char *[]){
2786                                 "usb1_mock_utmi_clk_src"
2787                         },
2788                         .num_parents = 1,
2789                         .flags = CLK_SET_RATE_PARENT,
2790                         .ops = &clk_branch2_ops,
2791                 },
2792         },
2793 };
2794
2795 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2796         .halt_reg = 0x3f080,
2797         .clkr = {
2798                 .enable_reg = 0x3f080,
2799                 .enable_mask = BIT(0),
2800                 .hw.init = &(struct clk_init_data){
2801                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2802                         .parent_names = (const char *[]){
2803                                 "pcnoc_clk_src"
2804                         },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_usb1_pipe_clk = {
2813         .halt_reg = 0x3f040,
2814         .halt_check = BRANCH_HALT_DELAY,
2815         .clkr = {
2816                 .enable_reg = 0x3f040,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_usb1_pipe_clk",
2820                         .parent_names = (const char *[]){
2821                                 "usb1_pipe_clk_src"
2822                         },
2823                         .num_parents = 1,
2824                         .flags = CLK_SET_RATE_PARENT,
2825                         .ops = &clk_branch2_ops,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch gcc_usb1_sleep_clk = {
2831         .halt_reg = 0x3f004,
2832         .clkr = {
2833                 .enable_reg = 0x3f004,
2834                 .enable_mask = BIT(0),
2835                 .hw.init = &(struct clk_init_data){
2836                         .name = "gcc_usb1_sleep_clk",
2837                         .parent_names = (const char *[]){
2838                                 "gcc_sleep_clk_src"
2839                         },
2840                         .num_parents = 1,
2841                         .flags = CLK_SET_RATE_PARENT,
2842                         .ops = &clk_branch2_ops,
2843                 },
2844         },
2845 };
2846
2847 static struct clk_branch gcc_sdcc1_ahb_clk = {
2848         .halt_reg = 0x4201c,
2849         .clkr = {
2850                 .enable_reg = 0x4201c,
2851                 .enable_mask = BIT(0),
2852                 .hw.init = &(struct clk_init_data){
2853                         .name = "gcc_sdcc1_ahb_clk",
2854                         .parent_names = (const char *[]){
2855                                 "pcnoc_clk_src"
2856                         },
2857                         .num_parents = 1,
2858                         .flags = CLK_SET_RATE_PARENT,
2859                         .ops = &clk_branch2_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch gcc_sdcc1_apps_clk = {
2865         .halt_reg = 0x42018,
2866         .clkr = {
2867                 .enable_reg = 0x42018,
2868                 .enable_mask = BIT(0),
2869                 .hw.init = &(struct clk_init_data){
2870                         .name = "gcc_sdcc1_apps_clk",
2871                         .parent_names = (const char *[]){
2872                                 "sdcc1_apps_clk_src"
2873                         },
2874                         .num_parents = 1,
2875                         .flags = CLK_SET_RATE_PARENT,
2876                         .ops = &clk_branch2_ops,
2877                 },
2878         },
2879 };
2880
2881 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2882         .halt_reg = 0x5d014,
2883         .clkr = {
2884                 .enable_reg = 0x5d014,
2885                 .enable_mask = BIT(0),
2886                 .hw.init = &(struct clk_init_data){
2887                         .name = "gcc_sdcc1_ice_core_clk",
2888                         .parent_names = (const char *[]){
2889                                 "sdcc1_ice_core_clk_src"
2890                         },
2891                         .num_parents = 1,
2892                         .flags = CLK_SET_RATE_PARENT,
2893                         .ops = &clk_branch2_ops,
2894                 },
2895         },
2896 };
2897
2898 static struct clk_branch gcc_sdcc2_ahb_clk = {
2899         .halt_reg = 0x4301c,
2900         .clkr = {
2901                 .enable_reg = 0x4301c,
2902                 .enable_mask = BIT(0),
2903                 .hw.init = &(struct clk_init_data){
2904                         .name = "gcc_sdcc2_ahb_clk",
2905                         .parent_names = (const char *[]){
2906                                 "pcnoc_clk_src"
2907                         },
2908                         .num_parents = 1,
2909                         .flags = CLK_SET_RATE_PARENT,
2910                         .ops = &clk_branch2_ops,
2911                 },
2912         },
2913 };
2914
2915 static struct clk_branch gcc_sdcc2_apps_clk = {
2916         .halt_reg = 0x43018,
2917         .clkr = {
2918                 .enable_reg = 0x43018,
2919                 .enable_mask = BIT(0),
2920                 .hw.init = &(struct clk_init_data){
2921                         .name = "gcc_sdcc2_apps_clk",
2922                         .parent_names = (const char *[]){
2923                                 "sdcc2_apps_clk_src"
2924                         },
2925                         .num_parents = 1,
2926                         .flags = CLK_SET_RATE_PARENT,
2927                         .ops = &clk_branch2_ops,
2928                 },
2929         },
2930 };
2931
2932 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2933         .halt_reg = 0x1d03c,
2934         .clkr = {
2935                 .enable_reg = 0x1d03c,
2936                 .enable_mask = BIT(0),
2937                 .hw.init = &(struct clk_init_data){
2938                         .name = "gcc_mem_noc_nss_axi_clk",
2939                         .parent_names = (const char *[]){
2940                                 "nss_noc_clk_src"
2941                         },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_nss_ce_apb_clk = {
2950         .halt_reg = 0x68174,
2951         .clkr = {
2952                 .enable_reg = 0x68174,
2953                 .enable_mask = BIT(0),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "gcc_nss_ce_apb_clk",
2956                         .parent_names = (const char *[]){
2957                                 "nss_ce_clk_src"
2958                         },
2959                         .num_parents = 1,
2960                         .flags = CLK_SET_RATE_PARENT,
2961                         .ops = &clk_branch2_ops,
2962                 },
2963         },
2964 };
2965
2966 static struct clk_branch gcc_nss_ce_axi_clk = {
2967         .halt_reg = 0x68170,
2968         .clkr = {
2969                 .enable_reg = 0x68170,
2970                 .enable_mask = BIT(0),
2971                 .hw.init = &(struct clk_init_data){
2972                         .name = "gcc_nss_ce_axi_clk",
2973                         .parent_names = (const char *[]){
2974                                 "nss_ce_clk_src"
2975                         },
2976                         .num_parents = 1,
2977                         .flags = CLK_SET_RATE_PARENT,
2978                         .ops = &clk_branch2_ops,
2979                 },
2980         },
2981 };
2982
2983 static struct clk_branch gcc_nss_cfg_clk = {
2984         .halt_reg = 0x68160,
2985         .clkr = {
2986                 .enable_reg = 0x68160,
2987                 .enable_mask = BIT(0),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "gcc_nss_cfg_clk",
2990                         .parent_names = (const char *[]){
2991                                 "pcnoc_clk_src"
2992                         },
2993                         .num_parents = 1,
2994                         .flags = CLK_SET_RATE_PARENT,
2995                         .ops = &clk_branch2_ops,
2996                 },
2997         },
2998 };
2999
3000 static struct clk_branch gcc_nss_crypto_clk = {
3001         .halt_reg = 0x68164,
3002         .clkr = {
3003                 .enable_reg = 0x68164,
3004                 .enable_mask = BIT(0),
3005                 .hw.init = &(struct clk_init_data){
3006                         .name = "gcc_nss_crypto_clk",
3007                         .parent_names = (const char *[]){
3008                                 "nss_crypto_clk_src"
3009                         },
3010                         .num_parents = 1,
3011                         .flags = CLK_SET_RATE_PARENT,
3012                         .ops = &clk_branch2_ops,
3013                 },
3014         },
3015 };
3016
3017 static struct clk_branch gcc_nss_csr_clk = {
3018         .halt_reg = 0x68318,
3019         .clkr = {
3020                 .enable_reg = 0x68318,
3021                 .enable_mask = BIT(0),
3022                 .hw.init = &(struct clk_init_data){
3023                         .name = "gcc_nss_csr_clk",
3024                         .parent_names = (const char *[]){
3025                                 "nss_ce_clk_src"
3026                         },
3027                         .num_parents = 1,
3028                         .flags = CLK_SET_RATE_PARENT,
3029                         .ops = &clk_branch2_ops,
3030                 },
3031         },
3032 };
3033
3034 static struct clk_branch gcc_nss_edma_cfg_clk = {
3035         .halt_reg = 0x6819c,
3036         .clkr = {
3037                 .enable_reg = 0x6819c,
3038                 .enable_mask = BIT(0),
3039                 .hw.init = &(struct clk_init_data){
3040                         .name = "gcc_nss_edma_cfg_clk",
3041                         .parent_names = (const char *[]){
3042                                 "nss_ppe_clk_src"
3043                         },
3044                         .num_parents = 1,
3045                         .flags = CLK_SET_RATE_PARENT,
3046                         .ops = &clk_branch2_ops,
3047                 },
3048         },
3049 };
3050
3051 static struct clk_branch gcc_nss_edma_clk = {
3052         .halt_reg = 0x68198,
3053         .clkr = {
3054                 .enable_reg = 0x68198,
3055                 .enable_mask = BIT(0),
3056                 .hw.init = &(struct clk_init_data){
3057                         .name = "gcc_nss_edma_clk",
3058                         .parent_names = (const char *[]){
3059                                 "nss_ppe_clk_src"
3060                         },
3061                         .num_parents = 1,
3062                         .flags = CLK_SET_RATE_PARENT,
3063                         .ops = &clk_branch2_ops,
3064                 },
3065         },
3066 };
3067
3068 static struct clk_branch gcc_nss_imem_clk = {
3069         .halt_reg = 0x68178,
3070         .clkr = {
3071                 .enable_reg = 0x68178,
3072                 .enable_mask = BIT(0),
3073                 .hw.init = &(struct clk_init_data){
3074                         .name = "gcc_nss_imem_clk",
3075                         .parent_names = (const char *[]){
3076                                 "nss_imem_clk_src"
3077                         },
3078                         .num_parents = 1,
3079                         .flags = CLK_SET_RATE_PARENT,
3080                         .ops = &clk_branch2_ops,
3081                 },
3082         },
3083 };
3084
3085 static struct clk_branch gcc_nss_noc_clk = {
3086         .halt_reg = 0x68168,
3087         .clkr = {
3088                 .enable_reg = 0x68168,
3089                 .enable_mask = BIT(0),
3090                 .hw.init = &(struct clk_init_data){
3091                         .name = "gcc_nss_noc_clk",
3092                         .parent_names = (const char *[]){
3093                                 "nss_noc_clk_src"
3094                         },
3095                         .num_parents = 1,
3096                         .flags = CLK_SET_RATE_PARENT,
3097                         .ops = &clk_branch2_ops,
3098                 },
3099         },
3100 };
3101
3102 static struct clk_branch gcc_nss_ppe_btq_clk = {
3103         .halt_reg = 0x6833c,
3104         .clkr = {
3105                 .enable_reg = 0x6833c,
3106                 .enable_mask = BIT(0),
3107                 .hw.init = &(struct clk_init_data){
3108                         .name = "gcc_nss_ppe_btq_clk",
3109                         .parent_names = (const char *[]){
3110                                 "nss_ppe_clk_src"
3111                         },
3112                         .num_parents = 1,
3113                         .flags = CLK_SET_RATE_PARENT,
3114                         .ops = &clk_branch2_ops,
3115                 },
3116         },
3117 };
3118
3119 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3120         .halt_reg = 0x68194,
3121         .clkr = {
3122                 .enable_reg = 0x68194,
3123                 .enable_mask = BIT(0),
3124                 .hw.init = &(struct clk_init_data){
3125                         .name = "gcc_nss_ppe_cfg_clk",
3126                         .parent_names = (const char *[]){
3127                                 "nss_ppe_clk_src"
3128                         },
3129                         .num_parents = 1,
3130                         .flags = CLK_SET_RATE_PARENT,
3131                         .ops = &clk_branch2_ops,
3132                 },
3133         },
3134 };
3135
3136 static struct clk_branch gcc_nss_ppe_clk = {
3137         .halt_reg = 0x68190,
3138         .clkr = {
3139                 .enable_reg = 0x68190,
3140                 .enable_mask = BIT(0),
3141                 .hw.init = &(struct clk_init_data){
3142                         .name = "gcc_nss_ppe_clk",
3143                         .parent_names = (const char *[]){
3144                                 "nss_ppe_clk_src"
3145                         },
3146                         .num_parents = 1,
3147                         .flags = CLK_SET_RATE_PARENT,
3148                         .ops = &clk_branch2_ops,
3149                 },
3150         },
3151 };
3152
3153 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3154         .halt_reg = 0x68338,
3155         .clkr = {
3156                 .enable_reg = 0x68338,
3157                 .enable_mask = BIT(0),
3158                 .hw.init = &(struct clk_init_data){
3159                         .name = "gcc_nss_ppe_ipe_clk",
3160                         .parent_names = (const char *[]){
3161                                 "nss_ppe_clk_src"
3162                         },
3163                         .num_parents = 1,
3164                         .flags = CLK_SET_RATE_PARENT,
3165                         .ops = &clk_branch2_ops,
3166                 },
3167         },
3168 };
3169
3170 static struct clk_branch gcc_nss_ptp_ref_clk = {
3171         .halt_reg = 0x6816c,
3172         .clkr = {
3173                 .enable_reg = 0x6816c,
3174                 .enable_mask = BIT(0),
3175                 .hw.init = &(struct clk_init_data){
3176                         .name = "gcc_nss_ptp_ref_clk",
3177                         .parent_names = (const char *[]){
3178                                 "nss_ppe_cdiv_clk_src"
3179                         },
3180                         .num_parents = 1,
3181                         .flags = CLK_SET_RATE_PARENT,
3182                         .ops = &clk_branch2_ops,
3183                 },
3184         },
3185 };
3186
3187 static struct clk_branch gcc_crypto_ppe_clk = {
3188         .halt_reg = 0x68310,
3189         .halt_bit = 31,
3190         .clkr = {
3191                 .enable_reg = 0x68310,
3192                 .enable_mask = BIT(0),
3193                 .hw.init = &(struct clk_init_data){
3194                         .name = "gcc_crypto_ppe_clk",
3195                         .parent_names = (const char *[]){
3196                                 "nss_ppe_clk_src"
3197                         },
3198                         .num_parents = 1,
3199                         .flags = CLK_SET_RATE_PARENT,
3200                         .ops = &clk_branch2_ops,
3201                 },
3202         },
3203 };
3204
3205 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3206         .halt_reg = 0x6830c,
3207         .clkr = {
3208                 .enable_reg = 0x6830c,
3209                 .enable_mask = BIT(0),
3210                 .hw.init = &(struct clk_init_data){
3211                         .name = "gcc_nssnoc_ce_apb_clk",
3212                         .parent_names = (const char *[]){
3213                                 "nss_ce_clk_src"
3214                         },
3215                         .num_parents = 1,
3216                         .flags = CLK_SET_RATE_PARENT,
3217                         .ops = &clk_branch2_ops,
3218                 },
3219         },
3220 };
3221
3222 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3223         .halt_reg = 0x68308,
3224         .clkr = {
3225                 .enable_reg = 0x68308,
3226                 .enable_mask = BIT(0),
3227                 .hw.init = &(struct clk_init_data){
3228                         .name = "gcc_nssnoc_ce_axi_clk",
3229                         .parent_names = (const char *[]){
3230                                 "nss_ce_clk_src"
3231                         },
3232                         .num_parents = 1,
3233                         .flags = CLK_SET_RATE_PARENT,
3234                         .ops = &clk_branch2_ops,
3235                 },
3236         },
3237 };
3238
3239 static struct clk_branch gcc_nssnoc_crypto_clk = {
3240         .halt_reg = 0x68314,
3241         .clkr = {
3242                 .enable_reg = 0x68314,
3243                 .enable_mask = BIT(0),
3244                 .hw.init = &(struct clk_init_data){
3245                         .name = "gcc_nssnoc_crypto_clk",
3246                         .parent_names = (const char *[]){
3247                                 "nss_crypto_clk_src"
3248                         },
3249                         .num_parents = 1,
3250                         .flags = CLK_SET_RATE_PARENT,
3251                         .ops = &clk_branch2_ops,
3252                 },
3253         },
3254 };
3255
3256 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3257         .halt_reg = 0x68304,
3258         .clkr = {
3259                 .enable_reg = 0x68304,
3260                 .enable_mask = BIT(0),
3261                 .hw.init = &(struct clk_init_data){
3262                         .name = "gcc_nssnoc_ppe_cfg_clk",
3263                         .parent_names = (const char *[]){
3264                                 "nss_ppe_clk_src"
3265                         },
3266                         .num_parents = 1,
3267                         .flags = CLK_SET_RATE_PARENT,
3268                         .ops = &clk_branch2_ops,
3269                 },
3270         },
3271 };
3272
3273 static struct clk_branch gcc_nssnoc_ppe_clk = {
3274         .halt_reg = 0x68300,
3275         .clkr = {
3276                 .enable_reg = 0x68300,
3277                 .enable_mask = BIT(0),
3278                 .hw.init = &(struct clk_init_data){
3279                         .name = "gcc_nssnoc_ppe_clk",
3280                         .parent_names = (const char *[]){
3281                                 "nss_ppe_clk_src"
3282                         },
3283                         .num_parents = 1,
3284                         .flags = CLK_SET_RATE_PARENT,
3285                         .ops = &clk_branch2_ops,
3286                 },
3287         },
3288 };
3289
3290 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3291         .halt_reg = 0x68180,
3292         .clkr = {
3293                 .enable_reg = 0x68180,
3294                 .enable_mask = BIT(0),
3295                 .hw.init = &(struct clk_init_data){
3296                         .name = "gcc_nssnoc_qosgen_ref_clk",
3297                         .parent_names = (const char *[]){
3298                                 "gcc_xo_clk_src"
3299                         },
3300                         .num_parents = 1,
3301                         .flags = CLK_SET_RATE_PARENT,
3302                         .ops = &clk_branch2_ops,
3303                 },
3304         },
3305 };
3306
3307 static struct clk_branch gcc_nssnoc_snoc_clk = {
3308         .halt_reg = 0x68188,
3309         .clkr = {
3310                 .enable_reg = 0x68188,
3311                 .enable_mask = BIT(0),
3312                 .hw.init = &(struct clk_init_data){
3313                         .name = "gcc_nssnoc_snoc_clk",
3314                         .parent_names = (const char *[]){
3315                                 "system_noc_clk_src"
3316                         },
3317                         .num_parents = 1,
3318                         .flags = CLK_SET_RATE_PARENT,
3319                         .ops = &clk_branch2_ops,
3320                 },
3321         },
3322 };
3323
3324 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3325         .halt_reg = 0x68184,
3326         .clkr = {
3327                 .enable_reg = 0x68184,
3328                 .enable_mask = BIT(0),
3329                 .hw.init = &(struct clk_init_data){
3330                         .name = "gcc_nssnoc_timeout_ref_clk",
3331                         .parent_names = (const char *[]){
3332                                 "gcc_xo_div4_clk_src"
3333                         },
3334                         .num_parents = 1,
3335                         .flags = CLK_SET_RATE_PARENT,
3336                         .ops = &clk_branch2_ops,
3337                 },
3338         },
3339 };
3340
3341 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3342         .halt_reg = 0x68270,
3343         .clkr = {
3344                 .enable_reg = 0x68270,
3345                 .enable_mask = BIT(0),
3346                 .hw.init = &(struct clk_init_data){
3347                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3348                         .parent_names = (const char *[]){
3349                                 "nss_ce_clk_src"
3350                         },
3351                         .num_parents = 1,
3352                         .flags = CLK_SET_RATE_PARENT,
3353                         .ops = &clk_branch2_ops,
3354                 },
3355         },
3356 };
3357
3358 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3359         .halt_reg = 0x68274,
3360         .clkr = {
3361                 .enable_reg = 0x68274,
3362                 .enable_mask = BIT(0),
3363                 .hw.init = &(struct clk_init_data){
3364                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3365                         .parent_names = (const char *[]){
3366                                 "nss_ce_clk_src"
3367                         },
3368                         .num_parents = 1,
3369                         .flags = CLK_SET_RATE_PARENT,
3370                         .ops = &clk_branch2_ops,
3371                 },
3372         },
3373 };
3374
3375 static struct clk_branch gcc_ubi0_ahb_clk = {
3376         .halt_reg = 0x6820c,
3377         .halt_check = BRANCH_HALT_DELAY,
3378         .clkr = {
3379                 .enable_reg = 0x6820c,
3380                 .enable_mask = BIT(0),
3381                 .hw.init = &(struct clk_init_data){
3382                         .name = "gcc_ubi0_ahb_clk",
3383                         .parent_names = (const char *[]){
3384                                 "nss_ce_clk_src"
3385                         },
3386                         .num_parents = 1,
3387                         .flags = CLK_SET_RATE_PARENT,
3388                         .ops = &clk_branch2_ops,
3389                 },
3390         },
3391 };
3392
3393 static struct clk_branch gcc_ubi0_axi_clk = {
3394         .halt_reg = 0x68200,
3395         .halt_check = BRANCH_HALT_DELAY,
3396         .clkr = {
3397                 .enable_reg = 0x68200,
3398                 .enable_mask = BIT(0),
3399                 .hw.init = &(struct clk_init_data){
3400                         .name = "gcc_ubi0_axi_clk",
3401                         .parent_names = (const char *[]){
3402                                 "nss_noc_clk_src"
3403                         },
3404                         .num_parents = 1,
3405                         .flags = CLK_SET_RATE_PARENT,
3406                         .ops = &clk_branch2_ops,
3407                 },
3408         },
3409 };
3410
3411 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3412         .halt_reg = 0x68204,
3413         .halt_check = BRANCH_HALT_DELAY,
3414         .clkr = {
3415                 .enable_reg = 0x68204,
3416                 .enable_mask = BIT(0),
3417                 .hw.init = &(struct clk_init_data){
3418                         .name = "gcc_ubi0_nc_axi_clk",
3419                         .parent_names = (const char *[]){
3420                                 "nss_noc_clk_src"
3421                         },
3422                         .num_parents = 1,
3423                         .flags = CLK_SET_RATE_PARENT,
3424                         .ops = &clk_branch2_ops,
3425                 },
3426         },
3427 };
3428
3429 static struct clk_branch gcc_ubi0_core_clk = {
3430         .halt_reg = 0x68210,
3431         .halt_check = BRANCH_HALT_DELAY,
3432         .clkr = {
3433                 .enable_reg = 0x68210,
3434                 .enable_mask = BIT(0),
3435                 .hw.init = &(struct clk_init_data){
3436                         .name = "gcc_ubi0_core_clk",
3437                         .parent_names = (const char *[]){
3438                                 "nss_ubi0_div_clk_src"
3439                         },
3440                         .num_parents = 1,
3441                         .flags = CLK_SET_RATE_PARENT,
3442                         .ops = &clk_branch2_ops,
3443                 },
3444         },
3445 };
3446
3447 static struct clk_branch gcc_ubi0_mpt_clk = {
3448         .halt_reg = 0x68208,
3449         .halt_check = BRANCH_HALT_DELAY,
3450         .clkr = {
3451                 .enable_reg = 0x68208,
3452                 .enable_mask = BIT(0),
3453                 .hw.init = &(struct clk_init_data){
3454                         .name = "gcc_ubi0_mpt_clk",
3455                         .parent_names = (const char *[]){
3456                                 "ubi_mpt_clk_src"
3457                         },
3458                         .num_parents = 1,
3459                         .flags = CLK_SET_RATE_PARENT,
3460                         .ops = &clk_branch2_ops,
3461                 },
3462         },
3463 };
3464
3465 static struct clk_branch gcc_ubi1_ahb_clk = {
3466         .halt_reg = 0x6822c,
3467         .halt_check = BRANCH_HALT_DELAY,
3468         .clkr = {
3469                 .enable_reg = 0x6822c,
3470                 .enable_mask = BIT(0),
3471                 .hw.init = &(struct clk_init_data){
3472                         .name = "gcc_ubi1_ahb_clk",
3473                         .parent_names = (const char *[]){
3474                                 "nss_ce_clk_src"
3475                         },
3476                         .num_parents = 1,
3477                         .flags = CLK_SET_RATE_PARENT,
3478                         .ops = &clk_branch2_ops,
3479                 },
3480         },
3481 };
3482
3483 static struct clk_branch gcc_ubi1_axi_clk = {
3484         .halt_reg = 0x68220,
3485         .halt_check = BRANCH_HALT_DELAY,
3486         .clkr = {
3487                 .enable_reg = 0x68220,
3488                 .enable_mask = BIT(0),
3489                 .hw.init = &(struct clk_init_data){
3490                         .name = "gcc_ubi1_axi_clk",
3491                         .parent_names = (const char *[]){
3492                                 "nss_noc_clk_src"
3493                         },
3494                         .num_parents = 1,
3495                         .flags = CLK_SET_RATE_PARENT,
3496                         .ops = &clk_branch2_ops,
3497                 },
3498         },
3499 };
3500
3501 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3502         .halt_reg = 0x68224,
3503         .halt_check = BRANCH_HALT_DELAY,
3504         .clkr = {
3505                 .enable_reg = 0x68224,
3506                 .enable_mask = BIT(0),
3507                 .hw.init = &(struct clk_init_data){
3508                         .name = "gcc_ubi1_nc_axi_clk",
3509                         .parent_names = (const char *[]){
3510                                 "nss_noc_clk_src"
3511                         },
3512                         .num_parents = 1,
3513                         .flags = CLK_SET_RATE_PARENT,
3514                         .ops = &clk_branch2_ops,
3515                 },
3516         },
3517 };
3518
3519 static struct clk_branch gcc_ubi1_core_clk = {
3520         .halt_reg = 0x68230,
3521         .halt_check = BRANCH_HALT_DELAY,
3522         .clkr = {
3523                 .enable_reg = 0x68230,
3524                 .enable_mask = BIT(0),
3525                 .hw.init = &(struct clk_init_data){
3526                         .name = "gcc_ubi1_core_clk",
3527                         .parent_names = (const char *[]){
3528                                 "nss_ubi1_div_clk_src"
3529                         },
3530                         .num_parents = 1,
3531                         .flags = CLK_SET_RATE_PARENT,
3532                         .ops = &clk_branch2_ops,
3533                 },
3534         },
3535 };
3536
3537 static struct clk_branch gcc_ubi1_mpt_clk = {
3538         .halt_reg = 0x68228,
3539         .halt_check = BRANCH_HALT_DELAY,
3540         .clkr = {
3541                 .enable_reg = 0x68228,
3542                 .enable_mask = BIT(0),
3543                 .hw.init = &(struct clk_init_data){
3544                         .name = "gcc_ubi1_mpt_clk",
3545                         .parent_names = (const char *[]){
3546                                 "ubi_mpt_clk_src"
3547                         },
3548                         .num_parents = 1,
3549                         .flags = CLK_SET_RATE_PARENT,
3550                         .ops = &clk_branch2_ops,
3551                 },
3552         },
3553 };
3554
3555 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3556         .halt_reg = 0x56308,
3557         .clkr = {
3558                 .enable_reg = 0x56308,
3559                 .enable_mask = BIT(0),
3560                 .hw.init = &(struct clk_init_data){
3561                         .name = "gcc_cmn_12gpll_ahb_clk",
3562                         .parent_names = (const char *[]){
3563                                 "pcnoc_clk_src"
3564                         },
3565                         .num_parents = 1,
3566                         .flags = CLK_SET_RATE_PARENT,
3567                         .ops = &clk_branch2_ops,
3568                 },
3569         },
3570 };
3571
3572 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3573         .halt_reg = 0x5630c,
3574         .clkr = {
3575                 .enable_reg = 0x5630c,
3576                 .enable_mask = BIT(0),
3577                 .hw.init = &(struct clk_init_data){
3578                         .name = "gcc_cmn_12gpll_sys_clk",
3579                         .parent_names = (const char *[]){
3580                                 "gcc_xo_clk_src"
3581                         },
3582                         .num_parents = 1,
3583                         .flags = CLK_SET_RATE_PARENT,
3584                         .ops = &clk_branch2_ops,
3585                 },
3586         },
3587 };
3588
3589 static struct clk_branch gcc_mdio_ahb_clk = {
3590         .halt_reg = 0x58004,
3591         .clkr = {
3592                 .enable_reg = 0x58004,
3593                 .enable_mask = BIT(0),
3594                 .hw.init = &(struct clk_init_data){
3595                         .name = "gcc_mdio_ahb_clk",
3596                         .parent_names = (const char *[]){
3597                                 "pcnoc_clk_src"
3598                         },
3599                         .num_parents = 1,
3600                         .flags = CLK_SET_RATE_PARENT,
3601                         .ops = &clk_branch2_ops,
3602                 },
3603         },
3604 };
3605
3606 static struct clk_branch gcc_uniphy0_ahb_clk = {
3607         .halt_reg = 0x56008,
3608         .clkr = {
3609                 .enable_reg = 0x56008,
3610                 .enable_mask = BIT(0),
3611                 .hw.init = &(struct clk_init_data){
3612                         .name = "gcc_uniphy0_ahb_clk",
3613                         .parent_names = (const char *[]){
3614                                 "pcnoc_clk_src"
3615                         },
3616                         .num_parents = 1,
3617                         .flags = CLK_SET_RATE_PARENT,
3618                         .ops = &clk_branch2_ops,
3619                 },
3620         },
3621 };
3622
3623 static struct clk_branch gcc_uniphy0_sys_clk = {
3624         .halt_reg = 0x5600c,
3625         .clkr = {
3626                 .enable_reg = 0x5600c,
3627                 .enable_mask = BIT(0),
3628                 .hw.init = &(struct clk_init_data){
3629                         .name = "gcc_uniphy0_sys_clk",
3630                         .parent_names = (const char *[]){
3631                                 "gcc_xo_clk_src"
3632                         },
3633                         .num_parents = 1,
3634                         .flags = CLK_SET_RATE_PARENT,
3635                         .ops = &clk_branch2_ops,
3636                 },
3637         },
3638 };
3639
3640 static struct clk_branch gcc_uniphy1_ahb_clk = {
3641         .halt_reg = 0x56108,
3642         .clkr = {
3643                 .enable_reg = 0x56108,
3644                 .enable_mask = BIT(0),
3645                 .hw.init = &(struct clk_init_data){
3646                         .name = "gcc_uniphy1_ahb_clk",
3647                         .parent_names = (const char *[]){
3648                                 "pcnoc_clk_src"
3649                         },
3650                         .num_parents = 1,
3651                         .flags = CLK_SET_RATE_PARENT,
3652                         .ops = &clk_branch2_ops,
3653                 },
3654         },
3655 };
3656
3657 static struct clk_branch gcc_uniphy1_sys_clk = {
3658         .halt_reg = 0x5610c,
3659         .clkr = {
3660                 .enable_reg = 0x5610c,
3661                 .enable_mask = BIT(0),
3662                 .hw.init = &(struct clk_init_data){
3663                         .name = "gcc_uniphy1_sys_clk",
3664                         .parent_names = (const char *[]){
3665                                 "gcc_xo_clk_src"
3666                         },
3667                         .num_parents = 1,
3668                         .flags = CLK_SET_RATE_PARENT,
3669                         .ops = &clk_branch2_ops,
3670                 },
3671         },
3672 };
3673
3674 static struct clk_branch gcc_uniphy2_ahb_clk = {
3675         .halt_reg = 0x56208,
3676         .clkr = {
3677                 .enable_reg = 0x56208,
3678                 .enable_mask = BIT(0),
3679                 .hw.init = &(struct clk_init_data){
3680                         .name = "gcc_uniphy2_ahb_clk",
3681                         .parent_names = (const char *[]){
3682                                 "pcnoc_clk_src"
3683                         },
3684                         .num_parents = 1,
3685                         .flags = CLK_SET_RATE_PARENT,
3686                         .ops = &clk_branch2_ops,
3687                 },
3688         },
3689 };
3690
3691 static struct clk_branch gcc_uniphy2_sys_clk = {
3692         .halt_reg = 0x5620c,
3693         .clkr = {
3694                 .enable_reg = 0x5620c,
3695                 .enable_mask = BIT(0),
3696                 .hw.init = &(struct clk_init_data){
3697                         .name = "gcc_uniphy2_sys_clk",
3698                         .parent_names = (const char *[]){
3699                                 "gcc_xo_clk_src"
3700                         },
3701                         .num_parents = 1,
3702                         .flags = CLK_SET_RATE_PARENT,
3703                         .ops = &clk_branch2_ops,
3704                 },
3705         },
3706 };
3707
3708 static struct clk_branch gcc_nss_port1_rx_clk = {
3709         .halt_reg = 0x68240,
3710         .clkr = {
3711                 .enable_reg = 0x68240,
3712                 .enable_mask = BIT(0),
3713                 .hw.init = &(struct clk_init_data){
3714                         .name = "gcc_nss_port1_rx_clk",
3715                         .parent_names = (const char *[]){
3716                                 "nss_port1_rx_div_clk_src"
3717                         },
3718                         .num_parents = 1,
3719                         .flags = CLK_SET_RATE_PARENT,
3720                         .ops = &clk_branch2_ops,
3721                 },
3722         },
3723 };
3724
3725 static struct clk_branch gcc_nss_port1_tx_clk = {
3726         .halt_reg = 0x68244,
3727         .clkr = {
3728                 .enable_reg = 0x68244,
3729                 .enable_mask = BIT(0),
3730                 .hw.init = &(struct clk_init_data){
3731                         .name = "gcc_nss_port1_tx_clk",
3732                         .parent_names = (const char *[]){
3733                                 "nss_port1_tx_div_clk_src"
3734                         },
3735                         .num_parents = 1,
3736                         .flags = CLK_SET_RATE_PARENT,
3737                         .ops = &clk_branch2_ops,
3738                 },
3739         },
3740 };
3741
3742 static struct clk_branch gcc_nss_port2_rx_clk = {
3743         .halt_reg = 0x68248,
3744         .clkr = {
3745                 .enable_reg = 0x68248,
3746                 .enable_mask = BIT(0),
3747                 .hw.init = &(struct clk_init_data){
3748                         .name = "gcc_nss_port2_rx_clk",
3749                         .parent_names = (const char *[]){
3750                                 "nss_port2_rx_div_clk_src"
3751                         },
3752                         .num_parents = 1,
3753                         .flags = CLK_SET_RATE_PARENT,
3754                         .ops = &clk_branch2_ops,
3755                 },
3756         },
3757 };
3758
3759 static struct clk_branch gcc_nss_port2_tx_clk = {
3760         .halt_reg = 0x6824c,
3761         .clkr = {
3762                 .enable_reg = 0x6824c,
3763                 .enable_mask = BIT(0),
3764                 .hw.init = &(struct clk_init_data){
3765                         .name = "gcc_nss_port2_tx_clk",
3766                         .parent_names = (const char *[]){
3767                                 "nss_port2_tx_div_clk_src"
3768                         },
3769                         .num_parents = 1,
3770                         .flags = CLK_SET_RATE_PARENT,
3771                         .ops = &clk_branch2_ops,
3772                 },
3773         },
3774 };
3775
3776 static struct clk_branch gcc_nss_port3_rx_clk = {
3777         .halt_reg = 0x68250,
3778         .clkr = {
3779                 .enable_reg = 0x68250,
3780                 .enable_mask = BIT(0),
3781                 .hw.init = &(struct clk_init_data){
3782                         .name = "gcc_nss_port3_rx_clk",
3783                         .parent_names = (const char *[]){
3784                                 "nss_port3_rx_div_clk_src"
3785                         },
3786                         .num_parents = 1,
3787                         .flags = CLK_SET_RATE_PARENT,
3788                         .ops = &clk_branch2_ops,
3789                 },
3790         },
3791 };
3792
3793 static struct clk_branch gcc_nss_port3_tx_clk = {
3794         .halt_reg = 0x68254,
3795         .clkr = {
3796                 .enable_reg = 0x68254,
3797                 .enable_mask = BIT(0),
3798                 .hw.init = &(struct clk_init_data){
3799                         .name = "gcc_nss_port3_tx_clk",
3800                         .parent_names = (const char *[]){
3801                                 "nss_port3_tx_div_clk_src"
3802                         },
3803                         .num_parents = 1,
3804                         .flags = CLK_SET_RATE_PARENT,
3805                         .ops = &clk_branch2_ops,
3806                 },
3807         },
3808 };
3809
3810 static struct clk_branch gcc_nss_port4_rx_clk = {
3811         .halt_reg = 0x68258,
3812         .clkr = {
3813                 .enable_reg = 0x68258,
3814                 .enable_mask = BIT(0),
3815                 .hw.init = &(struct clk_init_data){
3816                         .name = "gcc_nss_port4_rx_clk",
3817                         .parent_names = (const char *[]){
3818                                 "nss_port4_rx_div_clk_src"
3819                         },
3820                         .num_parents = 1,
3821                         .flags = CLK_SET_RATE_PARENT,
3822                         .ops = &clk_branch2_ops,
3823                 },
3824         },
3825 };
3826
3827 static struct clk_branch gcc_nss_port4_tx_clk = {
3828         .halt_reg = 0x6825c,
3829         .clkr = {
3830                 .enable_reg = 0x6825c,
3831                 .enable_mask = BIT(0),
3832                 .hw.init = &(struct clk_init_data){
3833                         .name = "gcc_nss_port4_tx_clk",
3834                         .parent_names = (const char *[]){
3835                                 "nss_port4_tx_div_clk_src"
3836                         },
3837                         .num_parents = 1,
3838                         .flags = CLK_SET_RATE_PARENT,
3839                         .ops = &clk_branch2_ops,
3840                 },
3841         },
3842 };
3843
3844 static struct clk_branch gcc_nss_port5_rx_clk = {
3845         .halt_reg = 0x68260,
3846         .clkr = {
3847                 .enable_reg = 0x68260,
3848                 .enable_mask = BIT(0),
3849                 .hw.init = &(struct clk_init_data){
3850                         .name = "gcc_nss_port5_rx_clk",
3851                         .parent_names = (const char *[]){
3852                                 "nss_port5_rx_div_clk_src"
3853                         },
3854                         .num_parents = 1,
3855                         .flags = CLK_SET_RATE_PARENT,
3856                         .ops = &clk_branch2_ops,
3857                 },
3858         },
3859 };
3860
3861 static struct clk_branch gcc_nss_port5_tx_clk = {
3862         .halt_reg = 0x68264,
3863         .clkr = {
3864                 .enable_reg = 0x68264,
3865                 .enable_mask = BIT(0),
3866                 .hw.init = &(struct clk_init_data){
3867                         .name = "gcc_nss_port5_tx_clk",
3868                         .parent_names = (const char *[]){
3869                                 "nss_port5_tx_div_clk_src"
3870                         },
3871                         .num_parents = 1,
3872                         .flags = CLK_SET_RATE_PARENT,
3873                         .ops = &clk_branch2_ops,
3874                 },
3875         },
3876 };
3877
3878 static struct clk_branch gcc_nss_port6_rx_clk = {
3879         .halt_reg = 0x68268,
3880         .clkr = {
3881                 .enable_reg = 0x68268,
3882                 .enable_mask = BIT(0),
3883                 .hw.init = &(struct clk_init_data){
3884                         .name = "gcc_nss_port6_rx_clk",
3885                         .parent_names = (const char *[]){
3886                                 "nss_port6_rx_div_clk_src"
3887                         },
3888                         .num_parents = 1,
3889                         .flags = CLK_SET_RATE_PARENT,
3890                         .ops = &clk_branch2_ops,
3891                 },
3892         },
3893 };
3894
3895 static struct clk_branch gcc_nss_port6_tx_clk = {
3896         .halt_reg = 0x6826c,
3897         .clkr = {
3898                 .enable_reg = 0x6826c,
3899                 .enable_mask = BIT(0),
3900                 .hw.init = &(struct clk_init_data){
3901                         .name = "gcc_nss_port6_tx_clk",
3902                         .parent_names = (const char *[]){
3903                                 "nss_port6_tx_div_clk_src"
3904                         },
3905                         .num_parents = 1,
3906                         .flags = CLK_SET_RATE_PARENT,
3907                         .ops = &clk_branch2_ops,
3908                 },
3909         },
3910 };
3911
3912 static struct clk_branch gcc_port1_mac_clk = {
3913         .halt_reg = 0x68320,
3914         .clkr = {
3915                 .enable_reg = 0x68320,
3916                 .enable_mask = BIT(0),
3917                 .hw.init = &(struct clk_init_data){
3918                         .name = "gcc_port1_mac_clk",
3919                         .parent_names = (const char *[]){
3920                                 "nss_ppe_clk_src"
3921                         },
3922                         .num_parents = 1,
3923                         .flags = CLK_SET_RATE_PARENT,
3924                         .ops = &clk_branch2_ops,
3925                 },
3926         },
3927 };
3928
3929 static struct clk_branch gcc_port2_mac_clk = {
3930         .halt_reg = 0x68324,
3931         .clkr = {
3932                 .enable_reg = 0x68324,
3933                 .enable_mask = BIT(0),
3934                 .hw.init = &(struct clk_init_data){
3935                         .name = "gcc_port2_mac_clk",
3936                         .parent_names = (const char *[]){
3937                                 "nss_ppe_clk_src"
3938                         },
3939                         .num_parents = 1,
3940                         .flags = CLK_SET_RATE_PARENT,
3941                         .ops = &clk_branch2_ops,
3942                 },
3943         },
3944 };
3945
3946 static struct clk_branch gcc_port3_mac_clk = {
3947         .halt_reg = 0x68328,
3948         .clkr = {
3949                 .enable_reg = 0x68328,
3950                 .enable_mask = BIT(0),
3951                 .hw.init = &(struct clk_init_data){
3952                         .name = "gcc_port3_mac_clk",
3953                         .parent_names = (const char *[]){
3954                                 "nss_ppe_clk_src"
3955                         },
3956                         .num_parents = 1,
3957                         .flags = CLK_SET_RATE_PARENT,
3958                         .ops = &clk_branch2_ops,
3959                 },
3960         },
3961 };
3962
3963 static struct clk_branch gcc_port4_mac_clk = {
3964         .halt_reg = 0x6832c,
3965         .clkr = {
3966                 .enable_reg = 0x6832c,
3967                 .enable_mask = BIT(0),
3968                 .hw.init = &(struct clk_init_data){
3969                         .name = "gcc_port4_mac_clk",
3970                         .parent_names = (const char *[]){
3971                                 "nss_ppe_clk_src"
3972                         },
3973                         .num_parents = 1,
3974                         .flags = CLK_SET_RATE_PARENT,
3975                         .ops = &clk_branch2_ops,
3976                 },
3977         },
3978 };
3979
3980 static struct clk_branch gcc_port5_mac_clk = {
3981         .halt_reg = 0x68330,
3982         .clkr = {
3983                 .enable_reg = 0x68330,
3984                 .enable_mask = BIT(0),
3985                 .hw.init = &(struct clk_init_data){
3986                         .name = "gcc_port5_mac_clk",
3987                         .parent_names = (const char *[]){
3988                                 "nss_ppe_clk_src"
3989                         },
3990                         .num_parents = 1,
3991                         .flags = CLK_SET_RATE_PARENT,
3992                         .ops = &clk_branch2_ops,
3993                 },
3994         },
3995 };
3996
3997 static struct clk_branch gcc_port6_mac_clk = {
3998         .halt_reg = 0x68334,
3999         .clkr = {
4000                 .enable_reg = 0x68334,
4001                 .enable_mask = BIT(0),
4002                 .hw.init = &(struct clk_init_data){
4003                         .name = "gcc_port6_mac_clk",
4004                         .parent_names = (const char *[]){
4005                                 "nss_ppe_clk_src"
4006                         },
4007                         .num_parents = 1,
4008                         .flags = CLK_SET_RATE_PARENT,
4009                         .ops = &clk_branch2_ops,
4010                 },
4011         },
4012 };
4013
4014 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
4015         .halt_reg = 0x56010,
4016         .clkr = {
4017                 .enable_reg = 0x56010,
4018                 .enable_mask = BIT(0),
4019                 .hw.init = &(struct clk_init_data){
4020                         .name = "gcc_uniphy0_port1_rx_clk",
4021                         .parent_names = (const char *[]){
4022                                 "nss_port1_rx_div_clk_src"
4023                         },
4024                         .num_parents = 1,
4025                         .flags = CLK_SET_RATE_PARENT,
4026                         .ops = &clk_branch2_ops,
4027                 },
4028         },
4029 };
4030
4031 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
4032         .halt_reg = 0x56014,
4033         .clkr = {
4034                 .enable_reg = 0x56014,
4035                 .enable_mask = BIT(0),
4036                 .hw.init = &(struct clk_init_data){
4037                         .name = "gcc_uniphy0_port1_tx_clk",
4038                         .parent_names = (const char *[]){
4039                                 "nss_port1_tx_div_clk_src"
4040                         },
4041                         .num_parents = 1,
4042                         .flags = CLK_SET_RATE_PARENT,
4043                         .ops = &clk_branch2_ops,
4044                 },
4045         },
4046 };
4047
4048 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4049         .halt_reg = 0x56018,
4050         .clkr = {
4051                 .enable_reg = 0x56018,
4052                 .enable_mask = BIT(0),
4053                 .hw.init = &(struct clk_init_data){
4054                         .name = "gcc_uniphy0_port2_rx_clk",
4055                         .parent_names = (const char *[]){
4056                                 "nss_port2_rx_div_clk_src"
4057                         },
4058                         .num_parents = 1,
4059                         .flags = CLK_SET_RATE_PARENT,
4060                         .ops = &clk_branch2_ops,
4061                 },
4062         },
4063 };
4064
4065 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4066         .halt_reg = 0x5601c,
4067         .clkr = {
4068                 .enable_reg = 0x5601c,
4069                 .enable_mask = BIT(0),
4070                 .hw.init = &(struct clk_init_data){
4071                         .name = "gcc_uniphy0_port2_tx_clk",
4072                         .parent_names = (const char *[]){
4073                                 "nss_port2_tx_div_clk_src"
4074                         },
4075                         .num_parents = 1,
4076                         .flags = CLK_SET_RATE_PARENT,
4077                         .ops = &clk_branch2_ops,
4078                 },
4079         },
4080 };
4081
4082 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4083         .halt_reg = 0x56020,
4084         .clkr = {
4085                 .enable_reg = 0x56020,
4086                 .enable_mask = BIT(0),
4087                 .hw.init = &(struct clk_init_data){
4088                         .name = "gcc_uniphy0_port3_rx_clk",
4089                         .parent_names = (const char *[]){
4090                                 "nss_port3_rx_div_clk_src"
4091                         },
4092                         .num_parents = 1,
4093                         .flags = CLK_SET_RATE_PARENT,
4094                         .ops = &clk_branch2_ops,
4095                 },
4096         },
4097 };
4098
4099 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4100         .halt_reg = 0x56024,
4101         .clkr = {
4102                 .enable_reg = 0x56024,
4103                 .enable_mask = BIT(0),
4104                 .hw.init = &(struct clk_init_data){
4105                         .name = "gcc_uniphy0_port3_tx_clk",
4106                         .parent_names = (const char *[]){
4107                                 "nss_port3_tx_div_clk_src"
4108                         },
4109                         .num_parents = 1,
4110                         .flags = CLK_SET_RATE_PARENT,
4111                         .ops = &clk_branch2_ops,
4112                 },
4113         },
4114 };
4115
4116 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4117         .halt_reg = 0x56028,
4118         .clkr = {
4119                 .enable_reg = 0x56028,
4120                 .enable_mask = BIT(0),
4121                 .hw.init = &(struct clk_init_data){
4122                         .name = "gcc_uniphy0_port4_rx_clk",
4123                         .parent_names = (const char *[]){
4124                                 "nss_port4_rx_div_clk_src"
4125                         },
4126                         .num_parents = 1,
4127                         .flags = CLK_SET_RATE_PARENT,
4128                         .ops = &clk_branch2_ops,
4129                 },
4130         },
4131 };
4132
4133 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4134         .halt_reg = 0x5602c,
4135         .clkr = {
4136                 .enable_reg = 0x5602c,
4137                 .enable_mask = BIT(0),
4138                 .hw.init = &(struct clk_init_data){
4139                         .name = "gcc_uniphy0_port4_tx_clk",
4140                         .parent_names = (const char *[]){
4141                                 "nss_port4_tx_div_clk_src"
4142                         },
4143                         .num_parents = 1,
4144                         .flags = CLK_SET_RATE_PARENT,
4145                         .ops = &clk_branch2_ops,
4146                 },
4147         },
4148 };
4149
4150 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4151         .halt_reg = 0x56030,
4152         .clkr = {
4153                 .enable_reg = 0x56030,
4154                 .enable_mask = BIT(0),
4155                 .hw.init = &(struct clk_init_data){
4156                         .name = "gcc_uniphy0_port5_rx_clk",
4157                         .parent_names = (const char *[]){
4158                                 "nss_port5_rx_div_clk_src"
4159                         },
4160                         .num_parents = 1,
4161                         .flags = CLK_SET_RATE_PARENT,
4162                         .ops = &clk_branch2_ops,
4163                 },
4164         },
4165 };
4166
4167 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4168         .halt_reg = 0x56034,
4169         .clkr = {
4170                 .enable_reg = 0x56034,
4171                 .enable_mask = BIT(0),
4172                 .hw.init = &(struct clk_init_data){
4173                         .name = "gcc_uniphy0_port5_tx_clk",
4174                         .parent_names = (const char *[]){
4175                                 "nss_port5_tx_div_clk_src"
4176                         },
4177                         .num_parents = 1,
4178                         .flags = CLK_SET_RATE_PARENT,
4179                         .ops = &clk_branch2_ops,
4180                 },
4181         },
4182 };
4183
4184 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4185         .halt_reg = 0x56110,
4186         .clkr = {
4187                 .enable_reg = 0x56110,
4188                 .enable_mask = BIT(0),
4189                 .hw.init = &(struct clk_init_data){
4190                         .name = "gcc_uniphy1_port5_rx_clk",
4191                         .parent_names = (const char *[]){
4192                                 "nss_port5_rx_div_clk_src"
4193                         },
4194                         .num_parents = 1,
4195                         .flags = CLK_SET_RATE_PARENT,
4196                         .ops = &clk_branch2_ops,
4197                 },
4198         },
4199 };
4200
4201 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4202         .halt_reg = 0x56114,
4203         .clkr = {
4204                 .enable_reg = 0x56114,
4205                 .enable_mask = BIT(0),
4206                 .hw.init = &(struct clk_init_data){
4207                         .name = "gcc_uniphy1_port5_tx_clk",
4208                         .parent_names = (const char *[]){
4209                                 "nss_port5_tx_div_clk_src"
4210                         },
4211                         .num_parents = 1,
4212                         .flags = CLK_SET_RATE_PARENT,
4213                         .ops = &clk_branch2_ops,
4214                 },
4215         },
4216 };
4217
4218 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4219         .halt_reg = 0x56210,
4220         .clkr = {
4221                 .enable_reg = 0x56210,
4222                 .enable_mask = BIT(0),
4223                 .hw.init = &(struct clk_init_data){
4224                         .name = "gcc_uniphy2_port6_rx_clk",
4225                         .parent_names = (const char *[]){
4226                                 "nss_port6_rx_div_clk_src"
4227                         },
4228                         .num_parents = 1,
4229                         .flags = CLK_SET_RATE_PARENT,
4230                         .ops = &clk_branch2_ops,
4231                 },
4232         },
4233 };
4234
4235 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4236         .halt_reg = 0x56214,
4237         .clkr = {
4238                 .enable_reg = 0x56214,
4239                 .enable_mask = BIT(0),
4240                 .hw.init = &(struct clk_init_data){
4241                         .name = "gcc_uniphy2_port6_tx_clk",
4242                         .parent_names = (const char *[]){
4243                                 "nss_port6_tx_div_clk_src"
4244                         },
4245                         .num_parents = 1,
4246                         .flags = CLK_SET_RATE_PARENT,
4247                         .ops = &clk_branch2_ops,
4248                 },
4249         },
4250 };
4251
4252 static struct clk_branch gcc_crypto_ahb_clk = {
4253         .halt_reg = 0x16024,
4254         .halt_check = BRANCH_HALT_VOTED,
4255         .clkr = {
4256                 .enable_reg = 0x0b004,
4257                 .enable_mask = BIT(0),
4258                 .hw.init = &(struct clk_init_data){
4259                         .name = "gcc_crypto_ahb_clk",
4260                         .parent_names = (const char *[]){
4261                                 "pcnoc_clk_src"
4262                         },
4263                         .num_parents = 1,
4264                         .flags = CLK_SET_RATE_PARENT,
4265                         .ops = &clk_branch2_ops,
4266                 },
4267         },
4268 };
4269
4270 static struct clk_branch gcc_crypto_axi_clk = {
4271         .halt_reg = 0x16020,
4272         .halt_check = BRANCH_HALT_VOTED,
4273         .clkr = {
4274                 .enable_reg = 0x0b004,
4275                 .enable_mask = BIT(1),
4276                 .hw.init = &(struct clk_init_data){
4277                         .name = "gcc_crypto_axi_clk",
4278                         .parent_names = (const char *[]){
4279                                 "pcnoc_clk_src"
4280                         },
4281                         .num_parents = 1,
4282                         .flags = CLK_SET_RATE_PARENT,
4283                         .ops = &clk_branch2_ops,
4284                 },
4285         },
4286 };
4287
4288 static struct clk_branch gcc_crypto_clk = {
4289         .halt_reg = 0x1601c,
4290         .halt_check = BRANCH_HALT_VOTED,
4291         .clkr = {
4292                 .enable_reg = 0x0b004,
4293                 .enable_mask = BIT(2),
4294                 .hw.init = &(struct clk_init_data){
4295                         .name = "gcc_crypto_clk",
4296                         .parent_names = (const char *[]){
4297                                 "crypto_clk_src"
4298                         },
4299                         .num_parents = 1,
4300                         .flags = CLK_SET_RATE_PARENT,
4301                         .ops = &clk_branch2_ops,
4302                 },
4303         },
4304 };
4305
4306 static struct clk_branch gcc_gp1_clk = {
4307         .halt_reg = 0x08000,
4308         .clkr = {
4309                 .enable_reg = 0x08000,
4310                 .enable_mask = BIT(0),
4311                 .hw.init = &(struct clk_init_data){
4312                         .name = "gcc_gp1_clk",
4313                         .parent_names = (const char *[]){
4314                                 "gp1_clk_src"
4315                         },
4316                         .num_parents = 1,
4317                         .flags = CLK_SET_RATE_PARENT,
4318                         .ops = &clk_branch2_ops,
4319                 },
4320         },
4321 };
4322
4323 static struct clk_branch gcc_gp2_clk = {
4324         .halt_reg = 0x09000,
4325         .clkr = {
4326                 .enable_reg = 0x09000,
4327                 .enable_mask = BIT(0),
4328                 .hw.init = &(struct clk_init_data){
4329                         .name = "gcc_gp2_clk",
4330                         .parent_names = (const char *[]){
4331                                 "gp2_clk_src"
4332                         },
4333                         .num_parents = 1,
4334                         .flags = CLK_SET_RATE_PARENT,
4335                         .ops = &clk_branch2_ops,
4336                 },
4337         },
4338 };
4339
4340 static struct clk_branch gcc_gp3_clk = {
4341         .halt_reg = 0x0a000,
4342         .clkr = {
4343                 .enable_reg = 0x0a000,
4344                 .enable_mask = BIT(0),
4345                 .hw.init = &(struct clk_init_data){
4346                         .name = "gcc_gp3_clk",
4347                         .parent_names = (const char *[]){
4348                                 "gp3_clk_src"
4349                         },
4350                         .num_parents = 1,
4351                         .flags = CLK_SET_RATE_PARENT,
4352                         .ops = &clk_branch2_ops,
4353                 },
4354         },
4355 };
4356
4357 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
4358         F(19200000, P_XO, 1, 0, 0),
4359         F(100000000, P_GPLL0, 8, 0, 0),
4360         { }
4361 };
4362
4363 static struct clk_rcg2 pcie0_rchng_clk_src = {
4364         .cmd_rcgr = 0x75070,
4365         .freq_tbl = ftbl_pcie_rchng_clk_src,
4366         .hid_width = 5,
4367         .parent_map = gcc_xo_gpll0_map,
4368         .clkr.hw.init = &(struct clk_init_data){
4369                 .name = "pcie0_rchng_clk_src",
4370                 .parent_data = gcc_xo_gpll0,
4371                 .num_parents = 2,
4372                 .ops = &clk_rcg2_ops,
4373         },
4374 };
4375
4376 static struct clk_branch gcc_pcie0_rchng_clk = {
4377         .halt_reg = 0x75070,
4378         .halt_bit = 31,
4379         .clkr = {
4380                 .enable_reg = 0x75070,
4381                 .enable_mask = BIT(1),
4382                 .hw.init = &(struct clk_init_data){
4383                         .name = "gcc_pcie0_rchng_clk",
4384                         .parent_hws = (const struct clk_hw *[]){
4385                                 &pcie0_rchng_clk_src.clkr.hw,
4386                         },
4387                         .num_parents = 1,
4388                         .flags = CLK_SET_RATE_PARENT,
4389                         .ops = &clk_branch2_ops,
4390                 },
4391         },
4392 };
4393
4394 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
4395         .halt_reg = 0x75048,
4396         .halt_bit = 31,
4397         .clkr = {
4398                 .enable_reg = 0x75048,
4399                 .enable_mask = BIT(0),
4400                 .hw.init = &(struct clk_init_data){
4401                         .name = "gcc_pcie0_axi_s_bridge_clk",
4402                         .parent_hws = (const struct clk_hw *[]){
4403                                 &pcie0_axi_clk_src.clkr.hw,
4404                         },
4405                         .num_parents = 1,
4406                         .flags = CLK_SET_RATE_PARENT,
4407                         .ops = &clk_branch2_ops,
4408                 },
4409         },
4410 };
4411
4412 static struct gdsc usb0_gdsc = {
4413         .gdscr = 0x3e078,
4414         .pd = {
4415                 .name = "usb0_gdsc",
4416         },
4417         .pwrsts = PWRSTS_OFF_ON,
4418 };
4419
4420 static struct gdsc usb1_gdsc = {
4421         .gdscr = 0x3f078,
4422         .pd = {
4423                 .name = "usb1_gdsc",
4424         },
4425         .pwrsts = PWRSTS_OFF_ON,
4426 };
4427
4428 static const struct alpha_pll_config ubi32_pll_config = {
4429         .l = 0x4e,
4430         .config_ctl_val = 0x200d4aa8,
4431         .config_ctl_hi_val = 0x3c2,
4432         .main_output_mask = BIT(0),
4433         .aux_output_mask = BIT(1),
4434         .pre_div_val = 0x0,
4435         .pre_div_mask = BIT(12),
4436         .post_div_val = 0x0,
4437         .post_div_mask = GENMASK(9, 8),
4438 };
4439
4440 static const struct alpha_pll_config nss_crypto_pll_config = {
4441         .l = 0x3e,
4442         .alpha = 0x0,
4443         .alpha_hi = 0x80,
4444         .config_ctl_val = 0x4001055b,
4445         .main_output_mask = BIT(0),
4446         .pre_div_val = 0x0,
4447         .pre_div_mask = GENMASK(14, 12),
4448         .post_div_val = 0x1 << 8,
4449         .post_div_mask = GENMASK(11, 8),
4450         .vco_mask = GENMASK(21, 20),
4451         .vco_val = 0x0,
4452         .alpha_en_mask = BIT(24),
4453 };
4454
4455 static struct clk_hw *gcc_ipq8074_hws[] = {
4456         &gpll0_out_main_div2.hw,
4457         &gpll6_out_main_div2.hw,
4458         &pcnoc_clk_src.hw,
4459         &system_noc_clk_src.hw,
4460         &gcc_xo_div4_clk_src.hw,
4461         &nss_noc_clk_src.hw,
4462         &nss_ppe_cdiv_clk_src.hw,
4463 };
4464
4465 static struct clk_regmap *gcc_ipq8074_clks[] = {
4466         [GPLL0_MAIN] = &gpll0_main.clkr,
4467         [GPLL0] = &gpll0.clkr,
4468         [GPLL2_MAIN] = &gpll2_main.clkr,
4469         [GPLL2] = &gpll2.clkr,
4470         [GPLL4_MAIN] = &gpll4_main.clkr,
4471         [GPLL4] = &gpll4.clkr,
4472         [GPLL6_MAIN] = &gpll6_main.clkr,
4473         [GPLL6] = &gpll6.clkr,
4474         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4475         [UBI32_PLL] = &ubi32_pll.clkr,
4476         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4477         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4478         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4479         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4480         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4481         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4482         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4483         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4484         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4485         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4486         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4487         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4488         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4489         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4490         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4491         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4492         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4493         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4494         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4495         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4496         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4497         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4498         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4499         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4500         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4501         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4502         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4503         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4504         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4505         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4506         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4507         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4508         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4509         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4510         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4511         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4512         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4513         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4514         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4515         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4516         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4517         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4518         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4519         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4520         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4521         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4522         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4523         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4524         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4525         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4526         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4527         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4528         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4529         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4530         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4531         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4532         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4533         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4534         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4535         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4536         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4537         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4538         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4539         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4540         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4541         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4542         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4543         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4544         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4545         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4546         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4547         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4548         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4549         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4550         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4551         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4552         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4553         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4554         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4555         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4556         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4557         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4558         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4559         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4560         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4561         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4562         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4563         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4564         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4565         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4566         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4567         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4568         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4569         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4570         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4571         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4572         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4573         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4574         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4575         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4576         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4577         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4578         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4579         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4580         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4581         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4582         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4583         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4584         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4585         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4586         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4587         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4588         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4589         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4590         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4591         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4592         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4593         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4594         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4595         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4596         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4597         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4598         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4599         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4600         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4601         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4602         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4603         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4604         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4605         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4606         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4607         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4608         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4609         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4610         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4611         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4612         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4613         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4614         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4615         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4616         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4617         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4618         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4619         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4620         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4621         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4622         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4623         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4624         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4625         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4626         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4627         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4628         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4629         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4630         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4631         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4632         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4633         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4634         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4635         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4636         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4637         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4638         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4639         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4640         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4641         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4642         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4643         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4644         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4645         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4646         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4647         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4648         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4649         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4650         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4651         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4652         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4653         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4654         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4655         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4656         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4657         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4658         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4659         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4660         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4661         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4662         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4663         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4664         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4665         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4666         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4667         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4668         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4669         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4670         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4671         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4672         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4673         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4674         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4675         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4676         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4677         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4678         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4679         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4680         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4681         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4682         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4683         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4684         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4685         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4686         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4687         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4688         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4689         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4690         [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4691         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4692         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4693         [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4694 };
4695
4696 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4697         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4698         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4699         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4700         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4701         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4702         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4703         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4704         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4705         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4706         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4707         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4708         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4709         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4710         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4711         [GCC_SMMU_BCR] = { 0x12000, 0 },
4712         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4713         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4714         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4715         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4716         [GCC_PRNG_BCR] = { 0x13000, 0 },
4717         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4718         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4719         [GCC_WCSS_BCR] = { 0x18000, 0 },
4720         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4721         [GCC_NSS_BCR] = { 0x19000, 0 },
4722         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4723         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4724         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4725         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4726         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4727         [GCC_TCSR_BCR] = { 0x28000, 0 },
4728         [GCC_QDSS_BCR] = { 0x29000, 0 },
4729         [GCC_DCD_BCR] = { 0x2a000, 0 },
4730         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4731         [GCC_MPM_BCR] = { 0x2c000, 0 },
4732         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4733         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4734         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4735         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4736         [GCC_TLMM_BCR] = { 0x34000, 0 },
4737         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4738         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4739         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4740         [GCC_USB0_BCR] = { 0x3e070, 0 },
4741         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4742         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4743         [GCC_USB1_BCR] = { 0x3f070, 0 },
4744         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4745         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4746         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4747         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4748         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4749         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4750         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4751         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4752         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4753         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4754         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4755         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4756         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4757         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4758         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4759         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4760         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4761         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4762         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4763         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4764         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4765         [GCC_QPIC_BCR] = { 0x57018, 0 },
4766         [GCC_MDIO_BCR] = { 0x58000, 0 },
4767         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4768         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4769         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4770         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4771         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4772         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4773         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4774         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4775         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4776         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4777         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4778         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4779         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4780         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4781         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4782         [GCC_DCC_BCR] = { 0x77000, 0 },
4783         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4784         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4785         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4786         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4787         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4788         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4789         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4790         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4791         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4792         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4793         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4794         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4795         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4796         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4797         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4798         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4799         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4800         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4801         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4802         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4803         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4804         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4805         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4806         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4807         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4808         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4809         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4810         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4811         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4812         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4813         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4814         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4815         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4816         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4817         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4818         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4819         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4820         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4821         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4822         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4823         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4824         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4825         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4826         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4827         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4828         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4829 };
4830
4831 static struct gdsc *gcc_ipq8074_gdscs[] = {
4832         [USB0_GDSC] = &usb0_gdsc,
4833         [USB1_GDSC] = &usb1_gdsc,
4834 };
4835
4836 static const struct of_device_id gcc_ipq8074_match_table[] = {
4837         { .compatible = "qcom,gcc-ipq8074" },
4838         { }
4839 };
4840 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4841
4842 static const struct regmap_config gcc_ipq8074_regmap_config = {
4843         .reg_bits       = 32,
4844         .reg_stride     = 4,
4845         .val_bits       = 32,
4846         .max_register   = 0x7fffc,
4847         .fast_io        = true,
4848 };
4849
4850 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4851         .config = &gcc_ipq8074_regmap_config,
4852         .clks = gcc_ipq8074_clks,
4853         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4854         .resets = gcc_ipq8074_resets,
4855         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4856         .clk_hws = gcc_ipq8074_hws,
4857         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4858         .gdscs = gcc_ipq8074_gdscs,
4859         .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
4860 };
4861
4862 static int gcc_ipq8074_probe(struct platform_device *pdev)
4863 {
4864         struct regmap *regmap;
4865
4866         regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4867         if (IS_ERR(regmap))
4868                 return PTR_ERR(regmap);
4869
4870         /* SW Workaround for UBI32 Huayra PLL */
4871         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4872
4873         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4874         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4875                                 &nss_crypto_pll_config);
4876
4877         return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4878 }
4879
4880 static struct platform_driver gcc_ipq8074_driver = {
4881         .probe = gcc_ipq8074_probe,
4882         .driver = {
4883                 .name   = "qcom,gcc-ipq8074",
4884                 .of_match_table = gcc_ipq8074_match_table,
4885         },
4886 };
4887
4888 static int __init gcc_ipq8074_init(void)
4889 {
4890         return platform_driver_register(&gcc_ipq8074_driver);
4891 }
4892 core_initcall(gcc_ipq8074_init);
4893
4894 static void __exit gcc_ipq8074_exit(void)
4895 {
4896         platform_driver_unregister(&gcc_ipq8074_driver);
4897 }
4898 module_exit(gcc_ipq8074_exit);
4899
4900 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4901 MODULE_LICENSE("GPL v2");
4902 MODULE_ALIAS("platform:gcc-ipq8074");