drivers/clk/qcom/gcc-ipq6018.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <linux/reset-controller.h>
  16 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  17 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "clk-alpha-pll.h"
  25 #include "clk-regmap-divider.h"
  26 #include "clk-regmap-mux.h"
  27 #include "reset.h"
  28
  29 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  30
  31 enum {
  32         P_XO,
  33         P_BIAS_PLL,
  34         P_UNIPHY0_RX,
  35         P_UNIPHY0_TX,
  36         P_UNIPHY1_RX,
  37         P_BIAS_PLL_NSS_NOC,
  38         P_UNIPHY1_TX,
  39         P_PCIE20_PHY0_PIPE,
  40         P_USB3PHY_0_PIPE,
  41         P_GPLL0,
  42         P_GPLL0_DIV2,
  43         P_GPLL2,
  44         P_GPLL4,
  45         P_GPLL6,
  46         P_SLEEP_CLK,
  47         P_UBI32_PLL,
  48         P_NSS_CRYPTO_PLL,
  49         P_PI_SLEEP,
  50 };
  51
  52 static struct clk_alpha_pll gpll0_main = {
  53         .offset = 0x21000,
  54         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  55         .clkr = {
  56                 .enable_reg = 0x0b000,
  57                 .enable_mask = BIT(0),
  58                 .hw.init = &(struct clk_init_data){
  59                         .name = "gpll0_main",
  60                         .parent_data = &(const struct clk_parent_data){
  61                                 .fw_name = "xo",
  62                         },
  63                         .num_parents = 1,
  64                         .ops = &clk_alpha_pll_ops,
  65                 },
  66         },
  67 };
  68
  69 static struct clk_fixed_factor gpll0_out_main_div2 = {
  70         .mult = 1,
  71         .div = 2,
  72         .hw.init = &(struct clk_init_data){
  73                 .name = "gpll0_out_main_div2",
  74                 .parent_hws = (const struct clk_hw *[]){
  75                                 &gpll0_main.clkr.hw },
  76                 .num_parents = 1,
  77                 .ops = &clk_fixed_factor_ops,
  78         },
  79 };
  80
  81 static struct clk_alpha_pll_postdiv gpll0 = {
  82         .offset = 0x21000,
  83         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  84         .width = 4,
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll0",
  87                 .parent_hws = (const struct clk_hw *[]){
  88                                 &gpll0_main.clkr.hw },
  89                 .num_parents = 1,
  90                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  91         },
  92 };
  93
  94 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
  95         { .fw_name = "xo" },
  96         { .hw = &gpll0.clkr.hw},
  97         { .hw = &gpll0_out_main_div2.hw},
  98 };
  99
 100 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 101         { P_XO, 0 },
 102         { P_GPLL0, 1 },
 103         { P_GPLL0_DIV2, 4 },
 104 };
 105
 106 static struct clk_alpha_pll ubi32_pll_main = {
 107         .offset = 0x25000,
 108         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 109         .flags = SUPPORTS_DYNAMIC_UPDATE,
 110         .clkr = {
 111                 .enable_reg = 0x0b000,
 112                 .enable_mask = BIT(6),
 113                 .hw.init = &(struct clk_init_data){
 114                         .name = "ubi32_pll_main",
 115                         .parent_data = &(const struct clk_parent_data){
 116                                 .fw_name = "xo",
 117                         },
 118                         .num_parents = 1,
 119                         .ops = &clk_alpha_pll_huayra_ops,
 120                 },
 121         },
 122 };
 123
 124 static struct clk_alpha_pll_postdiv ubi32_pll = {
 125         .offset = 0x25000,
 126         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 127         .width = 2,
 128         .clkr.hw.init = &(struct clk_init_data){
 129                 .name = "ubi32_pll",
 130                 .parent_hws = (const struct clk_hw *[]){
 131                                 &ubi32_pll_main.clkr.hw },
 132                 .num_parents = 1,
 133                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 134                 .flags = CLK_SET_RATE_PARENT,
 135         },
 136 };
 137
 138 static struct clk_alpha_pll gpll6_main = {
 139         .offset = 0x37000,
 140         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 141         .clkr = {
 142                 .enable_reg = 0x0b000,
 143                 .enable_mask = BIT(7),
 144                 .hw.init = &(struct clk_init_data){
 145                         .name = "gpll6_main",
 146                         .parent_data = &(const struct clk_parent_data){
 147                                 .fw_name = "xo",
 148                         },
 149                         .num_parents = 1,
 150                         .ops = &clk_alpha_pll_ops,
 151                 },
 152         },
 153 };
 154
 155 static struct clk_alpha_pll_postdiv gpll6 = {
 156         .offset = 0x37000,
 157         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 158         .width = 2,
 159         .clkr.hw.init = &(struct clk_init_data){
 160                 .name = "gpll6",
 161                 .parent_hws = (const struct clk_hw *[]){
 162                                 &gpll6_main.clkr.hw },
 163                 .num_parents = 1,
 164                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 165         },
 166 };
 167
 168 static struct clk_alpha_pll gpll4_main = {
 169         .offset = 0x24000,
 170         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 171         .clkr = {
 172                 .enable_reg = 0x0b000,
 173                 .enable_mask = BIT(5),
 174                 .hw.init = &(struct clk_init_data){
 175                         .name = "gpll4_main",
 176                         .parent_data = &(const struct clk_parent_data){
 177                                 .fw_name = "xo",
 178                         },
 179                         .num_parents = 1,
 180                         .ops = &clk_alpha_pll_ops,
 181                 },
 182         },
 183 };
 184
 185 static struct clk_alpha_pll_postdiv gpll4 = {
 186         .offset = 0x24000,
 187         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 188         .width = 4,
 189         .clkr.hw.init = &(struct clk_init_data){
 190                 .name = "gpll4",
 191                 .parent_hws = (const struct clk_hw *[]){
 192                                 &gpll4_main.clkr.hw },
 193                 .num_parents = 1,
 194                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 195         },
 196 };
 197
 198 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 199         F(24000000, P_XO, 1, 0, 0),
 200         F(50000000, P_GPLL0, 16, 0, 0),
 201         F(100000000, P_GPLL0, 8, 0, 0),
 202         { }
 203 };
 204
 205 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 206         .cmd_rcgr = 0x27000,
 207         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 208         .hid_width = 5,
 209         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 210         .clkr.hw.init = &(struct clk_init_data){
 211                 .name = "pcnoc_bfdcd_clk_src",
 212                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 213                 .num_parents = 3,
 214                 .ops = &clk_rcg2_ops,
 215         },
 216 };
 217
 218 static struct clk_alpha_pll gpll2_main = {
 219         .offset = 0x4a000,
 220         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 221         .clkr = {
 222                 .enable_reg = 0x0b000,
 223                 .enable_mask = BIT(2),
 224                 .hw.init = &(struct clk_init_data){
 225                         .name = "gpll2_main",
 226                         .parent_data = &(const struct clk_parent_data){
 227                                 .fw_name = "xo",
 228                         },
 229                         .num_parents = 1,
 230                         .ops = &clk_alpha_pll_ops,
 231                 },
 232         },
 233 };
 234
 235 static struct clk_alpha_pll_postdiv gpll2 = {
 236         .offset = 0x4a000,
 237         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 238         .width = 4,
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "gpll2",
 241                 .parent_hws = (const struct clk_hw *[]){
 242                                 &gpll2_main.clkr.hw },
 243                 .num_parents = 1,
 244                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 245         },
 246 };
 247
 248 static struct clk_alpha_pll nss_crypto_pll_main = {
 249         .offset = 0x22000,
 250         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 251         .clkr = {
 252                 .enable_reg = 0x0b000,
 253                 .enable_mask = BIT(4),
 254                 .hw.init = &(struct clk_init_data){
 255                         .name = "nss_crypto_pll_main",
 256                         .parent_data = &(const struct clk_parent_data){
 257                                 .fw_name = "xo",
 258                         },
 259                         .num_parents = 1,
 260                         .ops = &clk_alpha_pll_ops,
 261                 },
 262         },
 263 };
 264
 265 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 266         .offset = 0x22000,
 267         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 268         .width = 4,
 269         .clkr.hw.init = &(struct clk_init_data){
 270                 .name = "nss_crypto_pll",
 271                 .parent_hws = (const struct clk_hw *[]){
 272                                 &nss_crypto_pll_main.clkr.hw },
 273                 .num_parents = 1,
 274                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 275         },
 276 };
 277
 278 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
 279         F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
 280         F(320000000, P_GPLL0, 2.5, 0, 0),
 281         F(600000000, P_GPLL4, 2, 0, 0),
 282         { }
 283 };
 284
 285 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
 286         { .fw_name = "xo" },
 287         { .hw = &gpll4.clkr.hw },
 288         { .hw = &gpll0.clkr.hw },
 289         { .hw = &gpll6.clkr.hw },
 290         { .hw = &gpll0_out_main_div2.hw },
 291 };
 292
 293 static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
 294         { P_XO, 0 },
 295         { P_GPLL4, 1 },
 296         { P_GPLL0, 2 },
 297         { P_GPLL6, 3 },
 298         { P_GPLL0_DIV2, 4 },
 299 };
 300
 301 static struct clk_rcg2 qdss_tsctr_clk_src = {
 302         .cmd_rcgr = 0x29064,
 303         .freq_tbl = ftbl_qdss_tsctr_clk_src,
 304         .hid_width = 5,
 305         .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 306         .clkr.hw.init = &(struct clk_init_data){
 307                 .name = "qdss_tsctr_clk_src",
 308                 .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 309                 .num_parents = 5,
 310                 .ops = &clk_rcg2_ops,
 311         },
 312 };
 313
 314 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
 315         .mult = 1,
 316         .div = 4,
 317         .hw.init = &(struct clk_init_data){
 318                 .name = "qdss_dap_sync_clk_src",
 319                 .parent_hws = (const struct clk_hw *[]){
 320                                 &qdss_tsctr_clk_src.clkr.hw },
 321                 .num_parents = 1,
 322                 .ops = &clk_fixed_factor_ops,
 323         },
 324 };
 325
 326 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 327         F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 328         F(240000000, P_GPLL4, 5, 0, 0),
 329         { }
 330 };
 331
 332 static struct clk_rcg2 qdss_at_clk_src = {
 333         .cmd_rcgr = 0x2900c,
 334         .freq_tbl = ftbl_qdss_at_clk_src,
 335         .hid_width = 5,
 336         .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 337         .clkr.hw.init = &(struct clk_init_data){
 338                 .name = "qdss_at_clk_src",
 339                 .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 340                 .num_parents = 5,
 341                 .ops = &clk_rcg2_ops,
 342         },
 343 };
 344
 345 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
 346         .mult = 1,
 347         .div = 2,
 348         .hw.init = &(struct clk_init_data){
 349                 .name = "qdss_tsctr_div2_clk_src",
 350                 .parent_hws = (const struct clk_hw *[]){
 351                                 &qdss_tsctr_clk_src.clkr.hw },
 352                 .num_parents = 1,
 353                 .flags = CLK_SET_RATE_PARENT,
 354                 .ops = &clk_fixed_factor_ops,
 355         },
 356 };
 357
 358 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 359         F(24000000, P_XO, 1, 0, 0),
 360         F(300000000, P_BIAS_PLL, 1, 0, 0),
 361         { }
 362 };
 363
 364 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 365         { .fw_name = "xo" },
 366         { .fw_name = "bias_pll_cc_clk" },
 367         { .hw = &gpll0.clkr.hw },
 368         { .hw = &gpll4.clkr.hw },
 369         { .hw = &nss_crypto_pll.clkr.hw },
 370         { .hw = &ubi32_pll.clkr.hw },
 371 };
 372
 373 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 374         { P_XO, 0 },
 375         { P_BIAS_PLL, 1 },
 376         { P_GPLL0, 2 },
 377         { P_GPLL4, 3 },
 378         { P_NSS_CRYPTO_PLL, 4 },
 379         { P_UBI32_PLL, 5 },
 380 };
 381
 382 static struct clk_rcg2 nss_ppe_clk_src = {
 383         .cmd_rcgr = 0x68080,
 384         .freq_tbl = ftbl_nss_ppe_clk_src,
 385         .hid_width = 5,
 386         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "nss_ppe_clk_src",
 389                 .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
 390                 .num_parents = 6,
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static struct clk_branch gcc_xo_clk_src = {
 396         .halt_reg = 0x30018,
 397         .clkr = {
 398                 .enable_reg = 0x30018,
 399                 .enable_mask = BIT(1),
 400                 .hw.init = &(struct clk_init_data){
 401                         .name = "gcc_xo_clk_src",
 402                         .parent_data = &(const struct clk_parent_data){
 403                                 .fw_name = "xo",
 404                         },
 405                         .num_parents = 1,
 406                         .flags = CLK_SET_RATE_PARENT,
 407                         .ops = &clk_branch2_ops,
 408                 },
 409         },
 410 };
 411
 412 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
 413         F(24000000, P_XO, 1, 0, 0),
 414         F(200000000, P_GPLL0, 4, 0, 0),
 415         { }
 416 };
 417
 418 static const struct clk_parent_data gcc_xo_gpll0[] = {
 419         { .fw_name = "xo" },
 420         { .hw = &gpll0.clkr.hw },
 421 };
 422
 423 static const struct parent_map gcc_xo_gpll0_map[] = {
 424         { P_XO, 0 },
 425         { P_GPLL0, 1 },
 426 };
 427
 428 static struct clk_rcg2 nss_ce_clk_src = {
 429         .cmd_rcgr = 0x68098,
 430         .freq_tbl = ftbl_nss_ce_clk_src,
 431         .hid_width = 5,
 432         .parent_map = gcc_xo_gpll0_map,
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "nss_ce_clk_src",
 435                 .parent_data = gcc_xo_gpll0,
 436                 .num_parents = 2,
 437                 .ops = &clk_rcg2_ops,
 438         },
 439 };
 440
 441 static struct clk_branch gcc_sleep_clk_src = {
 442         .halt_reg = 0x30000,
 443         .clkr = {
 444                 .enable_reg = 0x30000,
 445                 .enable_mask = BIT(1),
 446                 .hw.init = &(struct clk_init_data){
 447                         .name = "gcc_sleep_clk_src",
 448                         .parent_data = &(const struct clk_parent_data){
 449                                 .fw_name = "sleep_clk",
 450                         },
 451                         .num_parents = 1,
 452                         .ops = &clk_branch2_ops,
 453                 },
 454         },
 455 };
 456
 457 static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
 458         F(24000000, P_XO, 1, 0, 0),
 459         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 460         F(100000000, P_GPLL0, 8, 0, 0),
 461         F(133333333, P_GPLL0, 6, 0, 0),
 462         F(160000000, P_GPLL0, 5, 0, 0),
 463         F(200000000, P_GPLL0, 4, 0, 0),
 464         F(266666667, P_GPLL0, 3, 0, 0),
 465         { }
 466 };
 467
 468 static const struct clk_parent_data
 469                         gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 470         { .fw_name = "xo" },
 471         { .hw = &gpll0.clkr.hw },
 472         { .hw = &gpll6.clkr.hw },
 473         { .hw = &gpll0_out_main_div2.hw },
 474 };
 475
 476 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 477         { P_XO, 0 },
 478         { P_GPLL0, 1 },
 479         { P_GPLL6, 2 },
 480         { P_GPLL0_DIV2, 3 },
 481 };
 482
 483 static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
 484         .cmd_rcgr = 0x76054,
 485         .freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
 486         .hid_width = 5,
 487         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
 488         .clkr.hw.init = &(struct clk_init_data){
 489                 .name = "snoc_nssnoc_bfdcd_clk_src",
 490                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
 491                 .num_parents = 4,
 492                 .ops = &clk_rcg2_ops,
 493         },
 494 };
 495
 496 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 497         F(24000000, P_XO, 1, 0, 0),
 498         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 499         F(50000000, P_GPLL0, 16, 0, 0),
 500         F(100000000, P_GPLL0, 8, 0, 0),
 501         { }
 502 };
 503
 504 static struct clk_rcg2 apss_ahb_clk_src = {
 505         .cmd_rcgr = 0x46000,
 506         .freq_tbl = ftbl_apss_ahb_clk_src,
 507         .hid_width = 5,
 508         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "apss_ahb_clk_src",
 511                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 512                 .num_parents = 3,
 513                 .ops = &clk_rcg2_ops,
 514         },
 515 };
 516
 517 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
 518         F(24000000, P_XO, 1, 0, 0),
 519         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
 520         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 521         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
 522         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
 523         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 524         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
 525         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
 526         { }
 527 };
 528
 529 static const struct clk_parent_data
 530 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 531         { .fw_name = "xo" },
 532         { .fw_name = "uniphy0_gcc_rx_clk" },
 533         { .fw_name = "uniphy0_gcc_tx_clk" },
 534         { .fw_name = "uniphy1_gcc_rx_clk" },
 535         { .fw_name = "uniphy1_gcc_tx_clk" },
 536         { .hw = &ubi32_pll.clkr.hw },
 537         { .fw_name = "bias_pll_cc_clk" },
 538 };
 539
 540 static const struct parent_map
 541 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 542         { P_XO, 0 },
 543         { P_UNIPHY0_RX, 1 },
 544         { P_UNIPHY0_TX, 2 },
 545         { P_UNIPHY1_RX, 3 },
 546         { P_UNIPHY1_TX, 4 },
 547         { P_UBI32_PLL, 5 },
 548         { P_BIAS_PLL, 6 },
 549 };
 550
 551 static struct clk_rcg2 nss_port5_rx_clk_src = {
 552         .cmd_rcgr = 0x68060,
 553         .freq_tbl = ftbl_nss_port5_rx_clk_src,
 554         .hid_width = 5,
 555         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
 556         .clkr.hw.init = &(struct clk_init_data){
 557                 .name = "nss_port5_rx_clk_src",
 558                 .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
 559                 .num_parents = 7,
 560                 .ops = &clk_rcg2_ops,
 561         },
 562 };
 563
 564 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
 565         F(24000000, P_XO, 1, 0, 0),
 566         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
 567         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 568         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
 569         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
 570         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 571         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
 572         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
 573         { }
 574 };
 575
 576 static const struct clk_parent_data
 577 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 578         { .fw_name = "xo" },
 579         { .fw_name = "uniphy0_gcc_tx_clk" },
 580         { .fw_name = "uniphy0_gcc_rx_clk" },
 581         { .fw_name = "uniphy1_gcc_tx_clk" },
 582         { .fw_name = "uniphy1_gcc_rx_clk" },
 583         { .hw = &ubi32_pll.clkr.hw },
 584         { .fw_name = "bias_pll_cc_clk" },
 585 };
 586
 587 static const struct parent_map
 588 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 589         { P_XO, 0 },
 590         { P_UNIPHY0_TX, 1 },
 591         { P_UNIPHY0_RX, 2 },
 592         { P_UNIPHY1_TX, 3 },
 593         { P_UNIPHY1_RX, 4 },
 594         { P_UBI32_PLL, 5 },
 595         { P_BIAS_PLL, 6 },
 596 };
 597
 598 static struct clk_rcg2 nss_port5_tx_clk_src = {
 599         .cmd_rcgr = 0x68068,
 600         .freq_tbl = ftbl_nss_port5_tx_clk_src,
 601         .hid_width = 5,
 602         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
 603         .clkr.hw.init = &(struct clk_init_data){
 604                 .name = "nss_port5_tx_clk_src",
 605                 .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
 606                 .num_parents = 7,
 607                 .ops = &clk_rcg2_ops,
 608         },
 609 };
 610
 611 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 612         F(24000000, P_XO, 1, 0, 0),
 613         F(200000000, P_GPLL0, 4, 0, 0),
 614         F(240000000, P_GPLL4, 5, 0, 0),
 615         { }
 616 };
 617
 618 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
 619         F(24000000, P_XO, 1, 0, 0),
 620         F(100000000, P_GPLL0, 8, 0, 0),
 621         { }
 622 };
 623
 624 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 625         { .fw_name = "xo" },
 626         { .hw = &gpll0.clkr.hw },
 627         { .hw = &gpll4.clkr.hw },
 628 };
 629
 630 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 631         { P_XO, 0 },
 632         { P_GPLL0, 1 },
 633         { P_GPLL4, 2 },
 634 };
 635
 636 static struct clk_rcg2 pcie0_axi_clk_src = {
 637         .cmd_rcgr = 0x75054,
 638         .freq_tbl = ftbl_pcie_axi_clk_src,
 639         .hid_width = 5,
 640         .parent_map = gcc_xo_gpll0_gpll4_map,
 641         .clkr.hw.init = &(struct clk_init_data){
 642                 .name = "pcie0_axi_clk_src",
 643                 .parent_data = gcc_xo_gpll0_gpll4,
 644                 .num_parents = 3,
 645                 .ops = &clk_rcg2_ops,
 646         },
 647 };
 648
 649 static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
 650         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 651         F(100000000, P_GPLL0, 8, 0, 0),
 652         F(133330000, P_GPLL0, 6, 0, 0),
 653         F(200000000, P_GPLL0, 4, 0, 0),
 654         { }
 655 };
 656
 657 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 658         { .fw_name = "xo" },
 659         { .hw = &gpll0_out_main_div2.hw },
 660         { .hw = &gpll0.clkr.hw },
 661 };
 662
 663 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 664         { P_XO, 0 },
 665         { P_GPLL0_DIV2, 2 },
 666         { P_GPLL0, 1 },
 667 };
 668
 669 static struct clk_rcg2 usb0_master_clk_src = {
 670         .cmd_rcgr = 0x3e00c,
 671         .freq_tbl = ftbl_usb0_master_clk_src,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 675         .clkr.hw.init = &(struct clk_init_data){
 676                 .name = "usb0_master_clk_src",
 677                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 678                 .num_parents = 3,
 679                 .ops = &clk_rcg2_ops,
 680         },
 681 };
 682
 683 static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
 684         .reg = 0x46018,
 685         .shift = 4,
 686         .width = 4,
 687         .clkr = {
 688                 .hw.init = &(struct clk_init_data){
 689                         .name = "apss_ahb_postdiv_clk_src",
 690                         .parent_hws = (const struct clk_hw *[]){
 691                                         &apss_ahb_clk_src.clkr.hw },
 692                         .num_parents = 1,
 693                         .ops = &clk_regmap_div_ops,
 694                 },
 695         },
 696 };
 697
 698 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 699         .mult = 1,
 700         .div = 4,
 701         .hw.init = &(struct clk_init_data){
 702                 .name = "gcc_xo_div4_clk_src",
 703                 .parent_hws = (const struct clk_hw *[]){
 704                                 &gcc_xo_clk_src.clkr.hw },
 705                 .num_parents = 1,
 706                 .ops = &clk_fixed_factor_ops,
 707                 .flags = CLK_SET_RATE_PARENT,
 708         },
 709 };
 710
 711 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
 712         F(24000000, P_XO, 1, 0, 0),
 713         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 714         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 715         { }
 716 };
 717
 718 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 719         { .fw_name = "xo" },
 720         { .fw_name = "uniphy0_gcc_rx_clk" },
 721         { .fw_name = "uniphy0_gcc_tx_clk" },
 722         { .hw = &ubi32_pll.clkr.hw },
 723         { .fw_name = "bias_pll_cc_clk" },
 724 };
 725
 726 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 727         { P_XO, 0 },
 728         { P_UNIPHY0_RX, 1 },
 729         { P_UNIPHY0_TX, 2 },
 730         { P_UBI32_PLL, 5 },
 731         { P_BIAS_PLL, 6 },
 732 };
 733
 734 static struct clk_rcg2 nss_port1_rx_clk_src = {
 735         .cmd_rcgr = 0x68020,
 736         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 737         .hid_width = 5,
 738         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 739         .clkr.hw.init = &(struct clk_init_data){
 740                 .name = "nss_port1_rx_clk_src",
 741                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 742                 .num_parents = 5,
 743                 .ops = &clk_rcg2_ops,
 744         },
 745 };
 746
 747 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
 748         F(24000000, P_XO, 1, 0, 0),
 749         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 750         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 751         { }
 752 };
 753
 754 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 755         { .fw_name = "xo" },
 756         { .fw_name = "uniphy0_gcc_tx_clk" },
 757         { .fw_name = "uniphy0_gcc_rx_clk" },
 758         { .hw = &ubi32_pll.clkr.hw },
 759         { .fw_name = "bias_pll_cc_clk" },
 760 };
 761
 762 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 763         { P_XO, 0 },
 764         { P_UNIPHY0_TX, 1 },
 765         { P_UNIPHY0_RX, 2 },
 766         { P_UBI32_PLL, 5 },
 767         { P_BIAS_PLL, 6 },
 768 };
 769
 770 static struct clk_rcg2 nss_port1_tx_clk_src = {
 771         .cmd_rcgr = 0x68028,
 772         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 773         .hid_width = 5,
 774         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 775         .clkr.hw.init = &(struct clk_init_data){
 776                 .name = "nss_port1_tx_clk_src",
 777                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 778                 .num_parents = 5,
 779                 .ops = &clk_rcg2_ops,
 780         },
 781 };
 782
 783 static struct clk_rcg2 nss_port2_rx_clk_src = {
 784         .cmd_rcgr = 0x68030,
 785         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 786         .hid_width = 5,
 787         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 788         .clkr.hw.init = &(struct clk_init_data){
 789                 .name = "nss_port2_rx_clk_src",
 790                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 791                 .num_parents = 5,
 792                 .ops = &clk_rcg2_ops,
 793         },
 794 };
 795
 796 static struct clk_rcg2 nss_port2_tx_clk_src = {
 797         .cmd_rcgr = 0x68038,
 798         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 799         .hid_width = 5,
 800         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "nss_port2_tx_clk_src",
 803                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 804                 .num_parents = 5,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 nss_port3_rx_clk_src = {
 810         .cmd_rcgr = 0x68040,
 811         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 812         .hid_width = 5,
 813         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "nss_port3_rx_clk_src",
 816                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 817                 .num_parents = 5,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static struct clk_rcg2 nss_port3_tx_clk_src = {
 823         .cmd_rcgr = 0x68048,
 824         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 825         .hid_width = 5,
 826         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 827         .clkr.hw.init = &(struct clk_init_data){
 828                 .name = "nss_port3_tx_clk_src",
 829                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 830                 .num_parents = 5,
 831                 .ops = &clk_rcg2_ops,
 832         },
 833 };
 834
 835 static struct clk_rcg2 nss_port4_rx_clk_src = {
 836         .cmd_rcgr = 0x68050,
 837         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 838         .hid_width = 5,
 839         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 840         .clkr.hw.init = &(struct clk_init_data){
 841                 .name = "nss_port4_rx_clk_src",
 842                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 843                 .num_parents = 5,
 844                 .ops = &clk_rcg2_ops,
 845         },
 846 };
 847
 848 static struct clk_rcg2 nss_port4_tx_clk_src = {
 849         .cmd_rcgr = 0x68058,
 850         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 851         .hid_width = 5,
 852         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "nss_port4_tx_clk_src",
 855                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 856                 .num_parents = 5,
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 862         .reg = 0x68440,
 863         .shift = 0,
 864         .width = 4,
 865         .clkr = {
 866                 .hw.init = &(struct clk_init_data){
 867                         .name = "nss_port5_rx_div_clk_src",
 868                         .parent_hws = (const struct clk_hw *[]){
 869                                         &nss_port5_rx_clk_src.clkr.hw },
 870                         .num_parents = 1,
 871                         .ops = &clk_regmap_div_ops,
 872                         .flags = CLK_SET_RATE_PARENT,
 873                 },
 874         },
 875 };
 876
 877 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
 878         .reg = 0x68444,
 879         .shift = 0,
 880         .width = 4,
 881         .clkr = {
 882                 .hw.init = &(struct clk_init_data){
 883                         .name = "nss_port5_tx_div_clk_src",
 884                         .parent_hws = (const struct clk_hw *[]){
 885                                         &nss_port5_tx_clk_src.clkr.hw },
 886                         .num_parents = 1,
 887                         .ops = &clk_regmap_div_ops,
 888                         .flags = CLK_SET_RATE_PARENT,
 889                 },
 890         },
 891 };
 892
 893 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 894         F(24000000, P_XO, 1, 0, 0),
 895         F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 896         F(200000000, P_GPLL0, 4, 0, 0),
 897         F(308570000, P_GPLL6, 3.5, 0, 0),
 898         F(400000000, P_GPLL0, 2, 0, 0),
 899         F(533000000, P_GPLL0, 1.5, 0, 0),
 900         { }
 901 };
 902
 903 static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
 904         { .fw_name = "xo" },
 905         { .hw = &gpll0.clkr.hw },
 906         { .hw = &gpll6.clkr.hw },
 907         { .hw = &ubi32_pll.clkr.hw },
 908         { .hw = &gpll0_out_main_div2.hw },
 909 };
 910
 911 static const struct parent_map
 912 gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
 913         { P_XO, 0 },
 914         { P_GPLL0, 1 },
 915         { P_GPLL6, 2 },
 916         { P_UBI32_PLL, 3 },
 917         { P_GPLL0_DIV2, 6 },
 918 };
 919
 920 static struct clk_rcg2 apss_axi_clk_src = {
 921         .cmd_rcgr = 0x38048,
 922         .freq_tbl = ftbl_apss_axi_clk_src,
 923         .hid_width = 5,
 924         .parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
 925         .clkr.hw.init = &(struct clk_init_data){
 926                 .name = "apss_axi_clk_src",
 927                 .parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
 928                 .num_parents = 5,
 929                 .ops = &clk_rcg2_ops,
 930         },
 931 };
 932
 933 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
 934         F(24000000, P_XO, 1, 0, 0),
 935         F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
 936         { }
 937 };
 938
 939 static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
 940         { .fw_name = "xo" },
 941         { .hw = &nss_crypto_pll.clkr.hw },
 942         { .hw = &gpll0.clkr.hw },
 943 };
 944
 945 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 946         { P_XO, 0 },
 947         { P_NSS_CRYPTO_PLL, 1 },
 948         { P_GPLL0, 2 },
 949 };
 950
 951 static struct clk_rcg2 nss_crypto_clk_src = {
 952         .cmd_rcgr = 0x68144,
 953         .freq_tbl = ftbl_nss_crypto_clk_src,
 954         .mnd_width = 16,
 955         .hid_width = 5,
 956         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
 957         .clkr.hw.init = &(struct clk_init_data){
 958                 .name = "nss_crypto_clk_src",
 959                 .parent_data = gcc_xo_nss_crypto_pll_gpll0,
 960                 .num_parents = 3,
 961                 .ops = &clk_rcg2_ops,
 962         },
 963 };
 964
 965 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
 966         .reg = 0x68400,
 967         .shift = 0,
 968         .width = 4,
 969         .clkr = {
 970                 .hw.init = &(struct clk_init_data){
 971                         .name = "nss_port1_rx_div_clk_src",
 972                         .parent_hws = (const struct clk_hw *[]){
 973                                 &nss_port1_rx_clk_src.clkr.hw },
 974                         .num_parents = 1,
 975                         .ops = &clk_regmap_div_ops,
 976                         .flags = CLK_SET_RATE_PARENT,
 977                 },
 978         },
 979 };
 980
 981 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
 982         .reg = 0x68404,
 983         .shift = 0,
 984         .width = 4,
 985         .clkr = {
 986                 .hw.init = &(struct clk_init_data){
 987                         .name = "nss_port1_tx_div_clk_src",
 988                         .parent_hws = (const struct clk_hw *[]){
 989                                         &nss_port1_tx_clk_src.clkr.hw },
 990                         .num_parents = 1,
 991                         .ops = &clk_regmap_div_ops,
 992                         .flags = CLK_SET_RATE_PARENT,
 993                 },
 994         },
 995 };
 996
 997 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
 998         .reg = 0x68410,
 999         .shift = 0,
1000         .width = 4,
1001         .clkr = {
1002                 .hw.init = &(struct clk_init_data){
1003                         .name = "nss_port2_rx_div_clk_src",
1004                         .parent_hws = (const struct clk_hw *[]){
1005                                         &nss_port2_rx_clk_src.clkr.hw },
1006                         .num_parents = 1,
1007                         .ops = &clk_regmap_div_ops,
1008                         .flags = CLK_SET_RATE_PARENT,
1009                 },
1010         },
1011 };
1012
1013 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1014         .reg = 0x68414,
1015         .shift = 0,
1016         .width = 4,
1017         .clkr = {
1018                 .hw.init = &(struct clk_init_data){
1019                         .name = "nss_port2_tx_div_clk_src",
1020                         .parent_hws = (const struct clk_hw *[]){
1021                                         &nss_port2_tx_clk_src.clkr.hw },
1022                         .num_parents = 1,
1023                         .ops = &clk_regmap_div_ops,
1024                         .flags = CLK_SET_RATE_PARENT,
1025                 },
1026         },
1027 };
1028
1029 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1030         .reg = 0x68420,
1031         .shift = 0,
1032         .width = 4,
1033         .clkr = {
1034                 .hw.init = &(struct clk_init_data){
1035                         .name = "nss_port3_rx_div_clk_src",
1036                         .parent_hws = (const struct clk_hw *[]){
1037                                         &nss_port3_rx_clk_src.clkr.hw },
1038                         .num_parents = 1,
1039                         .ops = &clk_regmap_div_ops,
1040                         .flags = CLK_SET_RATE_PARENT,
1041                 },
1042         },
1043 };
1044
1045 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1046         .reg = 0x68424,
1047         .shift = 0,
1048         .width = 4,
1049         .clkr = {
1050                 .hw.init = &(struct clk_init_data){
1051                         .name = "nss_port3_tx_div_clk_src",
1052                         .parent_hws = (const struct clk_hw *[]){
1053                                         &nss_port3_tx_clk_src.clkr.hw },
1054                         .num_parents = 1,
1055                         .ops = &clk_regmap_div_ops,
1056                         .flags = CLK_SET_RATE_PARENT,
1057                 },
1058         },
1059 };
1060
1061 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1062         .reg = 0x68430,
1063         .shift = 0,
1064         .width = 4,
1065         .clkr = {
1066                 .hw.init = &(struct clk_init_data){
1067                         .name = "nss_port4_rx_div_clk_src",
1068                         .parent_hws = (const struct clk_hw *[]){
1069                                         &nss_port4_rx_clk_src.clkr.hw },
1070                         .num_parents = 1,
1071                         .ops = &clk_regmap_div_ops,
1072                         .flags = CLK_SET_RATE_PARENT,
1073                 },
1074         },
1075 };
1076
1077 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1078         .reg = 0x68434,
1079         .shift = 0,
1080         .width = 4,
1081         .clkr = {
1082                 .hw.init = &(struct clk_init_data){
1083                         .name = "nss_port4_tx_div_clk_src",
1084                         .parent_hws = (const struct clk_hw *[]){
1085                                         &nss_port4_tx_clk_src.clkr.hw },
1086                         .num_parents = 1,
1087                         .ops = &clk_regmap_div_ops,
1088                         .flags = CLK_SET_RATE_PARENT,
1089                 },
1090         },
1091 };
1092
1093 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1094         F(24000000, P_XO, 1, 0, 0),
1095         F(149760000, P_UBI32_PLL, 10, 0, 0),
1096         F(187200000, P_UBI32_PLL, 8, 0, 0),
1097         F(249600000, P_UBI32_PLL, 6, 0, 0),
1098         F(374400000, P_UBI32_PLL, 4, 0, 0),
1099         F(748800000, P_UBI32_PLL, 2, 0, 0),
1100         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1101         { }
1102 };
1103
1104 static const struct clk_parent_data
1105                         gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1106         { .fw_name = "xo" },
1107         { .hw = &ubi32_pll.clkr.hw },
1108         { .hw = &gpll0.clkr.hw },
1109         { .hw = &gpll2.clkr.hw },
1110         { .hw = &gpll4.clkr.hw },
1111         { .hw = &gpll6.clkr.hw },
1112 };
1113
1114 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1115         { P_XO, 0 },
1116         { P_UBI32_PLL, 1 },
1117         { P_GPLL0, 2 },
1118         { P_GPLL2, 3 },
1119         { P_GPLL4, 4 },
1120         { P_GPLL6, 5 },
1121 };
1122
1123 static struct clk_rcg2 nss_ubi0_clk_src = {
1124         .cmd_rcgr = 0x68104,
1125         .freq_tbl = ftbl_nss_ubi_clk_src,
1126         .hid_width = 5,
1127         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1128         .clkr.hw.init = &(struct clk_init_data){
1129                 .name = "nss_ubi0_clk_src",
1130                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1131                 .num_parents = 6,
1132                 .ops = &clk_rcg2_ops,
1133                 .flags = CLK_SET_RATE_PARENT,
1134         },
1135 };
1136
1137 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
1138         F(24000000, P_XO, 1, 0, 0),
1139         F(100000000, P_GPLL0, 8, 0, 0),
1140         { }
1141 };
1142
1143 static struct clk_rcg2 adss_pwm_clk_src = {
1144         .cmd_rcgr = 0x1c008,
1145         .freq_tbl = ftbl_adss_pwm_clk_src,
1146         .hid_width = 5,
1147         .parent_map = gcc_xo_gpll0_map,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "adss_pwm_clk_src",
1150                 .parent_data = gcc_xo_gpll0,
1151                 .num_parents = 2,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
1157         F(24000000, P_XO, 1, 0, 0),
1158         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1159         F(50000000, P_GPLL0, 16, 0, 0),
1160         { }
1161 };
1162
1163 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
1164         .cmd_rcgr = 0x0200c,
1165         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1166         .hid_width = 5,
1167         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1168         .clkr.hw.init = &(struct clk_init_data){
1169                 .name = "blsp1_qup1_i2c_apps_clk_src",
1170                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1171                 .num_parents = 3,
1172                 .ops = &clk_rcg2_ops,
1173         },
1174 };
1175
1176 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
1177         F(960000, P_XO, 10, 2, 5),
1178         F(4800000, P_XO, 5, 0, 0),
1179         F(9600000, P_XO, 2, 4, 5),
1180         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
1181         F(16000000, P_GPLL0, 10, 1, 5),
1182         F(24000000, P_XO, 1, 0, 0),
1183         F(25000000, P_GPLL0, 16, 1, 2),
1184         F(50000000, P_GPLL0, 16, 0, 0),
1185         { }
1186 };
1187
1188 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
1189         .cmd_rcgr = 0x02024,
1190         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1191         .mnd_width = 8,
1192         .hid_width = 5,
1193         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1194         .clkr.hw.init = &(struct clk_init_data){
1195                 .name = "blsp1_qup1_spi_apps_clk_src",
1196                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1197                 .num_parents = 3,
1198                 .ops = &clk_rcg2_ops,
1199         },
1200 };
1201
1202 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
1203         .cmd_rcgr = 0x03000,
1204         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1205         .hid_width = 5,
1206         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1207         .clkr.hw.init = &(struct clk_init_data){
1208                 .name = "blsp1_qup2_i2c_apps_clk_src",
1209                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1210                 .num_parents = 3,
1211                 .ops = &clk_rcg2_ops,
1212         },
1213 };
1214
1215 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
1216         .cmd_rcgr = 0x03014,
1217         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1218         .mnd_width = 8,
1219         .hid_width = 5,
1220         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1221         .clkr.hw.init = &(struct clk_init_data){
1222                 .name = "blsp1_qup2_spi_apps_clk_src",
1223                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1224                 .num_parents = 3,
1225                 .ops = &clk_rcg2_ops,
1226         },
1227 };
1228
1229 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
1230         .cmd_rcgr = 0x04000,
1231         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1232         .hid_width = 5,
1233         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1234         .clkr.hw.init = &(struct clk_init_data){
1235                 .name = "blsp1_qup3_i2c_apps_clk_src",
1236                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1237                 .num_parents = 3,
1238                 .ops = &clk_rcg2_ops,
1239         },
1240 };
1241
1242 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
1243         .cmd_rcgr = 0x04014,
1244         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1245         .mnd_width = 8,
1246         .hid_width = 5,
1247         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1248         .clkr.hw.init = &(struct clk_init_data){
1249                 .name = "blsp1_qup3_spi_apps_clk_src",
1250                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1251                 .num_parents = 3,
1252                 .ops = &clk_rcg2_ops,
1253         },
1254 };
1255
1256 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
1257         .cmd_rcgr = 0x05000,
1258         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1259         .hid_width = 5,
1260         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1261         .clkr.hw.init = &(struct clk_init_data){
1262                 .name = "blsp1_qup4_i2c_apps_clk_src",
1263                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1264                 .num_parents = 3,
1265                 .ops = &clk_rcg2_ops,
1266         },
1267 };
1268
1269 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
1270         .cmd_rcgr = 0x05014,
1271         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1272         .mnd_width = 8,
1273         .hid_width = 5,
1274         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1275         .clkr.hw.init = &(struct clk_init_data){
1276                 .name = "blsp1_qup4_spi_apps_clk_src",
1277                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1278                 .num_parents = 3,
1279                 .ops = &clk_rcg2_ops,
1280         },
1281 };
1282
1283 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
1284         .cmd_rcgr = 0x06000,
1285         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1286         .hid_width = 5,
1287         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1288         .clkr.hw.init = &(struct clk_init_data){
1289                 .name = "blsp1_qup5_i2c_apps_clk_src",
1290                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1291                 .num_parents = 3,
1292                 .ops = &clk_rcg2_ops,
1293         },
1294 };
1295
1296 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
1297         .cmd_rcgr = 0x06014,
1298         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1299         .mnd_width = 8,
1300         .hid_width = 5,
1301         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1302         .clkr.hw.init = &(struct clk_init_data){
1303                 .name = "blsp1_qup5_spi_apps_clk_src",
1304                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1305                 .num_parents = 3,
1306                 .ops = &clk_rcg2_ops,
1307         },
1308 };
1309
1310 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
1311         .cmd_rcgr = 0x07000,
1312         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1313         .hid_width = 5,
1314         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1315         .clkr.hw.init = &(struct clk_init_data){
1316                 .name = "blsp1_qup6_i2c_apps_clk_src",
1317                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1318                 .num_parents = 3,
1319                 .ops = &clk_rcg2_ops,
1320         },
1321 };
1322
1323 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
1324         .cmd_rcgr = 0x07014,
1325         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1326         .mnd_width = 8,
1327         .hid_width = 5,
1328         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1329         .clkr.hw.init = &(struct clk_init_data){
1330                 .name = "blsp1_qup6_spi_apps_clk_src",
1331                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1332                 .num_parents = 3,
1333                 .ops = &clk_rcg2_ops,
1334         },
1335 };
1336
1337 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
1338         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
1339         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
1340         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
1341         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
1342         F(24000000, P_XO, 1, 0, 0),
1343         F(24000000, P_GPLL0, 1, 3, 100),
1344         F(25000000, P_GPLL0, 16, 1, 2),
1345         F(32000000, P_GPLL0, 1, 1, 25),
1346         F(40000000, P_GPLL0, 1, 1, 20),
1347         F(46400000, P_GPLL0, 1, 29, 500),
1348         F(48000000, P_GPLL0, 1, 3, 50),
1349         F(51200000, P_GPLL0, 1, 8, 125),
1350         F(56000000, P_GPLL0, 1, 7, 100),
1351         F(58982400, P_GPLL0, 1, 1152, 15625),
1352         F(60000000, P_GPLL0, 1, 3, 40),
1353         F(64000000, P_GPLL0, 12.5, 1, 1),
1354         { }
1355 };
1356
1357 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
1358         .cmd_rcgr = 0x02044,
1359         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1360         .mnd_width = 16,
1361         .hid_width = 5,
1362         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1363         .clkr.hw.init = &(struct clk_init_data){
1364                 .name = "blsp1_uart1_apps_clk_src",
1365                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1366                 .num_parents = 3,
1367                 .ops = &clk_rcg2_ops,
1368         },
1369 };
1370
1371 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1372         .cmd_rcgr = 0x03034,
1373         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1374         .mnd_width = 16,
1375         .hid_width = 5,
1376         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1377         .clkr.hw.init = &(struct clk_init_data){
1378                 .name = "blsp1_uart2_apps_clk_src",
1379                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1380                 .num_parents = 3,
1381                 .ops = &clk_rcg2_ops,
1382         },
1383 };
1384
1385 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
1386         .cmd_rcgr = 0x04034,
1387         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1388         .mnd_width = 16,
1389         .hid_width = 5,
1390         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1391         .clkr.hw.init = &(struct clk_init_data){
1392                 .name = "blsp1_uart3_apps_clk_src",
1393                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1394                 .num_parents = 3,
1395                 .ops = &clk_rcg2_ops,
1396         },
1397 };
1398
1399 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
1400         .cmd_rcgr = 0x05034,
1401         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1402         .mnd_width = 16,
1403         .hid_width = 5,
1404         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1405         .clkr.hw.init = &(struct clk_init_data){
1406                 .name = "blsp1_uart4_apps_clk_src",
1407                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1408                 .num_parents = 3,
1409                 .ops = &clk_rcg2_ops,
1410         },
1411 };
1412
1413 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
1414         .cmd_rcgr = 0x06034,
1415         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1416         .mnd_width = 16,
1417         .hid_width = 5,
1418         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1419         .clkr.hw.init = &(struct clk_init_data){
1420                 .name = "blsp1_uart5_apps_clk_src",
1421                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1422                 .num_parents = 3,
1423                 .ops = &clk_rcg2_ops,
1424         },
1425 };
1426
1427 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
1428         .cmd_rcgr = 0x07034,
1429         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1430         .mnd_width = 16,
1431         .hid_width = 5,
1432         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1433         .clkr.hw.init = &(struct clk_init_data){
1434                 .name = "blsp1_uart6_apps_clk_src",
1435                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1436                 .num_parents = 3,
1437                 .ops = &clk_rcg2_ops,
1438         },
1439 };
1440
1441 static const struct freq_tbl ftbl_crypto_clk_src[] = {
1442         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1443         F(80000000, P_GPLL0, 10, 0, 0),
1444         F(100000000, P_GPLL0, 8, 0, 0),
1445         F(160000000, P_GPLL0, 5, 0, 0),
1446         { }
1447 };
1448
1449 static struct clk_rcg2 crypto_clk_src = {
1450         .cmd_rcgr = 0x16004,
1451         .freq_tbl = ftbl_crypto_clk_src,
1452         .hid_width = 5,
1453         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1454         .clkr.hw.init = &(struct clk_init_data){
1455                 .name = "crypto_clk_src",
1456                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1457                 .num_parents = 3,
1458                 .ops = &clk_rcg2_ops,
1459         },
1460 };
1461
1462 static const struct freq_tbl ftbl_gp_clk_src[] = {
1463         F(24000000, P_XO, 1, 0, 0),
1464         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1465         F(100000000, P_GPLL0, 8, 0, 0),
1466         F(200000000, P_GPLL0, 4, 0, 0),
1467         F(266666666, P_GPLL0, 3, 0, 0),
1468         { }
1469 };
1470
1471 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1472         { .fw_name = "xo" },
1473         { .hw = &gpll0.clkr.hw },
1474         { .hw = &gpll6.clkr.hw },
1475         { .hw = &gpll0_out_main_div2.hw },
1476         { .fw_name = "sleep_clk" },
1477 };
1478
1479 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1480         { P_XO, 0 },
1481         { P_GPLL0, 1 },
1482         { P_GPLL6, 2 },
1483         { P_GPLL0_DIV2, 4 },
1484         { P_SLEEP_CLK, 6 },
1485 };
1486
1487 static struct clk_rcg2 gp1_clk_src = {
1488         .cmd_rcgr = 0x08004,
1489         .freq_tbl = ftbl_gp_clk_src,
1490         .mnd_width = 8,
1491         .hid_width = 5,
1492         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1493         .clkr.hw.init = &(struct clk_init_data){
1494                 .name = "gp1_clk_src",
1495                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1496                 .num_parents = 5,
1497                 .ops = &clk_rcg2_ops,
1498         },
1499 };
1500
1501 static struct clk_rcg2 gp2_clk_src = {
1502         .cmd_rcgr = 0x09004,
1503         .freq_tbl = ftbl_gp_clk_src,
1504         .mnd_width = 8,
1505         .hid_width = 5,
1506         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1507         .clkr.hw.init = &(struct clk_init_data){
1508                 .name = "gp2_clk_src",
1509                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1510                 .num_parents = 5,
1511                 .ops = &clk_rcg2_ops,
1512         },
1513 };
1514
1515 static struct clk_rcg2 gp3_clk_src = {
1516         .cmd_rcgr = 0x0a004,
1517         .freq_tbl = ftbl_gp_clk_src,
1518         .mnd_width = 8,
1519         .hid_width = 5,
1520         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1521         .clkr.hw.init = &(struct clk_init_data){
1522                 .name = "gp3_clk_src",
1523                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1524                 .num_parents = 5,
1525                 .ops = &clk_rcg2_ops,
1526         },
1527 };
1528
1529 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1530         .mult = 1,
1531         .div = 4,
1532         .hw.init = &(struct clk_init_data){
1533                 .name = "nss_ppe_cdiv_clk_src",
1534                 .parent_hws = (const struct clk_hw *[]){
1535                                 &nss_ppe_clk_src.clkr.hw },
1536                 .num_parents = 1,
1537                 .ops = &clk_fixed_factor_ops,
1538                 .flags = CLK_SET_RATE_PARENT,
1539         },
1540 };
1541
1542 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1543         .reg = 0x68118,
1544         .shift = 0,
1545         .width = 4,
1546         .clkr = {
1547                 .hw.init = &(struct clk_init_data){
1548                         .name = "nss_ubi0_div_clk_src",
1549                         .parent_hws = (const struct clk_hw *[]){
1550                                 &nss_ubi0_clk_src.clkr.hw },
1551                         .num_parents = 1,
1552                         .ops = &clk_regmap_div_ro_ops,
1553                         .flags = CLK_SET_RATE_PARENT,
1554                 },
1555         },
1556 };
1557
1558 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1559         F(24000000, P_XO, 1, 0, 0),
1560         { }
1561 };
1562
1563 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
1564         { .fw_name = "xo" },
1565         { .hw = &gpll0.clkr.hw },
1566         { .fw_name = "sleep_clk" },
1567 };
1568
1569 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
1570         { P_XO, 0 },
1571         { P_GPLL0, 2 },
1572         { P_PI_SLEEP, 6 },
1573 };
1574
1575 static struct clk_rcg2 pcie0_aux_clk_src = {
1576         .cmd_rcgr = 0x75024,
1577         .freq_tbl = ftbl_pcie_aux_clk_src,
1578         .mnd_width = 16,
1579         .hid_width = 5,
1580         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1581         .clkr.hw.init = &(struct clk_init_data){
1582                 .name = "pcie0_aux_clk_src",
1583                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1584                 .num_parents = 3,
1585                 .ops = &clk_rcg2_ops,
1586         },
1587 };
1588
1589 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
1590         { .fw_name = "pcie20_phy0_pipe_clk" },
1591         { .fw_name = "xo" },
1592 };
1593
1594 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1595         { P_PCIE20_PHY0_PIPE, 0 },
1596         { P_XO, 2 },
1597 };
1598
1599 static struct clk_regmap_mux pcie0_pipe_clk_src = {
1600         .reg = 0x7501c,
1601         .shift = 8,
1602         .width = 2,
1603         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1604         .clkr = {
1605                 .hw.init = &(struct clk_init_data){
1606                         .name = "pcie0_pipe_clk_src",
1607                         .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1608                         .num_parents = 2,
1609                         .ops = &clk_regmap_mux_closest_ops,
1610                         .flags = CLK_SET_RATE_PARENT,
1611                 },
1612         },
1613 };
1614
1615 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1616         F(144000, P_XO, 16, 12, 125),
1617         F(400000, P_XO, 12, 1, 5),
1618         F(24000000, P_GPLL2, 12, 1, 4),
1619         F(48000000, P_GPLL2, 12, 1, 2),
1620         F(96000000, P_GPLL2, 12, 0, 0),
1621         F(177777778, P_GPLL0, 4.5, 0, 0),
1622         F(192000000, P_GPLL2, 6, 0, 0),
1623         F(384000000, P_GPLL2, 3, 0, 0),
1624         { }
1625 };
1626
1627 static const struct clk_parent_data
1628                         gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1629         { .fw_name = "xo" },
1630         { .hw = &gpll0.clkr.hw },
1631         { .hw = &gpll2.clkr.hw },
1632         { .hw = &gpll0_out_main_div2.hw },
1633 };
1634
1635 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1636         { P_XO, 0 },
1637         { P_GPLL0, 1 },
1638         { P_GPLL2, 2 },
1639         { P_GPLL0_DIV2, 4 },
1640 };
1641
1642 static struct clk_rcg2 sdcc1_apps_clk_src = {
1643         .cmd_rcgr = 0x42004,
1644         .freq_tbl = ftbl_sdcc_apps_clk_src,
1645         .mnd_width = 8,
1646         .hid_width = 5,
1647         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1648         .clkr.hw.init = &(struct clk_init_data){
1649                 .name = "sdcc1_apps_clk_src",
1650                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1651                 .num_parents = 4,
1652                 .ops = &clk_rcg2_floor_ops,
1653         },
1654 };
1655
1656 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1657         F(24000000, P_XO, 1, 0, 0),
1658         { }
1659 };
1660
1661 static struct clk_rcg2 usb0_aux_clk_src = {
1662         .cmd_rcgr = 0x3e05c,
1663         .freq_tbl = ftbl_usb_aux_clk_src,
1664         .mnd_width = 16,
1665         .hid_width = 5,
1666         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1667         .clkr.hw.init = &(struct clk_init_data){
1668                 .name = "usb0_aux_clk_src",
1669                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1670                 .num_parents = 3,
1671                 .ops = &clk_rcg2_ops,
1672         },
1673 };
1674
1675 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1676         F(24000000, P_XO, 1, 0, 0),
1677         F(60000000, P_GPLL6, 6, 1, 3),
1678         { }
1679 };
1680
1681 static const struct clk_parent_data
1682                         gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1683         { .fw_name = "xo" },
1684         { .hw = &gpll6.clkr.hw },
1685         { .hw = &gpll0.clkr.hw },
1686         { .hw = &gpll0_out_main_div2.hw },
1687 };
1688
1689 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1690         { P_XO, 0 },
1691         { P_GPLL6, 1 },
1692         { P_GPLL0, 3 },
1693         { P_GPLL0_DIV2, 4 },
1694 };
1695
1696 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1697         .cmd_rcgr = 0x3e020,
1698         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1699         .mnd_width = 8,
1700         .hid_width = 5,
1701         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1702         .clkr.hw.init = &(struct clk_init_data){
1703                 .name = "usb0_mock_utmi_clk_src",
1704                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1705                 .num_parents = 4,
1706                 .ops = &clk_rcg2_ops,
1707         },
1708 };
1709
1710 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1711         { .fw_name = "usb3phy_0_cc_pipe_clk" },
1712         { .fw_name = "xo" },
1713 };
1714
1715 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1716         { P_USB3PHY_0_PIPE, 0 },
1717         { P_XO, 2 },
1718 };
1719
1720 static struct clk_regmap_mux usb0_pipe_clk_src = {
1721         .reg = 0x3e048,
1722         .shift = 8,
1723         .width = 2,
1724         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1725         .clkr = {
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "usb0_pipe_clk_src",
1728                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1729                         .num_parents = 2,
1730                         .ops = &clk_regmap_mux_closest_ops,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                 },
1733         },
1734 };
1735
1736 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1737         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1738         F(160000000, P_GPLL0, 5, 0, 0),
1739         F(216000000, P_GPLL6, 5, 0, 0),
1740         F(308570000, P_GPLL6, 3.5, 0, 0),
1741         { }
1742 };
1743
1744 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1745         { .fw_name = "xo"},
1746         { .hw = &gpll0.clkr.hw },
1747         { .hw = &gpll6.clkr.hw },
1748         { .hw = &gpll0_out_main_div2.hw },
1749 };
1750
1751 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1752         { P_XO, 0 },
1753         { P_GPLL0, 1 },
1754         { P_GPLL6, 2 },
1755         { P_GPLL0_DIV2, 4 },
1756 };
1757
1758 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1759         .cmd_rcgr = 0x5d000,
1760         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1761         .mnd_width = 8,
1762         .hid_width = 5,
1763         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1764         .clkr.hw.init = &(struct clk_init_data){
1765                 .name = "sdcc1_ice_core_clk_src",
1766                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1767                 .num_parents = 4,
1768                 .ops = &clk_rcg2_ops,
1769         },
1770 };
1771
1772 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1773         F(24000000, P_XO, 1, 0, 0),
1774         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1775         F(100000000, P_GPLL0, 8, 0, 0),
1776         F(200000000, P_GPLL0, 4, 0, 0),
1777         { }
1778 };
1779
1780 static struct clk_rcg2 qdss_stm_clk_src = {
1781         .cmd_rcgr = 0x2902C,
1782         .freq_tbl = ftbl_qdss_stm_clk_src,
1783         .hid_width = 5,
1784         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1785         .clkr.hw.init = &(struct clk_init_data){
1786                 .name = "qdss_stm_clk_src",
1787                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1788                 .num_parents = 3,
1789                 .ops = &clk_rcg2_ops,
1790         },
1791 };
1792
1793 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1794         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1795         F(160000000, P_GPLL0, 5, 0, 0),
1796         F(300000000, P_GPLL4, 4, 0, 0),
1797         { }
1798 };
1799
1800 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
1801         { .fw_name = "xo" },
1802         { .hw = &gpll4.clkr.hw },
1803         { .hw = &gpll0.clkr.hw },
1804         { .hw = &gpll0_out_main_div2.hw },
1805 };
1806
1807 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
1808         { P_XO, 0 },
1809         { P_GPLL4, 1 },
1810         { P_GPLL0, 2 },
1811         { P_GPLL0_DIV2, 4 },
1812 };
1813
1814 static struct clk_rcg2 qdss_traceclkin_clk_src = {
1815         .cmd_rcgr = 0x29048,
1816         .freq_tbl = ftbl_qdss_traceclkin_clk_src,
1817         .hid_width = 5,
1818         .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
1819         .clkr.hw.init = &(struct clk_init_data){
1820                 .name = "qdss_traceclkin_clk_src",
1821                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
1822                 .num_parents = 4,
1823                 .ops = &clk_rcg2_ops,
1824         },
1825 };
1826
1827 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1828         .cmd_rcgr = 0x3f020,
1829         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1830         .mnd_width = 8,
1831         .hid_width = 5,
1832         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1833         .clkr.hw.init = &(struct clk_init_data){
1834                 .name = "usb1_mock_utmi_clk_src",
1835                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1836                 .num_parents = 4,
1837                 .ops = &clk_rcg2_ops,
1838         },
1839 };
1840
1841 static struct clk_branch gcc_adss_pwm_clk = {
1842         .halt_reg = 0x1c020,
1843         .clkr = {
1844                 .enable_reg = 0x1c020,
1845                 .enable_mask = BIT(0),
1846                 .hw.init = &(struct clk_init_data){
1847                         .name = "gcc_adss_pwm_clk",
1848                         .parent_hws = (const struct clk_hw *[]){
1849                                         &adss_pwm_clk_src.clkr.hw },
1850                         .num_parents = 1,
1851                         .flags = CLK_SET_RATE_PARENT,
1852                         .ops = &clk_branch2_ops,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gcc_apss_ahb_clk = {
1858         .halt_reg = 0x4601c,
1859         .halt_check = BRANCH_HALT_VOTED,
1860         .clkr = {
1861                 .enable_reg = 0x0b004,
1862                 .enable_mask = BIT(14),
1863                 .hw.init = &(struct clk_init_data){
1864                         .name = "gcc_apss_ahb_clk",
1865                         .parent_hws = (const struct clk_hw *[]){
1866                                         &apss_ahb_postdiv_clk_src.clkr.hw },
1867                         .num_parents = 1,
1868                         .flags = CLK_SET_RATE_PARENT,
1869                         .ops = &clk_branch2_ops,
1870                 },
1871         },
1872 };
1873
1874 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1875         F(24000000, P_XO, 1, 0, 0),
1876         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1877         F(100000000, P_GPLL0, 8, 0, 0),
1878         F(133333333, P_GPLL0, 6, 0, 0),
1879         F(160000000, P_GPLL0, 5, 0, 0),
1880         F(200000000, P_GPLL0, 4, 0, 0),
1881         F(266666667, P_GPLL0, 3, 0, 0),
1882         { }
1883 };
1884
1885 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1886         .cmd_rcgr = 0x26004,
1887         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1888         .hid_width = 5,
1889         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1890         .clkr.hw.init = &(struct clk_init_data){
1891                 .name = "system_noc_bfdcd_clk_src",
1892                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1893                 .num_parents = 4,
1894                 .ops = &clk_rcg2_ops,
1895         },
1896 };
1897
1898 static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
1899         F(24000000, P_XO, 1, 0, 0),
1900         F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1901         F(533333333, P_GPLL0, 1.5, 0, 0),
1902         { }
1903 };
1904
1905 static const struct clk_parent_data
1906                         gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
1907         { .fw_name = "xo" },
1908         { .hw = &gpll0.clkr.hw },
1909         { .hw = &gpll2.clkr.hw },
1910         { .fw_name = "bias_pll_nss_noc_clk" },
1911 };
1912
1913 static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
1914         { P_XO, 0 },
1915         { P_GPLL0, 1 },
1916         { P_GPLL2, 3 },
1917         { P_BIAS_PLL_NSS_NOC, 4 },
1918 };
1919
1920 static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
1921         .cmd_rcgr = 0x68088,
1922         .freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
1923         .hid_width = 5,
1924         .parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
1925         .clkr.hw.init = &(struct clk_init_data){
1926                 .name = "ubi32_mem_noc_bfdcd_clk_src",
1927                 .parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
1928                 .num_parents = 4,
1929                 .ops = &clk_rcg2_ops,
1930         },
1931 };
1932
1933 static struct clk_branch gcc_apss_axi_clk = {
1934         .halt_reg = 0x46020,
1935         .halt_check = BRANCH_HALT_VOTED,
1936         .clkr = {
1937                 .enable_reg = 0x0b004,
1938                 .enable_mask = BIT(13),
1939                 .hw.init = &(struct clk_init_data){
1940                         .name = "gcc_apss_axi_clk",
1941                         .parent_hws = (const struct clk_hw *[]){
1942                                         &apss_axi_clk_src.clkr.hw },
1943                         .num_parents = 1,
1944                         .flags = CLK_SET_RATE_PARENT,
1945                         .ops = &clk_branch2_ops,
1946                 },
1947         },
1948 };
1949
1950 static struct clk_branch gcc_blsp1_ahb_clk = {
1951         .halt_reg = 0x01008,
1952         .halt_check = BRANCH_HALT_VOTED,
1953         .clkr = {
1954                 .enable_reg = 0x0b004,
1955                 .enable_mask = BIT(10),
1956                 .hw.init = &(struct clk_init_data){
1957                         .name = "gcc_blsp1_ahb_clk",
1958                         .parent_hws = (const struct clk_hw *[]){
1959                                         &pcnoc_bfdcd_clk_src.clkr.hw },
1960                         .num_parents = 1,
1961                         .flags = CLK_SET_RATE_PARENT,
1962                         .ops = &clk_branch2_ops,
1963                 },
1964         },
1965 };
1966
1967 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1968         .halt_reg = 0x02008,
1969         .clkr = {
1970                 .enable_reg = 0x02008,
1971                 .enable_mask = BIT(0),
1972                 .hw.init = &(struct clk_init_data){
1973                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1974                         .parent_hws = (const struct clk_hw *[]){
1975                                         &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1984         .halt_reg = 0x02004,
1985         .clkr = {
1986                 .enable_reg = 0x02004,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1990                         .parent_hws = (const struct clk_hw *[]){
1991                                         &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1992                         .num_parents = 1,
1993                         .flags = CLK_SET_RATE_PARENT,
1994                         .ops = &clk_branch2_ops,
1995                 },
1996         },
1997 };
1998
1999 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2000         .halt_reg = 0x03010,
2001         .clkr = {
2002                 .enable_reg = 0x03010,
2003                 .enable_mask = BIT(0),
2004                 .hw.init = &(struct clk_init_data){
2005                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2006                         .parent_hws = (const struct clk_hw *[]){
2007                                         &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2016         .halt_reg = 0x0300c,
2017         .clkr = {
2018                 .enable_reg = 0x0300c,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2022                         .parent_hws = (const struct clk_hw *[]){
2023                                         &blsp1_qup2_spi_apps_clk_src.clkr.hw },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2032         .halt_reg = 0x04010,
2033         .clkr = {
2034                 .enable_reg = 0x04010,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2038                         .parent_hws = (const struct clk_hw *[]){
2039                                         &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2040                         .num_parents = 1,
2041                         .flags = CLK_SET_RATE_PARENT,
2042                         .ops = &clk_branch2_ops,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2048         .halt_reg = 0x0400c,
2049         .clkr = {
2050                 .enable_reg = 0x0400c,
2051                 .enable_mask = BIT(0),
2052                 .hw.init = &(struct clk_init_data){
2053                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2054                         .parent_hws = (const struct clk_hw *[]){
2055                                         &blsp1_qup3_spi_apps_clk_src.clkr.hw },
2056                         .num_parents = 1,
2057                         .flags = CLK_SET_RATE_PARENT,
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2064         .halt_reg = 0x05010,
2065         .clkr = {
2066                 .enable_reg = 0x05010,
2067                 .enable_mask = BIT(0),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2070                         .parent_hws = (const struct clk_hw *[]){
2071                                         &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2072                         .num_parents = 1,
2073                         .flags = CLK_SET_RATE_PARENT,
2074                         .ops = &clk_branch2_ops,
2075                 },
2076         },
2077 };
2078
2079 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2080         .halt_reg = 0x0500c,
2081         .clkr = {
2082                 .enable_reg = 0x0500c,
2083                 .enable_mask = BIT(0),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2086                         .parent_hws = (const struct clk_hw *[]){
2087                                         &blsp1_qup4_spi_apps_clk_src.clkr.hw },
2088                         .num_parents = 1,
2089                         .flags = CLK_SET_RATE_PARENT,
2090                         .ops = &clk_branch2_ops,
2091                 },
2092         },
2093 };
2094
2095 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2096         .halt_reg = 0x06010,
2097         .clkr = {
2098                 .enable_reg = 0x06010,
2099                 .enable_mask = BIT(0),
2100                 .hw.init = &(struct clk_init_data){
2101                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2102                         .parent_hws = (const struct clk_hw *[]){
2103                                         &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2104                         .num_parents = 1,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                         .ops = &clk_branch2_ops,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2112         .halt_reg = 0x0600c,
2113         .clkr = {
2114                 .enable_reg = 0x0600c,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2118                         .parent_hws = (const struct clk_hw *[]){
2119                                         &blsp1_qup5_spi_apps_clk_src.clkr.hw },
2120                         .num_parents = 1,
2121                         .flags = CLK_SET_RATE_PARENT,
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2128         .halt_reg = 0x0700c,
2129         .clkr = {
2130                 .enable_reg = 0x0700c,
2131                 .enable_mask = BIT(0),
2132                 .hw.init = &(struct clk_init_data){
2133                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2134                         .parent_hws = (const struct clk_hw *[]){
2135                                         &blsp1_qup6_spi_apps_clk_src.clkr.hw },
2136                         .num_parents = 1,
2137                         .flags = CLK_SET_RATE_PARENT,
2138                         .ops = &clk_branch2_ops,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2144         .halt_reg = 0x0203c,
2145         .clkr = {
2146                 .enable_reg = 0x0203c,
2147                 .enable_mask = BIT(0),
2148                 .hw.init = &(struct clk_init_data){
2149                         .name = "gcc_blsp1_uart1_apps_clk",
2150                         .parent_hws = (const struct clk_hw *[]){
2151                                         &blsp1_uart1_apps_clk_src.clkr.hw },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2160         .halt_reg = 0x0302c,
2161         .clkr = {
2162                 .enable_reg = 0x0302c,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_blsp1_uart2_apps_clk",
2166                         .parent_hws = (const struct clk_hw *[]){
2167                                         &blsp1_uart2_apps_clk_src.clkr.hw },
2168                         .num_parents = 1,
2169                         .flags = CLK_SET_RATE_PARENT,
2170                         .ops = &clk_branch2_ops,
2171                 },
2172         },
2173 };
2174
2175 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2176         .halt_reg = 0x0402c,
2177         .clkr = {
2178                 .enable_reg = 0x0402c,
2179                 .enable_mask = BIT(0),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "gcc_blsp1_uart3_apps_clk",
2182                         .parent_hws = (const struct clk_hw *[]){
2183                                         &blsp1_uart3_apps_clk_src.clkr.hw },
2184                         .num_parents = 1,
2185                         .flags = CLK_SET_RATE_PARENT,
2186                         .ops = &clk_branch2_ops,
2187                 },
2188         },
2189 };
2190
2191 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2192         .halt_reg = 0x0502c,
2193         .clkr = {
2194                 .enable_reg = 0x0502c,
2195                 .enable_mask = BIT(0),
2196                 .hw.init = &(struct clk_init_data){
2197                         .name = "gcc_blsp1_uart4_apps_clk",
2198                         .parent_hws = (const struct clk_hw *[]){
2199                                         &blsp1_uart4_apps_clk_src.clkr.hw },
2200                         .num_parents = 1,
2201                         .flags = CLK_SET_RATE_PARENT,
2202                         .ops = &clk_branch2_ops,
2203                 },
2204         },
2205 };
2206
2207 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2208         .halt_reg = 0x0602c,
2209         .clkr = {
2210                 .enable_reg = 0x0602c,
2211                 .enable_mask = BIT(0),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "gcc_blsp1_uart5_apps_clk",
2214                         .parent_hws = (const struct clk_hw *[]){
2215                                         &blsp1_uart5_apps_clk_src.clkr.hw },
2216                         .num_parents = 1,
2217                         .flags = CLK_SET_RATE_PARENT,
2218                         .ops = &clk_branch2_ops,
2219                 },
2220         },
2221 };
2222
2223 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2224         .halt_reg = 0x0702c,
2225         .clkr = {
2226                 .enable_reg = 0x0702c,
2227                 .enable_mask = BIT(0),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "gcc_blsp1_uart6_apps_clk",
2230                         .parent_hws = (const struct clk_hw *[]){
2231                                         &blsp1_uart6_apps_clk_src.clkr.hw },
2232                         .num_parents = 1,
2233                         .flags = CLK_SET_RATE_PARENT,
2234                         .ops = &clk_branch2_ops,
2235                 },
2236         },
2237 };
2238
2239 static struct clk_branch gcc_crypto_ahb_clk = {
2240         .halt_reg = 0x16024,
2241         .halt_check = BRANCH_HALT_VOTED,
2242         .clkr = {
2243                 .enable_reg = 0x0b004,
2244                 .enable_mask = BIT(0),
2245                 .hw.init = &(struct clk_init_data){
2246                         .name = "gcc_crypto_ahb_clk",
2247                         .parent_hws = (const struct clk_hw *[]){
2248                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2249                         .num_parents = 1,
2250                         .flags = CLK_SET_RATE_PARENT,
2251                         .ops = &clk_branch2_ops,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch gcc_crypto_axi_clk = {
2257         .halt_reg = 0x16020,
2258         .halt_check = BRANCH_HALT_VOTED,
2259         .clkr = {
2260                 .enable_reg = 0x0b004,
2261                 .enable_mask = BIT(1),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "gcc_crypto_axi_clk",
2264                         .parent_hws = (const struct clk_hw *[]){
2265                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2266                         .num_parents = 1,
2267                         .flags = CLK_SET_RATE_PARENT,
2268                         .ops = &clk_branch2_ops,
2269                 },
2270         },
2271 };
2272
2273 static struct clk_branch gcc_crypto_clk = {
2274         .halt_reg = 0x1601c,
2275         .halt_check = BRANCH_HALT_VOTED,
2276         .clkr = {
2277                 .enable_reg = 0x0b004,
2278                 .enable_mask = BIT(2),
2279                 .hw.init = &(struct clk_init_data){
2280                         .name = "gcc_crypto_clk",
2281                         .parent_hws = (const struct clk_hw *[]){
2282                                         &crypto_clk_src.clkr.hw },
2283                         .num_parents = 1,
2284                         .flags = CLK_SET_RATE_PARENT,
2285                         .ops = &clk_branch2_ops,
2286                 },
2287         },
2288 };
2289
2290 static struct clk_fixed_factor gpll6_out_main_div2 = {
2291         .mult = 1,
2292         .div = 2,
2293         .hw.init = &(struct clk_init_data){
2294                 .name = "gpll6_out_main_div2",
2295                 .parent_hws = (const struct clk_hw *[]){
2296                                 &gpll6_main.clkr.hw },
2297                 .num_parents = 1,
2298                 .ops = &clk_fixed_factor_ops,
2299                 .flags = CLK_SET_RATE_PARENT,
2300         },
2301 };
2302
2303 static struct clk_branch gcc_xo_clk = {
2304         .halt_reg = 0x30030,
2305         .clkr = {
2306                 .enable_reg = 0x30030,
2307                 .enable_mask = BIT(0),
2308                 .hw.init = &(struct clk_init_data){
2309                         .name = "gcc_xo_clk",
2310                         .parent_hws = (const struct clk_hw *[]){
2311                                         &gcc_xo_clk_src.clkr.hw },
2312                         .num_parents = 1,
2313                         .flags = CLK_SET_RATE_PARENT,
2314                         .ops = &clk_branch2_ops,
2315                 },
2316         },
2317 };
2318
2319 static struct clk_branch gcc_gp1_clk = {
2320         .halt_reg = 0x08000,
2321         .clkr = {
2322                 .enable_reg = 0x08000,
2323                 .enable_mask = BIT(0),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "gcc_gp1_clk",
2326                         .parent_hws = (const struct clk_hw *[]){
2327                                         &gp1_clk_src.clkr.hw },
2328                         .num_parents = 1,
2329                         .flags = CLK_SET_RATE_PARENT,
2330                         .ops = &clk_branch2_ops,
2331                 },
2332         },
2333 };
2334
2335 static struct clk_branch gcc_gp2_clk = {
2336         .halt_reg = 0x09000,
2337         .clkr = {
2338                 .enable_reg = 0x09000,
2339                 .enable_mask = BIT(0),
2340                 .hw.init = &(struct clk_init_data){
2341                         .name = "gcc_gp2_clk",
2342                         .parent_hws = (const struct clk_hw *[]){
2343                                         &gp2_clk_src.clkr.hw },
2344                         .num_parents = 1,
2345                         .flags = CLK_SET_RATE_PARENT,
2346                         .ops = &clk_branch2_ops,
2347                 },
2348         },
2349 };
2350
2351 static struct clk_branch gcc_gp3_clk = {
2352         .halt_reg = 0x0a000,
2353         .clkr = {
2354                 .enable_reg = 0x0a000,
2355                 .enable_mask = BIT(0),
2356                 .hw.init = &(struct clk_init_data){
2357                         .name = "gcc_gp3_clk",
2358                         .parent_hws = (const struct clk_hw *[]){
2359                                         &gp3_clk_src.clkr.hw },
2360                         .num_parents = 1,
2361                         .flags = CLK_SET_RATE_PARENT,
2362                         .ops = &clk_branch2_ops,
2363                 },
2364         },
2365 };
2366
2367 static struct clk_branch gcc_mdio_ahb_clk = {
2368         .halt_reg = 0x58004,
2369         .clkr = {
2370                 .enable_reg = 0x58004,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "gcc_mdio_ahb_clk",
2374                         .parent_hws = (const struct clk_hw *[]){
2375                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2376                         .num_parents = 1,
2377                         .flags = CLK_SET_RATE_PARENT,
2378                         .ops = &clk_branch2_ops,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch gcc_crypto_ppe_clk = {
2384         .halt_reg = 0x68310,
2385         .clkr = {
2386                 .enable_reg = 0x68310,
2387                 .enable_mask = BIT(0),
2388                 .hw.init = &(struct clk_init_data){
2389                         .name = "gcc_crypto_ppe_clk",
2390                         .parent_hws = (const struct clk_hw *[]){
2391                                         &nss_ppe_clk_src.clkr.hw },
2392                         .num_parents = 1,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                         .ops = &clk_branch2_ops,
2395                 },
2396         },
2397 };
2398
2399 static struct clk_branch gcc_nss_ce_apb_clk = {
2400         .halt_reg = 0x68174,
2401         .clkr = {
2402                 .enable_reg = 0x68174,
2403                 .enable_mask = BIT(0),
2404                 .hw.init = &(struct clk_init_data){
2405                         .name = "gcc_nss_ce_apb_clk",
2406                         .parent_hws = (const struct clk_hw *[]){
2407                                         &nss_ce_clk_src.clkr.hw },
2408                         .num_parents = 1,
2409                         .flags = CLK_SET_RATE_PARENT,
2410                         .ops = &clk_branch2_ops,
2411                 },
2412         },
2413 };
2414
2415 static struct clk_branch gcc_nss_ce_axi_clk = {
2416         .halt_reg = 0x68170,
2417         .clkr = {
2418                 .enable_reg = 0x68170,
2419                 .enable_mask = BIT(0),
2420                 .hw.init = &(struct clk_init_data){
2421                         .name = "gcc_nss_ce_axi_clk",
2422                         .parent_hws = (const struct clk_hw *[]){
2423                                         &nss_ce_clk_src.clkr.hw },
2424                         .num_parents = 1,
2425                         .flags = CLK_SET_RATE_PARENT,
2426                         .ops = &clk_branch2_ops,
2427                 },
2428         },
2429 };
2430
2431 static struct clk_branch gcc_nss_cfg_clk = {
2432         .halt_reg = 0x68160,
2433         .clkr = {
2434                 .enable_reg = 0x68160,
2435                 .enable_mask = BIT(0),
2436                 .hw.init = &(struct clk_init_data){
2437                         .name = "gcc_nss_cfg_clk",
2438                         .parent_hws = (const struct clk_hw *[]){
2439                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2440                         .num_parents = 1,
2441                         .flags = CLK_SET_RATE_PARENT,
2442                         .ops = &clk_branch2_ops,
2443                 },
2444         },
2445 };
2446
2447 static struct clk_branch gcc_nss_crypto_clk = {
2448         .halt_reg = 0x68164,
2449         .clkr = {
2450                 .enable_reg = 0x68164,
2451                 .enable_mask = BIT(0),
2452                 .hw.init = &(struct clk_init_data){
2453                         .name = "gcc_nss_crypto_clk",
2454                         .parent_hws = (const struct clk_hw *[]){
2455                                         &nss_crypto_clk_src.clkr.hw },
2456                         .num_parents = 1,
2457                         .flags = CLK_SET_RATE_PARENT,
2458                         .ops = &clk_branch2_ops,
2459                 },
2460         },
2461 };
2462
2463 static struct clk_branch gcc_nss_csr_clk = {
2464         .halt_reg = 0x68318,
2465         .clkr = {
2466                 .enable_reg = 0x68318,
2467                 .enable_mask = BIT(0),
2468                 .hw.init = &(struct clk_init_data){
2469                         .name = "gcc_nss_csr_clk",
2470                         .parent_hws = (const struct clk_hw *[]){
2471                                         &nss_ce_clk_src.clkr.hw },
2472                         .num_parents = 1,
2473                         .flags = CLK_SET_RATE_PARENT,
2474                         .ops = &clk_branch2_ops,
2475                 },
2476         },
2477 };
2478
2479 static struct clk_branch gcc_nss_edma_cfg_clk = {
2480         .halt_reg = 0x6819C,
2481         .clkr = {
2482                 .enable_reg = 0x6819C,
2483                 .enable_mask = BIT(0),
2484                 .hw.init = &(struct clk_init_data){
2485                         .name = "gcc_nss_edma_cfg_clk",
2486                         .parent_hws = (const struct clk_hw *[]){
2487                                         &nss_ppe_clk_src.clkr.hw },
2488                         .num_parents = 1,
2489                         .flags = CLK_SET_RATE_PARENT,
2490                         .ops = &clk_branch2_ops,
2491                 },
2492         },
2493 };
2494
2495 static struct clk_branch gcc_nss_edma_clk = {
2496         .halt_reg = 0x68198,
2497         .clkr = {
2498                 .enable_reg = 0x68198,
2499                 .enable_mask = BIT(0),
2500                 .hw.init = &(struct clk_init_data){
2501                         .name = "gcc_nss_edma_clk",
2502                         .parent_hws = (const struct clk_hw *[]){
2503                                         &nss_ppe_clk_src.clkr.hw },
2504                         .num_parents = 1,
2505                         .flags = CLK_SET_RATE_PARENT,
2506                         .ops = &clk_branch2_ops,
2507                 },
2508         },
2509 };
2510
2511 static struct clk_branch gcc_nss_noc_clk = {
2512         .halt_reg = 0x68168,
2513         .clkr = {
2514                 .enable_reg = 0x68168,
2515                 .enable_mask = BIT(0),
2516                 .hw.init = &(struct clk_init_data){
2517                         .name = "gcc_nss_noc_clk",
2518                         .parent_hws = (const struct clk_hw *[]){
2519                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2520                         .num_parents = 1,
2521                         .flags = CLK_SET_RATE_PARENT,
2522                         .ops = &clk_branch2_ops,
2523                 },
2524         },
2525 };
2526
2527 static struct clk_branch gcc_ubi0_utcm_clk = {
2528         .halt_reg = 0x2606c,
2529         .clkr = {
2530                 .enable_reg = 0x2606c,
2531                 .enable_mask = BIT(0),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "gcc_ubi0_utcm_clk",
2534                         .parent_hws = (const struct clk_hw *[]){
2535                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2536                         .num_parents = 1,
2537                         .flags = CLK_SET_RATE_PARENT,
2538                         .ops = &clk_branch2_ops,
2539                 },
2540         },
2541 };
2542
2543 static struct clk_branch gcc_snoc_nssnoc_clk = {
2544         .halt_reg = 0x26070,
2545         .clkr = {
2546                 .enable_reg = 0x26070,
2547                 .enable_mask = BIT(0),
2548                 .hw.init = &(struct clk_init_data){
2549                         .name = "gcc_snoc_nssnoc_clk",
2550                         .parent_hws = (const struct clk_hw *[]){
2551                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2552                         .num_parents = 1,
2553                         .flags = CLK_SET_RATE_PARENT,
2554                         .ops = &clk_branch2_ops,
2555                 },
2556         },
2557 };
2558
2559 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2560         F(24000000, P_XO, 1, 0, 0),
2561         F(133333333, P_GPLL0, 6, 0, 0),
2562         { }
2563 };
2564
2565 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
2566         F(24000000, P_XO, 1, 0, 0),
2567         F(400000000, P_GPLL0, 2, 0, 0),
2568         { }
2569 };
2570
2571 static struct clk_rcg2 wcss_ahb_clk_src = {
2572         .cmd_rcgr = 0x59020,
2573         .freq_tbl = ftbl_wcss_ahb_clk_src,
2574         .hid_width = 5,
2575         .parent_map = gcc_xo_gpll0_map,
2576         .clkr.hw.init = &(struct clk_init_data){
2577                 .name = "wcss_ahb_clk_src",
2578                 .parent_data = gcc_xo_gpll0,
2579                 .num_parents = 2,
2580                 .ops = &clk_rcg2_ops,
2581         },
2582 };
2583
2584 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
2585         { .fw_name = "xo" },
2586         { .hw = &gpll0.clkr.hw },
2587         { .hw = &gpll2.clkr.hw },
2588         { .hw = &gpll4.clkr.hw },
2589         { .hw = &gpll6.clkr.hw },
2590 };
2591
2592 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
2593         { P_XO, 0 },
2594         { P_GPLL0, 1 },
2595         { P_GPLL2, 2 },
2596         { P_GPLL4, 3 },
2597         { P_GPLL6, 4 },
2598 };
2599
2600 static struct clk_rcg2 q6_axi_clk_src = {
2601         .cmd_rcgr = 0x59120,
2602         .freq_tbl = ftbl_q6_axi_clk_src,
2603         .hid_width = 5,
2604         .parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
2605         .clkr.hw.init = &(struct clk_init_data){
2606                 .name = "q6_axi_clk_src",
2607                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
2608                 .num_parents = 5,
2609                 .ops = &clk_rcg2_ops,
2610         },
2611 };
2612
2613 static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
2614         F(24000000, P_XO, 1, 0, 0),
2615         F(100000000, P_GPLL0, 8, 0, 0),
2616         { }
2617 };
2618
2619 static struct clk_rcg2 lpass_core_axim_clk_src = {
2620         .cmd_rcgr = 0x1F020,
2621         .freq_tbl = ftbl_lpass_core_axim_clk_src,
2622         .hid_width = 5,
2623         .parent_map = gcc_xo_gpll0_map,
2624         .clkr.hw.init = &(struct clk_init_data){
2625                 .name = "lpass_core_axim_clk_src",
2626                 .parent_data = gcc_xo_gpll0,
2627                 .num_parents = 2,
2628                 .ops = &clk_rcg2_ops,
2629         },
2630 };
2631
2632 static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
2633         F(24000000, P_XO, 1, 0, 0),
2634         F(266666667, P_GPLL0, 3, 0, 0),
2635         { }
2636 };
2637
2638 static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
2639         .cmd_rcgr = 0x1F040,
2640         .freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
2641         .hid_width = 5,
2642         .parent_map = gcc_xo_gpll0_map,
2643         .clkr.hw.init = &(struct clk_init_data){
2644                 .name = "lpass_snoc_cfg_clk_src",
2645                 .parent_data = gcc_xo_gpll0,
2646                 .num_parents = 2,
2647                 .ops = &clk_rcg2_ops,
2648         },
2649 };
2650
2651 static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
2652         F(24000000, P_XO, 1, 0, 0),
2653         F(400000000, P_GPLL0, 2, 0, 0),
2654         { }
2655 };
2656
2657 static struct clk_rcg2 lpass_q6_axim_clk_src = {
2658         .cmd_rcgr = 0x1F008,
2659         .freq_tbl = ftbl_lpass_q6_axim_clk_src,
2660         .hid_width = 5,
2661         .parent_map = gcc_xo_gpll0_map,
2662         .clkr.hw.init = &(struct clk_init_data){
2663                 .name = "lpass_q6_axim_clk_src",
2664                 .parent_data = gcc_xo_gpll0,
2665                 .num_parents = 2,
2666                 .ops = &clk_rcg2_ops,
2667         },
2668 };
2669
2670 static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
2671         F(24000000, P_XO, 1, 0, 0),
2672         F(50000000, P_GPLL0, 16, 0, 0),
2673         { }
2674 };
2675
2676 static struct clk_rcg2 rbcpr_wcss_clk_src = {
2677         .cmd_rcgr = 0x3a00c,
2678         .freq_tbl = ftbl_rbcpr_wcss_clk_src,
2679         .hid_width = 5,
2680         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
2681         .clkr.hw.init = &(struct clk_init_data){
2682                 .name = "rbcpr_wcss_clk_src",
2683                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
2684                 .num_parents = 3,
2685                 .ops = &clk_rcg2_ops,
2686         },
2687 };
2688
2689 static struct clk_branch gcc_lpass_core_axim_clk = {
2690         .halt_reg = 0x1F028,
2691         .clkr = {
2692                 .enable_reg = 0x1F028,
2693                 .enable_mask = BIT(0),
2694                 .hw.init = &(struct clk_init_data){
2695                         .name = "gcc_lpass_core_axim_clk",
2696                         .parent_hws = (const struct clk_hw *[]){
2697                                         &lpass_core_axim_clk_src.clkr.hw },
2698                         .num_parents = 1,
2699                         .flags = CLK_SET_RATE_PARENT,
2700                         .ops = &clk_branch2_ops,
2701                 },
2702         },
2703 };
2704
2705 static struct clk_branch gcc_lpass_snoc_cfg_clk = {
2706         .halt_reg = 0x1F048,
2707         .clkr = {
2708                 .enable_reg = 0x1F048,
2709                 .enable_mask = BIT(0),
2710                 .hw.init = &(struct clk_init_data){
2711                         .name = "gcc_lpass_snoc_cfg_clk",
2712                         .parent_hws = (const struct clk_hw *[]){
2713                                         &lpass_snoc_cfg_clk_src.clkr.hw },
2714                         .num_parents = 1,
2715                         .flags = CLK_SET_RATE_PARENT,
2716                         .ops = &clk_branch2_ops,
2717                 },
2718         },
2719 };
2720
2721 static struct clk_branch gcc_lpass_q6_axim_clk = {
2722         .halt_reg = 0x1F010,
2723         .clkr = {
2724                 .enable_reg = 0x1F010,
2725                 .enable_mask = BIT(0),
2726                 .hw.init = &(struct clk_init_data){
2727                         .name = "gcc_lpass_q6_axim_clk",
2728                         .parent_hws = (const struct clk_hw *[]){
2729                                         &lpass_q6_axim_clk_src.clkr.hw },
2730                         .num_parents = 1,
2731                         .flags = CLK_SET_RATE_PARENT,
2732                         .ops = &clk_branch2_ops,
2733                 },
2734         },
2735 };
2736
2737 static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
2738         .halt_reg = 0x1F018,
2739         .clkr = {
2740                 .enable_reg = 0x1F018,
2741                 .enable_mask = BIT(0),
2742                 .hw.init = &(struct clk_init_data){
2743                         .name = "gcc_lpass_q6_atbm_at_clk",
2744                         .parent_hws = (const struct clk_hw *[]){
2745                                         &qdss_at_clk_src.clkr.hw },
2746                         .num_parents = 1,
2747                         .flags = CLK_SET_RATE_PARENT,
2748                         .ops = &clk_branch2_ops,
2749                 },
2750         },
2751 };
2752
2753 static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
2754         .halt_reg = 0x1F01C,
2755         .clkr = {
2756                 .enable_reg = 0x1F01C,
2757                 .enable_mask = BIT(0),
2758                 .hw.init = &(struct clk_init_data){
2759                         .name = "gcc_lpass_q6_pclkdbg_clk",
2760                         .parent_hws = (const struct clk_hw *[]){
2761                                         &qdss_dap_sync_clk_src.hw },
2762                         .num_parents = 1,
2763                         .flags = CLK_SET_RATE_PARENT,
2764                         .ops = &clk_branch2_ops,
2765                 },
2766         },
2767 };
2768
2769 static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
2770         .halt_reg = 0x1F014,
2771         .clkr = {
2772                 .enable_reg = 0x1F014,
2773                 .enable_mask = BIT(0),
2774                 .hw.init = &(struct clk_init_data){
2775                         .name = "gcc_lpass_q6ss_tsctr_1to2_clk",
2776                         .parent_hws = (const struct clk_hw *[]){
2777                                         &qdss_tsctr_div2_clk_src.hw },
2778                         .num_parents = 1,
2779                         .flags = CLK_SET_RATE_PARENT,
2780                         .ops = &clk_branch2_ops,
2781                 },
2782         },
2783 };
2784
2785 static struct clk_branch gcc_lpass_q6ss_trig_clk = {
2786         .halt_reg = 0x1F038,
2787         .clkr = {
2788                 .enable_reg = 0x1F038,
2789                 .enable_mask = BIT(0),
2790                 .hw.init = &(struct clk_init_data){
2791                         .name = "gcc_lpass_q6ss_trig_clk",
2792                         .parent_hws = (const struct clk_hw *[]){
2793                                         &qdss_dap_sync_clk_src.hw },
2794                         .num_parents = 1,
2795                         .flags = CLK_SET_RATE_PARENT,
2796                         .ops = &clk_branch2_ops,
2797                 },
2798         },
2799 };
2800
2801 static struct clk_branch gcc_lpass_tbu_clk = {
2802         .halt_reg = 0x12094,
2803         .clkr = {
2804                 .enable_reg = 0xb00c,
2805                 .enable_mask = BIT(10),
2806                 .hw.init = &(struct clk_init_data){
2807                         .name = "gcc_lpass_tbu_clk",
2808                         .parent_hws = (const struct clk_hw *[]){
2809                                         &lpass_q6_axim_clk_src.clkr.hw },
2810                         .num_parents = 1,
2811                         .flags = CLK_SET_RATE_PARENT,
2812                         .ops = &clk_branch2_ops,
2813                 },
2814         },
2815 };
2816
2817 static struct clk_branch gcc_pcnoc_lpass_clk = {
2818         .halt_reg = 0x27020,
2819         .clkr = {
2820                 .enable_reg = 0x27020,
2821                 .enable_mask = BIT(0),
2822                 .hw.init = &(struct clk_init_data){
2823                         .name = "gcc_pcnoc_lpass_clk",
2824                         .parent_hws = (const struct clk_hw *[]){
2825                                         &lpass_core_axim_clk_src.clkr.hw },
2826                         .num_parents = 1,
2827                         .flags = CLK_SET_RATE_PARENT,
2828                         .ops = &clk_branch2_ops,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch gcc_mem_noc_lpass_clk = {
2834         .halt_reg = 0x1D044,
2835         .clkr = {
2836                 .enable_reg = 0x1D044,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data){
2839                         .name = "gcc_mem_noc_lpass_clk",
2840                         .parent_hws = (const struct clk_hw *[]){
2841                                         &lpass_q6_axim_clk_src.clkr.hw },
2842                         .num_parents = 1,
2843                         .flags = CLK_SET_RATE_PARENT,
2844                         .ops = &clk_branch2_ops,
2845                 },
2846         },
2847 };
2848
2849 static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2850         .halt_reg = 0x26074,
2851         .clkr = {
2852                 .enable_reg = 0x26074,
2853                 .enable_mask = BIT(0),
2854                 .hw.init = &(struct clk_init_data){
2855                         .name = "gcc_snoc_lpass_cfg_clk",
2856                         .parent_hws = (const struct clk_hw *[]){
2857                                         &lpass_snoc_cfg_clk_src.clkr.hw },
2858                         .num_parents = 1,
2859                         .flags = CLK_SET_RATE_PARENT,
2860                         .ops = &clk_branch2_ops,
2861                 },
2862         },
2863 };
2864
2865 static struct clk_branch gcc_mem_noc_ubi32_clk = {
2866         .halt_reg = 0x1D03C,
2867         .clkr = {
2868                 .enable_reg = 0x1D03C,
2869                 .enable_mask = BIT(0),
2870                 .hw.init = &(struct clk_init_data){
2871                         .name = "gcc_mem_noc_ubi32_clk",
2872                         .parent_hws = (const struct clk_hw *[]){
2873                                         &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
2874                         .num_parents = 1,
2875                         .flags = CLK_SET_RATE_PARENT,
2876                         .ops = &clk_branch2_ops,
2877                 },
2878         },
2879 };
2880
2881 static struct clk_branch gcc_nss_port1_rx_clk = {
2882         .halt_reg = 0x68240,
2883         .clkr = {
2884                 .enable_reg = 0x68240,
2885                 .enable_mask = BIT(0),
2886                 .hw.init = &(struct clk_init_data){
2887                         .name = "gcc_nss_port1_rx_clk",
2888                         .parent_hws = (const struct clk_hw *[]){
2889                                         &nss_port1_rx_div_clk_src.clkr.hw },
2890                         .num_parents = 1,
2891                         .flags = CLK_SET_RATE_PARENT,
2892                         .ops = &clk_branch2_ops,
2893                 },
2894         },
2895 };
2896
2897 static struct clk_branch gcc_nss_port1_tx_clk = {
2898         .halt_reg = 0x68244,
2899         .clkr = {
2900                 .enable_reg = 0x68244,
2901                 .enable_mask = BIT(0),
2902                 .hw.init = &(struct clk_init_data){
2903                         .name = "gcc_nss_port1_tx_clk",
2904                         .parent_hws = (const struct clk_hw *[]){
2905                                         &nss_port1_tx_div_clk_src.clkr.hw },
2906                         .num_parents = 1,
2907                         .flags = CLK_SET_RATE_PARENT,
2908                         .ops = &clk_branch2_ops,
2909                 },
2910         },
2911 };
2912
2913 static struct clk_branch gcc_nss_port2_rx_clk = {
2914         .halt_reg = 0x68248,
2915         .clkr = {
2916                 .enable_reg = 0x68248,
2917                 .enable_mask = BIT(0),
2918                 .hw.init = &(struct clk_init_data){
2919                         .name = "gcc_nss_port2_rx_clk",
2920                         .parent_hws = (const struct clk_hw *[]){
2921                                         &nss_port2_rx_div_clk_src.clkr.hw },
2922                         .num_parents = 1,
2923                         .flags = CLK_SET_RATE_PARENT,
2924                         .ops = &clk_branch2_ops,
2925                 },
2926         },
2927 };
2928
2929 static struct clk_branch gcc_nss_port2_tx_clk = {
2930         .halt_reg = 0x6824c,
2931         .clkr = {
2932                 .enable_reg = 0x6824c,
2933                 .enable_mask = BIT(0),
2934                 .hw.init = &(struct clk_init_data){
2935                         .name = "gcc_nss_port2_tx_clk",
2936                         .parent_hws = (const struct clk_hw *[]){
2937                                         &nss_port2_tx_div_clk_src.clkr.hw },
2938                         .num_parents = 1,
2939                         .flags = CLK_SET_RATE_PARENT,
2940                         .ops = &clk_branch2_ops,
2941                 },
2942         },
2943 };
2944
2945 static struct clk_branch gcc_nss_port3_rx_clk = {
2946         .halt_reg = 0x68250,
2947         .clkr = {
2948                 .enable_reg = 0x68250,
2949                 .enable_mask = BIT(0),
2950                 .hw.init = &(struct clk_init_data){
2951                         .name = "gcc_nss_port3_rx_clk",
2952                         .parent_hws = (const struct clk_hw *[]){
2953                                         &nss_port3_rx_div_clk_src.clkr.hw },
2954                         .num_parents = 1,
2955                         .flags = CLK_SET_RATE_PARENT,
2956                         .ops = &clk_branch2_ops,
2957                 },
2958         },
2959 };
2960
2961 static struct clk_branch gcc_nss_port3_tx_clk = {
2962         .halt_reg = 0x68254,
2963         .clkr = {
2964                 .enable_reg = 0x68254,
2965                 .enable_mask = BIT(0),
2966                 .hw.init = &(struct clk_init_data){
2967                         .name = "gcc_nss_port3_tx_clk",
2968                         .parent_hws = (const struct clk_hw *[]){
2969                                         &nss_port3_tx_div_clk_src.clkr.hw },
2970                         .num_parents = 1,
2971                         .flags = CLK_SET_RATE_PARENT,
2972                         .ops = &clk_branch2_ops,
2973                 },
2974         },
2975 };
2976
2977 static struct clk_branch gcc_nss_port4_rx_clk = {
2978         .halt_reg = 0x68258,
2979         .clkr = {
2980                 .enable_reg = 0x68258,
2981                 .enable_mask = BIT(0),
2982                 .hw.init = &(struct clk_init_data){
2983                         .name = "gcc_nss_port4_rx_clk",
2984                         .parent_hws = (const struct clk_hw *[]){
2985                                         &nss_port4_rx_div_clk_src.clkr.hw },
2986                         .num_parents = 1,
2987                         .flags = CLK_SET_RATE_PARENT,
2988                         .ops = &clk_branch2_ops,
2989                 },
2990         },
2991 };
2992
2993 static struct clk_branch gcc_nss_port4_tx_clk = {
2994         .halt_reg = 0x6825c,
2995         .clkr = {
2996                 .enable_reg = 0x6825c,
2997                 .enable_mask = BIT(0),
2998                 .hw.init = &(struct clk_init_data){
2999                         .name = "gcc_nss_port4_tx_clk",
3000                         .parent_hws = (const struct clk_hw *[]){
3001                                         &nss_port4_tx_div_clk_src.clkr.hw },
3002                         .num_parents = 1,
3003                         .flags = CLK_SET_RATE_PARENT,
3004                         .ops = &clk_branch2_ops,
3005                 },
3006         },
3007 };
3008
3009 static struct clk_branch gcc_nss_port5_rx_clk = {
3010         .halt_reg = 0x68260,
3011         .clkr = {
3012                 .enable_reg = 0x68260,
3013                 .enable_mask = BIT(0),
3014                 .hw.init = &(struct clk_init_data){
3015                         .name = "gcc_nss_port5_rx_clk",
3016                         .parent_hws = (const struct clk_hw *[]){
3017                                         &nss_port5_rx_div_clk_src.clkr.hw },
3018                         .num_parents = 1,
3019                         .flags = CLK_SET_RATE_PARENT,
3020                         .ops = &clk_branch2_ops,
3021                 },
3022         },
3023 };
3024
3025 static struct clk_branch gcc_nss_port5_tx_clk = {
3026         .halt_reg = 0x68264,
3027         .clkr = {
3028                 .enable_reg = 0x68264,
3029                 .enable_mask = BIT(0),
3030                 .hw.init = &(struct clk_init_data){
3031                         .name = "gcc_nss_port5_tx_clk",
3032                         .parent_hws = (const struct clk_hw *[]){
3033                                         &nss_port5_tx_div_clk_src.clkr.hw },
3034                         .num_parents = 1,
3035                         .flags = CLK_SET_RATE_PARENT,
3036                         .ops = &clk_branch2_ops,
3037                 },
3038         },
3039 };
3040
3041 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3042         .halt_reg = 0x68194,
3043         .clkr = {
3044                 .enable_reg = 0x68194,
3045                 .enable_mask = BIT(0),
3046                 .hw.init = &(struct clk_init_data){
3047                         .name = "gcc_nss_ppe_cfg_clk",
3048                         .parent_hws = (const struct clk_hw *[]){
3049                                         &nss_ppe_clk_src.clkr.hw },
3050                         .num_parents = 1,
3051                         .flags = CLK_SET_RATE_PARENT,
3052                         .ops = &clk_branch2_ops,
3053                 },
3054         },
3055 };
3056
3057 static struct clk_branch gcc_nss_ppe_clk = {
3058         .halt_reg = 0x68190,
3059         .clkr = {
3060                 .enable_reg = 0x68190,
3061                 .enable_mask = BIT(0),
3062                 .hw.init = &(struct clk_init_data){
3063                         .name = "gcc_nss_ppe_clk",
3064                         .parent_hws = (const struct clk_hw *[]){
3065                                         &nss_ppe_clk_src.clkr.hw },
3066                         .num_parents = 1,
3067                         .flags = CLK_SET_RATE_PARENT,
3068                         .ops = &clk_branch2_ops,
3069                 },
3070         },
3071 };
3072
3073 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3074         .halt_reg = 0x68338,
3075         .clkr = {
3076                 .enable_reg = 0x68338,
3077                 .enable_mask = BIT(0),
3078                 .hw.init = &(struct clk_init_data){
3079                         .name = "gcc_nss_ppe_ipe_clk",
3080                         .parent_hws = (const struct clk_hw *[]){
3081                                         &nss_ppe_clk_src.clkr.hw },
3082                         .num_parents = 1,
3083                         .flags = CLK_SET_RATE_PARENT,
3084                         .ops = &clk_branch2_ops,
3085                 },
3086         },
3087 };
3088
3089 static struct clk_branch gcc_nss_ptp_ref_clk = {
3090         .halt_reg = 0x6816C,
3091         .clkr = {
3092                 .enable_reg = 0x6816C,
3093                 .enable_mask = BIT(0),
3094                 .hw.init = &(struct clk_init_data){
3095                         .name = "gcc_nss_ptp_ref_clk",
3096                         .parent_hws = (const struct clk_hw *[]){
3097                                         &nss_ppe_cdiv_clk_src.hw },
3098                         .num_parents = 1,
3099                         .flags = CLK_SET_RATE_PARENT,
3100                         .ops = &clk_branch2_ops,
3101                 },
3102         },
3103 };
3104
3105 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3106         .halt_reg = 0x6830C,
3107         .clkr = {
3108                 .enable_reg = 0x6830C,
3109                 .enable_mask = BIT(0),
3110                 .hw.init = &(struct clk_init_data){
3111                         .name = "gcc_nssnoc_ce_apb_clk",
3112                         .parent_hws = (const struct clk_hw *[]){
3113                                         &nss_ce_clk_src.clkr.hw },
3114                         .num_parents = 1,
3115                         .flags = CLK_SET_RATE_PARENT,
3116                         .ops = &clk_branch2_ops,
3117                 },
3118         },
3119 };
3120
3121 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3122         .halt_reg = 0x68308,
3123         .clkr = {
3124                 .enable_reg = 0x68308,
3125                 .enable_mask = BIT(0),
3126                 .hw.init = &(struct clk_init_data){
3127                         .name = "gcc_nssnoc_ce_axi_clk",
3128                         .parent_hws = (const struct clk_hw *[]){
3129                                         &nss_ce_clk_src.clkr.hw },
3130                         .num_parents = 1,
3131                         .flags = CLK_SET_RATE_PARENT,
3132                         .ops = &clk_branch2_ops,
3133                 },
3134         },
3135 };
3136
3137 static struct clk_branch gcc_nssnoc_crypto_clk = {
3138         .halt_reg = 0x68314,
3139         .clkr = {
3140                 .enable_reg = 0x68314,
3141                 .enable_mask = BIT(0),
3142                 .hw.init = &(struct clk_init_data){
3143                         .name = "gcc_nssnoc_crypto_clk",
3144                         .parent_hws = (const struct clk_hw *[]){
3145                                         &nss_crypto_clk_src.clkr.hw },
3146                         .num_parents = 1,
3147                         .flags = CLK_SET_RATE_PARENT,
3148                         .ops = &clk_branch2_ops,
3149                 },
3150         },
3151 };
3152
3153 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3154         .halt_reg = 0x68304,
3155         .clkr = {
3156                 .enable_reg = 0x68304,
3157                 .enable_mask = BIT(0),
3158                 .hw.init = &(struct clk_init_data){
3159                         .name = "gcc_nssnoc_ppe_cfg_clk",
3160                         .parent_hws = (const struct clk_hw *[]){
3161                                         &nss_ppe_clk_src.clkr.hw },
3162                         .flags = CLK_SET_RATE_PARENT,
3163                         .ops = &clk_branch2_ops,
3164                 },
3165         },
3166 };
3167
3168 static struct clk_branch gcc_nssnoc_ppe_clk = {
3169         .halt_reg = 0x68300,
3170         .clkr = {
3171                 .enable_reg = 0x68300,
3172                 .enable_mask = BIT(0),
3173                 .hw.init = &(struct clk_init_data){
3174                         .name = "gcc_nssnoc_ppe_clk",
3175                         .parent_hws = (const struct clk_hw *[]){
3176                                         &nss_ppe_clk_src.clkr.hw },
3177                         .num_parents = 1,
3178                         .flags = CLK_SET_RATE_PARENT,
3179                         .ops = &clk_branch2_ops,
3180                 },
3181         },
3182 };
3183
3184 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3185         .halt_reg = 0x68180,
3186         .clkr = {
3187                 .enable_reg = 0x68180,
3188                 .enable_mask = BIT(0),
3189                 .hw.init = &(struct clk_init_data){
3190                         .name = "gcc_nssnoc_qosgen_ref_clk",
3191                         .parent_hws = (const struct clk_hw *[]){
3192                                         &gcc_xo_clk_src.clkr.hw },
3193                         .num_parents = 1,
3194                         .flags = CLK_SET_RATE_PARENT,
3195                         .ops = &clk_branch2_ops,
3196                 },
3197         },
3198 };
3199
3200 static struct clk_branch gcc_nssnoc_snoc_clk = {
3201         .halt_reg = 0x68188,
3202         .clkr = {
3203                 .enable_reg = 0x68188,
3204                 .enable_mask = BIT(0),
3205                 .hw.init = &(struct clk_init_data){
3206                         .name = "gcc_nssnoc_snoc_clk",
3207                         .parent_hws = (const struct clk_hw *[]){
3208                                         &system_noc_bfdcd_clk_src.clkr.hw },
3209                         .num_parents = 1,
3210                         .flags = CLK_SET_RATE_PARENT,
3211                         .ops = &clk_branch2_ops,
3212                 },
3213         },
3214 };
3215
3216 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3217         .halt_reg = 0x68184,
3218         .clkr = {
3219                 .enable_reg = 0x68184,
3220                 .enable_mask = BIT(0),
3221                 .hw.init = &(struct clk_init_data){
3222                         .name = "gcc_nssnoc_timeout_ref_clk",
3223                         .parent_hws = (const struct clk_hw *[]){
3224                                         &gcc_xo_div4_clk_src.hw },
3225                         .num_parents = 1,
3226                         .flags = CLK_SET_RATE_PARENT,
3227                         .ops = &clk_branch2_ops,
3228                 },
3229         },
3230 };
3231
3232 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3233         .halt_reg = 0x68270,
3234         .clkr = {
3235                 .enable_reg = 0x68270,
3236                 .enable_mask = BIT(0),
3237                 .hw.init = &(struct clk_init_data){
3238                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3239                         .parent_hws = (const struct clk_hw *[]){
3240                                         &nss_ce_clk_src.clkr.hw },
3241                         .num_parents = 1,
3242                         .flags = CLK_SET_RATE_PARENT,
3243                         .ops = &clk_branch2_ops,
3244                 },
3245         },
3246 };
3247
3248 static struct clk_branch gcc_port1_mac_clk = {
3249         .halt_reg = 0x68320,
3250         .clkr = {
3251                 .enable_reg = 0x68320,
3252                 .enable_mask = BIT(0),
3253                 .hw.init = &(struct clk_init_data){
3254                         .name = "gcc_port1_mac_clk",
3255                         .parent_hws = (const struct clk_hw *[]){
3256                                         &nss_ppe_clk_src.clkr.hw },
3257                         .num_parents = 1,
3258                         .flags = CLK_SET_RATE_PARENT,
3259                         .ops = &clk_branch2_ops,
3260                 },
3261         },
3262 };
3263
3264 static struct clk_branch gcc_port2_mac_clk = {
3265         .halt_reg = 0x68324,
3266         .clkr = {
3267                 .enable_reg = 0x68324,
3268                 .enable_mask = BIT(0),
3269                 .hw.init = &(struct clk_init_data){
3270                         .name = "gcc_port2_mac_clk",
3271                         .parent_hws = (const struct clk_hw *[]){
3272                                         &nss_ppe_clk_src.clkr.hw },
3273                         .num_parents = 1,
3274                         .flags = CLK_SET_RATE_PARENT,
3275                         .ops = &clk_branch2_ops,
3276                 },
3277         },
3278 };
3279
3280 static struct clk_branch gcc_port3_mac_clk = {
3281         .halt_reg = 0x68328,
3282         .clkr = {
3283                 .enable_reg = 0x68328,
3284                 .enable_mask = BIT(0),
3285                 .hw.init = &(struct clk_init_data){
3286                         .name = "gcc_port3_mac_clk",
3287                         .parent_hws = (const struct clk_hw *[]){
3288                                         &nss_ppe_clk_src.clkr.hw },
3289                         .num_parents = 1,
3290                         .flags = CLK_SET_RATE_PARENT,
3291                         .ops = &clk_branch2_ops,
3292                 },
3293         },
3294 };
3295
3296 static struct clk_branch gcc_port4_mac_clk = {
3297         .halt_reg = 0x6832c,
3298         .clkr = {
3299                 .enable_reg = 0x6832c,
3300                 .enable_mask = BIT(0),
3301                 .hw.init = &(struct clk_init_data){
3302                         .name = "gcc_port4_mac_clk",
3303                         .parent_hws = (const struct clk_hw *[]){
3304                                         &nss_ppe_clk_src.clkr.hw },
3305                         .num_parents = 1,
3306                         .flags = CLK_SET_RATE_PARENT,
3307                         .ops = &clk_branch2_ops,
3308                 },
3309         },
3310 };
3311
3312 static struct clk_branch gcc_port5_mac_clk = {
3313         .halt_reg = 0x68330,
3314         .clkr = {
3315                 .enable_reg = 0x68330,
3316                 .enable_mask = BIT(0),
3317                 .hw.init = &(struct clk_init_data){
3318                         .name = "gcc_port5_mac_clk",
3319                         .parent_hws = (const struct clk_hw *[]){
3320                                         &nss_ppe_clk_src.clkr.hw },
3321                         .num_parents = 1,
3322                         .flags = CLK_SET_RATE_PARENT,
3323                         .ops = &clk_branch2_ops,
3324                 },
3325         },
3326 };
3327
3328 static struct clk_branch gcc_ubi0_ahb_clk = {
3329         .halt_reg = 0x6820C,
3330         .halt_check = BRANCH_HALT_DELAY,
3331         .clkr = {
3332                 .enable_reg = 0x6820C,
3333                 .enable_mask = BIT(0),
3334                 .hw.init = &(struct clk_init_data){
3335                         .name = "gcc_ubi0_ahb_clk",
3336                         .parent_hws = (const struct clk_hw *[]){
3337                                         &nss_ce_clk_src.clkr.hw },
3338                         .num_parents = 1,
3339                         .flags = CLK_SET_RATE_PARENT,
3340                         .ops = &clk_branch2_ops,
3341                 },
3342         },
3343 };
3344
3345 static struct clk_branch gcc_ubi0_axi_clk = {
3346         .halt_reg = 0x68200,
3347         .halt_check = BRANCH_HALT_DELAY,
3348         .clkr = {
3349                 .enable_reg = 0x68200,
3350                 .enable_mask = BIT(0),
3351                 .hw.init = &(struct clk_init_data){
3352                         .name = "gcc_ubi0_axi_clk",
3353                         .parent_hws = (const struct clk_hw *[]){
3354                                         &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
3355                         .num_parents = 1,
3356                         .flags = CLK_SET_RATE_PARENT,
3357                         .ops = &clk_branch2_ops,
3358                 },
3359         },
3360 };
3361
3362 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3363         .halt_reg = 0x68204,
3364         .halt_check = BRANCH_HALT_DELAY,
3365         .clkr = {
3366                 .enable_reg = 0x68204,
3367                 .enable_mask = BIT(0),
3368                 .hw.init = &(struct clk_init_data){
3369                         .name = "gcc_ubi0_nc_axi_clk",
3370                         .parent_hws = (const struct clk_hw *[]){
3371                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
3372                         .num_parents = 1,
3373                         .flags = CLK_SET_RATE_PARENT,
3374                         .ops = &clk_branch2_ops,
3375                 },
3376         },
3377 };
3378
3379 static struct clk_branch gcc_ubi0_core_clk = {
3380         .halt_reg = 0x68210,
3381         .halt_check = BRANCH_HALT_DELAY,
3382         .clkr = {
3383                 .enable_reg = 0x68210,
3384                 .enable_mask = BIT(0),
3385                 .hw.init = &(struct clk_init_data){
3386                         .name = "gcc_ubi0_core_clk",
3387                         .parent_hws = (const struct clk_hw *[]){
3388                                         &nss_ubi0_div_clk_src.clkr.hw },
3389                         .num_parents = 1,
3390                         .flags = CLK_SET_RATE_PARENT,
3391                         .ops = &clk_branch2_ops,
3392                 },
3393         },
3394 };
3395
3396 static struct clk_branch gcc_pcie0_ahb_clk = {
3397         .halt_reg = 0x75010,
3398         .clkr = {
3399                 .enable_reg = 0x75010,
3400                 .enable_mask = BIT(0),
3401                 .hw.init = &(struct clk_init_data){
3402                         .name = "gcc_pcie0_ahb_clk",
3403                         .parent_hws = (const struct clk_hw *[]){
3404                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3405                         .num_parents = 1,
3406                         .flags = CLK_SET_RATE_PARENT,
3407                         .ops = &clk_branch2_ops,
3408                 },
3409         },
3410 };
3411
3412 static struct clk_branch gcc_pcie0_aux_clk = {
3413         .halt_reg = 0x75014,
3414         .clkr = {
3415                 .enable_reg = 0x75014,
3416                 .enable_mask = BIT(0),
3417                 .hw.init = &(struct clk_init_data){
3418                         .name = "gcc_pcie0_aux_clk",
3419                         .parent_hws = (const struct clk_hw *[]){
3420                                         &pcie0_aux_clk_src.clkr.hw },
3421                         .num_parents = 1,
3422                         .flags = CLK_SET_RATE_PARENT,
3423                         .ops = &clk_branch2_ops,
3424                 },
3425         },
3426 };
3427
3428 static struct clk_branch gcc_pcie0_axi_m_clk = {
3429         .halt_reg = 0x75008,
3430         .clkr = {
3431                 .enable_reg = 0x75008,
3432                 .enable_mask = BIT(0),
3433                 .hw.init = &(struct clk_init_data){
3434                         .name = "gcc_pcie0_axi_m_clk",
3435                         .parent_hws = (const struct clk_hw *[]){
3436                                         &pcie0_axi_clk_src.clkr.hw },
3437                         .num_parents = 1,
3438                         .flags = CLK_SET_RATE_PARENT,
3439                         .ops = &clk_branch2_ops,
3440                 },
3441         },
3442 };
3443
3444 static struct clk_branch gcc_pcie0_axi_s_clk = {
3445         .halt_reg = 0x7500c,
3446         .clkr = {
3447                 .enable_reg = 0x7500c,
3448                 .enable_mask = BIT(0),
3449                 .hw.init = &(struct clk_init_data){
3450                         .name = "gcc_pcie0_axi_s_clk",
3451                         .parent_hws = (const struct clk_hw *[]){
3452                                         &pcie0_axi_clk_src.clkr.hw },
3453                         .num_parents = 1,
3454                         .flags = CLK_SET_RATE_PARENT,
3455                         .ops = &clk_branch2_ops,
3456                 },
3457         },
3458 };
3459
3460 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
3461         .halt_reg = 0x26048,
3462         .clkr = {
3463                 .enable_reg = 0x26048,
3464                 .enable_mask = BIT(0),
3465                 .hw.init = &(struct clk_init_data){
3466                         .name = "gcc_sys_noc_pcie0_axi_clk",
3467                         .parent_hws = (const struct clk_hw *[]){
3468                                         &pcie0_axi_clk_src.clkr.hw },
3469                         .num_parents = 1,
3470                         .flags = CLK_SET_RATE_PARENT,
3471                         .ops = &clk_branch2_ops,
3472                 },
3473         },
3474 };
3475
3476 static struct clk_branch gcc_pcie0_pipe_clk = {
3477         .halt_reg = 0x75018,
3478         .halt_check = BRANCH_HALT_DELAY,
3479         .clkr = {
3480                 .enable_reg = 0x75018,
3481                 .enable_mask = BIT(0),
3482                 .hw.init = &(struct clk_init_data){
3483                         .name = "gcc_pcie0_pipe_clk",
3484                         .parent_hws = (const struct clk_hw *[]){
3485                                         &pcie0_pipe_clk_src.clkr.hw },
3486                         .num_parents = 1,
3487                         .flags = CLK_SET_RATE_PARENT,
3488                         .ops = &clk_branch2_ops,
3489                 },
3490         },
3491 };
3492
3493 static struct clk_branch gcc_prng_ahb_clk = {
3494         .halt_reg = 0x13004,
3495         .halt_check = BRANCH_HALT_VOTED,
3496         .clkr = {
3497                 .enable_reg = 0x0b004,
3498                 .enable_mask = BIT(8),
3499                 .hw.init = &(struct clk_init_data){
3500                         .name = "gcc_prng_ahb_clk",
3501                         .parent_hws = (const struct clk_hw *[]){
3502                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3503                         .num_parents = 1,
3504                         .flags = CLK_SET_RATE_PARENT,
3505                         .ops = &clk_branch2_ops,
3506                 },
3507         },
3508 };
3509
3510 static struct clk_branch gcc_qdss_dap_clk = {
3511         .halt_reg = 0x29084,
3512         .clkr = {
3513                 .enable_reg = 0x29084,
3514                 .enable_mask = BIT(0),
3515                 .hw.init = &(struct clk_init_data){
3516                         .name = "gcc_qdss_dap_clk",
3517                         .parent_hws = (const struct clk_hw *[]){
3518                                         &qdss_dap_sync_clk_src.hw },
3519                         .num_parents = 1,
3520                         .flags = CLK_SET_RATE_PARENT,
3521                         .ops = &clk_branch2_ops,
3522                 },
3523         },
3524 };
3525
3526 static struct clk_branch gcc_qpic_ahb_clk = {
3527         .halt_reg = 0x57024,
3528         .clkr = {
3529                 .enable_reg = 0x57024,
3530                 .enable_mask = BIT(0),
3531                 .hw.init = &(struct clk_init_data){
3532                         .name = "gcc_qpic_ahb_clk",
3533                         .parent_hws = (const struct clk_hw *[]){
3534                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3535                         .num_parents = 1,
3536                         .flags = CLK_SET_RATE_PARENT,
3537                         .ops = &clk_branch2_ops,
3538                 },
3539         },
3540 };
3541
3542 static struct clk_branch gcc_qpic_clk = {
3543         .halt_reg = 0x57020,
3544         .clkr = {
3545                 .enable_reg = 0x57020,
3546                 .enable_mask = BIT(0),
3547                 .hw.init = &(struct clk_init_data){
3548                         .name = "gcc_qpic_clk",
3549                         .parent_hws = (const struct clk_hw *[]){
3550                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3551                         .num_parents = 1,
3552                         .flags = CLK_SET_RATE_PARENT,
3553                         .ops = &clk_branch2_ops,
3554                 },
3555         },
3556 };
3557
3558 static struct clk_branch gcc_sdcc1_ahb_clk = {
3559         .halt_reg = 0x4201c,
3560         .clkr = {
3561                 .enable_reg = 0x4201c,
3562                 .enable_mask = BIT(0),
3563                 .hw.init = &(struct clk_init_data){
3564                         .name = "gcc_sdcc1_ahb_clk",
3565                         .parent_hws = (const struct clk_hw *[]){
3566                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3567                         .num_parents = 1,
3568                         .flags = CLK_SET_RATE_PARENT,
3569                         .ops = &clk_branch2_ops,
3570                 },
3571         },
3572 };
3573
3574 static struct clk_branch gcc_sdcc1_apps_clk = {
3575         .halt_reg = 0x42018,
3576         .clkr = {
3577                 .enable_reg = 0x42018,
3578                 .enable_mask = BIT(0),
3579                 .hw.init = &(struct clk_init_data){
3580                         .name = "gcc_sdcc1_apps_clk",
3581                         .parent_hws = (const struct clk_hw *[]){
3582                                         &sdcc1_apps_clk_src.clkr.hw },
3583                         .num_parents = 1,
3584                         .flags = CLK_SET_RATE_PARENT,
3585                         .ops = &clk_branch2_ops,
3586                 },
3587         },
3588 };
3589
3590 static struct clk_branch gcc_uniphy0_ahb_clk = {
3591         .halt_reg = 0x56008,
3592         .clkr = {
3593                 .enable_reg = 0x56008,
3594                 .enable_mask = BIT(0),
3595                 .hw.init = &(struct clk_init_data){
3596                         .name = "gcc_uniphy0_ahb_clk",
3597                         .parent_hws = (const struct clk_hw *[]){
3598                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3599                         .num_parents = 1,
3600                         .flags = CLK_SET_RATE_PARENT,
3601                         .ops = &clk_branch2_ops,
3602                 },
3603         },
3604 };
3605
3606 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3607         .halt_reg = 0x56010,
3608         .clkr = {
3609                 .enable_reg = 0x56010,
3610                 .enable_mask = BIT(0),
3611                 .hw.init = &(struct clk_init_data){
3612                         .name = "gcc_uniphy0_port1_rx_clk",
3613                         .parent_hws = (const struct clk_hw *[]){
3614                                         &nss_port1_rx_div_clk_src.clkr.hw },
3615                         .num_parents = 1,
3616                         .flags = CLK_SET_RATE_PARENT,
3617                         .ops = &clk_branch2_ops,
3618                 },
3619         },
3620 };
3621
3622 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3623         .halt_reg = 0x56014,
3624         .clkr = {
3625                 .enable_reg = 0x56014,
3626                 .enable_mask = BIT(0),
3627                 .hw.init = &(struct clk_init_data){
3628                         .name = "gcc_uniphy0_port1_tx_clk",
3629                         .parent_hws = (const struct clk_hw *[]){
3630                                         &nss_port1_tx_div_clk_src.clkr.hw },
3631                         .num_parents = 1,
3632                         .flags = CLK_SET_RATE_PARENT,
3633                         .ops = &clk_branch2_ops,
3634                 },
3635         },
3636 };
3637
3638 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3639         .halt_reg = 0x56018,
3640         .clkr = {
3641                 .enable_reg = 0x56018,
3642                 .enable_mask = BIT(0),
3643                 .hw.init = &(struct clk_init_data){
3644                         .name = "gcc_uniphy0_port2_rx_clk",
3645                         .parent_hws = (const struct clk_hw *[]){
3646                                         &nss_port2_rx_div_clk_src.clkr.hw },
3647                         .num_parents = 1,
3648                         .flags = CLK_SET_RATE_PARENT,
3649                         .ops = &clk_branch2_ops,
3650                 },
3651         },
3652 };
3653
3654 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3655         .halt_reg = 0x5601c,
3656         .clkr = {
3657                 .enable_reg = 0x5601c,
3658                 .enable_mask = BIT(0),
3659                 .hw.init = &(struct clk_init_data){
3660                         .name = "gcc_uniphy0_port2_tx_clk",
3661                         .parent_hws = (const struct clk_hw *[]){
3662                                         &nss_port2_tx_div_clk_src.clkr.hw },
3663                         .num_parents = 1,
3664                         .flags = CLK_SET_RATE_PARENT,
3665                         .ops = &clk_branch2_ops,
3666                 },
3667         },
3668 };
3669
3670 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3671         .halt_reg = 0x56020,
3672         .clkr = {
3673                 .enable_reg = 0x56020,
3674                 .enable_mask = BIT(0),
3675                 .hw.init = &(struct clk_init_data){
3676                         .name = "gcc_uniphy0_port3_rx_clk",
3677                         .parent_hws = (const struct clk_hw *[]){
3678                                         &nss_port3_rx_div_clk_src.clkr.hw },
3679                         .num_parents = 1,
3680                         .flags = CLK_SET_RATE_PARENT,
3681                         .ops = &clk_branch2_ops,
3682                 },
3683         },
3684 };
3685
3686 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3687         .halt_reg = 0x56024,
3688         .clkr = {
3689                 .enable_reg = 0x56024,
3690                 .enable_mask = BIT(0),
3691                 .hw.init = &(struct clk_init_data){
3692                         .name = "gcc_uniphy0_port3_tx_clk",
3693                         .parent_hws = (const struct clk_hw *[]){
3694                                         &nss_port3_tx_div_clk_src.clkr.hw },
3695                         .num_parents = 1,
3696                         .flags = CLK_SET_RATE_PARENT,
3697                         .ops = &clk_branch2_ops,
3698                 },
3699         },
3700 };
3701
3702 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3703         .halt_reg = 0x56028,
3704         .clkr = {
3705                 .enable_reg = 0x56028,
3706                 .enable_mask = BIT(0),
3707                 .hw.init = &(struct clk_init_data){
3708                         .name = "gcc_uniphy0_port4_rx_clk",
3709                         .parent_hws = (const struct clk_hw *[]){
3710                                         &nss_port4_rx_div_clk_src.clkr.hw },
3711                         .num_parents = 1,
3712                         .flags = CLK_SET_RATE_PARENT,
3713                         .ops = &clk_branch2_ops,
3714                 },
3715         },
3716 };
3717
3718 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3719         .halt_reg = 0x5602c,
3720         .clkr = {
3721                 .enable_reg = 0x5602c,
3722                 .enable_mask = BIT(0),
3723                 .hw.init = &(struct clk_init_data){
3724                         .name = "gcc_uniphy0_port4_tx_clk",
3725                         .parent_hws = (const struct clk_hw *[]){
3726                                         &nss_port4_tx_div_clk_src.clkr.hw },
3727                         .num_parents = 1,
3728                         .flags = CLK_SET_RATE_PARENT,
3729                         .ops = &clk_branch2_ops,
3730                 },
3731         },
3732 };
3733
3734 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
3735         .halt_reg = 0x56030,
3736         .clkr = {
3737                 .enable_reg = 0x56030,
3738                 .enable_mask = BIT(0),
3739                 .hw.init = &(struct clk_init_data){
3740                         .name = "gcc_uniphy0_port5_rx_clk",
3741                         .parent_hws = (const struct clk_hw *[]){
3742                                         &nss_port5_rx_div_clk_src.clkr.hw },
3743                         .num_parents = 1,
3744                         .flags = CLK_SET_RATE_PARENT,
3745                         .ops = &clk_branch2_ops,
3746                 },
3747         },
3748 };
3749
3750 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
3751         .halt_reg = 0x56034,
3752         .clkr = {
3753                 .enable_reg = 0x56034,
3754                 .enable_mask = BIT(0),
3755                 .hw.init = &(struct clk_init_data){
3756                         .name = "gcc_uniphy0_port5_tx_clk",
3757                         .parent_hws = (const struct clk_hw *[]){
3758                                         &nss_port5_tx_div_clk_src.clkr.hw },
3759                         .num_parents = 1,
3760                         .flags = CLK_SET_RATE_PARENT,
3761                         .ops = &clk_branch2_ops,
3762                 },
3763         },
3764 };
3765
3766 static struct clk_branch gcc_uniphy0_sys_clk = {
3767         .halt_reg = 0x5600C,
3768         .clkr = {
3769                 .enable_reg = 0x5600C,
3770                 .enable_mask = BIT(0),
3771                 .hw.init = &(struct clk_init_data){
3772                         .name = "gcc_uniphy0_sys_clk",
3773                         .parent_hws = (const struct clk_hw *[]){
3774                                         &gcc_xo_clk_src.clkr.hw },
3775                         .num_parents = 1,
3776                         .flags = CLK_SET_RATE_PARENT,
3777                         .ops = &clk_branch2_ops,
3778                 },
3779         },
3780 };
3781
3782 static struct clk_branch gcc_uniphy1_ahb_clk = {
3783         .halt_reg = 0x56108,
3784         .clkr = {
3785                 .enable_reg = 0x56108,
3786                 .enable_mask = BIT(0),
3787                 .hw.init = &(struct clk_init_data){
3788                         .name = "gcc_uniphy1_ahb_clk",
3789                         .parent_hws = (const struct clk_hw *[]){
3790                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3791                         .num_parents = 1,
3792                         .flags = CLK_SET_RATE_PARENT,
3793                         .ops = &clk_branch2_ops,
3794                 },
3795         },
3796 };
3797
3798 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
3799         .halt_reg = 0x56110,
3800         .clkr = {
3801                 .enable_reg = 0x56110,
3802                 .enable_mask = BIT(0),
3803                 .hw.init = &(struct clk_init_data){
3804                         .name = "gcc_uniphy1_port5_rx_clk",
3805                         .parent_hws = (const struct clk_hw *[]){
3806                                         &nss_port5_rx_div_clk_src.clkr.hw },
3807                         .num_parents = 1,
3808                         .flags = CLK_SET_RATE_PARENT,
3809                         .ops = &clk_branch2_ops,
3810                 },
3811         },
3812 };
3813
3814 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
3815         .halt_reg = 0x56114,
3816         .clkr = {
3817                 .enable_reg = 0x56114,
3818                 .enable_mask = BIT(0),
3819                 .hw.init = &(struct clk_init_data){
3820                         .name = "gcc_uniphy1_port5_tx_clk",
3821                         .parent_hws = (const struct clk_hw *[]){
3822                                         &nss_port5_tx_div_clk_src.clkr.hw },
3823                         .num_parents = 1,
3824                         .flags = CLK_SET_RATE_PARENT,
3825                         .ops = &clk_branch2_ops,
3826                 },
3827         },
3828 };
3829
3830 static struct clk_branch gcc_uniphy1_sys_clk = {
3831         .halt_reg = 0x5610C,
3832         .clkr = {
3833                 .enable_reg = 0x5610C,
3834                 .enable_mask = BIT(0),
3835                 .hw.init = &(struct clk_init_data){
3836                         .name = "gcc_uniphy1_sys_clk",
3837                         .parent_hws = (const struct clk_hw *[]){
3838                                         &gcc_xo_clk_src.clkr.hw },
3839                         .num_parents = 1,
3840                         .flags = CLK_SET_RATE_PARENT,
3841                         .ops = &clk_branch2_ops,
3842                 },
3843         },
3844 };
3845
3846 static struct clk_branch gcc_usb0_aux_clk = {
3847         .halt_reg = 0x3e044,
3848         .clkr = {
3849                 .enable_reg = 0x3e044,
3850                 .enable_mask = BIT(0),
3851                 .hw.init = &(struct clk_init_data){
3852                         .name = "gcc_usb0_aux_clk",
3853                         .parent_hws = (const struct clk_hw *[]){
3854                                         &usb0_aux_clk_src.clkr.hw },
3855                         .num_parents = 1,
3856                         .flags = CLK_SET_RATE_PARENT,
3857                         .ops = &clk_branch2_ops,
3858                 },
3859         },
3860 };
3861
3862 static struct clk_branch gcc_usb0_master_clk = {
3863         .halt_reg = 0x3e000,
3864         .clkr = {
3865                 .enable_reg = 0x3e000,
3866                 .enable_mask = BIT(0),
3867                 .hw.init = &(struct clk_init_data){
3868                         .name = "gcc_usb0_master_clk",
3869                         .parent_hws = (const struct clk_hw *[]){
3870                                         &usb0_master_clk_src.clkr.hw },
3871                         .num_parents = 1,
3872                         .flags = CLK_SET_RATE_PARENT,
3873                         .ops = &clk_branch2_ops,
3874                 },
3875         },
3876 };
3877
3878 static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
3879         .halt_reg = 0x47014,
3880         .clkr = {
3881                 .enable_reg = 0x47014,
3882                 .enable_mask = BIT(0),
3883                 .hw.init = &(struct clk_init_data){
3884                         .name = "gcc_snoc_bus_timeout2_ahb_clk",
3885                         .parent_hws = (const struct clk_hw *[]){
3886                                         &usb0_master_clk_src.clkr.hw },
3887                         .num_parents = 1,
3888                         .flags = CLK_SET_RATE_PARENT,
3889                         .ops = &clk_branch2_ops,
3890                 },
3891         },
3892 };
3893
3894 static struct clk_rcg2 pcie0_rchng_clk_src = {
3895         .cmd_rcgr = 0x75070,
3896         .freq_tbl = ftbl_pcie_rchng_clk_src,
3897         .hid_width = 5,
3898         .parent_map = gcc_xo_gpll0_map,
3899         .clkr.hw.init = &(struct clk_init_data){
3900                 .name = "pcie0_rchng_clk_src",
3901                 .parent_data = gcc_xo_gpll0,
3902                 .num_parents = 2,
3903                 .ops = &clk_rcg2_ops,
3904         },
3905 };
3906
3907 static struct clk_branch gcc_pcie0_rchng_clk = {
3908         .halt_reg = 0x75070,
3909         .clkr = {
3910                 .enable_reg = 0x75070,
3911                 .enable_mask = BIT(1),
3912                 .hw.init = &(struct clk_init_data){
3913                         .name = "gcc_pcie0_rchng_clk",
3914                         .parent_hws = (const struct clk_hw *[]){
3915                                         &pcie0_rchng_clk_src.clkr.hw },
3916                         .num_parents = 1,
3917                         .flags = CLK_SET_RATE_PARENT,
3918                         .ops = &clk_branch2_ops,
3919                 },
3920         },
3921 };
3922
3923 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
3924         .halt_reg = 0x75048,
3925         .clkr = {
3926                 .enable_reg = 0x75048,
3927                 .enable_mask = BIT(0),
3928                 .hw.init = &(struct clk_init_data){
3929                         .name = "gcc_pcie0_axi_s_bridge_clk",
3930                         .parent_hws = (const struct clk_hw *[]){
3931                                         &pcie0_axi_clk_src.clkr.hw },
3932                         .num_parents = 1,
3933                         .flags = CLK_SET_RATE_PARENT,
3934                         .ops = &clk_branch2_ops,
3935                 },
3936         },
3937 };
3938
3939 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
3940         .halt_reg = 0x26040,
3941         .clkr = {
3942                 .enable_reg = 0x26040,
3943                 .enable_mask = BIT(0),
3944                 .hw.init = &(struct clk_init_data){
3945                         .name = "gcc_sys_noc_usb0_axi_clk",
3946                         .parent_hws = (const struct clk_hw *[]){
3947                                         &usb0_master_clk_src.clkr.hw },
3948                         .num_parents = 1,
3949                         .flags = CLK_SET_RATE_PARENT,
3950                         .ops = &clk_branch2_ops,
3951                 },
3952         },
3953 };
3954
3955 static struct clk_branch gcc_usb0_mock_utmi_clk = {
3956         .halt_reg = 0x3e008,
3957         .clkr = {
3958                 .enable_reg = 0x3e008,
3959                 .enable_mask = BIT(0),
3960                 .hw.init = &(struct clk_init_data){
3961                         .name = "gcc_usb0_mock_utmi_clk",
3962                         .parent_hws = (const struct clk_hw *[]){
3963                                         &usb0_mock_utmi_clk_src.clkr.hw },
3964                         .num_parents = 1,
3965                         .flags = CLK_SET_RATE_PARENT,
3966                         .ops = &clk_branch2_ops,
3967                 },
3968         },
3969 };
3970
3971 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3972         .halt_reg = 0x3e080,
3973         .clkr = {
3974                 .enable_reg = 0x3e080,
3975                 .enable_mask = BIT(0),
3976                 .hw.init = &(struct clk_init_data){
3977                         .name = "gcc_usb0_phy_cfg_ahb_clk",
3978                         .parent_hws = (const struct clk_hw *[]){
3979                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3980                         .num_parents = 1,
3981                         .flags = CLK_SET_RATE_PARENT,
3982                         .ops = &clk_branch2_ops,
3983                 },
3984         },
3985 };
3986
3987 static struct clk_branch gcc_usb0_pipe_clk = {
3988         .halt_reg = 0x3e040,
3989         .halt_check = BRANCH_HALT_DELAY,
3990         .clkr = {
3991                 .enable_reg = 0x3e040,
3992                 .enable_mask = BIT(0),
3993                 .hw.init = &(struct clk_init_data){
3994                         .name = "gcc_usb0_pipe_clk",
3995                         .parent_hws = (const struct clk_hw *[]){
3996                                         &usb0_pipe_clk_src.clkr.hw },
3997                         .num_parents = 1,
3998                         .flags = CLK_SET_RATE_PARENT,
3999                         .ops = &clk_branch2_ops,
4000                 },
4001         },
4002 };
4003
4004 static struct clk_branch gcc_usb0_sleep_clk = {
4005         .halt_reg = 0x3e004,
4006         .clkr = {
4007                 .enable_reg = 0x3e004,
4008                 .enable_mask = BIT(0),
4009                 .hw.init = &(struct clk_init_data){
4010                         .name = "gcc_usb0_sleep_clk",
4011                         .parent_hws = (const struct clk_hw *[]){
4012                                         &gcc_sleep_clk_src.clkr.hw },
4013                         .num_parents = 1,
4014                         .flags = CLK_SET_RATE_PARENT,
4015                         .ops = &clk_branch2_ops,
4016                 },
4017         },
4018 };
4019
4020 static struct clk_branch gcc_usb1_master_clk = {
4021         .halt_reg = 0x3f000,
4022         .clkr = {
4023                 .enable_reg = 0x3f000,
4024                 .enable_mask = BIT(0),
4025                 .hw.init = &(struct clk_init_data){
4026                         .name = "gcc_usb1_master_clk",
4027                         .parent_hws = (const struct clk_hw *[]){
4028                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4029                         .num_parents = 1,
4030                         .flags = CLK_SET_RATE_PARENT,
4031                         .ops = &clk_branch2_ops,
4032                 },
4033         },
4034 };
4035
4036 static struct clk_branch gcc_usb1_mock_utmi_clk = {
4037         .halt_reg = 0x3f008,
4038         .clkr = {
4039                 .enable_reg = 0x3f008,
4040                 .enable_mask = BIT(0),
4041                 .hw.init = &(struct clk_init_data){
4042                         .name = "gcc_usb1_mock_utmi_clk",
4043                         .parent_hws = (const struct clk_hw *[]){
4044                                         &usb1_mock_utmi_clk_src.clkr.hw },
4045                         .num_parents = 1,
4046                         .flags = CLK_SET_RATE_PARENT,
4047                         .ops = &clk_branch2_ops,
4048                 },
4049         },
4050 };
4051
4052 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
4053         .halt_reg = 0x3f080,
4054         .clkr = {
4055                 .enable_reg = 0x3f080,
4056                 .enable_mask = BIT(0),
4057                 .hw.init = &(struct clk_init_data){
4058                         .name = "gcc_usb1_phy_cfg_ahb_clk",
4059                         .parent_hws = (const struct clk_hw *[]){
4060                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4061                         .num_parents = 1,
4062                         .flags = CLK_SET_RATE_PARENT,
4063                         .ops = &clk_branch2_ops,
4064                 },
4065         },
4066 };
4067
4068 static struct clk_branch gcc_usb1_sleep_clk = {
4069         .halt_reg = 0x3f004,
4070         .clkr = {
4071                 .enable_reg = 0x3f004,
4072                 .enable_mask = BIT(0),
4073                 .hw.init = &(struct clk_init_data){
4074                         .name = "gcc_usb1_sleep_clk",
4075                         .parent_hws = (const struct clk_hw *[]){
4076                                         &gcc_sleep_clk_src.clkr.hw },
4077                         .num_parents = 1,
4078                         .flags = CLK_SET_RATE_PARENT,
4079                         .ops = &clk_branch2_ops,
4080                 },
4081         },
4082 };
4083
4084 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
4085         .halt_reg = 0x56308,
4086         .clkr = {
4087                 .enable_reg = 0x56308,
4088                 .enable_mask = BIT(0),
4089                 .hw.init = &(struct clk_init_data){
4090                         .name = "gcc_cmn_12gpll_ahb_clk",
4091                         .parent_hws = (const struct clk_hw *[]){
4092                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4093                         .num_parents = 1,
4094                         .flags = CLK_SET_RATE_PARENT,
4095                         .ops = &clk_branch2_ops,
4096                 },
4097         },
4098 };
4099
4100 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
4101         .halt_reg = 0x5630c,
4102         .clkr = {
4103                 .enable_reg = 0x5630c,
4104                 .enable_mask = BIT(0),
4105                 .hw.init = &(struct clk_init_data){
4106                         .name = "gcc_cmn_12gpll_sys_clk",
4107                         .parent_hws = (const struct clk_hw *[]){
4108                                         &gcc_xo_clk_src.clkr.hw },
4109                         .num_parents = 1,
4110                         .flags = CLK_SET_RATE_PARENT,
4111                         .ops = &clk_branch2_ops,
4112                 },
4113         },
4114 };
4115
4116 static struct clk_branch gcc_sdcc1_ice_core_clk = {
4117         .halt_reg = 0x5d014,
4118         .clkr = {
4119                 .enable_reg = 0x5d014,
4120                 .enable_mask = BIT(0),
4121                 .hw.init = &(struct clk_init_data){
4122                         .name = "gcc_sdcc1_ice_core_clk",
4123                         .parent_hws = (const struct clk_hw *[]){
4124                                         &sdcc1_ice_core_clk_src.clkr.hw },
4125                         .num_parents = 1,
4126                         .flags = CLK_SET_RATE_PARENT,
4127                         .ops = &clk_branch2_ops,
4128                 },
4129         },
4130 };
4131
4132 static struct clk_branch gcc_dcc_clk = {
4133         .halt_reg = 0x77004,
4134         .clkr = {
4135                 .enable_reg = 0x77004,
4136                 .enable_mask = BIT(0),
4137                 .hw.init = &(struct clk_init_data){
4138                         .name = "gcc_dcc_clk",
4139                         .parent_hws = (const struct clk_hw *[]){
4140                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4141                         .num_parents = 1,
4142                         .flags = CLK_SET_RATE_PARENT,
4143                         .ops = &clk_branch2_ops,
4144                 },
4145         },
4146 };
4147
4148 static const struct alpha_pll_config ubi32_pll_config = {
4149         .l = 0x3e,
4150         .alpha = 0x57,
4151         .config_ctl_val = 0x240d6aa8,
4152         .config_ctl_hi_val = 0x3c2,
4153         .main_output_mask = BIT(0),
4154         .aux_output_mask = BIT(1),
4155         .pre_div_val = 0x0,
4156         .pre_div_mask = BIT(12),
4157         .post_div_val = 0x0,
4158         .post_div_mask = GENMASK(9, 8),
4159 };
4160
4161 static const struct alpha_pll_config nss_crypto_pll_config = {
4162         .l = 0x32,
4163         .alpha = 0x0,
4164         .alpha_hi = 0x0,
4165         .config_ctl_val = 0x4001055b,
4166         .main_output_mask = BIT(0),
4167         .pre_div_val = 0x0,
4168         .pre_div_mask = GENMASK(14, 12),
4169         .post_div_val = 0x1 << 8,
4170         .post_div_mask = GENMASK(11, 8),
4171         .vco_mask = GENMASK(21, 20),
4172         .vco_val = 0x0,
4173         .alpha_en_mask = BIT(24),
4174 };
4175
4176 static struct clk_hw *gcc_ipq6018_hws[] = {
4177         &gpll0_out_main_div2.hw,
4178         &gcc_xo_div4_clk_src.hw,
4179         &nss_ppe_cdiv_clk_src.hw,
4180         &gpll6_out_main_div2.hw,
4181         &qdss_dap_sync_clk_src.hw,
4182         &qdss_tsctr_div2_clk_src.hw,
4183 };
4184
4185 static struct clk_regmap *gcc_ipq6018_clks[] = {
4186         [GPLL0_MAIN] = &gpll0_main.clkr,
4187         [GPLL0] = &gpll0.clkr,
4188         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4189         [UBI32_PLL] = &ubi32_pll.clkr,
4190         [GPLL6_MAIN] = &gpll6_main.clkr,
4191         [GPLL6] = &gpll6.clkr,
4192         [GPLL4_MAIN] = &gpll4_main.clkr,
4193         [GPLL4] = &gpll4.clkr,
4194         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4195         [GPLL2_MAIN] = &gpll2_main.clkr,
4196         [GPLL2] = &gpll2.clkr,
4197         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4198         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4199         [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4200         [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4201         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4202         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4203         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4204         [SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
4205         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4206         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4207         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4208         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4209         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4210         [UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
4211         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4212         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4213         [APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
4214         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4215         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4216         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4217         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4218         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4219         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4220         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4221         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4222         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4223         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4224         [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4225         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4226         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4227         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4228         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4229         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4230         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4231         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4232         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4233         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4234         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4235         [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4236         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4237         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4238         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4239         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4240         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4241         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4242         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4243         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4244         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4245         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4246         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4247         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4248         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4249         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4250         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4251         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4252         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4253         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4254         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4255         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4256         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4257         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4258         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4259         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4260         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4261         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4262         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4263         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4264         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4265         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4266         [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4267         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4268         [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4269         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4270         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4271         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4272         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4273         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4274         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4275         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4276         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4277         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4278         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4279         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4280         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4281         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4282         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4283         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4284         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4285         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4286         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4287         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4288         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4289         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4290         [GCC_XO_CLK] = &gcc_xo_clk.clkr,
4291         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4292         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4293         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4294         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4295         [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4296         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4297         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4298         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4299         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4300         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4301         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4302         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4303         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4304         [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
4305         [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
4306         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4307         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4308         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4309         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4310         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4311         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4312         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4313         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4314         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4315         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4316         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4317         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4318         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4319         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4320         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4321         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4322         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4323         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4324         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4325         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4326         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4327         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4328         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4329         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4330         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4331         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4332         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4333         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4334         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4335         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4336         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4337         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4338         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4339         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4340         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4341         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4342         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4343         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4344         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4345         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4346         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4347         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4348         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4349         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4350         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4351         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4352         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4353         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4354         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4355         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4356         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4357         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4358         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4359         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4360         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4361         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4362         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4363         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4364         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4365         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4366         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4367         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4368         [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
4369         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4370         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4371         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4372         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4373         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4374         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4375         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4376         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4377         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4378         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4379         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4380         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4381         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4382         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4383         [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4384         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4385         [PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4386         [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4387         [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4388         [RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
4389         [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
4390         [LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
4391         [GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
4392         [LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
4393         [GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
4394         [LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
4395         [GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
4396         [GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
4397         [GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
4398         [GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
4399         [GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
4400         [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
4401         [GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
4402         [GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
4403         [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
4404         [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4405         [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4406 };
4407
4408 static const struct qcom_reset_map gcc_ipq6018_resets[] = {
4409         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4410         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4411         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4412         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4413         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4414         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4415         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4416         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4417         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4418         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4419         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4420         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4421         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4422         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4423         [GCC_SMMU_BCR] = { 0x12000, 0 },
4424         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4425         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4426         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4427         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4428         [GCC_PRNG_BCR] = { 0x13000, 0 },
4429         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4430         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4431         [GCC_WCSS_BCR] = { 0x18000, 0 },
4432         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4433         [GCC_NSS_BCR] = { 0x19000, 0 },
4434         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4435         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4436         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4437         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4438         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4439         [GCC_TCSR_BCR] = { 0x28000, 0 },
4440         [GCC_QDSS_BCR] = { 0x29000, 0 },
4441         [GCC_DCD_BCR] = { 0x2a000, 0 },
4442         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4443         [GCC_MPM_BCR] = { 0x2c000, 0 },
4444         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4445         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4446         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4447         [GCC_TLMM_BCR] = { 0x34000, 0 },
4448         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4449         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4450         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4451         [GCC_USB0_BCR] = { 0x3e070, 0 },
4452         [GCC_USB1_BCR] = { 0x3f070, 0 },
4453         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4454         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4455         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4456         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4457         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4458         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4459         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4460         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4461         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4462         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4463         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4464         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4465         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4466         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4467         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4468         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4469         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4470         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4471         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4472         [GCC_QPIC_BCR] = { 0x57018, 0 },
4473         [GCC_MDIO_BCR] = { 0x58000, 0 },
4474         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4475         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4476         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4477         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4478         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4479         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4480         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4481         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4482         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4483         [GCC_DCC_BCR] = { 0x77000, 0 },
4484         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4485         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4486         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4487         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4488         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4489         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4490         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4491         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4492         [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4493         [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4494         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4495         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4496         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4497         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4498         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4499         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4500         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4501         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4502         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4503         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4504         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4505         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4506         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4507         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4508         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4509         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4510         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4511         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4512         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4513         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4514         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4515         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4516         [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4517         [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4518         [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4519         [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4520         [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4521         [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4522         [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4523         [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4524         [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4525         [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4526         [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4527         [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4528         [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4529         [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4530         [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4531         [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4532         [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4533         [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4534         [GCC_LPASS_BCR] = {0x1F000, 0},
4535         [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4536         [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4537         [GCC_WCSSAON_RESET] = {0x59010, 0},
4538         [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4539         [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4540         [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4541         [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4542         [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4543         [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4544         [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4545         [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4546         [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4547         [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4548         [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4549         [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4550         [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4551         [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4552         [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4553         [GCC_Q6_AHB_ARES] = {0x59110, 2},
4554         [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4555         [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4556 };
4557
4558 static const struct of_device_id gcc_ipq6018_match_table[] = {
4559         { .compatible = "qcom,gcc-ipq6018" },
4560         { }
4561 };
4562 MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
4563
4564 static const struct regmap_config gcc_ipq6018_regmap_config = {
4565         .reg_bits       = 32,
4566         .reg_stride     = 4,
4567         .val_bits       = 32,
4568         .max_register   = 0x7fffc,
4569         .fast_io        = true,
4570 };
4571
4572 static const struct qcom_cc_desc gcc_ipq6018_desc = {
4573         .config = &gcc_ipq6018_regmap_config,
4574         .clks = gcc_ipq6018_clks,
4575         .num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
4576         .resets = gcc_ipq6018_resets,
4577         .num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
4578         .clk_hws = gcc_ipq6018_hws,
4579         .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
4580 };
4581
4582 static int gcc_ipq6018_probe(struct platform_device *pdev)
4583 {
4584         struct regmap *regmap;
4585
4586         regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
4587         if (IS_ERR(regmap))
4588                 return PTR_ERR(regmap);
4589
4590         /* Disable SW_COLLAPSE for USB0 GDSCR */
4591         regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
4592         /* Enable SW_OVERRIDE for USB0 GDSCR */
4593         regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
4594         /* Disable SW_COLLAPSE for USB1 GDSCR */
4595         regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
4596         /* Enable SW_OVERRIDE for USB1 GDSCR */
4597         regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
4598
4599         /* SW Workaround for UBI Huyara PLL */
4600         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4601
4602         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4603
4604         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4605                                 &nss_crypto_pll_config);
4606
4607         return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
4608 }
4609
4610 static struct platform_driver gcc_ipq6018_driver = {
4611         .probe = gcc_ipq6018_probe,
4612         .driver = {
4613                 .name   = "qcom,gcc-ipq6018",
4614                 .of_match_table = gcc_ipq6018_match_table,
4615         },
4616 };
4617
4618 static int __init gcc_ipq6018_init(void)
4619 {
4620         return platform_driver_register(&gcc_ipq6018_driver);
4621 }
4622 core_initcall(gcc_ipq6018_init);
4623
4624 static void __exit gcc_ipq6018_exit(void)
4625 {
4626         platform_driver_unregister(&gcc_ipq6018_driver);
4627 }
4628 module_exit(gcc_ipq6018_exit);
4629
4630 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
4631 MODULE_LICENSE("GPL v2");