drivers/clk/qcom/dispcc-sm8250.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/regmap.h>
  11 #include <linux/reset-controller.h>
  12
  13 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
  14
  15 #include "clk-alpha-pll.h"
  16 #include "clk-branch.h"
  17 #include "clk-rcg.h"
  18 #include "clk-regmap-divider.h"
  19 #include "common.h"
  20 #include "gdsc.h"
  21 #include "reset.h"
  22
  23 enum {
  24         P_BI_TCXO,
  25         P_DISP_CC_PLL0_OUT_MAIN,
  26         P_DISP_CC_PLL1_OUT_EVEN,
  27         P_DISP_CC_PLL1_OUT_MAIN,
  28         P_DP_PHY_PLL_LINK_CLK,
  29         P_DP_PHY_PLL_VCO_DIV_CLK,
  30         P_DPTX1_PHY_PLL_LINK_CLK,
  31         P_DPTX1_PHY_PLL_VCO_DIV_CLK,
  32         P_DPTX2_PHY_PLL_LINK_CLK,
  33         P_DPTX2_PHY_PLL_VCO_DIV_CLK,
  34         P_EDP_PHY_PLL_LINK_CLK,
  35         P_EDP_PHY_PLL_VCO_DIV_CLK,
  36         P_DSI0_PHY_PLL_OUT_BYTECLK,
  37         P_DSI0_PHY_PLL_OUT_DSICLK,
  38         P_DSI1_PHY_PLL_OUT_BYTECLK,
  39         P_DSI1_PHY_PLL_OUT_DSICLK,
  40 };
  41
  42 static struct pll_vco vco_table[] = {
  43         { 249600000, 2000000000, 0 },
  44 };
  45
  46 static struct pll_vco lucid_5lpe_vco[] = {
  47         { 249600000, 1750000000, 0 },
  48 };
  49
  50 static struct alpha_pll_config disp_cc_pll0_config = {
  51         .l = 0x47,
  52         .alpha = 0xE000,
  53         .config_ctl_val = 0x20485699,
  54         .config_ctl_hi_val = 0x00002261,
  55         .config_ctl_hi1_val = 0x329A699C,
  56         .user_ctl_val = 0x00000000,
  57         .user_ctl_hi_val = 0x00000805,
  58         .user_ctl_hi1_val = 0x00000000,
  59 };
  60
  61 static struct clk_init_data disp_cc_pll0_init = {
  62         .name = "disp_cc_pll0",
  63         .parent_data = &(const struct clk_parent_data){
  64                 .fw_name = "bi_tcxo",
  65         },
  66         .num_parents = 1,
  67         .ops = &clk_alpha_pll_lucid_ops,
  68 };
  69
  70 static struct clk_alpha_pll disp_cc_pll0 = {
  71         .offset = 0x0,
  72         .vco_table = vco_table,
  73         .num_vco = ARRAY_SIZE(vco_table),
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  75         .clkr.hw.init = &disp_cc_pll0_init
  76 };
  77
  78 static struct alpha_pll_config disp_cc_pll1_config = {
  79         .l = 0x1F,
  80         .alpha = 0x4000,
  81         .config_ctl_val = 0x20485699,
  82         .config_ctl_hi_val = 0x00002261,
  83         .config_ctl_hi1_val = 0x329A699C,
  84         .user_ctl_val = 0x00000000,
  85         .user_ctl_hi_val = 0x00000805,
  86         .user_ctl_hi1_val = 0x00000000,
  87 };
  88
  89 static struct clk_init_data disp_cc_pll1_init = {
  90         .name = "disp_cc_pll1",
  91         .parent_data = &(const struct clk_parent_data){
  92                 .fw_name = "bi_tcxo",
  93         },
  94         .num_parents = 1,
  95         .ops = &clk_alpha_pll_lucid_ops,
  96 };
  97
  98 static struct clk_alpha_pll disp_cc_pll1 = {
  99         .offset = 0x1000,
 100         .vco_table = vco_table,
 101         .num_vco = ARRAY_SIZE(vco_table),
 102         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 103         .clkr.hw.init = &disp_cc_pll1_init
 104 };
 105
 106 static const struct parent_map disp_cc_parent_map_0[] = {
 107         { P_BI_TCXO, 0 },
 108         { P_DP_PHY_PLL_LINK_CLK, 1 },
 109         { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
 110         { P_DPTX1_PHY_PLL_LINK_CLK, 3 },
 111         { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
 112         { P_DPTX2_PHY_PLL_LINK_CLK, 5 },
 113         { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
 114 };
 115
 116 static const struct clk_parent_data disp_cc_parent_data_0[] = {
 117         { .fw_name = "bi_tcxo" },
 118         { .fw_name = "dp_phy_pll_link_clk" },
 119         { .fw_name = "dp_phy_pll_vco_div_clk" },
 120         { .fw_name = "dptx1_phy_pll_link_clk" },
 121         { .fw_name = "dptx1_phy_pll_vco_div_clk" },
 122         { .fw_name = "dptx2_phy_pll_link_clk" },
 123         { .fw_name = "dptx2_phy_pll_vco_div_clk" },
 124 };
 125
 126 static const struct parent_map disp_cc_parent_map_1[] = {
 127         { P_BI_TCXO, 0 },
 128 };
 129
 130 static const struct clk_parent_data disp_cc_parent_data_1[] = {
 131         { .fw_name = "bi_tcxo" },
 132 };
 133
 134 static const struct parent_map disp_cc_parent_map_2[] = {
 135         { P_BI_TCXO, 0 },
 136         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 137         { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
 138 };
 139
 140 static const struct clk_parent_data disp_cc_parent_data_2[] = {
 141         { .fw_name = "bi_tcxo" },
 142         { .fw_name = "dsi0_phy_pll_out_byteclk" },
 143         { .fw_name = "dsi1_phy_pll_out_byteclk" },
 144 };
 145
 146 static const struct parent_map disp_cc_parent_map_3[] = {
 147         { P_BI_TCXO, 0 },
 148         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 149 };
 150
 151 static const struct clk_parent_data disp_cc_parent_data_3[] = {
 152         { .fw_name = "bi_tcxo" },
 153         { .hw = &disp_cc_pll1.clkr.hw },
 154 };
 155
 156 static const struct parent_map disp_cc_parent_map_4[] = {
 157         { P_BI_TCXO, 0 },
 158         { P_EDP_PHY_PLL_LINK_CLK, 1 },
 159         { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
 160 };
 161
 162 static const struct clk_parent_data disp_cc_parent_data_4[] = {
 163         { .fw_name = "bi_tcxo" },
 164         { .fw_name = "edp_phy_pll_link_clk" },
 165         { .fw_name = "edp_phy_pll_vco_div_clk" },
 166 };
 167
 168 static const struct parent_map disp_cc_parent_map_5[] = {
 169         { P_BI_TCXO, 0 },
 170         { P_DISP_CC_PLL0_OUT_MAIN, 1 },
 171         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 172 };
 173
 174 static const struct clk_parent_data disp_cc_parent_data_5[] = {
 175         { .fw_name = "bi_tcxo" },
 176         { .hw = &disp_cc_pll0.clkr.hw },
 177         { .hw = &disp_cc_pll1.clkr.hw },
 178 };
 179
 180 static const struct parent_map disp_cc_parent_map_6[] = {
 181         { P_BI_TCXO, 0 },
 182         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 183         { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
 184 };
 185
 186 static const struct clk_parent_data disp_cc_parent_data_6[] = {
 187         { .fw_name = "bi_tcxo" },
 188         { .fw_name = "dsi0_phy_pll_out_dsiclk" },
 189         { .fw_name = "dsi1_phy_pll_out_dsiclk" },
 190 };
 191
 192 static const struct parent_map disp_cc_parent_map_7[] = {
 193         { P_BI_TCXO, 0 },
 194         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 195         /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
 196 };
 197
 198 static const struct clk_parent_data disp_cc_parent_data_7[] = {
 199         { .fw_name = "bi_tcxo" },
 200         { .hw = &disp_cc_pll1.clkr.hw },
 201         /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
 202 };
 203
 204 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 205         F(19200000, P_BI_TCXO, 1, 0, 0),
 206         F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 207         F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 208         { }
 209 };
 210
 211 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 212         .cmd_rcgr = 0x22bc,
 213         .mnd_width = 0,
 214         .hid_width = 5,
 215         .parent_map = disp_cc_parent_map_3,
 216         .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 217         .clkr.hw.init = &(struct clk_init_data){
 218                 .name = "disp_cc_mdss_ahb_clk_src",
 219                 .parent_data = disp_cc_parent_data_3,
 220                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 221                 .flags = CLK_SET_RATE_PARENT,
 222                 .ops = &clk_rcg2_shared_ops,
 223         },
 224 };
 225
 226 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
 227         F(19200000, P_BI_TCXO, 1, 0, 0),
 228         { }
 229 };
 230
 231 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 232         .cmd_rcgr = 0x2110,
 233         .mnd_width = 0,
 234         .hid_width = 5,
 235         .parent_map = disp_cc_parent_map_2,
 236         .clkr.hw.init = &(struct clk_init_data){
 237                 .name = "disp_cc_mdss_byte0_clk_src",
 238                 .parent_data = disp_cc_parent_data_2,
 239                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 240                 .flags = CLK_SET_RATE_PARENT,
 241                 .ops = &clk_byte2_ops,
 242         },
 243 };
 244
 245 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
 246         .cmd_rcgr = 0x212c,
 247         .mnd_width = 0,
 248         .hid_width = 5,
 249         .parent_map = disp_cc_parent_map_2,
 250         .clkr.hw.init = &(struct clk_init_data){
 251                 .name = "disp_cc_mdss_byte1_clk_src",
 252                 .parent_data = disp_cc_parent_data_2,
 253                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 254                 .flags = CLK_SET_RATE_PARENT,
 255                 .ops = &clk_byte2_ops,
 256         },
 257 };
 258
 259 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
 260         .cmd_rcgr = 0x2240,
 261         .mnd_width = 0,
 262         .hid_width = 5,
 263         .parent_map = disp_cc_parent_map_1,
 264         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 265         .clkr.hw.init = &(struct clk_init_data){
 266                 .name = "disp_cc_mdss_dp_aux1_clk_src",
 267                 .parent_data = disp_cc_parent_data_1,
 268                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 269                 .flags = CLK_SET_RATE_PARENT,
 270                 .ops = &clk_rcg2_ops,
 271         },
 272 };
 273
 274 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
 275         .cmd_rcgr = 0x21dc,
 276         .mnd_width = 0,
 277         .hid_width = 5,
 278         .parent_map = disp_cc_parent_map_1,
 279         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "disp_cc_mdss_dp_aux_clk_src",
 282                 .parent_data = disp_cc_parent_data_1,
 283                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 284                 .flags = CLK_SET_RATE_PARENT,
 285                 .ops = &clk_rcg2_ops,
 286         },
 287 };
 288
 289 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
 290         .cmd_rcgr = 0x220c,
 291         .mnd_width = 0,
 292         .hid_width = 5,
 293         .parent_map = disp_cc_parent_map_0,
 294         .clkr.hw.init = &(struct clk_init_data){
 295                 .name = "disp_cc_mdss_dp_link1_clk_src",
 296                 .parent_data = disp_cc_parent_data_0,
 297                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 298                 .ops = &clk_byte2_ops,
 299         },
 300 };
 301
 302 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 303         .cmd_rcgr = 0x2178,
 304         .mnd_width = 0,
 305         .hid_width = 5,
 306         .parent_map = disp_cc_parent_map_0,
 307         .clkr.hw.init = &(struct clk_init_data){
 308                 .name = "disp_cc_mdss_dp_link_clk_src",
 309                 .parent_data = disp_cc_parent_data_0,
 310                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 311                 .ops = &clk_byte2_ops,
 312         },
 313 };
 314
 315 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
 316         .cmd_rcgr = 0x21c4,
 317         .mnd_width = 16,
 318         .hid_width = 5,
 319         .parent_map = disp_cc_parent_map_0,
 320         .clkr.hw.init = &(struct clk_init_data){
 321                 .name = "disp_cc_mdss_dp_pixel1_clk_src",
 322                 .parent_data = disp_cc_parent_data_0,
 323                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 324                 .ops = &clk_dp_ops,
 325         },
 326 };
 327
 328 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
 329         .cmd_rcgr = 0x21f4,
 330         .mnd_width = 16,
 331         .hid_width = 5,
 332         .parent_map = disp_cc_parent_map_0,
 333         .clkr.hw.init = &(struct clk_init_data){
 334                 .name = "disp_cc_mdss_dp_pixel2_clk_src",
 335                 .parent_data = disp_cc_parent_data_0,
 336                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 337                 .ops = &clk_dp_ops,
 338         },
 339 };
 340
 341 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
 342         .cmd_rcgr = 0x21ac,
 343         .mnd_width = 16,
 344         .hid_width = 5,
 345         .parent_map = disp_cc_parent_map_0,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "disp_cc_mdss_dp_pixel_clk_src",
 348                 .parent_data = disp_cc_parent_data_0,
 349                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 350                 .ops = &clk_dp_ops,
 351         },
 352 };
 353
 354 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
 355         .cmd_rcgr = 0x228c,
 356         .mnd_width = 0,
 357         .hid_width = 5,
 358         .parent_map = disp_cc_parent_map_1,
 359         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 360         .clkr.hw.init = &(struct clk_init_data){
 361                 .name = "disp_cc_mdss_edp_aux_clk_src",
 362                 .parent_data = disp_cc_parent_data_1,
 363                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 364                 .flags = CLK_SET_RATE_PARENT,
 365                 .ops = &clk_rcg2_ops,
 366         },
 367 };
 368
 369 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
 370         .cmd_rcgr = 0x22a4,
 371         .mnd_width = 0,
 372         .hid_width = 5,
 373         .parent_map = disp_cc_parent_map_7,
 374         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 375         .clkr.hw.init = &(struct clk_init_data){
 376                 .name = "disp_cc_mdss_edp_gtc_clk_src",
 377                 .parent_data = disp_cc_parent_data_7,
 378                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
 379                 .flags = CLK_SET_RATE_PARENT,
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
 385         .cmd_rcgr = 0x2270,
 386         .mnd_width = 0,
 387         .hid_width = 5,
 388         .parent_map = disp_cc_parent_map_4,
 389         .clkr.hw.init = &(struct clk_init_data){
 390                 .name = "disp_cc_mdss_edp_link_clk_src",
 391                 .parent_data = disp_cc_parent_data_4,
 392                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 393                 .flags = CLK_SET_RATE_PARENT,
 394                 .ops = &clk_byte2_ops,
 395         },
 396 };
 397
 398 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
 399         .cmd_rcgr = 0x2258,
 400         .mnd_width = 16,
 401         .hid_width = 5,
 402         .parent_map = disp_cc_parent_map_4,
 403         .clkr.hw.init = &(struct clk_init_data){
 404                 .name = "disp_cc_mdss_edp_pixel_clk_src",
 405                 .parent_data = disp_cc_parent_data_4,
 406                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 407                 .ops = &clk_dp_ops,
 408         },
 409 };
 410
 411 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
 412         .halt_reg = 0x2078,
 413         .halt_check = BRANCH_HALT,
 414         .clkr = {
 415                 .enable_reg = 0x2078,
 416                 .enable_mask = BIT(0),
 417                 .hw.init = &(struct clk_init_data){
 418                         .name = "disp_cc_mdss_edp_aux_clk",
 419                         .parent_hws = (const struct clk_hw*[]){
 420                                 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
 421                         },
 422                         .num_parents = 1,
 423                         .flags = CLK_SET_RATE_PARENT,
 424                         .ops = &clk_branch2_ops,
 425                 },
 426         },
 427 };
 428
 429 static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
 430         .halt_reg = 0x207c,
 431         .halt_check = BRANCH_HALT,
 432         .clkr = {
 433                 .enable_reg = 0x207c,
 434                 .enable_mask = BIT(0),
 435                 .hw.init = &(struct clk_init_data){
 436                         .name = "disp_cc_mdss_edp_gtc_clk",
 437                         .parent_hws = (const struct clk_hw*[]){
 438                                 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
 439                         },
 440                         .num_parents = 1,
 441                         .flags = CLK_SET_RATE_PARENT,
 442                         .ops = &clk_branch2_ops,
 443                 },
 444         },
 445 };
 446
 447 static struct clk_branch disp_cc_mdss_edp_link_clk = {
 448         .halt_reg = 0x2070,
 449         .halt_check = BRANCH_HALT,
 450         .clkr = {
 451                 .enable_reg = 0x2070,
 452                 .enable_mask = BIT(0),
 453                 .hw.init = &(struct clk_init_data){
 454                         .name = "disp_cc_mdss_edp_link_clk",
 455                         .parent_hws = (const struct clk_hw*[]){
 456                                 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
 457                         },
 458                         .num_parents = 1,
 459                         .flags = CLK_SET_RATE_PARENT,
 460                         .ops = &clk_branch2_ops,
 461                 },
 462         },
 463 };
 464
 465 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
 466         .halt_reg = 0x2074,
 467         .halt_check = BRANCH_HALT,
 468         .clkr = {
 469                 .enable_reg = 0x2074,
 470                 .enable_mask = BIT(0),
 471                 .hw.init = &(struct clk_init_data){
 472                         .name = "disp_cc_mdss_edp_link_intf_clk",
 473                         .parent_hws = (const struct clk_hw*[]){
 474                                 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
 475                         },
 476                         .num_parents = 1,
 477                         .flags = CLK_GET_RATE_NOCACHE,
 478                         .ops = &clk_branch2_ops,
 479                 },
 480         },
 481 };
 482
 483 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
 484         .halt_reg = 0x206c,
 485         .halt_check = BRANCH_HALT,
 486         .clkr = {
 487                 .enable_reg = 0x206c,
 488                 .enable_mask = BIT(0),
 489                 .hw.init = &(struct clk_init_data){
 490                         .name = "disp_cc_mdss_edp_pixel_clk",
 491                         .parent_hws = (const struct clk_hw*[]){
 492                                 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
 493                         },
 494                         .num_parents = 1,
 495                         .flags = CLK_SET_RATE_PARENT,
 496                         .ops = &clk_branch2_ops,
 497                 },
 498         },
 499 };
 500
 501 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 502         .cmd_rcgr = 0x2148,
 503         .mnd_width = 0,
 504         .hid_width = 5,
 505         .parent_map = disp_cc_parent_map_2,
 506         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 507         .clkr.hw.init = &(struct clk_init_data){
 508                 .name = "disp_cc_mdss_esc0_clk_src",
 509                 .parent_data = disp_cc_parent_data_2,
 510                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 511                 .flags = CLK_SET_RATE_PARENT,
 512                 .ops = &clk_rcg2_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
 517         .cmd_rcgr = 0x2160,
 518         .mnd_width = 0,
 519         .hid_width = 5,
 520         .parent_map = disp_cc_parent_map_2,
 521         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 522         .clkr.hw.init = &(struct clk_init_data){
 523                 .name = "disp_cc_mdss_esc1_clk_src",
 524                 .parent_data = disp_cc_parent_data_2,
 525                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 526                 .flags = CLK_SET_RATE_PARENT,
 527                 .ops = &clk_rcg2_ops,
 528         },
 529 };
 530
 531 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 532         F(19200000, P_BI_TCXO, 1, 0, 0),
 533         F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
 534         F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
 535         F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
 536         F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
 537         F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
 538         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 539         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 540         { }
 541 };
 542
 543 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 544         .cmd_rcgr = 0x20c8,
 545         .mnd_width = 0,
 546         .hid_width = 5,
 547         .parent_map = disp_cc_parent_map_5,
 548         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 549         .clkr.hw.init = &(struct clk_init_data){
 550                 .name = "disp_cc_mdss_mdp_clk_src",
 551                 .parent_data = disp_cc_parent_data_5,
 552                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 553                 .flags = CLK_SET_RATE_PARENT,
 554                 .ops = &clk_rcg2_shared_ops,
 555         },
 556 };
 557
 558 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 559         .cmd_rcgr = 0x2098,
 560         .mnd_width = 8,
 561         .hid_width = 5,
 562         .parent_map = disp_cc_parent_map_6,
 563         .clkr.hw.init = &(struct clk_init_data){
 564                 .name = "disp_cc_mdss_pclk0_clk_src",
 565                 .parent_data = disp_cc_parent_data_6,
 566                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 567                 .flags = CLK_SET_RATE_PARENT,
 568                 .ops = &clk_pixel_ops,
 569         },
 570 };
 571
 572 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
 573         .cmd_rcgr = 0x20b0,
 574         .mnd_width = 8,
 575         .hid_width = 5,
 576         .parent_map = disp_cc_parent_map_6,
 577         .clkr.hw.init = &(struct clk_init_data){
 578                 .name = "disp_cc_mdss_pclk1_clk_src",
 579                 .parent_data = disp_cc_parent_data_6,
 580                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 581                 .flags = CLK_SET_RATE_PARENT,
 582                 .ops = &clk_pixel_ops,
 583         },
 584 };
 585
 586 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
 587         F(19200000, P_BI_TCXO, 1, 0, 0),
 588         F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
 589         F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
 590         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 591         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 592         { }
 593 };
 594
 595 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
 596         .cmd_rcgr = 0x20e0,
 597         .mnd_width = 0,
 598         .hid_width = 5,
 599         .parent_map = disp_cc_parent_map_5,
 600         .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
 601         .clkr.hw.init = &(struct clk_init_data){
 602                 .name = "disp_cc_mdss_rot_clk_src",
 603                 .parent_data = disp_cc_parent_data_5,
 604                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 605                 .flags = CLK_SET_RATE_PARENT,
 606                 .ops = &clk_rcg2_shared_ops,
 607         },
 608 };
 609
 610 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 611         .cmd_rcgr = 0x20f8,
 612         .mnd_width = 0,
 613         .hid_width = 5,
 614         .parent_map = disp_cc_parent_map_1,
 615         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 616         .clkr.hw.init = &(struct clk_init_data){
 617                 .name = "disp_cc_mdss_vsync_clk_src",
 618                 .parent_data = disp_cc_parent_data_1,
 619                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 620                 .flags = CLK_SET_RATE_PARENT,
 621                 .ops = &clk_rcg2_ops,
 622         },
 623 };
 624
 625 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 626         .reg = 0x2128,
 627         .shift = 0,
 628         .width = 2,
 629         .clkr.hw.init = &(struct clk_init_data) {
 630                 .name = "disp_cc_mdss_byte0_div_clk_src",
 631                 .parent_hws = (const struct clk_hw*[]){
 632                         &disp_cc_mdss_byte0_clk_src.clkr.hw,
 633                 },
 634                 .num_parents = 1,
 635                 .ops = &clk_regmap_div_ops,
 636         },
 637 };
 638
 639
 640 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
 641         .reg = 0x2144,
 642         .shift = 0,
 643         .width = 2,
 644         .clkr.hw.init = &(struct clk_init_data) {
 645                 .name = "disp_cc_mdss_byte1_div_clk_src",
 646                 .parent_hws = (const struct clk_hw*[]){
 647                         &disp_cc_mdss_byte1_clk_src.clkr.hw,
 648                 },
 649                 .num_parents = 1,
 650                 .ops = &clk_regmap_div_ops,
 651         },
 652 };
 653
 654
 655 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
 656         .reg = 0x2224,
 657         .shift = 0,
 658         .width = 2,
 659         .clkr.hw.init = &(struct clk_init_data) {
 660                 .name = "disp_cc_mdss_dp_link1_div_clk_src",
 661                 .parent_hws = (const struct clk_hw*[]){
 662                         &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
 663                 },
 664                 .num_parents = 1,
 665                 .ops = &clk_regmap_div_ro_ops,
 666         },
 667 };
 668
 669
 670 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
 671         .reg = 0x2190,
 672         .shift = 0,
 673         .width = 2,
 674         .clkr.hw.init = &(struct clk_init_data) {
 675                 .name = "disp_cc_mdss_dp_link_div_clk_src",
 676                 .parent_hws = (const struct clk_hw*[]){
 677                         &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 678                 },
 679                 .num_parents = 1,
 680                 .ops = &clk_regmap_div_ro_ops,
 681         },
 682 };
 683
 684 static struct clk_branch disp_cc_mdss_ahb_clk = {
 685         .halt_reg = 0x2080,
 686         .halt_check = BRANCH_HALT,
 687         .clkr = {
 688                 .enable_reg = 0x2080,
 689                 .enable_mask = BIT(0),
 690                 .hw.init = &(struct clk_init_data){
 691                         .name = "disp_cc_mdss_ahb_clk",
 692                         .parent_hws = (const struct clk_hw*[]){
 693                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
 694                         },
 695                         .num_parents = 1,
 696                         .flags = CLK_SET_RATE_PARENT,
 697                         .ops = &clk_branch2_ops,
 698                 },
 699         },
 700 };
 701
 702 static struct clk_branch disp_cc_mdss_byte0_clk = {
 703         .halt_reg = 0x2028,
 704         .halt_check = BRANCH_HALT,
 705         .clkr = {
 706                 .enable_reg = 0x2028,
 707                 .enable_mask = BIT(0),
 708                 .hw.init = &(struct clk_init_data){
 709                         .name = "disp_cc_mdss_byte0_clk",
 710                         .parent_hws = (const struct clk_hw*[]){
 711                                 &disp_cc_mdss_byte0_clk_src.clkr.hw,
 712                         },
 713                         .num_parents = 1,
 714                         .flags = CLK_SET_RATE_PARENT,
 715                         .ops = &clk_branch2_ops,
 716                 },
 717         },
 718 };
 719
 720 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 721         .halt_reg = 0x202c,
 722         .halt_check = BRANCH_HALT,
 723         .clkr = {
 724                 .enable_reg = 0x202c,
 725                 .enable_mask = BIT(0),
 726                 .hw.init = &(struct clk_init_data){
 727                         .name = "disp_cc_mdss_byte0_intf_clk",
 728                         .parent_hws = (const struct clk_hw*[]){
 729                                 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 730                         },
 731                         .num_parents = 1,
 732                         .flags = CLK_SET_RATE_PARENT,
 733                         .ops = &clk_branch2_ops,
 734                 },
 735         },
 736 };
 737
 738 static struct clk_branch disp_cc_mdss_byte1_clk = {
 739         .halt_reg = 0x2030,
 740         .halt_check = BRANCH_HALT,
 741         .clkr = {
 742                 .enable_reg = 0x2030,
 743                 .enable_mask = BIT(0),
 744                 .hw.init = &(struct clk_init_data){
 745                         .name = "disp_cc_mdss_byte1_clk",
 746                         .parent_hws = (const struct clk_hw*[]){
 747                                 &disp_cc_mdss_byte1_clk_src.clkr.hw,
 748                         },
 749                         .num_parents = 1,
 750                         .flags = CLK_SET_RATE_PARENT,
 751                         .ops = &clk_branch2_ops,
 752                 },
 753         },
 754 };
 755
 756 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
 757         .halt_reg = 0x2034,
 758         .halt_check = BRANCH_HALT,
 759         .clkr = {
 760                 .enable_reg = 0x2034,
 761                 .enable_mask = BIT(0),
 762                 .hw.init = &(struct clk_init_data){
 763                         .name = "disp_cc_mdss_byte1_intf_clk",
 764                         .parent_hws = (const struct clk_hw*[]){
 765                                 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
 766                         },
 767                         .num_parents = 1,
 768                         .flags = CLK_SET_RATE_PARENT,
 769                         .ops = &clk_branch2_ops,
 770                 },
 771         },
 772 };
 773
 774 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
 775         .halt_reg = 0x2068,
 776         .halt_check = BRANCH_HALT,
 777         .clkr = {
 778                 .enable_reg = 0x2068,
 779                 .enable_mask = BIT(0),
 780                 .hw.init = &(struct clk_init_data){
 781                         .name = "disp_cc_mdss_dp_aux1_clk",
 782                         .parent_hws = (const struct clk_hw*[]){
 783                                 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
 784                         },
 785                         .num_parents = 1,
 786                         .flags = CLK_SET_RATE_PARENT,
 787                         .ops = &clk_branch2_ops,
 788                 },
 789         },
 790 };
 791
 792 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
 793         .halt_reg = 0x2054,
 794         .halt_check = BRANCH_HALT,
 795         .clkr = {
 796                 .enable_reg = 0x2054,
 797                 .enable_mask = BIT(0),
 798                 .hw.init = &(struct clk_init_data){
 799                         .name = "disp_cc_mdss_dp_aux_clk",
 800                         .parent_hws = (const struct clk_hw*[]){
 801                                 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
 802                         },
 803                         .num_parents = 1,
 804                         .flags = CLK_SET_RATE_PARENT,
 805                         .ops = &clk_branch2_ops,
 806                 },
 807         },
 808 };
 809
 810 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
 811         .halt_reg = 0x205c,
 812         .halt_check = BRANCH_HALT,
 813         .clkr = {
 814                 .enable_reg = 0x205c,
 815                 .enable_mask = BIT(0),
 816                 .hw.init = &(struct clk_init_data){
 817                         .name = "disp_cc_mdss_dp_link1_clk",
 818                         .parent_hws = (const struct clk_hw*[]){
 819                                 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
 820                         },
 821                         .num_parents = 1,
 822                         .flags = CLK_SET_RATE_PARENT,
 823                         .ops = &clk_branch2_ops,
 824                 },
 825         },
 826 };
 827
 828 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
 829         .halt_reg = 0x2060,
 830         .halt_check = BRANCH_HALT,
 831         .clkr = {
 832                 .enable_reg = 0x2060,
 833                 .enable_mask = BIT(0),
 834                 .hw.init = &(struct clk_init_data){
 835                         .name = "disp_cc_mdss_dp_link1_intf_clk",
 836                         .parent_hws = (const struct clk_hw*[]){
 837                                 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
 838                         },
 839                         .num_parents = 1,
 840                         .ops = &clk_branch2_ops,
 841                 },
 842         },
 843 };
 844
 845 static struct clk_branch disp_cc_mdss_dp_link_clk = {
 846         .halt_reg = 0x2040,
 847         .halt_check = BRANCH_HALT,
 848         .clkr = {
 849                 .enable_reg = 0x2040,
 850                 .enable_mask = BIT(0),
 851                 .hw.init = &(struct clk_init_data){
 852                         .name = "disp_cc_mdss_dp_link_clk",
 853                         .parent_hws = (const struct clk_hw*[]){
 854                                 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 855                         },
 856                         .num_parents = 1,
 857                         .flags = CLK_SET_RATE_PARENT,
 858                         .ops = &clk_branch2_ops,
 859                 },
 860         },
 861 };
 862
 863 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
 864         .halt_reg = 0x2044,
 865         .halt_check = BRANCH_HALT,
 866         .clkr = {
 867                 .enable_reg = 0x2044,
 868                 .enable_mask = BIT(0),
 869                 .hw.init = &(struct clk_init_data){
 870                         .name = "disp_cc_mdss_dp_link_intf_clk",
 871                         .parent_hws = (const struct clk_hw*[]){
 872                                 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
 873                         },
 874                         .num_parents = 1,
 875                         .ops = &clk_branch2_ops,
 876                 },
 877         },
 878 };
 879
 880 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
 881         .halt_reg = 0x2050,
 882         .halt_check = BRANCH_HALT,
 883         .clkr = {
 884                 .enable_reg = 0x2050,
 885                 .enable_mask = BIT(0),
 886                 .hw.init = &(struct clk_init_data){
 887                         .name = "disp_cc_mdss_dp_pixel1_clk",
 888                         .parent_hws = (const struct clk_hw*[]){
 889                                 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
 890                         },
 891                         .num_parents = 1,
 892                         .flags = CLK_SET_RATE_PARENT,
 893                         .ops = &clk_branch2_ops,
 894                 },
 895         },
 896 };
 897
 898 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
 899         .halt_reg = 0x2058,
 900         .halt_check = BRANCH_HALT,
 901         .clkr = {
 902                 .enable_reg = 0x2058,
 903                 .enable_mask = BIT(0),
 904                 .hw.init = &(struct clk_init_data){
 905                         .name = "disp_cc_mdss_dp_pixel2_clk",
 906                         .parent_hws = (const struct clk_hw*[]){
 907                                 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
 908                         },
 909                         .num_parents = 1,
 910                         .flags = CLK_SET_RATE_PARENT,
 911                         .ops = &clk_branch2_ops,
 912                 },
 913         },
 914 };
 915
 916 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
 917         .halt_reg = 0x204c,
 918         .halt_check = BRANCH_HALT,
 919         .clkr = {
 920                 .enable_reg = 0x204c,
 921                 .enable_mask = BIT(0),
 922                 .hw.init = &(struct clk_init_data){
 923                         .name = "disp_cc_mdss_dp_pixel_clk",
 924                         .parent_hws = (const struct clk_hw*[]){
 925                                 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
 926                         },
 927                         .num_parents = 1,
 928                         .flags = CLK_SET_RATE_PARENT,
 929                         .ops = &clk_branch2_ops,
 930                 },
 931         },
 932 };
 933
 934 static struct clk_branch disp_cc_mdss_esc0_clk = {
 935         .halt_reg = 0x2038,
 936         .halt_check = BRANCH_HALT,
 937         .clkr = {
 938                 .enable_reg = 0x2038,
 939                 .enable_mask = BIT(0),
 940                 .hw.init = &(struct clk_init_data){
 941                         .name = "disp_cc_mdss_esc0_clk",
 942                         .parent_hws = (const struct clk_hw*[]){
 943                                 &disp_cc_mdss_esc0_clk_src.clkr.hw,
 944                         },
 945                         .num_parents = 1,
 946                         .flags = CLK_SET_RATE_PARENT,
 947                         .ops = &clk_branch2_ops,
 948                 },
 949         },
 950 };
 951
 952 static struct clk_branch disp_cc_mdss_esc1_clk = {
 953         .halt_reg = 0x203c,
 954         .halt_check = BRANCH_HALT,
 955         .clkr = {
 956                 .enable_reg = 0x203c,
 957                 .enable_mask = BIT(0),
 958                 .hw.init = &(struct clk_init_data){
 959                         .name = "disp_cc_mdss_esc1_clk",
 960                         .parent_hws = (const struct clk_hw*[]){
 961                                 &disp_cc_mdss_esc1_clk_src.clkr.hw,
 962                         },
 963                         .num_parents = 1,
 964                         .flags = CLK_SET_RATE_PARENT,
 965                         .ops = &clk_branch2_ops,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_branch disp_cc_mdss_mdp_clk = {
 971         .halt_reg = 0x200c,
 972         .halt_check = BRANCH_HALT,
 973         .clkr = {
 974                 .enable_reg = 0x200c,
 975                 .enable_mask = BIT(0),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "disp_cc_mdss_mdp_clk",
 978                         .parent_hws = (const struct clk_hw*[]){
 979                                 &disp_cc_mdss_mdp_clk_src.clkr.hw,
 980                         },
 981                         .num_parents = 1,
 982                         .flags = CLK_SET_RATE_PARENT,
 983                         .ops = &clk_branch2_ops,
 984                 },
 985         },
 986 };
 987
 988 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
 989         .halt_reg = 0x201c,
 990         .halt_check = BRANCH_VOTED,
 991         .clkr = {
 992                 .enable_reg = 0x201c,
 993                 .enable_mask = BIT(0),
 994                 .hw.init = &(struct clk_init_data){
 995                         .name = "disp_cc_mdss_mdp_lut_clk",
 996                         .parent_hws = (const struct clk_hw*[]){
 997                                 &disp_cc_mdss_mdp_clk_src.clkr.hw,
 998                         },
 999                         .num_parents = 1,
1000                         .ops = &clk_branch2_ops,
1001                 },
1002         },
1003 };
1004
1005 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1006         .halt_reg = 0x4004,
1007         .halt_check = BRANCH_VOTED,
1008         .clkr = {
1009                 .enable_reg = 0x4004,
1010                 .enable_mask = BIT(0),
1011                 .hw.init = &(struct clk_init_data){
1012                         .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1013                         .parent_hws = (const struct clk_hw*[]){
1014                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1015                         },
1016                         .num_parents = 1,
1017                         .flags = CLK_SET_RATE_PARENT,
1018                         .ops = &clk_branch2_ops,
1019                 },
1020         },
1021 };
1022
1023 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1024         .halt_reg = 0x2004,
1025         .halt_check = BRANCH_HALT,
1026         .clkr = {
1027                 .enable_reg = 0x2004,
1028                 .enable_mask = BIT(0),
1029                 .hw.init = &(struct clk_init_data){
1030                         .name = "disp_cc_mdss_pclk0_clk",
1031                         .parent_hws = (const struct clk_hw*[]){
1032                                 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1033                         },
1034                         .num_parents = 1,
1035                         .flags = CLK_SET_RATE_PARENT,
1036                         .ops = &clk_branch2_ops,
1037                 },
1038         },
1039 };
1040
1041 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1042         .halt_reg = 0x2008,
1043         .halt_check = BRANCH_HALT,
1044         .clkr = {
1045                 .enable_reg = 0x2008,
1046                 .enable_mask = BIT(0),
1047                 .hw.init = &(struct clk_init_data){
1048                         .name = "disp_cc_mdss_pclk1_clk",
1049                         .parent_hws = (const struct clk_hw*[]){
1050                                 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1051                         },
1052                         .num_parents = 1,
1053                         .flags = CLK_SET_RATE_PARENT,
1054                         .ops = &clk_branch2_ops,
1055                 },
1056         },
1057 };
1058
1059 static struct clk_branch disp_cc_mdss_rot_clk = {
1060         .halt_reg = 0x2014,
1061         .halt_check = BRANCH_HALT,
1062         .clkr = {
1063                 .enable_reg = 0x2014,
1064                 .enable_mask = BIT(0),
1065                 .hw.init = &(struct clk_init_data){
1066                         .name = "disp_cc_mdss_rot_clk",
1067                         .parent_hws = (const struct clk_hw*[]){
1068                                 &disp_cc_mdss_rot_clk_src.clkr.hw,
1069                         },
1070                         .num_parents = 1,
1071                         .flags = CLK_SET_RATE_PARENT,
1072                         .ops = &clk_branch2_ops,
1073                 },
1074         },
1075 };
1076
1077 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1078         .halt_reg = 0x400c,
1079         .halt_check = BRANCH_HALT,
1080         .clkr = {
1081                 .enable_reg = 0x400c,
1082                 .enable_mask = BIT(0),
1083                 .hw.init = &(struct clk_init_data){
1084                         .name = "disp_cc_mdss_rscc_ahb_clk",
1085                         .parent_hws = (const struct clk_hw*[]){
1086                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1087                         },
1088                         .num_parents = 1,
1089                         .flags = CLK_SET_RATE_PARENT,
1090                         .ops = &clk_branch2_ops,
1091                 },
1092         },
1093 };
1094
1095 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1096         .halt_reg = 0x4008,
1097         .halt_check = BRANCH_HALT,
1098         .clkr = {
1099                 .enable_reg = 0x4008,
1100                 .enable_mask = BIT(0),
1101                 .hw.init = &(struct clk_init_data){
1102                         .name = "disp_cc_mdss_rscc_vsync_clk",
1103                         .parent_hws = (const struct clk_hw*[]){
1104                                 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1105                         },
1106                         .num_parents = 1,
1107                         .flags = CLK_SET_RATE_PARENT,
1108                         .ops = &clk_branch2_ops,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_branch disp_cc_mdss_vsync_clk = {
1114         .halt_reg = 0x2024,
1115         .halt_check = BRANCH_HALT,
1116         .clkr = {
1117                 .enable_reg = 0x2024,
1118                 .enable_mask = BIT(0),
1119                 .hw.init = &(struct clk_init_data){
1120                         .name = "disp_cc_mdss_vsync_clk",
1121                         .parent_hws = (const struct clk_hw*[]){
1122                                 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1123                         },
1124                         .num_parents = 1,
1125                         .flags = CLK_SET_RATE_PARENT,
1126                         .ops = &clk_branch2_ops,
1127                 },
1128         },
1129 };
1130
1131 static struct gdsc mdss_gdsc = {
1132         .gdscr = 0x3000,
1133         .en_rest_wait_val = 0x2,
1134         .en_few_wait_val = 0x2,
1135         .clk_dis_wait_val = 0xf,
1136         .pd = {
1137                 .name = "mdss_gdsc",
1138         },
1139         .pwrsts = PWRSTS_OFF_ON,
1140         .flags = HW_CTRL,
1141 };
1142
1143 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1144         [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1145         [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1146         [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1147         [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1148         [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1149         [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1150         [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1151         [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1152         [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1153         [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1154         [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1155         [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1156         [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1157         [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1158         [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1159         [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1160         [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1161         [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1162         [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1163         [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1164         [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1165         [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1166         [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1167         [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1168         [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1169         [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1170         [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1171         [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1172         [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1173         [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1174         [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1175         [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1176         [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1177         [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1178         [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1179         [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1180         [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1181         [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1182         [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1183         [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1184         [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1185         [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1186         [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1187         [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1188         [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1189         [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1190         [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1191         [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1192         [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1193         [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1194         [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1195         [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1196         [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1197         [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1198         [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1199         [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1200         [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1201 };
1202
1203 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1204         [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1205         [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1206 };
1207
1208 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1209         [MDSS_GDSC] = &mdss_gdsc,
1210 };
1211
1212 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1213         .reg_bits       = 32,
1214         .reg_stride     = 4,
1215         .val_bits       = 32,
1216         .max_register   = 0x10000,
1217         .fast_io        = true,
1218 };
1219
1220 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1221         .config = &disp_cc_sm8250_regmap_config,
1222         .clks = disp_cc_sm8250_clocks,
1223         .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1224         .resets = disp_cc_sm8250_resets,
1225         .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1226         .gdscs = disp_cc_sm8250_gdscs,
1227         .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1228 };
1229
1230 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1231         { .compatible = "qcom,sc8180x-dispcc" },
1232         { .compatible = "qcom,sm8150-dispcc" },
1233         { .compatible = "qcom,sm8250-dispcc" },
1234         { .compatible = "qcom,sm8350-dispcc" },
1235         { }
1236 };
1237 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1238
1239 static void disp_cc_sm8250_pm_runtime_disable(void *data)
1240 {
1241         pm_runtime_disable(data);
1242 }
1243
1244 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1245 {
1246         struct regmap *regmap;
1247         int ret;
1248
1249         pm_runtime_enable(&pdev->dev);
1250
1251         ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8250_pm_runtime_disable, &pdev->dev);
1252         if (ret)
1253                 return ret;
1254
1255         ret = pm_runtime_resume_and_get(&pdev->dev);
1256         if (ret)
1257                 return ret;
1258
1259         regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1260         if (IS_ERR(regmap)) {
1261                 pm_runtime_put(&pdev->dev);
1262                 return PTR_ERR(regmap);
1263         }
1264
1265         /* Apply differences for SM8150 and SM8350 */
1266         BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1267         if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1268             of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1269                 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1270                 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1271                 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1272                 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1273                 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1274                 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1275                 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1276                 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1277         } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1278                 static struct clk_rcg2 * const rcgs[] = {
1279                         &disp_cc_mdss_byte0_clk_src,
1280                         &disp_cc_mdss_byte1_clk_src,
1281                         &disp_cc_mdss_dp_aux1_clk_src,
1282                         &disp_cc_mdss_dp_aux_clk_src,
1283                         &disp_cc_mdss_dp_link1_clk_src,
1284                         &disp_cc_mdss_dp_link_clk_src,
1285                         &disp_cc_mdss_dp_pixel1_clk_src,
1286                         &disp_cc_mdss_dp_pixel2_clk_src,
1287                         &disp_cc_mdss_dp_pixel_clk_src,
1288                         &disp_cc_mdss_esc0_clk_src,
1289                         &disp_cc_mdss_mdp_clk_src,
1290                         &disp_cc_mdss_pclk0_clk_src,
1291                         &disp_cc_mdss_pclk1_clk_src,
1292                         &disp_cc_mdss_rot_clk_src,
1293                         &disp_cc_mdss_vsync_clk_src,
1294                 };
1295                 static struct clk_regmap_div * const divs[] = {
1296                         &disp_cc_mdss_byte0_div_clk_src,
1297                         &disp_cc_mdss_byte1_div_clk_src,
1298                         &disp_cc_mdss_dp_link1_div_clk_src,
1299                         &disp_cc_mdss_dp_link_div_clk_src,
1300                 };
1301                 unsigned int i;
1302                 static bool offset_applied;
1303
1304                 /*
1305                  * note: trion == lucid, except for the prepare() op
1306                  * only apply the offsets once (in case of deferred probe)
1307                  */
1308                 if (!offset_applied) {
1309                         for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1310                                 rcgs[i]->cmd_rcgr -= 4;
1311
1312                         for (i = 0; i < ARRAY_SIZE(divs); i++) {
1313                                 divs[i]->reg -= 4;
1314                                 divs[i]->width = 4;
1315                         }
1316
1317                         disp_cc_mdss_ahb_clk.halt_reg -= 4;
1318                         disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1319
1320                         offset_applied = true;
1321                 }
1322
1323                 disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1324
1325                 disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1326                 disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1327                 disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1328                 disp_cc_pll0.vco_table = lucid_5lpe_vco;
1329                 disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1330                 disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1331                 disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1332                 disp_cc_pll1.vco_table = lucid_5lpe_vco;
1333         }
1334
1335         clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1336         clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1337
1338         /* Enable clock gating for MDP clocks */
1339         regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1340
1341         /* DISP_CC_XO_CLK always-on */
1342         regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
1343
1344         ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
1345
1346         pm_runtime_put(&pdev->dev);
1347
1348         return ret;
1349 }
1350
1351 static struct platform_driver disp_cc_sm8250_driver = {
1352         .probe = disp_cc_sm8250_probe,
1353         .driver = {
1354                 .name = "disp_cc-sm8250",
1355                 .of_match_table = disp_cc_sm8250_match_table,
1356         },
1357 };
1358
1359 static int __init disp_cc_sm8250_init(void)
1360 {
1361         return platform_driver_register(&disp_cc_sm8250_driver);
1362 }
1363 subsys_initcall(disp_cc_sm8250_init);
1364
1365 static void __exit disp_cc_sm8250_exit(void)
1366 {
1367         platform_driver_unregister(&disp_cc_sm8250_driver);
1368 }
1369 module_exit(disp_cc_sm8250_exit);
1370
1371 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1372 MODULE_LICENSE("GPL v2");