1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap-divider.h"
22 P_DISP_CC_PLL0_OUT_EVEN,
23 P_DISP_CC_PLL0_OUT_MAIN,
24 P_DP_PHY_PLL_LINK_CLK,
25 P_DP_PHY_PLL_VCO_DIV_CLK,
26 P_DSI0_PHY_PLL_OUT_BYTECLK,
27 P_DSI0_PHY_PLL_OUT_DSICLK,
31 static const struct pll_vco fabia_vco[] = {
32 { 249600000, 2000000000, 0 },
35 static struct clk_alpha_pll disp_cc_pll0 = {
37 .vco_table = fabia_vco,
38 .num_vco = ARRAY_SIZE(fabia_vco),
39 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
41 .hw.init = &(struct clk_init_data){
42 .name = "disp_cc_pll0",
43 .parent_data = &(const struct clk_parent_data){
47 .ops = &clk_alpha_pll_fabia_ops,
52 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
57 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
60 .post_div_table = post_div_table_disp_cc_pll0_out_even,
61 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
64 .clkr.hw.init = &(struct clk_init_data){
65 .name = "disp_cc_pll0_out_even",
66 .parent_hws = (const struct clk_hw*[]){
67 &disp_cc_pll0.clkr.hw,
70 .flags = CLK_SET_RATE_PARENT,
71 .ops = &clk_alpha_pll_postdiv_fabia_ops,
75 static const struct parent_map disp_cc_parent_map_0[] = {
79 static const struct clk_parent_data disp_cc_parent_data_0[] = {
80 { .fw_name = "bi_tcxo" },
83 static const struct parent_map disp_cc_parent_map_1[] = {
85 { P_DP_PHY_PLL_LINK_CLK, 1 },
86 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
89 static const struct clk_parent_data disp_cc_parent_data_1[] = {
90 { .fw_name = "bi_tcxo" },
91 { .fw_name = "dp_phy_pll_link_clk" },
92 { .fw_name = "dp_phy_pll_vco_div_clk" },
95 static const struct parent_map disp_cc_parent_map_2[] = {
97 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
100 static const struct clk_parent_data disp_cc_parent_data_2[] = {
101 { .fw_name = "bi_tcxo" },
102 { .fw_name = "dsi0_phy_pll_out_byteclk" },
105 static const struct parent_map disp_cc_parent_map_3[] = {
107 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
108 { P_GPLL0_OUT_MAIN, 4 },
109 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
112 static const struct clk_parent_data disp_cc_parent_data_3[] = {
113 { .fw_name = "bi_tcxo" },
114 { .hw = &disp_cc_pll0.clkr.hw },
115 { .fw_name = "gcc_disp_gpll0_clk_src" },
116 { .hw = &disp_cc_pll0_out_even.clkr.hw },
119 static const struct parent_map disp_cc_parent_map_4[] = {
121 { P_GPLL0_OUT_MAIN, 4 },
124 static const struct clk_parent_data disp_cc_parent_data_4[] = {
125 { .fw_name = "bi_tcxo" },
126 { .fw_name = "gcc_disp_gpll0_clk_src" },
129 static const struct parent_map disp_cc_parent_map_5[] = {
131 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
134 static const struct clk_parent_data disp_cc_parent_data_5[] = {
135 { .fw_name = "bi_tcxo" },
136 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
139 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
140 F(19200000, P_BI_TCXO, 1, 0, 0),
141 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
142 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
146 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
150 .parent_map = disp_cc_parent_map_4,
151 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
152 .clkr.hw.init = &(struct clk_init_data){
153 .name = "disp_cc_mdss_ahb_clk_src",
154 .parent_data = disp_cc_parent_data_4,
155 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
156 .flags = CLK_SET_RATE_PARENT,
157 .ops = &clk_rcg2_shared_ops,
161 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
165 .parent_map = disp_cc_parent_map_2,
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "disp_cc_mdss_byte0_clk_src",
168 .parent_data = disp_cc_parent_data_2,
169 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
170 .flags = CLK_SET_RATE_PARENT,
171 .ops = &clk_byte2_ops,
175 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
176 F(19200000, P_BI_TCXO, 1, 0, 0),
180 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
184 .parent_map = disp_cc_parent_map_0,
185 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
186 .clkr.hw.init = &(struct clk_init_data){
187 .name = "disp_cc_mdss_dp_aux_clk_src",
188 .parent_data = disp_cc_parent_data_0,
189 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
190 .ops = &clk_rcg2_ops,
194 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
198 .parent_map = disp_cc_parent_map_1,
199 .clkr.hw.init = &(struct clk_init_data){
200 .name = "disp_cc_mdss_dp_crypto_clk_src",
201 .parent_data = disp_cc_parent_data_1,
202 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
203 .ops = &clk_byte2_ops,
207 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
211 .parent_map = disp_cc_parent_map_1,
212 .clkr.hw.init = &(struct clk_init_data){
213 .name = "disp_cc_mdss_dp_link_clk_src",
214 .parent_data = disp_cc_parent_data_1,
215 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
216 .ops = &clk_byte2_ops,
220 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
224 .parent_map = disp_cc_parent_map_1,
225 .clkr.hw.init = &(struct clk_init_data){
226 .name = "disp_cc_mdss_dp_pixel_clk_src",
227 .parent_data = disp_cc_parent_data_1,
228 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
233 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
237 .parent_map = disp_cc_parent_map_2,
238 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "disp_cc_mdss_esc0_clk_src",
241 .parent_data = disp_cc_parent_data_2,
242 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
243 .ops = &clk_rcg2_ops,
247 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
248 F(19200000, P_BI_TCXO, 1, 0, 0),
249 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
250 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
251 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
252 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
256 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
260 .parent_map = disp_cc_parent_map_3,
261 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
262 .clkr.hw.init = &(struct clk_init_data){
263 .name = "disp_cc_mdss_mdp_clk_src",
264 .parent_data = disp_cc_parent_data_3,
265 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
266 .ops = &clk_rcg2_shared_ops,
270 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
274 .parent_map = disp_cc_parent_map_5,
275 .clkr.hw.init = &(struct clk_init_data){
276 .name = "disp_cc_mdss_pclk0_clk_src",
277 .parent_data = disp_cc_parent_data_5,
278 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
279 .flags = CLK_SET_RATE_PARENT,
280 .ops = &clk_pixel_ops,
284 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
288 .parent_map = disp_cc_parent_map_3,
289 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
290 .clkr.hw.init = &(struct clk_init_data){
291 .name = "disp_cc_mdss_rot_clk_src",
292 .parent_data = disp_cc_parent_data_3,
293 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
294 .ops = &clk_rcg2_shared_ops,
298 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
302 .parent_map = disp_cc_parent_map_0,
303 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "disp_cc_mdss_vsync_clk_src",
306 .parent_data = disp_cc_parent_data_0,
307 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
308 .ops = &clk_rcg2_shared_ops,
312 static struct clk_branch disp_cc_mdss_ahb_clk = {
314 .halt_check = BRANCH_HALT,
316 .enable_reg = 0x2080,
317 .enable_mask = BIT(0),
318 .hw.init = &(struct clk_init_data){
319 .name = "disp_cc_mdss_ahb_clk",
320 .parent_hws = (const struct clk_hw*[]){
321 &disp_cc_mdss_ahb_clk_src.clkr.hw,
324 .flags = CLK_SET_RATE_PARENT,
325 .ops = &clk_branch2_ops,
330 static struct clk_branch disp_cc_mdss_byte0_clk = {
332 .halt_check = BRANCH_HALT,
334 .enable_reg = 0x2028,
335 .enable_mask = BIT(0),
336 .hw.init = &(struct clk_init_data){
337 .name = "disp_cc_mdss_byte0_clk",
338 .parent_hws = (const struct clk_hw*[]){
339 &disp_cc_mdss_byte0_clk_src.clkr.hw,
342 .flags = CLK_SET_RATE_PARENT,
343 .ops = &clk_branch2_ops,
348 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
352 .clkr.hw.init = &(struct clk_init_data) {
353 .name = "disp_cc_mdss_byte0_div_clk_src",
354 .parent_data = &(const struct clk_parent_data){
355 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
358 .ops = &clk_regmap_div_ops,
362 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
366 .clkr.hw.init = &(struct clk_init_data) {
367 .name = "disp_cc_mdss_dp_link_div_clk_src",
368 .parent_data = &(const struct clk_parent_data){
369 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
372 .ops = &clk_regmap_div_ops,
376 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
378 .halt_check = BRANCH_HALT,
380 .enable_reg = 0x202c,
381 .enable_mask = BIT(0),
382 .hw.init = &(struct clk_init_data){
383 .name = "disp_cc_mdss_byte0_intf_clk",
384 .parent_hws = (const struct clk_hw*[]){
385 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
388 .flags = CLK_SET_RATE_PARENT,
389 .ops = &clk_branch2_ops,
394 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
396 .halt_check = BRANCH_HALT,
398 .enable_reg = 0x2054,
399 .enable_mask = BIT(0),
400 .hw.init = &(struct clk_init_data){
401 .name = "disp_cc_mdss_dp_aux_clk",
402 .parent_hws = (const struct clk_hw*[]){
403 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
406 .flags = CLK_SET_RATE_PARENT,
407 .ops = &clk_branch2_ops,
412 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
414 .halt_check = BRANCH_HALT,
416 .enable_reg = 0x2048,
417 .enable_mask = BIT(0),
418 .hw.init = &(struct clk_init_data){
419 .name = "disp_cc_mdss_dp_crypto_clk",
420 .parent_hws = (const struct clk_hw*[]){
421 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
424 .flags = CLK_SET_RATE_PARENT,
425 .ops = &clk_branch2_ops,
430 static struct clk_branch disp_cc_mdss_dp_link_clk = {
432 .halt_check = BRANCH_HALT,
434 .enable_reg = 0x2040,
435 .enable_mask = BIT(0),
436 .hw.init = &(struct clk_init_data){
437 .name = "disp_cc_mdss_dp_link_clk",
438 .parent_hws = (const struct clk_hw*[]){
439 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
442 .flags = CLK_SET_RATE_PARENT,
443 .ops = &clk_branch2_ops,
448 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
450 .halt_check = BRANCH_HALT,
452 .enable_reg = 0x2044,
453 .enable_mask = BIT(0),
454 .hw.init = &(struct clk_init_data){
455 .name = "disp_cc_mdss_dp_link_intf_clk",
456 .parent_hws = (const struct clk_hw*[]){
457 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
460 .ops = &clk_branch2_ops,
465 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
467 .halt_check = BRANCH_HALT,
469 .enable_reg = 0x204c,
470 .enable_mask = BIT(0),
471 .hw.init = &(struct clk_init_data){
472 .name = "disp_cc_mdss_dp_pixel_clk",
473 .parent_hws = (const struct clk_hw*[]){
474 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
477 .flags = CLK_SET_RATE_PARENT,
478 .ops = &clk_branch2_ops,
483 static struct clk_branch disp_cc_mdss_esc0_clk = {
485 .halt_check = BRANCH_HALT,
487 .enable_reg = 0x2038,
488 .enable_mask = BIT(0),
489 .hw.init = &(struct clk_init_data){
490 .name = "disp_cc_mdss_esc0_clk",
491 .parent_hws = (const struct clk_hw*[]){
492 &disp_cc_mdss_esc0_clk_src.clkr.hw,
495 .flags = CLK_SET_RATE_PARENT,
496 .ops = &clk_branch2_ops,
501 static struct clk_branch disp_cc_mdss_mdp_clk = {
503 .halt_check = BRANCH_HALT,
505 .enable_reg = 0x200c,
506 .enable_mask = BIT(0),
507 .hw.init = &(struct clk_init_data){
508 .name = "disp_cc_mdss_mdp_clk",
509 .parent_hws = (const struct clk_hw*[]){
510 &disp_cc_mdss_mdp_clk_src.clkr.hw,
513 .flags = CLK_SET_RATE_PARENT,
514 .ops = &clk_branch2_ops,
519 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
521 .halt_check = BRANCH_VOTED,
523 .enable_reg = 0x201c,
524 .enable_mask = BIT(0),
525 .hw.init = &(struct clk_init_data){
526 .name = "disp_cc_mdss_mdp_lut_clk",
527 .parent_hws = (const struct clk_hw*[]){
528 &disp_cc_mdss_mdp_clk_src.clkr.hw,
531 .ops = &clk_branch2_ops,
536 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
538 .halt_check = BRANCH_VOTED,
540 .enable_reg = 0x4004,
541 .enable_mask = BIT(0),
542 .hw.init = &(struct clk_init_data){
543 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
544 .parent_hws = (const struct clk_hw*[]){
545 &disp_cc_mdss_ahb_clk_src.clkr.hw,
548 .flags = CLK_SET_RATE_PARENT,
549 .ops = &clk_branch2_ops,
554 static struct clk_branch disp_cc_mdss_pclk0_clk = {
556 .halt_check = BRANCH_HALT,
558 .enable_reg = 0x2004,
559 .enable_mask = BIT(0),
560 .hw.init = &(struct clk_init_data){
561 .name = "disp_cc_mdss_pclk0_clk",
562 .parent_hws = (const struct clk_hw*[]){
563 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
566 .flags = CLK_SET_RATE_PARENT,
567 .ops = &clk_branch2_ops,
572 static struct clk_branch disp_cc_mdss_rot_clk = {
574 .halt_check = BRANCH_HALT,
576 .enable_reg = 0x2014,
577 .enable_mask = BIT(0),
578 .hw.init = &(struct clk_init_data){
579 .name = "disp_cc_mdss_rot_clk",
580 .parent_hws = (const struct clk_hw*[]){
581 &disp_cc_mdss_rot_clk_src.clkr.hw,
584 .flags = CLK_SET_RATE_PARENT,
585 .ops = &clk_branch2_ops,
590 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
592 .halt_check = BRANCH_HALT,
594 .enable_reg = 0x4008,
595 .enable_mask = BIT(0),
596 .hw.init = &(struct clk_init_data){
597 .name = "disp_cc_mdss_rscc_vsync_clk",
598 .parent_hws = (const struct clk_hw*[]){
599 &disp_cc_mdss_vsync_clk_src.clkr.hw,
602 .flags = CLK_SET_RATE_PARENT,
603 .ops = &clk_branch2_ops,
608 static struct clk_branch disp_cc_mdss_vsync_clk = {
610 .halt_check = BRANCH_HALT,
612 .enable_reg = 0x2024,
613 .enable_mask = BIT(0),
614 .hw.init = &(struct clk_init_data){
615 .name = "disp_cc_mdss_vsync_clk",
616 .parent_hws = (const struct clk_hw*[]){
617 &disp_cc_mdss_vsync_clk_src.clkr.hw,
620 .flags = CLK_SET_RATE_PARENT,
621 .ops = &clk_branch2_ops,
626 static struct gdsc mdss_gdsc = {
628 .en_rest_wait_val = 0x2,
629 .en_few_wait_val = 0x2,
630 .clk_dis_wait_val = 0xf,
634 .pwrsts = PWRSTS_OFF_ON,
638 static struct gdsc *disp_cc_sc7180_gdscs[] = {
639 [MDSS_GDSC] = &mdss_gdsc,
642 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
643 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
644 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
645 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
646 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
647 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
648 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
649 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
650 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
651 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
652 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
653 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
654 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
655 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
656 &disp_cc_mdss_dp_link_div_clk_src.clkr,
657 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
658 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
659 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
660 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
661 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
662 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
663 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
664 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
665 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
666 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
667 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
668 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
669 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
670 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
671 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
672 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
673 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
674 [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
677 static const struct regmap_config disp_cc_sc7180_regmap_config = {
681 .max_register = 0x10000,
685 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
686 .config = &disp_cc_sc7180_regmap_config,
687 .clks = disp_cc_sc7180_clocks,
688 .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
689 .gdscs = disp_cc_sc7180_gdscs,
690 .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
693 static const struct of_device_id disp_cc_sc7180_match_table[] = {
694 { .compatible = "qcom,sc7180-dispcc" },
697 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
699 static int disp_cc_sc7180_probe(struct platform_device *pdev)
701 struct regmap *regmap;
702 struct alpha_pll_config disp_cc_pll_config = {};
704 regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
706 return PTR_ERR(regmap);
708 /* 1380MHz configuration */
709 disp_cc_pll_config.l = 0x47;
710 disp_cc_pll_config.alpha = 0xe000;
711 disp_cc_pll_config.user_ctl_val = 0x00000001;
712 disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
714 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
716 return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
719 static struct platform_driver disp_cc_sc7180_driver = {
720 .probe = disp_cc_sc7180_probe,
722 .name = "sc7180-dispcc",
723 .of_match_table = disp_cc_sc7180_match_table,
727 static int __init disp_cc_sc7180_init(void)
729 return platform_driver_register(&disp_cc_sc7180_driver);
731 subsys_initcall(disp_cc_sc7180_init);
733 static void __exit disp_cc_sc7180_exit(void)
735 platform_driver_unregister(&disp_cc_sc7180_driver);
737 module_exit(disp_cc_sc7180_exit);
739 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
740 MODULE_LICENSE("GPL v2");