1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
4 #ifndef __QCOM_CLK_ALPHA_PLL_H__
5 #define __QCOM_CLK_ALPHA_PLL_H__
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
12 CLK_ALPHA_PLL_TYPE_DEFAULT,
13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
17 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
18 CLK_ALPHA_PLL_TYPE_AGERA,
19 CLK_ALPHA_PLL_TYPE_ZONDA,
20 CLK_ALPHA_PLL_TYPE_MAX,
33 PLL_OFF_CONFIG_CTL_U1,
44 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
47 unsigned long min_freq;
48 unsigned long max_freq;
52 #define VCO(a, b, c) { \
59 * struct clk_alpha_pll - phase locked loop (PLL)
60 * @offset: base address of registers
61 * @vco_table: array of VCO settings
62 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
63 * @clkr: regmap clock handle
65 struct clk_alpha_pll {
69 const struct pll_vco *vco_table;
71 #define SUPPORTS_OFFLINE_REQ BIT(0)
72 #define SUPPORTS_FSM_MODE BIT(2)
73 #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
76 struct clk_regmap clkr;
80 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
81 * @offset: base address of registers
82 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
83 * @width: width of post-divider
84 * @post_div_shift: shift to differentiate between odd & even post-divider
85 * @post_div_table: table with PLL odd and even post-divider settings
86 * @num_post_div: Number of PLL post-divider settings
88 * @clkr: regmap clock handle
90 struct clk_alpha_pll_postdiv {
95 struct clk_regmap clkr;
97 const struct clk_div_table *post_div_table;
101 struct alpha_pll_config {
106 u32 config_ctl_hi_val;
107 u32 config_ctl_hi1_val;
110 u32 user_ctl_hi1_val;
113 u32 test_ctl_hi1_val;
114 u32 main_output_mask;
116 u32 aux2_output_mask;
117 u32 early_output_mask;
128 extern const struct clk_ops clk_alpha_pll_ops;
129 extern const struct clk_ops clk_alpha_pll_fixed_ops;
130 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
131 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
132 extern const struct clk_ops clk_alpha_pll_huayra_ops;
133 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
135 extern const struct clk_ops clk_alpha_pll_fabia_ops;
136 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
137 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
139 extern const struct clk_ops clk_alpha_pll_trion_ops;
140 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
141 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
143 extern const struct clk_ops clk_alpha_pll_lucid_ops;
144 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
145 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
146 extern const struct clk_ops clk_alpha_pll_agera_ops;
148 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
149 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
150 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
152 extern const struct clk_ops clk_alpha_pll_zonda_ops;
153 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
155 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
156 const struct alpha_pll_config *config);
157 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
158 const struct alpha_pll_config *config);
159 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
160 const struct alpha_pll_config *config);
161 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
162 const struct alpha_pll_config *config);
163 #define clk_lucid_pll_configure(pll, regmap, config) \
164 clk_trion_pll_configure(pll, regmap, config)
166 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
167 const struct alpha_pll_config *config);