drivers/clk/qcom/clk-alpha-pll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/export.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/regmap.h>
  10 #include <linux/delay.h>
  11
  12 #include "clk-alpha-pll.h"
  13 #include "common.h"
  14
  15 #define PLL_MODE(p)             ((p)->offset + 0x0)
  16 # define PLL_OUTCTRL            BIT(0)
  17 # define PLL_BYPASSNL           BIT(1)
  18 # define PLL_RESET_N            BIT(2)
  19 # define PLL_OFFLINE_REQ        BIT(7)
  20 # define PLL_LOCK_COUNT_SHIFT   8
  21 # define PLL_LOCK_COUNT_MASK    0x3f
  22 # define PLL_BIAS_COUNT_SHIFT   14
  23 # define PLL_BIAS_COUNT_MASK    0x3f
  24 # define PLL_VOTE_FSM_ENA       BIT(20)
  25 # define PLL_FSM_ENA            BIT(20)
  26 # define PLL_VOTE_FSM_RESET     BIT(21)
  27 # define PLL_UPDATE             BIT(22)
  28 # define PLL_UPDATE_BYPASS      BIT(23)
  29 # define PLL_OFFLINE_ACK        BIT(28)
  30 # define ALPHA_PLL_ACK_LATCH    BIT(29)
  31 # define PLL_ACTIVE_FLAG        BIT(30)
  32 # define PLL_LOCK_DET           BIT(31)
  33
  34 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
  35 #define PLL_CAL_L_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
  36 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
  37 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
  38
  39 #define PLL_USER_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
  40 # define PLL_POST_DIV_SHIFT     8
  41 # define PLL_POST_DIV_MASK(p)   GENMASK((p)->width, 0)
  42 # define PLL_ALPHA_EN           BIT(24)
  43 # define PLL_ALPHA_MODE         BIT(25)
  44 # define PLL_VCO_SHIFT          20
  45 # define PLL_VCO_MASK           0x3
  46
  47 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
  48 #define PLL_USER_CTL_U1(p)      ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
  49
  50 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
  51 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
  52 #define PLL_CONFIG_CTL_U1(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
  53 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
  54 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
  55 #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
  56 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
  57 #define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
  58 #define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
  59
  60 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  61         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
  62                 [PLL_OFF_L_VAL] = 0x04,
  63                 [PLL_OFF_ALPHA_VAL] = 0x08,
  64                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  65                 [PLL_OFF_USER_CTL] = 0x10,
  66                 [PLL_OFF_USER_CTL_U] = 0x14,
  67                 [PLL_OFF_CONFIG_CTL] = 0x18,
  68                 [PLL_OFF_TEST_CTL] = 0x1c,
  69                 [PLL_OFF_TEST_CTL_U] = 0x20,
  70                 [PLL_OFF_STATUS] = 0x24,
  71         },
  72         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  73                 [PLL_OFF_L_VAL] = 0x04,
  74                 [PLL_OFF_ALPHA_VAL] = 0x08,
  75                 [PLL_OFF_USER_CTL] = 0x10,
  76                 [PLL_OFF_CONFIG_CTL] = 0x14,
  77                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  78                 [PLL_OFF_TEST_CTL] = 0x1c,
  79                 [PLL_OFF_TEST_CTL_U] = 0x20,
  80                 [PLL_OFF_STATUS] = 0x24,
  81         },
  82         [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
  83                 [PLL_OFF_L_VAL] = 0x04,
  84                 [PLL_OFF_ALPHA_VAL] = 0x08,
  85                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  86                 [PLL_OFF_USER_CTL] = 0x10,
  87                 [PLL_OFF_CONFIG_CTL] = 0x18,
  88                 [PLL_OFF_TEST_CTL] = 0x1c,
  89                 [PLL_OFF_STATUS] = 0x24,
  90         },
  91         [CLK_ALPHA_PLL_TYPE_FABIA] =  {
  92                 [PLL_OFF_L_VAL] = 0x04,
  93                 [PLL_OFF_USER_CTL] = 0x0c,
  94                 [PLL_OFF_USER_CTL_U] = 0x10,
  95                 [PLL_OFF_CONFIG_CTL] = 0x14,
  96                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  97                 [PLL_OFF_TEST_CTL] = 0x1c,
  98                 [PLL_OFF_TEST_CTL_U] = 0x20,
  99                 [PLL_OFF_STATUS] = 0x24,
 100                 [PLL_OFF_OPMODE] = 0x2c,
 101                 [PLL_OFF_FRAC] = 0x38,
 102         },
 103         [CLK_ALPHA_PLL_TYPE_TRION] = {
 104                 [PLL_OFF_L_VAL] = 0x04,
 105                 [PLL_OFF_CAL_L_VAL] = 0x08,
 106                 [PLL_OFF_USER_CTL] = 0x0c,
 107                 [PLL_OFF_USER_CTL_U] = 0x10,
 108                 [PLL_OFF_USER_CTL_U1] = 0x14,
 109                 [PLL_OFF_CONFIG_CTL] = 0x18,
 110                 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
 111                 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
 112                 [PLL_OFF_TEST_CTL] = 0x24,
 113                 [PLL_OFF_TEST_CTL_U] = 0x28,
 114                 [PLL_OFF_TEST_CTL_U1] = 0x2c,
 115                 [PLL_OFF_STATUS] = 0x30,
 116                 [PLL_OFF_OPMODE] = 0x38,
 117                 [PLL_OFF_ALPHA_VAL] = 0x40,
 118         },
 119 };
 120 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 121
 122 /*
 123  * Even though 40 bits are present, use only 32 for ease of calculation.
 124  */
 125 #define ALPHA_REG_BITWIDTH      40
 126 #define ALPHA_REG_16BIT_WIDTH   16
 127 #define ALPHA_BITWIDTH          32U
 128 #define ALPHA_SHIFT(w)          min(w, ALPHA_BITWIDTH)
 129
 130 #define PLL_HUAYRA_M_WIDTH              8
 131 #define PLL_HUAYRA_M_SHIFT              8
 132 #define PLL_HUAYRA_M_MASK               0xff
 133 #define PLL_HUAYRA_N_SHIFT              0
 134 #define PLL_HUAYRA_N_MASK               0xff
 135 #define PLL_HUAYRA_ALPHA_WIDTH          16
 136
 137 #define PLL_STANDBY             0x0
 138 #define PLL_RUN                 0x1
 139 #define PLL_OUT_MASK            0x7
 140 #define PLL_RATE_MARGIN         500
 141
 142 /* TRION PLL specific settings and offsets */
 143 #define TRION_PLL_CAL_VAL       0x44
 144 #define TRION_PCAL_DONE         BIT(26)
 145
 146 /* LUCID PLL specific settings and offsets */
 147 #define LUCID_PCAL_DONE         BIT(27)
 148
 149 #define pll_alpha_width(p)                                      \
 150                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
 151                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
 152
 153 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
 154
 155 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
 156                                            struct clk_alpha_pll, clkr)
 157
 158 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
 159                                            struct clk_alpha_pll_postdiv, clkr)
 160
 161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 162                         const char *action)
 163 {
 164         u32 val;
 165         int count;
 166         int ret;
 167         const char *name = clk_hw_get_name(&pll->clkr.hw);
 168
 169         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 170         if (ret)
 171                 return ret;
 172
 173         for (count = 100; count > 0; count--) {
 174                 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 175                 if (ret)
 176                         return ret;
 177                 if (inverse && !(val & mask))
 178                         return 0;
 179                 else if ((val & mask) == mask)
 180                         return 0;
 181
 182                 udelay(1);
 183         }
 184
 185         WARN(1, "%s failed to %s!\n", name, action);
 186         return -ETIMEDOUT;
 187 }
 188
 189 #define wait_for_pll_enable_active(pll) \
 190         wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
 191
 192 #define wait_for_pll_enable_lock(pll) \
 193         wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
 194
 195 #define wait_for_pll_disable(pll) \
 196         wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
 197
 198 #define wait_for_pll_offline(pll) \
 199         wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 200
 201 #define wait_for_pll_update(pll) \
 202         wait_for_pll(pll, PLL_UPDATE, 1, "update")
 203
 204 #define wait_for_pll_update_ack_set(pll) \
 205         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
 206
 207 #define wait_for_pll_update_ack_clear(pll) \
 208         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
 209
 210 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 211                              const struct alpha_pll_config *config)
 212 {
 213         u32 val, mask;
 214
 215         regmap_write(regmap, PLL_L_VAL(pll), config->l);
 216         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
 217         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
 218
 219         if (pll_has_64bit_config(pll))
 220                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
 221                              config->config_ctl_hi_val);
 222
 223         if (pll_alpha_width(pll) > 32)
 224                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
 225
 226         val = config->main_output_mask;
 227         val |= config->aux_output_mask;
 228         val |= config->aux2_output_mask;
 229         val |= config->early_output_mask;
 230         val |= config->pre_div_val;
 231         val |= config->post_div_val;
 232         val |= config->vco_val;
 233         val |= config->alpha_en_mask;
 234         val |= config->alpha_mode_mask;
 235
 236         mask = config->main_output_mask;
 237         mask |= config->aux_output_mask;
 238         mask |= config->aux2_output_mask;
 239         mask |= config->early_output_mask;
 240         mask |= config->pre_div_mask;
 241         mask |= config->post_div_mask;
 242         mask |= config->vco_mask;
 243
 244         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 245
 246         if (pll->flags & SUPPORTS_FSM_MODE)
 247                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 248 }
 249 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 250
 251 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 252 {
 253         int ret;
 254         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 255         u32 val;
 256
 257         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 258         if (ret)
 259                 return ret;
 260
 261         val |= PLL_FSM_ENA;
 262
 263         if (pll->flags & SUPPORTS_OFFLINE_REQ)
 264                 val &= ~PLL_OFFLINE_REQ;
 265
 266         ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
 267         if (ret)
 268                 return ret;
 269
 270         /* Make sure enable request goes through before waiting for update */
 271         mb();
 272
 273         return wait_for_pll_enable_active(pll);
 274 }
 275
 276 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 277 {
 278         int ret;
 279         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 280         u32 val;
 281
 282         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 283         if (ret)
 284                 return;
 285
 286         if (pll->flags & SUPPORTS_OFFLINE_REQ) {
 287                 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 288                                          PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 289                 if (ret)
 290                         return;
 291
 292                 ret = wait_for_pll_offline(pll);
 293                 if (ret)
 294                         return;
 295         }
 296
 297         /* Disable hwfsm */
 298         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 299                                  PLL_FSM_ENA, 0);
 300         if (ret)
 301                 return;
 302
 303         wait_for_pll_disable(pll);
 304 }
 305
 306 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 307 {
 308         int ret;
 309         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 310         u32 val;
 311
 312         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 313         if (ret)
 314                 return ret;
 315
 316         return !!(val & mask);
 317 }
 318
 319 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
 320 {
 321         return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
 322 }
 323
 324 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
 325 {
 326         return pll_is_enabled(hw, PLL_LOCK_DET);
 327 }
 328
 329 static int clk_alpha_pll_enable(struct clk_hw *hw)
 330 {
 331         int ret;
 332         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 333         u32 val, mask;
 334
 335         mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 336         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 337         if (ret)
 338                 return ret;
 339
 340         /* If in FSM mode, just vote for it */
 341         if (val & PLL_VOTE_FSM_ENA) {
 342                 ret = clk_enable_regmap(hw);
 343                 if (ret)
 344                         return ret;
 345                 return wait_for_pll_enable_active(pll);
 346         }
 347
 348         /* Skip if already enabled */
 349         if ((val & mask) == mask)
 350                 return 0;
 351
 352         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 353                                  PLL_BYPASSNL, PLL_BYPASSNL);
 354         if (ret)
 355                 return ret;
 356
 357         /*
 358          * H/W requires a 5us delay between disabling the bypass and
 359          * de-asserting the reset.
 360          */
 361         mb();
 362         udelay(5);
 363
 364         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 365                                  PLL_RESET_N, PLL_RESET_N);
 366         if (ret)
 367                 return ret;
 368
 369         ret = wait_for_pll_enable_lock(pll);
 370         if (ret)
 371                 return ret;
 372
 373         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 374                                  PLL_OUTCTRL, PLL_OUTCTRL);
 375
 376         /* Ensure that the write above goes through before returning. */
 377         mb();
 378         return ret;
 379 }
 380
 381 static void clk_alpha_pll_disable(struct clk_hw *hw)
 382 {
 383         int ret;
 384         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 385         u32 val, mask;
 386
 387         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 388         if (ret)
 389                 return;
 390
 391         /* If in FSM mode, just unvote it */
 392         if (val & PLL_VOTE_FSM_ENA) {
 393                 clk_disable_regmap(hw);
 394                 return;
 395         }
 396
 397         mask = PLL_OUTCTRL;
 398         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 399
 400         /* Delay of 2 output clock ticks required until output is disabled */
 401         mb();
 402         udelay(1);
 403
 404         mask = PLL_RESET_N | PLL_BYPASSNL;
 405         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 406 }
 407
 408 static unsigned long
 409 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 410 {
 411         return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 412 }
 413
 414 static unsigned long
 415 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
 416                      u32 alpha_width)
 417 {
 418         u64 remainder;
 419         u64 quotient;
 420
 421         quotient = rate;
 422         remainder = do_div(quotient, prate);
 423         *l = quotient;
 424
 425         if (!remainder) {
 426                 *a = 0;
 427                 return rate;
 428         }
 429
 430         /* Upper ALPHA_BITWIDTH bits of Alpha */
 431         quotient = remainder << ALPHA_SHIFT(alpha_width);
 432
 433         remainder = do_div(quotient, prate);
 434
 435         if (remainder)
 436                 quotient++;
 437
 438         *a = quotient;
 439         return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
 440 }
 441
 442 static const struct pll_vco *
 443 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
 444 {
 445         const struct pll_vco *v = pll->vco_table;
 446         const struct pll_vco *end = v + pll->num_vco;
 447
 448         for (; v < end; v++)
 449                 if (rate >= v->min_freq && rate <= v->max_freq)
 450                         return v;
 451
 452         return NULL;
 453 }
 454
 455 static unsigned long
 456 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 457 {
 458         u32 l, low, high, ctl;
 459         u64 a = 0, prate = parent_rate;
 460         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 461         u32 alpha_width = pll_alpha_width(pll);
 462
 463         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 464
 465         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 466         if (ctl & PLL_ALPHA_EN) {
 467                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
 468                 if (alpha_width > 32) {
 469                         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 470                                     &high);
 471                         a = (u64)high << 32 | low;
 472                 } else {
 473                         a = low & GENMASK(alpha_width - 1, 0);
 474                 }
 475
 476                 if (alpha_width > ALPHA_BITWIDTH)
 477                         a >>= alpha_width - ALPHA_BITWIDTH;
 478         }
 479
 480         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 481 }
 482
 483
 484 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
 485 {
 486         int ret;
 487         u32 mode;
 488
 489         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 490
 491         /* Latch the input to the PLL */
 492         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
 493                            PLL_UPDATE);
 494
 495         /* Wait for 2 reference cycle before checking ACK bit */
 496         udelay(1);
 497
 498         /*
 499          * PLL will latch the new L, Alpha and freq control word.
 500          * PLL will respond by raising PLL_ACK_LATCH output when new programming
 501          * has been latched in and PLL is being updated. When
 502          * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
 503          * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
 504          */
 505         if (mode & PLL_UPDATE_BYPASS) {
 506                 ret = wait_for_pll_update_ack_set(pll);
 507                 if (ret)
 508                         return ret;
 509
 510                 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
 511         } else {
 512                 ret = wait_for_pll_update(pll);
 513                 if (ret)
 514                         return ret;
 515         }
 516
 517         ret = wait_for_pll_update_ack_clear(pll);
 518         if (ret)
 519                 return ret;
 520
 521         /* Wait for PLL output to stabilize */
 522         udelay(10);
 523
 524         return 0;
 525 }
 526
 527 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
 528                                       int (*is_enabled)(struct clk_hw *))
 529 {
 530         if (!is_enabled(&pll->clkr.hw) ||
 531             !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
 532                 return 0;
 533
 534         return __clk_alpha_pll_update_latch(pll);
 535 }
 536
 537 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 538                                     unsigned long prate,
 539                                     int (*is_enabled)(struct clk_hw *))
 540 {
 541         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 542         const struct pll_vco *vco;
 543         u32 l, alpha_width = pll_alpha_width(pll);
 544         u64 a;
 545
 546         rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 547         vco = alpha_pll_find_vco(pll, rate);
 548         if (pll->vco_table && !vco) {
 549                 pr_err("%s: alpha pll not in a valid vco range\n",
 550                        clk_hw_get_name(hw));
 551                 return -EINVAL;
 552         }
 553
 554         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 555
 556         if (alpha_width > ALPHA_BITWIDTH)
 557                 a <<= alpha_width - ALPHA_BITWIDTH;
 558
 559         if (alpha_width > 32)
 560                 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
 561
 562         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 563
 564         if (vco) {
 565                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 566                                    PLL_VCO_MASK << PLL_VCO_SHIFT,
 567                                    vco->val << PLL_VCO_SHIFT);
 568         }
 569
 570         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 571                            PLL_ALPHA_EN, PLL_ALPHA_EN);
 572
 573         return clk_alpha_pll_update_latch(pll, is_enabled);
 574 }
 575
 576 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 577                                   unsigned long prate)
 578 {
 579         return __clk_alpha_pll_set_rate(hw, rate, prate,
 580                                         clk_alpha_pll_is_enabled);
 581 }
 582
 583 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
 584                                         unsigned long prate)
 585 {
 586         return __clk_alpha_pll_set_rate(hw, rate, prate,
 587                                         clk_alpha_pll_hwfsm_is_enabled);
 588 }
 589
 590 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 591                                      unsigned long *prate)
 592 {
 593         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 594         u32 l, alpha_width = pll_alpha_width(pll);
 595         u64 a;
 596         unsigned long min_freq, max_freq;
 597
 598         rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
 599         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 600                 return rate;
 601
 602         min_freq = pll->vco_table[0].min_freq;
 603         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 604
 605         return clamp(rate, min_freq, max_freq);
 606 }
 607
 608 static unsigned long
 609 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
 610 {
 611         /*
 612          * a contains 16 bit alpha_val in two’s complement number in the range
 613          * of [-0.5, 0.5).
 614          */
 615         if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 616                 l -= 1;
 617
 618         return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
 619 }
 620
 621 static unsigned long
 622 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
 623                             u32 *l, u32 *a)
 624 {
 625         u64 remainder;
 626         u64 quotient;
 627
 628         quotient = rate;
 629         remainder = do_div(quotient, prate);
 630         *l = quotient;
 631
 632         if (!remainder) {
 633                 *a = 0;
 634                 return rate;
 635         }
 636
 637         quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
 638         remainder = do_div(quotient, prate);
 639
 640         if (remainder)
 641                 quotient++;
 642
 643         /*
 644          * alpha_val should be in two’s complement number in the range
 645          * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
 646          * since alpha value will be subtracted in this case.
 647          */
 648         if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 649                 *l += 1;
 650
 651         *a = quotient;
 652         return alpha_huayra_pll_calc_rate(prate, *l, *a);
 653 }
 654
 655 static unsigned long
 656 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 657 {
 658         u64 rate = parent_rate, tmp;
 659         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 660         u32 l, alpha = 0, ctl, alpha_m, alpha_n;
 661
 662         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 663         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 664
 665         if (ctl & PLL_ALPHA_EN) {
 666                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
 667                 /*
 668                  * Depending upon alpha_mode, it can be treated as M/N value or
 669                  * as a two’s complement number. When alpha_mode=1,
 670                  * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
 671                  *
 672                  *              Fout=FIN*(L+(M/N))
 673                  *
 674                  * M is a signed number (-128 to 127) and N is unsigned
 675                  * (0 to 255). M/N has to be within +/-0.5.
 676                  *
 677                  * When alpha_mode=0, it is a two’s complement number in the
 678                  * range [-0.5, 0.5).
 679                  *
 680                  *              Fout=FIN*(L+(alpha_val)/2^16)
 681                  *
 682                  * where alpha_val is two’s complement number.
 683                  */
 684                 if (!(ctl & PLL_ALPHA_MODE))
 685                         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 686
 687                 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
 688                 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
 689
 690                 rate *= l;
 691                 tmp = parent_rate;
 692                 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
 693                         alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
 694                         tmp *= alpha_m;
 695                         do_div(tmp, alpha_n);
 696                         rate -= tmp;
 697                 } else {
 698                         tmp *= alpha_m;
 699                         do_div(tmp, alpha_n);
 700                         rate += tmp;
 701                 }
 702
 703                 return rate;
 704         }
 705
 706         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 707 }
 708
 709 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 710                                      unsigned long prate)
 711 {
 712         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 713         u32 l, a, ctl, cur_alpha = 0;
 714
 715         rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
 716
 717         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 718
 719         if (ctl & PLL_ALPHA_EN)
 720                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
 721
 722         /*
 723          * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
 724          * without having to go through the power on sequence.
 725          */
 726         if (clk_alpha_pll_is_enabled(hw)) {
 727                 if (cur_alpha != a) {
 728                         pr_err("%s: clock needs to be gated\n",
 729                                clk_hw_get_name(hw));
 730                         return -EBUSY;
 731                 }
 732
 733                 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 734                 /* Ensure that the write above goes to detect L val change. */
 735                 mb();
 736                 return wait_for_pll_enable_lock(pll);
 737         }
 738
 739         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 740         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 741
 742         if (a == 0)
 743                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 744                                    PLL_ALPHA_EN, 0x0);
 745         else
 746                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 747                                    PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
 748
 749         return 0;
 750 }
 751
 752 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 753                                         unsigned long *prate)
 754 {
 755         u32 l, a;
 756
 757         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 758 }
 759
 760 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
 761                                 struct regmap *regmap)
 762 {
 763         u32 mode_regval, opmode_regval;
 764         int ret;
 765
 766         ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
 767         ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
 768         if (ret)
 769                 return 0;
 770
 771         return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
 772 }
 773
 774 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
 775 {
 776         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 777
 778         return trion_pll_is_enabled(pll, pll->clkr.regmap);
 779 }
 780
 781 static int clk_trion_pll_enable(struct clk_hw *hw)
 782 {
 783         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 784         struct regmap *regmap = pll->clkr.regmap;
 785         u32 val;
 786         int ret;
 787
 788         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 789         if (ret)
 790                 return ret;
 791
 792         /* If in FSM mode, just vote for it */
 793         if (val & PLL_VOTE_FSM_ENA) {
 794                 ret = clk_enable_regmap(hw);
 795                 if (ret)
 796                         return ret;
 797                 return wait_for_pll_enable_active(pll);
 798         }
 799
 800         /* Set operation mode to RUN */
 801         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 802
 803         ret = wait_for_pll_enable_lock(pll);
 804         if (ret)
 805                 return ret;
 806
 807         /* Enable the PLL outputs */
 808         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 809                                  PLL_OUT_MASK, PLL_OUT_MASK);
 810         if (ret)
 811                 return ret;
 812
 813         /* Enable the global PLL outputs */
 814         return regmap_update_bits(regmap, PLL_MODE(pll),
 815                                  PLL_OUTCTRL, PLL_OUTCTRL);
 816 }
 817
 818 static void clk_trion_pll_disable(struct clk_hw *hw)
 819 {
 820         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 821         struct regmap *regmap = pll->clkr.regmap;
 822         u32 val;
 823         int ret;
 824
 825         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 826         if (ret)
 827                 return;
 828
 829         /* If in FSM mode, just unvote it */
 830         if (val & PLL_VOTE_FSM_ENA) {
 831                 clk_disable_regmap(hw);
 832                 return;
 833         }
 834
 835         /* Disable the global PLL output */
 836         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
 837         if (ret)
 838                 return;
 839
 840         /* Disable the PLL outputs */
 841         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 842                                  PLL_OUT_MASK, 0);
 843         if (ret)
 844                 return;
 845
 846         /* Place the PLL mode in STANDBY */
 847         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 848         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 849 }
 850
 851 static unsigned long
 852 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 853 {
 854         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 855         u32 l, frac, alpha_width = pll_alpha_width(pll);
 856
 857         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 858         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
 859
 860         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
 861 }
 862
 863 const struct clk_ops clk_alpha_pll_fixed_ops = {
 864         .enable = clk_alpha_pll_enable,
 865         .disable = clk_alpha_pll_disable,
 866         .is_enabled = clk_alpha_pll_is_enabled,
 867         .recalc_rate = clk_alpha_pll_recalc_rate,
 868 };
 869 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
 870
 871 const struct clk_ops clk_alpha_pll_ops = {
 872         .enable = clk_alpha_pll_enable,
 873         .disable = clk_alpha_pll_disable,
 874         .is_enabled = clk_alpha_pll_is_enabled,
 875         .recalc_rate = clk_alpha_pll_recalc_rate,
 876         .round_rate = clk_alpha_pll_round_rate,
 877         .set_rate = clk_alpha_pll_set_rate,
 878 };
 879 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 880
 881 const struct clk_ops clk_alpha_pll_huayra_ops = {
 882         .enable = clk_alpha_pll_enable,
 883         .disable = clk_alpha_pll_disable,
 884         .is_enabled = clk_alpha_pll_is_enabled,
 885         .recalc_rate = alpha_pll_huayra_recalc_rate,
 886         .round_rate = alpha_pll_huayra_round_rate,
 887         .set_rate = alpha_pll_huayra_set_rate,
 888 };
 889 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
 890
 891 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 892         .enable = clk_alpha_pll_hwfsm_enable,
 893         .disable = clk_alpha_pll_hwfsm_disable,
 894         .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
 895         .recalc_rate = clk_alpha_pll_recalc_rate,
 896         .round_rate = clk_alpha_pll_round_rate,
 897         .set_rate = clk_alpha_pll_hwfsm_set_rate,
 898 };
 899 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 900
 901 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
 902         .enable = clk_trion_pll_enable,
 903         .disable = clk_trion_pll_disable,
 904         .is_enabled = clk_trion_pll_is_enabled,
 905         .recalc_rate = clk_trion_pll_recalc_rate,
 906         .round_rate = clk_alpha_pll_round_rate,
 907 };
 908 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
 909
 910 static unsigned long
 911 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 912 {
 913         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 914         u32 ctl;
 915
 916         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 917
 918         ctl >>= PLL_POST_DIV_SHIFT;
 919         ctl &= PLL_POST_DIV_MASK(pll);
 920
 921         return parent_rate >> fls(ctl);
 922 }
 923
 924 static const struct clk_div_table clk_alpha_div_table[] = {
 925         { 0x0, 1 },
 926         { 0x1, 2 },
 927         { 0x3, 4 },
 928         { 0x7, 8 },
 929         { 0xf, 16 },
 930         { }
 931 };
 932
 933 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
 934         { 0x0, 1 },
 935         { 0x1, 2 },
 936         { 0x3, 4 },
 937         { }
 938 };
 939
 940 static long
 941 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
 942                                  unsigned long *prate)
 943 {
 944         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 945         const struct clk_div_table *table;
 946
 947         if (pll->width == 2)
 948                 table = clk_alpha_2bit_div_table;
 949         else
 950                 table = clk_alpha_div_table;
 951
 952         return divider_round_rate(hw, rate, prate, table,
 953                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
 954 }
 955
 956 static long
 957 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
 958                                     unsigned long *prate)
 959 {
 960         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 961         u32 ctl, div;
 962
 963         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 964
 965         ctl >>= PLL_POST_DIV_SHIFT;
 966         ctl &= BIT(pll->width) - 1;
 967         div = 1 << fls(ctl);
 968
 969         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
 970                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
 971
 972         return DIV_ROUND_UP_ULL((u64)*prate, div);
 973 }
 974
 975 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 976                                           unsigned long parent_rate)
 977 {
 978         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 979         int div;
 980
 981         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
 982         div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
 983
 984         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 985                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
 986                                   div << PLL_POST_DIV_SHIFT);
 987 }
 988
 989 const struct clk_ops clk_alpha_pll_postdiv_ops = {
 990         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 991         .round_rate = clk_alpha_pll_postdiv_round_rate,
 992         .set_rate = clk_alpha_pll_postdiv_set_rate,
 993 };
 994 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
 995
 996 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
 997         .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
 998         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 999 };
1000 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1001
1002 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1003                              const struct alpha_pll_config *config)
1004 {
1005         u32 val, mask;
1006
1007         if (config->l)
1008                 regmap_write(regmap, PLL_L_VAL(pll), config->l);
1009
1010         if (config->alpha)
1011                 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
1012
1013         if (config->config_ctl_val)
1014                 regmap_write(regmap, PLL_CONFIG_CTL(pll),
1015                                                 config->config_ctl_val);
1016
1017         if (config->config_ctl_hi_val)
1018                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
1019                                                 config->config_ctl_hi_val);
1020
1021         if (config->user_ctl_val)
1022                 regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1023
1024         if (config->user_ctl_hi_val)
1025                 regmap_write(regmap, PLL_USER_CTL_U(pll),
1026                                                 config->user_ctl_hi_val);
1027
1028         if (config->test_ctl_val)
1029                 regmap_write(regmap, PLL_TEST_CTL(pll),
1030                                                 config->test_ctl_val);
1031
1032         if (config->test_ctl_hi_val)
1033                 regmap_write(regmap, PLL_TEST_CTL_U(pll),
1034                                                 config->test_ctl_hi_val);
1035
1036         if (config->post_div_mask) {
1037                 mask = config->post_div_mask;
1038                 val = config->post_div_val;
1039                 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1040         }
1041
1042         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1043                                                         PLL_UPDATE_BYPASS);
1044
1045         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1046 }
1047 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1048
1049 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1050 {
1051         int ret;
1052         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1053         u32 val, opmode_val;
1054         struct regmap *regmap = pll->clkr.regmap;
1055
1056         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1057         if (ret)
1058                 return ret;
1059
1060         /* If in FSM mode, just vote for it */
1061         if (val & PLL_VOTE_FSM_ENA) {
1062                 ret = clk_enable_regmap(hw);
1063                 if (ret)
1064                         return ret;
1065                 return wait_for_pll_enable_active(pll);
1066         }
1067
1068         ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1069         if (ret)
1070                 return ret;
1071
1072         /* Skip If PLL is already running */
1073         if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1074                 return 0;
1075
1076         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1077         if (ret)
1078                 return ret;
1079
1080         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1081         if (ret)
1082                 return ret;
1083
1084         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1085                                  PLL_RESET_N);
1086         if (ret)
1087                 return ret;
1088
1089         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1090         if (ret)
1091                 return ret;
1092
1093         ret = wait_for_pll_enable_lock(pll);
1094         if (ret)
1095                 return ret;
1096
1097         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1098                                  PLL_OUT_MASK, PLL_OUT_MASK);
1099         if (ret)
1100                 return ret;
1101
1102         return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1103                                  PLL_OUTCTRL);
1104 }
1105
1106 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1107 {
1108         int ret;
1109         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1110         u32 val;
1111         struct regmap *regmap = pll->clkr.regmap;
1112
1113         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1114         if (ret)
1115                 return;
1116
1117         /* If in FSM mode, just unvote it */
1118         if (val & PLL_FSM_ENA) {
1119                 clk_disable_regmap(hw);
1120                 return;
1121         }
1122
1123         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1124         if (ret)
1125                 return;
1126
1127         /* Disable main outputs */
1128         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1129         if (ret)
1130                 return;
1131
1132         /* Place the PLL in STANDBY */
1133         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1134 }
1135
1136 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1137                                                 unsigned long parent_rate)
1138 {
1139         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1140         u32 l, frac, alpha_width = pll_alpha_width(pll);
1141
1142         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1143         regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1144
1145         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1146 }
1147
1148 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1149                                                 unsigned long prate)
1150 {
1151         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1152         u32 l, alpha_width = pll_alpha_width(pll);
1153         u64 a;
1154         unsigned long rrate, max = rate + PLL_RATE_MARGIN;
1155
1156         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1157
1158         /*
1159          * Due to limited number of bits for fractional rate programming, the
1160          * rounded up rate could be marginally higher than the requested rate.
1161          */
1162         if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
1163                 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1164                        clk_hw_get_name(hw), rrate, rate, max);
1165                 return -EINVAL;
1166         }
1167
1168         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1169         regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1170
1171         return __clk_alpha_pll_update_latch(pll);
1172 }
1173
1174 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1175 {
1176         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1177         const struct pll_vco *vco;
1178         struct clk_hw *parent_hw;
1179         unsigned long cal_freq, rrate;
1180         u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1181         const char *name = clk_hw_get_name(hw);
1182         u64 a;
1183         int ret;
1184
1185         /* Check if calibration needs to be done i.e. PLL is in reset */
1186         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1187         if (ret)
1188                 return ret;
1189
1190         /* Return early if calibration is not needed. */
1191         if (val & PLL_RESET_N)
1192                 return 0;
1193
1194         vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1195         if (!vco) {
1196                 pr_err("%s: alpha pll not in a valid vco range\n", name);
1197                 return -EINVAL;
1198         }
1199
1200         cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1201                                 pll->vco_table[0].max_freq) * 54, 100);
1202
1203         parent_hw = clk_hw_get_parent(hw);
1204         if (!parent_hw)
1205                 return -EINVAL;
1206
1207         rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1208                                         &cal_l, &a, alpha_width);
1209         /*
1210          * Due to a limited number of bits for fractional rate programming, the
1211          * rounded up rate could be marginally higher than the requested rate.
1212          */
1213         if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
1214                 return -EINVAL;
1215
1216         /* Setup PLL for calibration frequency */
1217         regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1218
1219         /* Bringup the PLL at calibration frequency */
1220         ret = clk_alpha_pll_enable(hw);
1221         if (ret) {
1222                 pr_err("%s: alpha pll calibration failed\n", name);
1223                 return ret;
1224         }
1225
1226         clk_alpha_pll_disable(hw);
1227
1228         return 0;
1229 }
1230
1231 const struct clk_ops clk_alpha_pll_fabia_ops = {
1232         .prepare = alpha_pll_fabia_prepare,
1233         .enable = alpha_pll_fabia_enable,
1234         .disable = alpha_pll_fabia_disable,
1235         .is_enabled = clk_alpha_pll_is_enabled,
1236         .set_rate = alpha_pll_fabia_set_rate,
1237         .recalc_rate = alpha_pll_fabia_recalc_rate,
1238         .round_rate = clk_alpha_pll_round_rate,
1239 };
1240 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1241
1242 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1243         .enable = alpha_pll_fabia_enable,
1244         .disable = alpha_pll_fabia_disable,
1245         .is_enabled = clk_alpha_pll_is_enabled,
1246         .recalc_rate = alpha_pll_fabia_recalc_rate,
1247         .round_rate = clk_alpha_pll_round_rate,
1248 };
1249 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1250
1251 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1252                                         unsigned long parent_rate)
1253 {
1254         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1255         u32 i, div = 1, val;
1256         int ret;
1257
1258         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1259         if (ret)
1260                 return ret;
1261
1262         val >>= pll->post_div_shift;
1263         val &= BIT(pll->width) - 1;
1264
1265         for (i = 0; i < pll->num_post_div; i++) {
1266                 if (pll->post_div_table[i].val == val) {
1267                         div = pll->post_div_table[i].div;
1268                         break;
1269                 }
1270         }
1271
1272         return (parent_rate / div);
1273 }
1274
1275 static unsigned long
1276 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1277 {
1278         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1279         struct regmap *regmap = pll->clkr.regmap;
1280         u32 i, div = 1, val;
1281
1282         regmap_read(regmap, PLL_USER_CTL(pll), &val);
1283
1284         val >>= pll->post_div_shift;
1285         val &= PLL_POST_DIV_MASK(pll);
1286
1287         for (i = 0; i < pll->num_post_div; i++) {
1288                 if (pll->post_div_table[i].val == val) {
1289                         div = pll->post_div_table[i].div;
1290                         break;
1291                 }
1292         }
1293
1294         return (parent_rate / div);
1295 }
1296
1297 static long
1298 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1299                                  unsigned long *prate)
1300 {
1301         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1302
1303         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1304                                   pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1305 };
1306
1307 static int
1308 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1309                                unsigned long parent_rate)
1310 {
1311         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1312         struct regmap *regmap = pll->clkr.regmap;
1313         int i, val = 0, div;
1314
1315         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1316         for (i = 0; i < pll->num_post_div; i++) {
1317                 if (pll->post_div_table[i].div == div) {
1318                         val = pll->post_div_table[i].val;
1319                         break;
1320                 }
1321         }
1322
1323         return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1324                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1325                                   val << PLL_POST_DIV_SHIFT);
1326 }
1327
1328 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1329         .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1330         .round_rate = clk_trion_pll_postdiv_round_rate,
1331         .set_rate = clk_trion_pll_postdiv_set_rate,
1332 };
1333 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1334
1335 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1336                                 unsigned long rate, unsigned long *prate)
1337 {
1338         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1339
1340         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1341                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1342 }
1343
1344 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1345                                 unsigned long rate, unsigned long parent_rate)
1346 {
1347         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1348         int i, val = 0, div, ret;
1349
1350         /*
1351          * If the PLL is in FSM mode, then treat set_rate callback as a
1352          * no-operation.
1353          */
1354         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1355         if (ret)
1356                 return ret;
1357
1358         if (val & PLL_VOTE_FSM_ENA)
1359                 return 0;
1360
1361         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1362         for (i = 0; i < pll->num_post_div; i++) {
1363                 if (pll->post_div_table[i].div == div) {
1364                         val = pll->post_div_table[i].val;
1365                         break;
1366                 }
1367         }
1368
1369         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1370                                 (BIT(pll->width) - 1) << pll->post_div_shift,
1371                                 val << pll->post_div_shift);
1372 }
1373
1374 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1375         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1376         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1377         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1378 };
1379 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1380
1381 /**
1382  * clk_trion_pll_configure - configure the trion pll
1383  *
1384  * @pll: clk alpha pll
1385  * @regmap: register map
1386  * @config: configuration to apply for pll
1387  */
1388 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1389                              const struct alpha_pll_config *config)
1390 {
1391         if (config->l)
1392                 regmap_write(regmap, PLL_L_VAL(pll), config->l);
1393
1394         regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1395
1396         if (config->alpha)
1397                 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1398
1399         if (config->config_ctl_val)
1400                 regmap_write(regmap, PLL_CONFIG_CTL(pll),
1401                              config->config_ctl_val);
1402
1403         if (config->config_ctl_hi_val)
1404                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
1405                              config->config_ctl_hi_val);
1406
1407         if (config->config_ctl_hi1_val)
1408                 regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
1409                              config->config_ctl_hi1_val);
1410
1411         if (config->user_ctl_val)
1412                 regmap_write(regmap, PLL_USER_CTL(pll),
1413                              config->user_ctl_val);
1414
1415         if (config->user_ctl_hi_val)
1416                 regmap_write(regmap, PLL_USER_CTL_U(pll),
1417                              config->user_ctl_hi_val);
1418
1419         if (config->user_ctl_hi1_val)
1420                 regmap_write(regmap, PLL_USER_CTL_U1(pll),
1421                              config->user_ctl_hi1_val);
1422
1423         if (config->test_ctl_val)
1424                 regmap_write(regmap, PLL_TEST_CTL(pll),
1425                              config->test_ctl_val);
1426
1427         if (config->test_ctl_hi_val)
1428                 regmap_write(regmap, PLL_TEST_CTL_U(pll),
1429                              config->test_ctl_hi_val);
1430
1431         if (config->test_ctl_hi1_val)
1432                 regmap_write(regmap, PLL_TEST_CTL_U1(pll),
1433                              config->test_ctl_hi1_val);
1434
1435         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1436                            PLL_UPDATE_BYPASS);
1437
1438         /* Disable PLL output */
1439         regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1440
1441         /* Set operation mode to OFF */
1442         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1443
1444         /* Place the PLL in STANDBY mode */
1445         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1446 }
1447 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1448
1449 /*
1450  * The TRION PLL requires a power-on self-calibration which happens when the
1451  * PLL comes out of reset. Calibrate in case it is not completed.
1452  */
1453 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1454 {
1455         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1456         u32 regval;
1457         int ret;
1458
1459         /* Return early if calibration is not needed. */
1460         regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
1461         if (regval & pcal_done)
1462                 return 0;
1463
1464         /* On/off to calibrate */
1465         ret = clk_trion_pll_enable(hw);
1466         if (!ret)
1467                 clk_trion_pll_disable(hw);
1468
1469         return ret;
1470 }
1471
1472 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1473 {
1474         return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1475 }
1476
1477 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1478 {
1479         return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1480 }
1481
1482 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1483                                     unsigned long prate)
1484 {
1485         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1486         unsigned long rrate;
1487         u32 regval, l, alpha_width = pll_alpha_width(pll);
1488         u64 a;
1489         int ret;
1490
1491         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1492
1493         /*
1494          * Due to a limited number of bits for fractional rate programming, the
1495          * rounded up rate could be marginally higher than the requested rate.
1496          */
1497         if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
1498                 pr_err("Call set rate on the PLL with rounded rates!\n");
1499                 return -EINVAL;
1500         }
1501
1502         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1503         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1504
1505         /* Latch the PLL input */
1506         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
1507                                  PLL_UPDATE, PLL_UPDATE);
1508         if (ret)
1509                 return ret;
1510
1511         /* Wait for 2 reference cycles before checking the ACK bit. */
1512         udelay(1);
1513         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
1514         if (!(regval & ALPHA_PLL_ACK_LATCH)) {
1515                 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1516                 return -EINVAL;
1517         }
1518
1519         /* Return the latch input to 0 */
1520         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
1521                                  PLL_UPDATE, 0);
1522         if (ret)
1523                 return ret;
1524
1525         if (clk_hw_is_enabled(hw)) {
1526                 ret = wait_for_pll_enable_lock(pll);
1527                 if (ret)
1528                         return ret;
1529         }
1530
1531         /* Wait for PLL output to stabilize */
1532         udelay(100);
1533         return 0;
1534 }
1535
1536 const struct clk_ops clk_alpha_pll_trion_ops = {
1537         .prepare = alpha_pll_trion_prepare,
1538         .enable = clk_trion_pll_enable,
1539         .disable = clk_trion_pll_disable,
1540         .is_enabled = clk_trion_pll_is_enabled,
1541         .recalc_rate = clk_trion_pll_recalc_rate,
1542         .round_rate = clk_alpha_pll_round_rate,
1543         .set_rate = alpha_pll_trion_set_rate,
1544 };
1545 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1546
1547 const struct clk_ops clk_alpha_pll_lucid_ops = {
1548         .prepare = alpha_pll_lucid_prepare,
1549         .enable = clk_trion_pll_enable,
1550         .disable = clk_trion_pll_disable,
1551         .is_enabled = clk_trion_pll_is_enabled,
1552         .recalc_rate = clk_trion_pll_recalc_rate,
1553         .round_rate = clk_alpha_pll_round_rate,
1554         .set_rate = alpha_pll_trion_set_rate,
1555 };
1556 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1557
1558 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1559         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1560         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1561         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1562 };
1563 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);