2 * Marvell Orion SoC clocks
4 * Copyright (C) 2014 Thomas Petazzoni
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/clk-provider.h>
19 static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
20 { .id = 0, .name = "ddrclk", }
27 #define SAR_MV88F5181_TCLK_FREQ 8
28 #define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
30 static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
32 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
33 SAR_MV88F5181_TCLK_FREQ_MASK;
44 #define SAR_MV88F5181_CPU_FREQ 4
45 #define SAR_MV88F5181_CPU_FREQ_MASK 0xf
47 static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
49 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
50 SAR_MV88F5181_CPU_FREQ_MASK;
53 else if (opt == 1 || opt == 2)
61 static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
64 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
65 SAR_MV88F5181_CPU_FREQ_MASK;
66 if (opt == 0 || opt == 1) {
69 } else if (opt == 2 || opt == 3) {
78 static const struct coreclk_soc_desc mv88f5181_coreclks = {
79 .get_tclk_freq = mv88f5181_get_tclk_freq,
80 .get_cpu_freq = mv88f5181_get_cpu_freq,
81 .get_clk_ratio = mv88f5181_get_clk_ratio,
82 .ratios = orion_coreclk_ratios,
83 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
86 static void __init mv88f5181_clk_init(struct device_node *np)
88 return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
91 CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
97 #define SAR_MV88F5182_TCLK_FREQ 8
98 #define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
100 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
102 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
103 SAR_MV88F5182_TCLK_FREQ_MASK;
112 #define SAR_MV88F5182_CPU_FREQ 4
113 #define SAR_MV88F5182_CPU_FREQ_MASK 0xf
115 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
117 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
118 SAR_MV88F5182_CPU_FREQ_MASK;
121 else if (opt == 1 || opt == 2)
129 static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
132 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
133 SAR_MV88F5182_CPU_FREQ_MASK;
134 if (opt == 0 || opt == 1) {
137 } else if (opt == 2 || opt == 3) {
146 static const struct coreclk_soc_desc mv88f5182_coreclks = {
147 .get_tclk_freq = mv88f5182_get_tclk_freq,
148 .get_cpu_freq = mv88f5182_get_cpu_freq,
149 .get_clk_ratio = mv88f5182_get_clk_ratio,
150 .ratios = orion_coreclk_ratios,
151 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
154 static void __init mv88f5182_clk_init(struct device_node *np)
156 return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
159 CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
165 static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
167 /* On 5281, tclk is always 166 Mhz */
171 #define SAR_MV88F5281_CPU_FREQ 4
172 #define SAR_MV88F5281_CPU_FREQ_MASK 0xf
174 static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
176 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
177 SAR_MV88F5281_CPU_FREQ_MASK;
178 if (opt == 1 || opt == 2)
186 static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
189 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
190 SAR_MV88F5281_CPU_FREQ_MASK;
194 } else if (opt == 2 || opt == 3) {
203 static const struct coreclk_soc_desc mv88f5281_coreclks = {
204 .get_tclk_freq = mv88f5281_get_tclk_freq,
205 .get_cpu_freq = mv88f5281_get_cpu_freq,
206 .get_clk_ratio = mv88f5281_get_clk_ratio,
207 .ratios = orion_coreclk_ratios,
208 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
211 static void __init mv88f5281_clk_init(struct device_node *np)
213 return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
216 CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
222 #define SAR_MV88F6183_TCLK_FREQ 9
223 #define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
225 static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
227 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
228 SAR_MV88F6183_TCLK_FREQ_MASK;
237 #define SAR_MV88F6183_CPU_FREQ 1
238 #define SAR_MV88F6183_CPU_FREQ_MASK 0x3f
240 static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
242 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
243 SAR_MV88F6183_CPU_FREQ_MASK;
252 static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
255 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
256 SAR_MV88F6183_CPU_FREQ_MASK;
257 if (opt == 9 || opt == 17) {
266 static const struct coreclk_soc_desc mv88f6183_coreclks = {
267 .get_tclk_freq = mv88f6183_get_tclk_freq,
268 .get_cpu_freq = mv88f6183_get_cpu_freq,
269 .get_clk_ratio = mv88f6183_get_clk_ratio,
270 .ratios = orion_coreclk_ratios,
271 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
275 static void __init mv88f6183_clk_init(struct device_node *np)
277 return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
280 CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);