2 * Marvell Armada CP110 System Controller
4 * Copyright (C) 2016 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 * CP110 has 6 core clocks:
17 * - PPv2 core (1/3 PLL0)
18 * - x2 Core (1/2 PLL0)
19 * - Core (1/2 x2 Core)
22 * - NAND clock, which is either:
23 * - Equal to SDIO clock
26 * CP110 has 32 gatable clocks, for the various peripherals in the IP.
29 #define pr_fmt(fmt) "cp110-system-controller: " fmt
31 #include <linux/clk-provider.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/init.h>
35 #include <linux/of_address.h>
36 #include <linux/platform_device.h>
37 #include <linux/regmap.h>
38 #include <linux/slab.h>
40 #define CP110_PM_CLOCK_GATING_REG 0x220
41 #define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
42 #define NF_CLOCK_SEL_400_MASK BIT(0)
46 CP110_CLK_TYPE_GATABLE,
49 #define CP110_MAX_CORE_CLOCKS 6
50 #define CP110_MAX_GATABLE_CLOCKS 32
52 #define CP110_CLK_NUM \
53 (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
55 #define CP110_CORE_PLL0 0
56 #define CP110_CORE_PPV2 1
57 #define CP110_CORE_X2CORE 2
58 #define CP110_CORE_CORE 3
59 #define CP110_CORE_NAND 4
60 #define CP110_CORE_SDIO 5
62 /* A number of gatable clocks need special handling */
63 #define CP110_GATE_AUDIO 0
64 #define CP110_GATE_COMM_UNIT 1
65 #define CP110_GATE_NAND 2
66 #define CP110_GATE_PPV2 3
67 #define CP110_GATE_SDIO 4
68 #define CP110_GATE_MG 5
69 #define CP110_GATE_MG_CORE 6
70 #define CP110_GATE_XOR1 7
71 #define CP110_GATE_XOR0 8
72 #define CP110_GATE_GOP_DP 9
73 #define CP110_GATE_PCIE_X1_0 11
74 #define CP110_GATE_PCIE_X1_1 12
75 #define CP110_GATE_PCIE_X4 13
76 #define CP110_GATE_PCIE_XOR 14
77 #define CP110_GATE_SATA 15
78 #define CP110_GATE_SATA_USB 16
79 #define CP110_GATE_MAIN 17
80 #define CP110_GATE_SDMMC_GOP 18
81 #define CP110_GATE_SLOW_IO 21
82 #define CP110_GATE_USB3H0 22
83 #define CP110_GATE_USB3H1 23
84 #define CP110_GATE_USB3DEV 24
85 #define CP110_GATE_EIP150 25
86 #define CP110_GATE_EIP197 26
88 static const char * const gate_base_names[] = {
89 [CP110_GATE_AUDIO] = "audio",
90 [CP110_GATE_COMM_UNIT] = "communit",
91 [CP110_GATE_NAND] = "nand",
92 [CP110_GATE_PPV2] = "ppv2",
93 [CP110_GATE_SDIO] = "sdio",
94 [CP110_GATE_MG] = "mg-domain",
95 [CP110_GATE_MG_CORE] = "mg-core",
96 [CP110_GATE_XOR1] = "xor1",
97 [CP110_GATE_XOR0] = "xor0",
98 [CP110_GATE_GOP_DP] = "gop-dp",
99 [CP110_GATE_PCIE_X1_0] = "pcie_x10",
100 [CP110_GATE_PCIE_X1_1] = "pcie_x11",
101 [CP110_GATE_PCIE_X4] = "pcie_x4",
102 [CP110_GATE_PCIE_XOR] = "pcie-xor",
103 [CP110_GATE_SATA] = "sata",
104 [CP110_GATE_SATA_USB] = "sata-usb",
105 [CP110_GATE_MAIN] = "main",
106 [CP110_GATE_SDMMC_GOP] = "sd-mmc-gop",
107 [CP110_GATE_SLOW_IO] = "slow-io",
108 [CP110_GATE_USB3H0] = "usb3h0",
109 [CP110_GATE_USB3H1] = "usb3h1",
110 [CP110_GATE_USB3DEV] = "usb3dev",
111 [CP110_GATE_EIP150] = "eip150",
112 [CP110_GATE_EIP197] = "eip197"
115 struct cp110_gate_clk {
117 struct regmap *regmap;
121 #define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
123 static int cp110_gate_enable(struct clk_hw *hw)
125 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
127 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
128 BIT(gate->bit_idx), BIT(gate->bit_idx));
133 static void cp110_gate_disable(struct clk_hw *hw)
135 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
137 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
138 BIT(gate->bit_idx), 0);
141 static int cp110_gate_is_enabled(struct clk_hw *hw)
143 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
146 regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
148 return val & BIT(gate->bit_idx);
151 static const struct clk_ops cp110_gate_ops = {
152 .enable = cp110_gate_enable,
153 .disable = cp110_gate_disable,
154 .is_enabled = cp110_gate_is_enabled,
157 static struct clk_hw *cp110_register_gate(const char *name,
158 const char *parent_name,
159 struct regmap *regmap, u8 bit_idx)
161 struct cp110_gate_clk *gate;
163 struct clk_init_data init;
166 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
168 return ERR_PTR(-ENOMEM);
170 memset(&init, 0, sizeof(init));
173 init.ops = &cp110_gate_ops;
174 init.parent_names = &parent_name;
175 init.num_parents = 1;
177 gate->regmap = regmap;
178 gate->bit_idx = bit_idx;
179 gate->hw.init = &init;
182 ret = clk_hw_register(NULL, hw);
191 static void cp110_unregister_gate(struct clk_hw *hw)
193 clk_hw_unregister(hw);
194 kfree(to_cp110_gate_clk(hw));
197 static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
200 struct clk_hw_onecell_data *clk_data = data;
201 unsigned int type = clkspec->args[0];
202 unsigned int idx = clkspec->args[1];
204 if (type == CP110_CLK_TYPE_CORE) {
205 if (idx >= CP110_MAX_CORE_CLOCKS)
206 return ERR_PTR(-EINVAL);
207 return clk_data->hws[idx];
208 } else if (type == CP110_CLK_TYPE_GATABLE) {
209 if (idx >= CP110_MAX_GATABLE_CLOCKS)
210 return ERR_PTR(-EINVAL);
211 return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
214 return ERR_PTR(-EINVAL);
217 static char *cp110_unique_name(struct device *dev, struct device_node *np,
223 /* Do not create a name if there is no clock */
227 reg = of_get_property(np, "reg", NULL);
228 addr = of_translate_address(np, reg);
229 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
230 (unsigned long long)addr, name);
233 static int cp110_syscon_common_probe(struct platform_device *pdev,
234 struct device_node *syscon_node)
236 struct regmap *regmap;
237 struct device *dev = &pdev->dev;
238 struct device_node *np = dev->of_node;
239 const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name,
241 struct clk_hw_onecell_data *cp110_clk_data;
242 struct clk_hw *hw, **cp110_clks;
245 char *gate_name[ARRAY_SIZE(gate_base_names)];
247 regmap = syscon_node_to_regmap(syscon_node);
249 return PTR_ERR(regmap);
251 ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
256 cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
257 sizeof(struct clk_hw *) * CP110_CLK_NUM,
262 cp110_clks = cp110_clk_data->hws;
263 cp110_clk_data->num = CP110_CLK_NUM;
265 /* Register the PLL0 which is the root of the hw tree */
266 pll0_name = cp110_unique_name(dev, syscon_node, "pll0");
267 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
274 cp110_clks[CP110_CORE_PLL0] = hw;
277 ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core");
278 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
284 cp110_clks[CP110_CORE_PPV2] = hw;
286 /* X2CORE clock is PLL0/2 */
287 x2core_name = cp110_unique_name(dev, syscon_node, "x2core");
288 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
295 cp110_clks[CP110_CORE_X2CORE] = hw;
297 /* Core clock is X2CORE/2 */
298 core_name = cp110_unique_name(dev, syscon_node, "core");
299 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
306 cp110_clks[CP110_CORE_CORE] = hw;
307 /* NAND can be either PLL0/2.5 or core clock */
308 nand_name = cp110_unique_name(dev, syscon_node, "nand-core");
309 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
310 hw = clk_hw_register_fixed_factor(NULL, nand_name,
313 hw = clk_hw_register_fixed_factor(NULL, nand_name,
320 cp110_clks[CP110_CORE_NAND] = hw;
322 /* SDIO clock is PLL0/2.5 */
323 sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
324 hw = clk_hw_register_fixed_factor(NULL, sdio_name,
331 cp110_clks[CP110_CORE_SDIO] = hw;
333 /* create the unique name for all the gate clocks */
334 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
335 gate_name[i] = cp110_unique_name(dev, syscon_node,
338 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
341 if (gate_name[i] == NULL)
345 case CP110_GATE_NAND:
349 case CP110_GATE_GOP_DP:
350 case CP110_GATE_PPV2:
353 case CP110_GATE_SDIO:
356 case CP110_GATE_MAIN:
357 case CP110_GATE_PCIE_XOR:
358 case CP110_GATE_PCIE_X4:
359 case CP110_GATE_EIP150:
360 case CP110_GATE_EIP197:
361 parent = x2core_name;
367 hw = cp110_register_gate(gate_name[i], parent, regmap, i);
374 cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
377 ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
381 platform_set_drvdata(pdev, cp110_clks);
387 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
388 hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
391 cp110_unregister_gate(hw);
394 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
396 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
398 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
400 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]);
402 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
404 clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]);
409 static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev)
411 dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
412 dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
413 dev_warn(&pdev->dev, FW_WARN
414 "This binding won't be supported in future kernels\n");
416 return cp110_syscon_common_probe(pdev, pdev->dev.of_node);
419 static int cp110_clk_probe(struct platform_device *pdev)
421 return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent);
424 static const struct of_device_id cp110_syscon_legacy_of_match[] = {
425 { .compatible = "marvell,cp110-system-controller0", },
429 static struct platform_driver cp110_syscon_legacy_driver = {
430 .probe = cp110_syscon_legacy_clk_probe,
432 .name = "marvell-cp110-system-controller0",
433 .of_match_table = cp110_syscon_legacy_of_match,
434 .suppress_bind_attrs = true,
437 builtin_platform_driver(cp110_syscon_legacy_driver);
439 static const struct of_device_id cp110_clock_of_match[] = {
440 { .compatible = "marvell,cp110-clock", },
444 static struct platform_driver cp110_clock_driver = {
445 .probe = cp110_clk_probe,
447 .name = "marvell-cp110-clock",
448 .of_match_table = cp110_clock_of_match,
449 .suppress_bind_attrs = true,
452 builtin_platform_driver(cp110_clock_driver);