2 * Marvell Armada AP806 System Controller
4 * Copyright (C) 2016 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #define pr_fmt(fmt) "ap806-system-controller: " fmt
15 #include <linux/clk-provider.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
23 #define AP806_SAR_REG 0x400
24 #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
26 #define AP806_CLK_NUM 4
28 static struct clk *ap806_clks[AP806_CLK_NUM];
30 static struct clk_onecell_data ap806_clk_data = {
32 .clk_num = AP806_CLK_NUM,
35 static int ap806_syscon_clk_probe(struct platform_device *pdev)
37 unsigned int freq_mode, cpuclk_freq;
38 const char *name, *fixedclk_name;
39 struct device_node *np = pdev->dev.of_node;
40 struct regmap *regmap;
44 regmap = syscon_node_to_regmap(np);
46 dev_err(&pdev->dev, "cannot get regmap\n");
47 return PTR_ERR(regmap);
50 ret = regmap_read(regmap, AP806_SAR_REG, ®);
52 dev_err(&pdev->dev, "cannot read from regmap\n");
56 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
92 dev_err(&pdev->dev, "invalid SAR value\n");
96 /* Convert to hertz */
97 cpuclk_freq *= 1000 * 1000;
99 /* CPU clocks depend on the Sample At Reset configuration */
100 of_property_read_string_index(np, "clock-output-names",
102 ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL,
104 if (IS_ERR(ap806_clks[0])) {
105 ret = PTR_ERR(ap806_clks[0]);
109 of_property_read_string_index(np, "clock-output-names",
111 ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0,
113 if (IS_ERR(ap806_clks[1])) {
114 ret = PTR_ERR(ap806_clks[1]);
118 /* Fixed clock is always 1200 Mhz */
119 of_property_read_string_index(np, "clock-output-names",
121 ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL,
122 0, 1200 * 1000 * 1000);
123 if (IS_ERR(ap806_clks[2])) {
124 ret = PTR_ERR(ap806_clks[2]);
128 /* MSS Clock is fixed clock divided by 6 */
129 of_property_read_string_index(np, "clock-output-names",
131 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
133 if (IS_ERR(ap806_clks[3])) {
134 ret = PTR_ERR(ap806_clks[3]);
138 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
145 clk_unregister_fixed_factor(ap806_clks[3]);
147 clk_unregister_fixed_rate(ap806_clks[2]);
149 clk_unregister_fixed_rate(ap806_clks[1]);
151 clk_unregister_fixed_rate(ap806_clks[0]);
156 static int ap806_syscon_clk_remove(struct platform_device *pdev)
158 of_clk_del_provider(pdev->dev.of_node);
159 clk_unregister_fixed_factor(ap806_clks[3]);
160 clk_unregister_fixed_rate(ap806_clks[2]);
161 clk_unregister_fixed_rate(ap806_clks[1]);
162 clk_unregister_fixed_rate(ap806_clks[0]);
167 static const struct of_device_id ap806_syscon_of_match[] = {
168 { .compatible = "marvell,ap806-system-controller", },
171 MODULE_DEVICE_TABLE(of, armada8k_pcie_of_match);
173 static struct platform_driver ap806_syscon_driver = {
174 .probe = ap806_syscon_clk_probe,
175 .remove = ap806_syscon_clk_remove,
177 .name = "marvell-ap806-system-controller",
178 .of_match_table = ap806_syscon_of_match,
182 module_platform_driver(ap806_syscon_driver);
184 MODULE_DESCRIPTION("Marvell AP806 System Controller driver");
185 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
186 MODULE_LICENSE("GPL");