drivers/clk/mmp/clk-of-pxa168.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * pxa168 clock framework source file
   4  *
   5  * Copyright (C) 2012 Marvell
   6  * Chao Xie <xiechao.mail@gmail.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/of_address.h>
  16
  17 #include <dt-bindings/clock/marvell,pxa168.h>
  18
  19 #include "clk.h"
  20 #include "reset.h"
  21
  22 #define APBC_UART0      0x0
  23 #define APBC_UART1      0x4
  24 #define APBC_GPIO       0x8
  25 #define APBC_PWM0       0xc
  26 #define APBC_PWM1       0x10
  27 #define APBC_PWM2       0x14
  28 #define APBC_PWM3       0x18
  29 #define APBC_RTC        0x28
  30 #define APBC_TWSI0      0x2c
  31 #define APBC_KPC        0x30
  32 #define APBC_TIMER      0x34
  33 #define APBC_AIB        0x3c
  34 #define APBC_SW_JTAG    0x40
  35 #define APBC_ONEWIRE    0x48
  36 #define APBC_TWSI1      0x6c
  37 #define APBC_UART2      0x70
  38 #define APBC_AC97       0x84
  39 #define APBC_SSP0       0x81c
  40 #define APBC_SSP1       0x820
  41 #define APBC_SSP2       0x84c
  42 #define APBC_SSP3       0x858
  43 #define APBC_SSP4       0x85c
  44 #define APMU_DISP0      0x4c
  45 #define APMU_CCIC0      0x50
  46 #define APMU_SDH0       0x54
  47 #define APMU_SDH1       0x58
  48 #define APMU_USB        0x5c
  49 #define APMU_DFC        0x60
  50 #define APMU_DMA        0x64
  51 #define APMU_BUS        0x6c
  52 #define APMU_GC         0xcc
  53 #define APMU_SMC        0xd4
  54 #define APMU_XD         0xdc
  55 #define APMU_SDH2       0xe0
  56 #define APMU_SDH3       0xe4
  57 #define APMU_CF         0xf0
  58 #define APMU_MSP        0xf4
  59 #define APMU_CMU        0xf8
  60 #define APMU_FE         0xfc
  61 #define APMU_PCIE       0x100
  62 #define APMU_EPD        0x104
  63 #define MPMU_UART_PLL   0x14
  64
  65 #define NR_CLKS         200
  66
  67 struct pxa168_clk_unit {
  68         struct mmp_clk_unit unit;
  69         void __iomem *mpmu_base;
  70         void __iomem *apmu_base;
  71         void __iomem *apbc_base;
  72 };
  73
  74 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
  75         {PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
  76         {PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
  77         {PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
  78         {PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
  79 };
  80
  81 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
  82         {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
  83         {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
  84         {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
  85         {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
  86         {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
  87         {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
  88         {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
  89         {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
  90         {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
  91         {PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
  92         {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
  93         {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0},
  94         {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0},
  95         {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
  96         {PXA168_CLK_PLL1_2_1_10, "pll1_2_1_10", "pll1_2", 1, 10, 0},
  97         {PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
  98         {PXA168_CLK_CLK32_2, "clk32_2", "clk32", 1, 2, 0},
  99 };
 100
 101 static struct mmp_clk_factor_masks uart_factor_masks = {
 102         .factor = 2,
 103         .num_mask = 0x1fff,
 104         .den_mask = 0x1fff,
 105         .num_shift = 16,
 106         .den_shift = 0,
 107 };
 108
 109 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
 110         {.num = 8125, .den = 1536},     /*14.745MHZ */
 111 };
 112
 113 static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
 114 {
 115         struct clk *clk;
 116         struct mmp_clk_unit *unit = &pxa_unit->unit;
 117
 118         mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
 119                                         ARRAY_SIZE(fixed_rate_clks));
 120
 121         mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
 122                                         ARRAY_SIZE(fixed_factor_clks));
 123
 124         clk = mmp_clk_register_factor("uart_pll", "pll1_4",
 125                                 CLK_SET_RATE_PARENT,
 126                                 pxa_unit->mpmu_base + MPMU_UART_PLL,
 127                                 &uart_factor_masks, uart_factor_tbl,
 128                                 ARRAY_SIZE(uart_factor_tbl), NULL);
 129         mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
 130 }
 131
 132 static DEFINE_SPINLOCK(twsi0_lock);
 133 static DEFINE_SPINLOCK(twsi1_lock);
 134 static const char * const twsi_parent_names[] = {"pll1_2_1_10", "pll1_2_1_5"};
 135
 136 static DEFINE_SPINLOCK(kpc_lock);
 137 static const char * const kpc_parent_names[] = {"clk32", "clk32_2", "pll1_24"};
 138
 139 static DEFINE_SPINLOCK(pwm0_lock);
 140 static DEFINE_SPINLOCK(pwm1_lock);
 141 static DEFINE_SPINLOCK(pwm2_lock);
 142 static DEFINE_SPINLOCK(pwm3_lock);
 143 static const char * const pwm_parent_names[] = {"pll1_48", "clk32"};
 144
 145 static DEFINE_SPINLOCK(uart0_lock);
 146 static DEFINE_SPINLOCK(uart1_lock);
 147 static DEFINE_SPINLOCK(uart2_lock);
 148 static const char * const uart_parent_names[] = {"pll1_2_3_16", "uart_pll"};
 149
 150 static DEFINE_SPINLOCK(ssp0_lock);
 151 static DEFINE_SPINLOCK(ssp1_lock);
 152 static DEFINE_SPINLOCK(ssp2_lock);
 153 static DEFINE_SPINLOCK(ssp3_lock);
 154 static DEFINE_SPINLOCK(ssp4_lock);
 155 static const char * const ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
 156
 157 static DEFINE_SPINLOCK(timer_lock);
 158 static const char * const timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"};
 159
 160 static DEFINE_SPINLOCK(reset_lock);
 161
 162 static struct mmp_param_mux_clk apbc_mux_clks[] = {
 163         {0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
 164         {0, "twsi1_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
 165         {0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3, 0, &kpc_lock},
 166         {0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
 167         {0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
 168         {0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
 169         {0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
 170         {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
 171         {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
 172         {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
 173         {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
 174         {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
 175         {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
 176         {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
 177         {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
 178         {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
 179 };
 180
 181 static struct mmp_param_gate_clk apbc_gate_clks[] = {
 182         {PXA168_CLK_TWSI0, "twsi0_clk", "twsi0_mux", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &twsi0_lock},
 183         {PXA168_CLK_TWSI1, "twsi1_clk", "twsi1_mux", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &twsi1_lock},
 184         {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock},
 185         {PXA168_CLK_KPC, "kpc_clk", "kpc_mux", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &kpc_lock},
 186         {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
 187         {PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_lock},
 188         {PXA168_CLK_PWM1, "pwm1_clk", "pwm1_mux", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &pwm1_lock},
 189         {PXA168_CLK_PWM2, "pwm2_clk", "pwm2_mux", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &pwm2_lock},
 190         {PXA168_CLK_PWM3, "pwm3_clk", "pwm3_mux", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &pwm3_lock},
 191         {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
 192         {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
 193         {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
 194         {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
 195         {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
 196         {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
 197         {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
 198         {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
 199         {PXA168_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x3, 0x3, 0x0, 0, &timer_lock},
 200 };
 201
 202 static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
 203 {
 204         struct mmp_clk_unit *unit = &pxa_unit->unit;
 205
 206         mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
 207                                 ARRAY_SIZE(apbc_mux_clks));
 208
 209         mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
 210                                 ARRAY_SIZE(apbc_gate_clks));
 211
 212 }
 213
 214 static DEFINE_SPINLOCK(dfc_lock);
 215 static const char * const dfc_parent_names[] = {"pll1_4", "pll1_8"};
 216
 217 static DEFINE_SPINLOCK(sdh0_lock);
 218 static DEFINE_SPINLOCK(sdh1_lock);
 219 static DEFINE_SPINLOCK(sdh2_lock);
 220 static DEFINE_SPINLOCK(sdh3_lock);
 221 static const char * const sdh_parent_names[] = {"pll1_13", "pll1_12", "pll1_8"};
 222
 223 static DEFINE_SPINLOCK(usb_lock);
 224
 225 static DEFINE_SPINLOCK(disp0_lock);
 226 static const char * const disp_parent_names[] = {"pll1", "pll1_2"};
 227
 228 static DEFINE_SPINLOCK(ccic0_lock);
 229 static const char * const ccic_parent_names[] = {"pll1_4", "pll1_8"};
 230 static const char * const ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
 231
 232 static struct mmp_param_mux_clk apmu_mux_clks[] = {
 233         {0, "dfc_mux", dfc_parent_names, ARRAY_SIZE(dfc_parent_names), CLK_SET_RATE_PARENT, APMU_DFC, 6, 1, 0, &dfc_lock},
 234         {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 2, 0, &sdh0_lock},
 235         {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 2, 0, &sdh1_lock},
 236         {0, "sdh2_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH2, 6, 2, 0, &sdh2_lock},
 237         {0, "sdh3_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH3, 6, 2, 0, &sdh3_lock},
 238         {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
 239         {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
 240         {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
 241 };
 242
 243 static struct mmp_param_div_clk apmu_div_clks[] = {
 244         {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
 245 };
 246
 247 static struct mmp_param_gate_clk apmu_gate_clks[] = {
 248         {PXA168_CLK_DFC, "dfc_clk", "dfc_mux", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, &dfc_lock},
 249         {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
 250         {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
 251         {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
 252         {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
 253         {PXA168_CLK_SDH2, "sdh2_clk", "sdh2_mux", CLK_SET_RATE_PARENT, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock},
 254         {PXA168_CLK_SDH3, "sdh3_clk", "sdh3_mux", CLK_SET_RATE_PARENT, APMU_SDH3, 0x12, 0x12, 0x0, 0, &sdh3_lock},
 255         /* SDH0/1 and 2/3 AXI clocks are also gated by common bits in SDH0 and SDH2 registers */
 256         {PXA168_CLK_SDH01_AXI, "sdh01_axi_clk", NULL, CLK_SET_RATE_PARENT, APMU_SDH0, 0x9, 0x9, 0x0, 0, &sdh0_lock},
 257         {PXA168_CLK_SDH23_AXI, "sdh23_axi_clk", NULL, CLK_SET_RATE_PARENT, APMU_SDH2, 0x9, 0x9, 0x0, 0, &sdh2_lock},
 258         {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
 259         {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
 260         {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
 261         {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
 262 };
 263
 264 static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
 265 {
 266         struct mmp_clk_unit *unit = &pxa_unit->unit;
 267
 268         mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
 269                                 ARRAY_SIZE(apmu_mux_clks));
 270
 271         mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
 272                                 ARRAY_SIZE(apmu_div_clks));
 273
 274         mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
 275                                 ARRAY_SIZE(apmu_gate_clks));
 276 }
 277
 278 static void pxa168_clk_reset_init(struct device_node *np,
 279                                 struct pxa168_clk_unit *pxa_unit)
 280 {
 281         struct mmp_clk_reset_cell *cells;
 282         int i, nr_resets;
 283
 284         nr_resets = ARRAY_SIZE(apbc_gate_clks);
 285         cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
 286         if (!cells)
 287                 return;
 288
 289         for (i = 0; i < nr_resets; i++) {
 290                 cells[i].clk_id = apbc_gate_clks[i].id;
 291                 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
 292                 cells[i].flags = 0;
 293                 cells[i].lock = apbc_gate_clks[i].lock;
 294                 cells[i].bits = 0x4;
 295         }
 296
 297         mmp_clk_reset_register(np, cells, nr_resets);
 298 }
 299
 300 static void __init pxa168_clk_init(struct device_node *np)
 301 {
 302         struct pxa168_clk_unit *pxa_unit;
 303
 304         pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
 305         if (!pxa_unit)
 306                 return;
 307
 308         pxa_unit->mpmu_base = of_iomap(np, 0);
 309         if (!pxa_unit->mpmu_base) {
 310                 pr_err("failed to map mpmu registers\n");
 311                 kfree(pxa_unit);
 312                 return;
 313         }
 314
 315         pxa_unit->apmu_base = of_iomap(np, 1);
 316         if (!pxa_unit->apmu_base) {
 317                 pr_err("failed to map apmu registers\n");
 318                 kfree(pxa_unit);
 319                 return;
 320         }
 321
 322         pxa_unit->apbc_base = of_iomap(np, 2);
 323         if (!pxa_unit->apbc_base) {
 324                 pr_err("failed to map apbc registers\n");
 325                 kfree(pxa_unit);
 326                 return;
 327         }
 328
 329         mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
 330
 331         pxa168_pll_init(pxa_unit);
 332
 333         pxa168_apb_periph_clk_init(pxa_unit);
 334
 335         pxa168_axi_periph_clk_init(pxa_unit);
 336
 337         pxa168_clk_reset_init(np, pxa_unit);
 338 }
 339
 340 CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);