1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
6 * Sample clock generator divider:
7 * This HW divider gates with value 0 but is otherwise a zero based divider:
12 * The duty cycle may also be set for the LR clock variant. The duty cycle
16 * duty_cycle = (1 + hi) / (1 + val)
19 #include <linux/clk-provider.h>
20 #include <linux/module.h>
22 #include "clk-regmap.h"
25 static inline struct meson_sclk_div_data *
26 meson_sclk_div_data(struct clk_regmap *clk)
28 return (struct meson_sclk_div_data *)clk->data;
31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
33 return (1 << sclk->div.width) - 1;
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
38 return sclk_div_maxval(sclk) + 1;
41 static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
42 unsigned long prate, int maxdiv)
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
46 return clamp(div, 2, maxdiv);
49 static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
51 struct meson_sclk_div_data *sclk)
53 struct clk_hw *parent = clk_hw_get_parent(hw);
55 unsigned long maxdiv, now, parent_now;
56 unsigned long best = 0, best_parent = 0;
61 maxdiv = sclk_div_maxdiv(sclk);
63 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
64 return sclk_div_getdiv(hw, rate, *prate, maxdiv);
67 * The maximum divider we can use without overflowing
68 * unsigned long in rate * i below
70 maxdiv = min(ULONG_MAX / rate, maxdiv);
72 for (i = 2; i <= maxdiv; i++) {
74 * It's the most ideal case if the requested rate can be
75 * divided from parent clock without needing to change
76 * parent rate, so return the divider immediately.
78 if (rate * i == *prate)
81 parent_now = clk_hw_round_rate(parent, rate * i);
82 now = DIV_ROUND_UP_ULL((u64)parent_now, i);
84 if (abs(rate - now) < abs(rate - best)) {
87 best_parent = parent_now;
92 bestdiv = sclk_div_maxdiv(sclk);
99 static int sclk_div_determine_rate(struct clk_hw *hw,
100 struct clk_rate_request *req)
102 struct clk_regmap *clk = to_clk_regmap(hw);
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
107 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
112 static void sclk_apply_ratio(struct clk_regmap *clk,
113 struct meson_sclk_div_data *sclk)
115 unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
116 sclk->cached_duty.num,
117 sclk->cached_duty.den);
122 meson_parm_write(clk->map, &sclk->hi, hi);
125 static int sclk_div_set_duty_cycle(struct clk_hw *hw,
126 struct clk_duty *duty)
128 struct clk_regmap *clk = to_clk_regmap(hw);
129 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
131 if (MESON_PARM_APPLICABLE(&sclk->hi)) {
132 memcpy(&sclk->cached_duty, duty, sizeof(*duty));
133 sclk_apply_ratio(clk, sclk);
139 static int sclk_div_get_duty_cycle(struct clk_hw *hw,
140 struct clk_duty *duty)
142 struct clk_regmap *clk = to_clk_regmap(hw);
143 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
146 if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
152 hi = meson_parm_read(clk->map, &sclk->hi);
154 duty->den = sclk->cached_div;
158 static void sclk_apply_divider(struct clk_regmap *clk,
159 struct meson_sclk_div_data *sclk)
161 if (MESON_PARM_APPLICABLE(&sclk->hi))
162 sclk_apply_ratio(clk, sclk);
164 meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
167 static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
170 struct clk_regmap *clk = to_clk_regmap(hw);
171 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
172 unsigned long maxdiv = sclk_div_maxdiv(sclk);
174 sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
176 if (clk_hw_is_enabled(hw))
177 sclk_apply_divider(clk, sclk);
182 static unsigned long sclk_div_recalc_rate(struct clk_hw *hw,
185 struct clk_regmap *clk = to_clk_regmap(hw);
186 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
188 return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
191 static int sclk_div_enable(struct clk_hw *hw)
193 struct clk_regmap *clk = to_clk_regmap(hw);
194 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
196 sclk_apply_divider(clk, sclk);
201 static void sclk_div_disable(struct clk_hw *hw)
203 struct clk_regmap *clk = to_clk_regmap(hw);
204 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
206 meson_parm_write(clk->map, &sclk->div, 0);
209 static int sclk_div_is_enabled(struct clk_hw *hw)
211 struct clk_regmap *clk = to_clk_regmap(hw);
212 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
214 if (meson_parm_read(clk->map, &sclk->div))
220 static int sclk_div_init(struct clk_hw *hw)
222 struct clk_regmap *clk = to_clk_regmap(hw);
223 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
226 val = meson_parm_read(clk->map, &sclk->div);
228 /* if the divider is initially disabled, assume max */
230 sclk->cached_div = sclk_div_maxdiv(sclk);
232 sclk->cached_div = val + 1;
234 sclk_div_get_duty_cycle(hw, &sclk->cached_duty);
239 const struct clk_ops meson_sclk_div_ops = {
240 .recalc_rate = sclk_div_recalc_rate,
241 .determine_rate = sclk_div_determine_rate,
242 .set_rate = sclk_div_set_rate,
243 .enable = sclk_div_enable,
244 .disable = sclk_div_disable,
245 .is_enabled = sclk_div_is_enabled,
246 .get_duty_cycle = sclk_div_get_duty_cycle,
247 .set_duty_cycle = sclk_div_set_duty_cycle,
248 .init = sclk_div_init,
250 EXPORT_SYMBOL_GPL(meson_sclk_div_ops);
252 MODULE_DESCRIPTION("Amlogic Sample divider driver");
253 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
254 MODULE_LICENSE("GPL v2");