GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / clk / meson / meson8b.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2015 Endless Mobile, Inc.
4  * Author: Carlo Caione <carlo@endlessm.com>
5  *
6  * Copyright (c) 2016 BayLibre, Inc.
7  * Michael Turquette <mturquette@baylibre.com>
8  */
9
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/init.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset-controller.h>
16 #include <linux/slab.h>
17 #include <linux/regmap.h>
18
19 #include "clkc.h"
20 #include "meson8b.h"
21 #include "clk-regmap.h"
22
23 static DEFINE_SPINLOCK(meson_clk_lock);
24
25 static void __iomem *clk_base;
26
27 struct meson8b_clk_reset {
28         struct reset_controller_dev reset;
29         void __iomem *base;
30 };
31
32 static const struct pll_rate_table sys_pll_rate_table[] = {
33         PLL_RATE(312000000, 52, 1, 2),
34         PLL_RATE(336000000, 56, 1, 2),
35         PLL_RATE(360000000, 60, 1, 2),
36         PLL_RATE(384000000, 64, 1, 2),
37         PLL_RATE(408000000, 68, 1, 2),
38         PLL_RATE(432000000, 72, 1, 2),
39         PLL_RATE(456000000, 76, 1, 2),
40         PLL_RATE(480000000, 80, 1, 2),
41         PLL_RATE(504000000, 84, 1, 2),
42         PLL_RATE(528000000, 88, 1, 2),
43         PLL_RATE(552000000, 92, 1, 2),
44         PLL_RATE(576000000, 96, 1, 2),
45         PLL_RATE(600000000, 50, 1, 1),
46         PLL_RATE(624000000, 52, 1, 1),
47         PLL_RATE(648000000, 54, 1, 1),
48         PLL_RATE(672000000, 56, 1, 1),
49         PLL_RATE(696000000, 58, 1, 1),
50         PLL_RATE(720000000, 60, 1, 1),
51         PLL_RATE(744000000, 62, 1, 1),
52         PLL_RATE(768000000, 64, 1, 1),
53         PLL_RATE(792000000, 66, 1, 1),
54         PLL_RATE(816000000, 68, 1, 1),
55         PLL_RATE(840000000, 70, 1, 1),
56         PLL_RATE(864000000, 72, 1, 1),
57         PLL_RATE(888000000, 74, 1, 1),
58         PLL_RATE(912000000, 76, 1, 1),
59         PLL_RATE(936000000, 78, 1, 1),
60         PLL_RATE(960000000, 80, 1, 1),
61         PLL_RATE(984000000, 82, 1, 1),
62         PLL_RATE(1008000000, 84, 1, 1),
63         PLL_RATE(1032000000, 86, 1, 1),
64         PLL_RATE(1056000000, 88, 1, 1),
65         PLL_RATE(1080000000, 90, 1, 1),
66         PLL_RATE(1104000000, 92, 1, 1),
67         PLL_RATE(1128000000, 94, 1, 1),
68         PLL_RATE(1152000000, 96, 1, 1),
69         PLL_RATE(1176000000, 98, 1, 1),
70         PLL_RATE(1200000000, 50, 1, 0),
71         PLL_RATE(1224000000, 51, 1, 0),
72         PLL_RATE(1248000000, 52, 1, 0),
73         PLL_RATE(1272000000, 53, 1, 0),
74         PLL_RATE(1296000000, 54, 1, 0),
75         PLL_RATE(1320000000, 55, 1, 0),
76         PLL_RATE(1344000000, 56, 1, 0),
77         PLL_RATE(1368000000, 57, 1, 0),
78         PLL_RATE(1392000000, 58, 1, 0),
79         PLL_RATE(1416000000, 59, 1, 0),
80         PLL_RATE(1440000000, 60, 1, 0),
81         PLL_RATE(1464000000, 61, 1, 0),
82         PLL_RATE(1488000000, 62, 1, 0),
83         PLL_RATE(1512000000, 63, 1, 0),
84         PLL_RATE(1536000000, 64, 1, 0),
85         { /* sentinel */ },
86 };
87
88 static struct clk_fixed_rate meson8b_xtal = {
89         .fixed_rate = 24000000,
90         .hw.init = &(struct clk_init_data){
91                 .name = "xtal",
92                 .num_parents = 0,
93                 .ops = &clk_fixed_rate_ops,
94         },
95 };
96
97 static struct clk_regmap meson8b_fixed_pll = {
98         .data = &(struct meson_clk_pll_data){
99                 .m = {
100                         .reg_off = HHI_MPLL_CNTL,
101                         .shift   = 0,
102                         .width   = 9,
103                 },
104                 .n = {
105                         .reg_off = HHI_MPLL_CNTL,
106                         .shift   = 9,
107                         .width   = 5,
108                 },
109                 .od = {
110                         .reg_off = HHI_MPLL_CNTL,
111                         .shift   = 16,
112                         .width   = 2,
113                 },
114                 .frac = {
115                         .reg_off = HHI_MPLL_CNTL2,
116                         .shift   = 0,
117                         .width   = 12,
118                 },
119                 .l = {
120                         .reg_off = HHI_MPLL_CNTL,
121                         .shift   = 31,
122                         .width   = 1,
123                 },
124                 .rst = {
125                         .reg_off = HHI_MPLL_CNTL,
126                         .shift   = 29,
127                         .width   = 1,
128                 },
129         },
130         .hw.init = &(struct clk_init_data){
131                 .name = "fixed_pll",
132                 .ops = &meson_clk_pll_ro_ops,
133                 .parent_names = (const char *[]){ "xtal" },
134                 .num_parents = 1,
135         },
136 };
137
138 static struct clk_regmap meson8b_vid_pll = {
139         .data = &(struct meson_clk_pll_data){
140                 .m = {
141                         .reg_off = HHI_VID_PLL_CNTL,
142                         .shift   = 0,
143                         .width   = 9,
144                 },
145                 .n = {
146                         .reg_off = HHI_VID_PLL_CNTL,
147                         .shift   = 10,
148                         .width   = 5,
149                 },
150                 .od = {
151                         .reg_off = HHI_VID_PLL_CNTL,
152                         .shift   = 16,
153                         .width   = 2,
154                 },
155                 .l = {
156                         .reg_off = HHI_VID_PLL_CNTL,
157                         .shift   = 31,
158                         .width   = 1,
159                 },
160                 .rst = {
161                         .reg_off = HHI_VID_PLL_CNTL,
162                         .shift   = 29,
163                         .width   = 1,
164                 },
165         },
166         .hw.init = &(struct clk_init_data){
167                 .name = "vid_pll",
168                 .ops = &meson_clk_pll_ro_ops,
169                 .parent_names = (const char *[]){ "xtal" },
170                 .num_parents = 1,
171         },
172 };
173
174 static struct clk_regmap meson8b_sys_pll = {
175         .data = &(struct meson_clk_pll_data){
176                 .m = {
177                         .reg_off = HHI_SYS_PLL_CNTL,
178                         .shift   = 0,
179                         .width   = 9,
180                 },
181                 .n = {
182                         .reg_off = HHI_SYS_PLL_CNTL,
183                         .shift   = 9,
184                         .width   = 5,
185                 },
186                 .od = {
187                         .reg_off = HHI_SYS_PLL_CNTL,
188                         .shift   = 16,
189                         .width   = 2,
190                 },
191                 .l = {
192                         .reg_off = HHI_SYS_PLL_CNTL,
193                         .shift   = 31,
194                         .width   = 1,
195                 },
196                 .rst = {
197                         .reg_off = HHI_SYS_PLL_CNTL,
198                         .shift   = 29,
199                         .width   = 1,
200                 },
201                 .table = sys_pll_rate_table,
202         },
203         .hw.init = &(struct clk_init_data){
204                 .name = "sys_pll",
205                 .ops = &meson_clk_pll_ro_ops,
206                 .parent_names = (const char *[]){ "xtal" },
207                 .num_parents = 1,
208         },
209 };
210
211 static struct clk_fixed_factor meson8b_fclk_div2_div = {
212         .mult = 1,
213         .div = 2,
214         .hw.init = &(struct clk_init_data){
215                 .name = "fclk_div2_div",
216                 .ops = &clk_fixed_factor_ops,
217                 .parent_names = (const char *[]){ "fixed_pll" },
218                 .num_parents = 1,
219         },
220 };
221
222 static struct clk_regmap meson8b_fclk_div2 = {
223         .data = &(struct clk_regmap_gate_data){
224                 .offset = HHI_MPLL_CNTL6,
225                 .bit_idx = 27,
226         },
227         .hw.init = &(struct clk_init_data){
228                 .name = "fclk_div2",
229                 .ops = &clk_regmap_gate_ops,
230                 .parent_names = (const char *[]){ "fclk_div2_div" },
231                 .num_parents = 1,
232                 /*
233                  * FIXME: Ethernet with a RGMII PHYs is not working if
234                  * fclk_div2 is disabled. it is currently unclear why this
235                  * is. keep it enabled until the Ethernet driver knows how
236                  * to manage this clock.
237                  */
238                 .flags = CLK_IS_CRITICAL,
239         },
240 };
241
242 static struct clk_fixed_factor meson8b_fclk_div3_div = {
243         .mult = 1,
244         .div = 3,
245         .hw.init = &(struct clk_init_data){
246                 .name = "fclk_div3_div",
247                 .ops = &clk_fixed_factor_ops,
248                 .parent_names = (const char *[]){ "fixed_pll" },
249                 .num_parents = 1,
250         },
251 };
252
253 static struct clk_regmap meson8b_fclk_div3 = {
254         .data = &(struct clk_regmap_gate_data){
255                 .offset = HHI_MPLL_CNTL6,
256                 .bit_idx = 28,
257         },
258         .hw.init = &(struct clk_init_data){
259                 .name = "fclk_div3",
260                 .ops = &clk_regmap_gate_ops,
261                 .parent_names = (const char *[]){ "fclk_div3_div" },
262                 .num_parents = 1,
263         },
264 };
265
266 static struct clk_fixed_factor meson8b_fclk_div4_div = {
267         .mult = 1,
268         .div = 4,
269         .hw.init = &(struct clk_init_data){
270                 .name = "fclk_div4_div",
271                 .ops = &clk_fixed_factor_ops,
272                 .parent_names = (const char *[]){ "fixed_pll" },
273                 .num_parents = 1,
274         },
275 };
276
277 static struct clk_regmap meson8b_fclk_div4 = {
278         .data = &(struct clk_regmap_gate_data){
279                 .offset = HHI_MPLL_CNTL6,
280                 .bit_idx = 29,
281         },
282         .hw.init = &(struct clk_init_data){
283                 .name = "fclk_div4",
284                 .ops = &clk_regmap_gate_ops,
285                 .parent_names = (const char *[]){ "fclk_div4_div" },
286                 .num_parents = 1,
287         },
288 };
289
290 static struct clk_fixed_factor meson8b_fclk_div5_div = {
291         .mult = 1,
292         .div = 5,
293         .hw.init = &(struct clk_init_data){
294                 .name = "fclk_div5_div",
295                 .ops = &clk_fixed_factor_ops,
296                 .parent_names = (const char *[]){ "fixed_pll" },
297                 .num_parents = 1,
298         },
299 };
300
301 static struct clk_regmap meson8b_fclk_div5 = {
302         .data = &(struct clk_regmap_gate_data){
303                 .offset = HHI_MPLL_CNTL6,
304                 .bit_idx = 30,
305         },
306         .hw.init = &(struct clk_init_data){
307                 .name = "fclk_div5",
308                 .ops = &clk_regmap_gate_ops,
309                 .parent_names = (const char *[]){ "fclk_div5_div" },
310                 .num_parents = 1,
311         },
312 };
313
314 static struct clk_fixed_factor meson8b_fclk_div7_div = {
315         .mult = 1,
316         .div = 7,
317         .hw.init = &(struct clk_init_data){
318                 .name = "fclk_div7_div",
319                 .ops = &clk_fixed_factor_ops,
320                 .parent_names = (const char *[]){ "fixed_pll" },
321                 .num_parents = 1,
322         },
323 };
324
325 static struct clk_regmap meson8b_fclk_div7 = {
326         .data = &(struct clk_regmap_gate_data){
327                 .offset = HHI_MPLL_CNTL6,
328                 .bit_idx = 31,
329         },
330         .hw.init = &(struct clk_init_data){
331                 .name = "fclk_div7",
332                 .ops = &clk_regmap_gate_ops,
333                 .parent_names = (const char *[]){ "fclk_div7_div" },
334                 .num_parents = 1,
335         },
336 };
337
338 static struct clk_regmap meson8b_mpll_prediv = {
339         .data = &(struct clk_regmap_div_data){
340                 .offset = HHI_MPLL_CNTL5,
341                 .shift = 12,
342                 .width = 1,
343         },
344         .hw.init = &(struct clk_init_data){
345                 .name = "mpll_prediv",
346                 .ops = &clk_regmap_divider_ro_ops,
347                 .parent_names = (const char *[]){ "fixed_pll" },
348                 .num_parents = 1,
349         },
350 };
351
352 static struct clk_regmap meson8b_mpll0_div = {
353         .data = &(struct meson_clk_mpll_data){
354                 .sdm = {
355                         .reg_off = HHI_MPLL_CNTL7,
356                         .shift   = 0,
357                         .width   = 14,
358                 },
359                 .sdm_en = {
360                         .reg_off = HHI_MPLL_CNTL7,
361                         .shift   = 15,
362                         .width   = 1,
363                 },
364                 .n2 = {
365                         .reg_off = HHI_MPLL_CNTL7,
366                         .shift   = 16,
367                         .width   = 9,
368                 },
369                 .ssen = {
370                         .reg_off = HHI_MPLL_CNTL,
371                         .shift   = 25,
372                         .width   = 1,
373                 },
374                 .lock = &meson_clk_lock,
375         },
376         .hw.init = &(struct clk_init_data){
377                 .name = "mpll0_div",
378                 .ops = &meson_clk_mpll_ops,
379                 .parent_names = (const char *[]){ "mpll_prediv" },
380                 .num_parents = 1,
381         },
382 };
383
384 static struct clk_regmap meson8b_mpll0 = {
385         .data = &(struct clk_regmap_gate_data){
386                 .offset = HHI_MPLL_CNTL7,
387                 .bit_idx = 14,
388         },
389         .hw.init = &(struct clk_init_data){
390                 .name = "mpll0",
391                 .ops = &clk_regmap_gate_ops,
392                 .parent_names = (const char *[]){ "mpll0_div" },
393                 .num_parents = 1,
394                 .flags = CLK_SET_RATE_PARENT,
395         },
396 };
397
398 static struct clk_regmap meson8b_mpll1_div = {
399         .data = &(struct meson_clk_mpll_data){
400                 .sdm = {
401                         .reg_off = HHI_MPLL_CNTL8,
402                         .shift   = 0,
403                         .width   = 14,
404                 },
405                 .sdm_en = {
406                         .reg_off = HHI_MPLL_CNTL8,
407                         .shift   = 15,
408                         .width   = 1,
409                 },
410                 .n2 = {
411                         .reg_off = HHI_MPLL_CNTL8,
412                         .shift   = 16,
413                         .width   = 9,
414                 },
415                 .lock = &meson_clk_lock,
416         },
417         .hw.init = &(struct clk_init_data){
418                 .name = "mpll1_div",
419                 .ops = &meson_clk_mpll_ops,
420                 .parent_names = (const char *[]){ "mpll_prediv" },
421                 .num_parents = 1,
422         },
423 };
424
425 static struct clk_regmap meson8b_mpll1 = {
426         .data = &(struct clk_regmap_gate_data){
427                 .offset = HHI_MPLL_CNTL8,
428                 .bit_idx = 14,
429         },
430         .hw.init = &(struct clk_init_data){
431                 .name = "mpll1",
432                 .ops = &clk_regmap_gate_ops,
433                 .parent_names = (const char *[]){ "mpll1_div" },
434                 .num_parents = 1,
435                 .flags = CLK_SET_RATE_PARENT,
436         },
437 };
438
439 static struct clk_regmap meson8b_mpll2_div = {
440         .data = &(struct meson_clk_mpll_data){
441                 .sdm = {
442                         .reg_off = HHI_MPLL_CNTL9,
443                         .shift   = 0,
444                         .width   = 14,
445                 },
446                 .sdm_en = {
447                         .reg_off = HHI_MPLL_CNTL9,
448                         .shift   = 15,
449                         .width   = 1,
450                 },
451                 .n2 = {
452                         .reg_off = HHI_MPLL_CNTL9,
453                         .shift   = 16,
454                         .width   = 9,
455                 },
456                 .lock = &meson_clk_lock,
457         },
458         .hw.init = &(struct clk_init_data){
459                 .name = "mpll2_div",
460                 .ops = &meson_clk_mpll_ops,
461                 .parent_names = (const char *[]){ "mpll_prediv" },
462                 .num_parents = 1,
463         },
464 };
465
466 static struct clk_regmap meson8b_mpll2 = {
467         .data = &(struct clk_regmap_gate_data){
468                 .offset = HHI_MPLL_CNTL9,
469                 .bit_idx = 14,
470         },
471         .hw.init = &(struct clk_init_data){
472                 .name = "mpll2",
473                 .ops = &clk_regmap_gate_ops,
474                 .parent_names = (const char *[]){ "mpll2_div" },
475                 .num_parents = 1,
476                 .flags = CLK_SET_RATE_PARENT,
477         },
478 };
479
480 static u32 mux_table_clk81[]    = { 6, 5, 7 };
481 static struct clk_regmap meson8b_mpeg_clk_sel = {
482         .data = &(struct clk_regmap_mux_data){
483                 .offset = HHI_MPEG_CLK_CNTL,
484                 .mask = 0x7,
485                 .shift = 12,
486                 .table = mux_table_clk81,
487         },
488         .hw.init = &(struct clk_init_data){
489                 .name = "mpeg_clk_sel",
490                 .ops = &clk_regmap_mux_ro_ops,
491                 /*
492                  * FIXME bits 14:12 selects from 8 possible parents:
493                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
494                  * fclk_div4, fclk_div3, fclk_div5
495                  */
496                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
497                         "fclk_div5" },
498                 .num_parents = 3,
499         },
500 };
501
502 static struct clk_regmap meson8b_mpeg_clk_div = {
503         .data = &(struct clk_regmap_div_data){
504                 .offset = HHI_MPEG_CLK_CNTL,
505                 .shift = 0,
506                 .width = 7,
507         },
508         .hw.init = &(struct clk_init_data){
509                 .name = "mpeg_clk_div",
510                 .ops = &clk_regmap_divider_ro_ops,
511                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
512                 .num_parents = 1,
513         },
514 };
515
516 static struct clk_regmap meson8b_clk81 = {
517         .data = &(struct clk_regmap_gate_data){
518                 .offset = HHI_MPEG_CLK_CNTL,
519                 .bit_idx = 7,
520         },
521         .hw.init = &(struct clk_init_data){
522                 .name = "clk81",
523                 .ops = &clk_regmap_gate_ops,
524                 .parent_names = (const char *[]){ "mpeg_clk_div" },
525                 .num_parents = 1,
526                 .flags = CLK_IS_CRITICAL,
527         },
528 };
529
530 static struct clk_regmap meson8b_cpu_in_sel = {
531         .data = &(struct clk_regmap_mux_data){
532                 .offset = HHI_SYS_CPU_CLK_CNTL0,
533                 .mask = 0x1,
534                 .shift = 0,
535         },
536         .hw.init = &(struct clk_init_data){
537                 .name = "cpu_in_sel",
538                 .ops = &clk_regmap_mux_ro_ops,
539                 .parent_names = (const char *[]){ "xtal", "sys_pll" },
540                 .num_parents = 2,
541                 .flags = (CLK_SET_RATE_PARENT |
542                           CLK_SET_RATE_NO_REPARENT),
543         },
544 };
545
546 static struct clk_fixed_factor meson8b_cpu_div2 = {
547         .mult = 1,
548         .div = 2,
549         .hw.init = &(struct clk_init_data){
550                 .name = "cpu_div2",
551                 .ops = &clk_fixed_factor_ops,
552                 .parent_names = (const char *[]){ "cpu_in_sel" },
553                 .num_parents = 1,
554                 .flags = CLK_SET_RATE_PARENT,
555         },
556 };
557
558 static struct clk_fixed_factor meson8b_cpu_div3 = {
559         .mult = 1,
560         .div = 3,
561         .hw.init = &(struct clk_init_data){
562                 .name = "cpu_div3",
563                 .ops = &clk_fixed_factor_ops,
564                 .parent_names = (const char *[]){ "cpu_in_sel" },
565                 .num_parents = 1,
566                 .flags = CLK_SET_RATE_PARENT,
567         },
568 };
569
570 static const struct clk_div_table cpu_scale_table[] = {
571         { .val = 1, .div = 4 },
572         { .val = 2, .div = 6 },
573         { .val = 3, .div = 8 },
574         { .val = 4, .div = 10 },
575         { .val = 5, .div = 12 },
576         { .val = 6, .div = 14 },
577         { .val = 7, .div = 16 },
578         { .val = 8, .div = 18 },
579         { /* sentinel */ },
580 };
581
582 static struct clk_regmap meson8b_cpu_scale_div = {
583         .data = &(struct clk_regmap_div_data){
584                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
585                 .shift = 20,
586                 .width = 10,
587                 .table = cpu_scale_table,
588                 .flags = CLK_DIVIDER_ALLOW_ZERO,
589         },
590         .hw.init = &(struct clk_init_data){
591                 .name = "cpu_scale_div",
592                 .ops = &clk_regmap_divider_ro_ops,
593                 .parent_names = (const char *[]){ "cpu_in_sel" },
594                 .num_parents = 1,
595                 .flags = CLK_SET_RATE_PARENT,
596         },
597 };
598
599 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
600 static struct clk_regmap meson8b_cpu_scale_out_sel = {
601         .data = &(struct clk_regmap_mux_data){
602                 .offset = HHI_SYS_CPU_CLK_CNTL0,
603                 .mask = 0x3,
604                 .shift = 2,
605                 .table = mux_table_cpu_scale_out_sel,
606         },
607         .hw.init = &(struct clk_init_data){
608                 .name = "cpu_scale_out_sel",
609                 .ops = &clk_regmap_mux_ro_ops,
610                 /*
611                  * NOTE: We are skipping the parent with value 0x2 (which is
612                  * "cpu_div3") because it results in a duty cycle of 33% which
613                  * makes the system unstable and can result in a lockup of the
614                  * whole system.
615                  */
616                 .parent_names = (const char *[]) { "cpu_in_sel",
617                                                    "cpu_div2",
618                                                    "cpu_scale_div" },
619                 .num_parents = 3,
620                 .flags = CLK_SET_RATE_PARENT,
621         },
622 };
623
624 static struct clk_regmap meson8b_cpu_clk = {
625         .data = &(struct clk_regmap_mux_data){
626                 .offset = HHI_SYS_CPU_CLK_CNTL0,
627                 .mask = 0x1,
628                 .shift = 7,
629         },
630         .hw.init = &(struct clk_init_data){
631                 .name = "cpu_clk",
632                 .ops = &clk_regmap_mux_ro_ops,
633                 .parent_names = (const char *[]){ "xtal",
634                                                   "cpu_scale_out_sel" },
635                 .num_parents = 2,
636                 .flags = (CLK_SET_RATE_PARENT |
637                           CLK_SET_RATE_NO_REPARENT |
638                           CLK_IS_CRITICAL),
639         },
640 };
641
642 static struct clk_regmap meson8b_nand_clk_sel = {
643         .data = &(struct clk_regmap_mux_data){
644                 .offset = HHI_NAND_CLK_CNTL,
645                 .mask = 0x7,
646                 .shift = 9,
647                 .flags = CLK_MUX_ROUND_CLOSEST,
648         },
649         .hw.init = &(struct clk_init_data){
650                 .name = "nand_clk_sel",
651                 .ops = &clk_regmap_mux_ops,
652                 /* FIXME all other parents are unknown: */
653                 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
654                         "fclk_div5", "fclk_div7", "xtal" },
655                 .num_parents = 5,
656                 .flags = CLK_SET_RATE_PARENT,
657         },
658 };
659
660 static struct clk_regmap meson8b_nand_clk_div = {
661         .data = &(struct clk_regmap_div_data){
662                 .offset =  HHI_NAND_CLK_CNTL,
663                 .shift = 0,
664                 .width = 7,
665                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
666         },
667         .hw.init = &(struct clk_init_data){
668                 .name = "nand_clk_div",
669                 .ops = &clk_regmap_divider_ops,
670                 .parent_names = (const char *[]){ "nand_clk_sel" },
671                 .num_parents = 1,
672                 .flags = CLK_SET_RATE_PARENT,
673         },
674 };
675
676 static struct clk_regmap meson8b_nand_clk_gate = {
677         .data = &(struct clk_regmap_gate_data){
678                 .offset = HHI_NAND_CLK_CNTL,
679                 .bit_idx = 8,
680         },
681         .hw.init = &(struct clk_init_data){
682                 .name = "nand_clk_gate",
683                 .ops = &clk_regmap_gate_ops,
684                 .parent_names = (const char *[]){ "nand_clk_div" },
685                 .num_parents = 1,
686                 .flags = CLK_SET_RATE_PARENT,
687         },
688 };
689
690 /* Everything Else (EE) domain gates */
691
692 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
693 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
694 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
695 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
696 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
697 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
698 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
699 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
700 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
701 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
702 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
703 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
704 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
705 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
706 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
707 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
708 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
709 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
710 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
711
712 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
713 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
714 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
715 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
716 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
717 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
718 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
719 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
720 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
721 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
722 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
723 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
724 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
725 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
726 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
727 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
728 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
729 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
730 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
731 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
732 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
733 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
734 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
735 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
736 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
737
738 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
739 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
740 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
741 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
742 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
743 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
744 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
745 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
746 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
747 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
748 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
749 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
750 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
751
752 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
753 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
754 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
755 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
756 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
757 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
758 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
759 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
760 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
761 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
762 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
763 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
764 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
765 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
766 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
767 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
768
769 /* Always On (AO) domain gates */
770
771 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
772 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
773 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
774 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
775
776 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
777         .hws = {
778                 [CLKID_XTAL] = &meson8b_xtal.hw,
779                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
780                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
781                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
782                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
783                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
784                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
785                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
786                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
787                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
788                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
789                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
790                 [CLKID_CLK81] = &meson8b_clk81.hw,
791                 [CLKID_DDR]                 = &meson8b_ddr.hw,
792                 [CLKID_DOS]                 = &meson8b_dos.hw,
793                 [CLKID_ISA]                 = &meson8b_isa.hw,
794                 [CLKID_PL301]               = &meson8b_pl301.hw,
795                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
796                 [CLKID_SPICC]               = &meson8b_spicc.hw,
797                 [CLKID_I2C]                 = &meson8b_i2c.hw,
798                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
799                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
800                 [CLKID_RNG0]                = &meson8b_rng0.hw,
801                 [CLKID_UART0]               = &meson8b_uart0.hw,
802                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
803                 [CLKID_STREAM]              = &meson8b_stream.hw,
804                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
805                 [CLKID_SDIO]                = &meson8b_sdio.hw,
806                 [CLKID_ABUF]                = &meson8b_abuf.hw,
807                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
808                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
809                 [CLKID_SPI]                 = &meson8b_spi.hw,
810                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
811                 [CLKID_ETH]                 = &meson8b_eth.hw,
812                 [CLKID_DEMUX]               = &meson8b_demux.hw,
813                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
814                 [CLKID_IEC958]              = &meson8b_iec958.hw,
815                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
816                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
817                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
818                 [CLKID_MIXER]               = &meson8b_mixer.hw,
819                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
820                 [CLKID_ADC]                 = &meson8b_adc.hw,
821                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
822                 [CLKID_AIU]                 = &meson8b_aiu.hw,
823                 [CLKID_UART1]               = &meson8b_uart1.hw,
824                 [CLKID_G2D]                 = &meson8b_g2d.hw,
825                 [CLKID_USB0]                = &meson8b_usb0.hw,
826                 [CLKID_USB1]                = &meson8b_usb1.hw,
827                 [CLKID_RESET]               = &meson8b_reset.hw,
828                 [CLKID_NAND]                = &meson8b_nand.hw,
829                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
830                 [CLKID_USB]                 = &meson8b_usb.hw,
831                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
832                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
833                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
834                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
835                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
836                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
837                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
838                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
839                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
840                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
841                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
842                 [CLKID_DVIN]                = &meson8b_dvin.hw,
843                 [CLKID_UART2]               = &meson8b_uart2.hw,
844                 [CLKID_SANA]                = &meson8b_sana.hw,
845                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
846                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
847                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
848                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
849                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
850                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
851                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
852                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
853                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
854                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
855                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
856                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
857                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
858                 [CLKID_RNG1]                = &meson8b_rng1.hw,
859                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
860                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
861                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
862                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
863                 [CLKID_EDP]                 = &meson8b_edp.hw,
864                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
865                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
866                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
867                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
868                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
869                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
870                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
871                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
872                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
873                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
874                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
875                 [CLKID_CPU_DIV2]            = &meson8b_cpu_div2.hw,
876                 [CLKID_CPU_DIV3]            = &meson8b_cpu_div3.hw,
877                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
878                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
879                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
880                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
881                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
882                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
883                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
884                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
885                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
886                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
887                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
888                 [CLK_NR_CLKS]               = NULL,
889         },
890         .num = CLK_NR_CLKS,
891 };
892
893 static struct clk_regmap *const meson8b_clk_regmaps[] = {
894         &meson8b_clk81,
895         &meson8b_ddr,
896         &meson8b_dos,
897         &meson8b_isa,
898         &meson8b_pl301,
899         &meson8b_periphs,
900         &meson8b_spicc,
901         &meson8b_i2c,
902         &meson8b_sar_adc,
903         &meson8b_smart_card,
904         &meson8b_rng0,
905         &meson8b_uart0,
906         &meson8b_sdhc,
907         &meson8b_stream,
908         &meson8b_async_fifo,
909         &meson8b_sdio,
910         &meson8b_abuf,
911         &meson8b_hiu_iface,
912         &meson8b_assist_misc,
913         &meson8b_spi,
914         &meson8b_i2s_spdif,
915         &meson8b_eth,
916         &meson8b_demux,
917         &meson8b_aiu_glue,
918         &meson8b_iec958,
919         &meson8b_i2s_out,
920         &meson8b_amclk,
921         &meson8b_aififo2,
922         &meson8b_mixer,
923         &meson8b_mixer_iface,
924         &meson8b_adc,
925         &meson8b_blkmv,
926         &meson8b_aiu,
927         &meson8b_uart1,
928         &meson8b_g2d,
929         &meson8b_usb0,
930         &meson8b_usb1,
931         &meson8b_reset,
932         &meson8b_nand,
933         &meson8b_dos_parser,
934         &meson8b_usb,
935         &meson8b_vdin1,
936         &meson8b_ahb_arb0,
937         &meson8b_efuse,
938         &meson8b_boot_rom,
939         &meson8b_ahb_data_bus,
940         &meson8b_ahb_ctrl_bus,
941         &meson8b_hdmi_intr_sync,
942         &meson8b_hdmi_pclk,
943         &meson8b_usb1_ddr_bridge,
944         &meson8b_usb0_ddr_bridge,
945         &meson8b_mmc_pclk,
946         &meson8b_dvin,
947         &meson8b_uart2,
948         &meson8b_sana,
949         &meson8b_vpu_intr,
950         &meson8b_sec_ahb_ahb3_bridge,
951         &meson8b_clk81_a9,
952         &meson8b_vclk2_venci0,
953         &meson8b_vclk2_venci1,
954         &meson8b_vclk2_vencp0,
955         &meson8b_vclk2_vencp1,
956         &meson8b_gclk_venci_int,
957         &meson8b_gclk_vencp_int,
958         &meson8b_dac_clk,
959         &meson8b_aoclk_gate,
960         &meson8b_iec958_gate,
961         &meson8b_enc480p,
962         &meson8b_rng1,
963         &meson8b_gclk_vencl_int,
964         &meson8b_vclk2_venclmcc,
965         &meson8b_vclk2_vencl,
966         &meson8b_vclk2_other,
967         &meson8b_edp,
968         &meson8b_ao_media_cpu,
969         &meson8b_ao_ahb_sram,
970         &meson8b_ao_ahb_bus,
971         &meson8b_ao_iface,
972         &meson8b_mpeg_clk_div,
973         &meson8b_mpeg_clk_sel,
974         &meson8b_mpll0,
975         &meson8b_mpll1,
976         &meson8b_mpll2,
977         &meson8b_mpll0_div,
978         &meson8b_mpll1_div,
979         &meson8b_mpll2_div,
980         &meson8b_fixed_pll,
981         &meson8b_vid_pll,
982         &meson8b_sys_pll,
983         &meson8b_cpu_in_sel,
984         &meson8b_cpu_scale_div,
985         &meson8b_cpu_scale_out_sel,
986         &meson8b_cpu_clk,
987         &meson8b_mpll_prediv,
988         &meson8b_fclk_div2,
989         &meson8b_fclk_div3,
990         &meson8b_fclk_div4,
991         &meson8b_fclk_div5,
992         &meson8b_fclk_div7,
993         &meson8b_nand_clk_sel,
994         &meson8b_nand_clk_div,
995         &meson8b_nand_clk_gate,
996 };
997
998 static const struct meson8b_clk_reset_line {
999         u32 reg;
1000         u8 bit_idx;
1001 } meson8b_clk_reset_bits[] = {
1002         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
1003                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
1004         },
1005         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
1006                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
1007         },
1008         [CLKC_RESET_SCU_SOFT_RESET] = {
1009                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
1010         },
1011         [CLKC_RESET_CPU3_SOFT_RESET] = {
1012                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
1013         },
1014         [CLKC_RESET_CPU2_SOFT_RESET] = {
1015                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
1016         },
1017         [CLKC_RESET_CPU1_SOFT_RESET] = {
1018                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
1019         },
1020         [CLKC_RESET_CPU0_SOFT_RESET] = {
1021                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
1022         },
1023         [CLKC_RESET_A5_GLOBAL_RESET] = {
1024                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
1025         },
1026         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
1027                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
1028         },
1029         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
1030                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
1031         },
1032         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
1033                 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
1034         },
1035         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
1036                 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
1037         },
1038         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
1039                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
1040         },
1041         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
1042                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
1043         },
1044         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
1045                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
1046         },
1047         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
1048                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
1049         },
1050 };
1051
1052 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
1053                                     unsigned long id, bool assert)
1054 {
1055         struct meson8b_clk_reset *meson8b_clk_reset =
1056                 container_of(rcdev, struct meson8b_clk_reset, reset);
1057         unsigned long flags;
1058         const struct meson8b_clk_reset_line *reset;
1059         u32 val;
1060
1061         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
1062                 return -EINVAL;
1063
1064         reset = &meson8b_clk_reset_bits[id];
1065
1066         spin_lock_irqsave(&meson_clk_lock, flags);
1067
1068         val = readl(meson8b_clk_reset->base + reset->reg);
1069         if (assert)
1070                 val |= BIT(reset->bit_idx);
1071         else
1072                 val &= ~BIT(reset->bit_idx);
1073         writel(val, meson8b_clk_reset->base + reset->reg);
1074
1075         spin_unlock_irqrestore(&meson_clk_lock, flags);
1076
1077         return 0;
1078 }
1079
1080 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
1081                                      unsigned long id)
1082 {
1083         return meson8b_clk_reset_update(rcdev, id, true);
1084 }
1085
1086 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
1087                                        unsigned long id)
1088 {
1089         return meson8b_clk_reset_update(rcdev, id, false);
1090 }
1091
1092 static const struct reset_control_ops meson8b_clk_reset_ops = {
1093         .assert = meson8b_clk_reset_assert,
1094         .deassert = meson8b_clk_reset_deassert,
1095 };
1096
1097 static const struct regmap_config clkc_regmap_config = {
1098         .reg_bits       = 32,
1099         .val_bits       = 32,
1100         .reg_stride     = 4,
1101 };
1102
1103 static int meson8b_clkc_probe(struct platform_device *pdev)
1104 {
1105         int ret, i;
1106         struct device *dev = &pdev->dev;
1107         struct regmap *map;
1108
1109         if (!clk_base)
1110                 return -ENXIO;
1111
1112         map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
1113         if (IS_ERR(map))
1114                 return PTR_ERR(map);
1115
1116         /* Populate regmap for the regmap backed clocks */
1117         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
1118                 meson8b_clk_regmaps[i]->map = map;
1119
1120         /*
1121          * register all clks
1122          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
1123          */
1124         for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
1125                 /* array might be sparse */
1126                 if (!meson8b_hw_onecell_data.hws[i])
1127                         continue;
1128
1129                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]);
1130                 if (ret)
1131                         return ret;
1132         }
1133
1134         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1135                                            &meson8b_hw_onecell_data);
1136 }
1137
1138 static const struct of_device_id meson8b_clkc_match_table[] = {
1139         { .compatible = "amlogic,meson8-clkc" },
1140         { .compatible = "amlogic,meson8b-clkc" },
1141         { .compatible = "amlogic,meson8m2-clkc" },
1142         { }
1143 };
1144
1145 static struct platform_driver meson8b_driver = {
1146         .probe          = meson8b_clkc_probe,
1147         .driver         = {
1148                 .name   = "meson8b-clkc",
1149                 .of_match_table = meson8b_clkc_match_table,
1150         },
1151 };
1152
1153 builtin_platform_driver(meson8b_driver);
1154
1155 static void __init meson8b_clkc_reset_init(struct device_node *np)
1156 {
1157         struct meson8b_clk_reset *rstc;
1158         int ret;
1159
1160         /* Generic clocks, PLLs and some of the reset-bits */
1161         clk_base = of_iomap(np, 1);
1162         if (!clk_base) {
1163                 pr_err("%s: Unable to map clk base\n", __func__);
1164                 return;
1165         }
1166
1167         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
1168         if (!rstc)
1169                 return;
1170
1171         /* Reset Controller */
1172         rstc->base = clk_base;
1173         rstc->reset.ops = &meson8b_clk_reset_ops;
1174         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
1175         rstc->reset.of_node = np;
1176         ret = reset_controller_register(&rstc->reset);
1177         if (ret) {
1178                 pr_err("%s: Failed to register clkc reset controller: %d\n",
1179                        __func__, ret);
1180                 return;
1181         }
1182 }
1183
1184 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
1185                       meson8b_clkc_reset_init);
1186 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
1187                       meson8b_clkc_reset_init);
1188 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
1189                       meson8b_clkc_reset_init);