1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
7 #include <linux/clk-provider.h>
8 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
13 #include "clk-regmap.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
19 static DEFINE_SPINLOCK(meson_clk_lock);
21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
85 static struct clk_regmap gxbb_fixed_pll_dco = {
86 .data = &(struct meson_clk_pll_data){
88 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_MPLL_CNTL,
98 .reg_off = HHI_MPLL_CNTL,
103 .reg_off = HHI_MPLL_CNTL2,
108 .reg_off = HHI_MPLL_CNTL,
113 .reg_off = HHI_MPLL_CNTL,
118 .hw.init = &(struct clk_init_data){
119 .name = "fixed_pll_dco",
120 .ops = &meson_clk_pll_ro_ops,
121 .parent_data = &(const struct clk_parent_data) {
128 static struct clk_regmap gxbb_fixed_pll = {
129 .data = &(struct clk_regmap_div_data){
130 .offset = HHI_MPLL_CNTL,
133 .flags = CLK_DIVIDER_POWER_OF_TWO,
135 .hw.init = &(struct clk_init_data){
137 .ops = &clk_regmap_divider_ro_ops,
138 .parent_hws = (const struct clk_hw *[]) {
139 &gxbb_fixed_pll_dco.hw
143 * This clock won't ever change at runtime so
144 * CLK_SET_RATE_PARENT is not required
149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
152 .hw.init = &(struct clk_init_data){
153 .name = "hdmi_pll_pre_mult",
154 .ops = &clk_fixed_factor_ops,
155 .parent_data = &(const struct clk_parent_data) {
162 static struct clk_regmap gxbb_hdmi_pll_dco = {
163 .data = &(struct meson_clk_pll_data){
165 .reg_off = HHI_HDMI_PLL_CNTL,
170 .reg_off = HHI_HDMI_PLL_CNTL,
175 .reg_off = HHI_HDMI_PLL_CNTL,
180 .reg_off = HHI_HDMI_PLL_CNTL2,
185 .reg_off = HHI_HDMI_PLL_CNTL,
190 .reg_off = HHI_HDMI_PLL_CNTL,
195 .hw.init = &(struct clk_init_data){
196 .name = "hdmi_pll_dco",
197 .ops = &meson_clk_pll_ro_ops,
198 .parent_hws = (const struct clk_hw *[]) {
199 &gxbb_hdmi_pll_pre_mult.hw
203 * Display directly handle hdmi pll registers ATM, we need
204 * NOCACHE to keep our view of the clock as accurate as possible
206 .flags = CLK_GET_RATE_NOCACHE,
210 static struct clk_regmap gxl_hdmi_pll_dco = {
211 .data = &(struct meson_clk_pll_data){
213 .reg_off = HHI_HDMI_PLL_CNTL,
218 .reg_off = HHI_HDMI_PLL_CNTL,
223 .reg_off = HHI_HDMI_PLL_CNTL,
228 * On gxl, there is a register shift due to
229 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
230 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
231 * instead which is defined at the same offset.
234 .reg_off = HHI_HDMI_PLL_CNTL2,
239 .reg_off = HHI_HDMI_PLL_CNTL,
244 .reg_off = HHI_HDMI_PLL_CNTL,
249 .hw.init = &(struct clk_init_data){
250 .name = "hdmi_pll_dco",
251 .ops = &meson_clk_pll_ro_ops,
252 .parent_data = &(const struct clk_parent_data) {
257 * Display directly handle hdmi pll registers ATM, we need
258 * NOCACHE to keep our view of the clock as accurate as possible
260 .flags = CLK_GET_RATE_NOCACHE,
264 static struct clk_regmap gxbb_hdmi_pll_od = {
265 .data = &(struct clk_regmap_div_data){
266 .offset = HHI_HDMI_PLL_CNTL2,
269 .flags = CLK_DIVIDER_POWER_OF_TWO,
271 .hw.init = &(struct clk_init_data){
272 .name = "hdmi_pll_od",
273 .ops = &clk_regmap_divider_ro_ops,
274 .parent_hws = (const struct clk_hw *[]) {
275 &gxbb_hdmi_pll_dco.hw
278 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
283 .data = &(struct clk_regmap_div_data){
284 .offset = HHI_HDMI_PLL_CNTL2,
287 .flags = CLK_DIVIDER_POWER_OF_TWO,
289 .hw.init = &(struct clk_init_data){
290 .name = "hdmi_pll_od2",
291 .ops = &clk_regmap_divider_ro_ops,
292 .parent_hws = (const struct clk_hw *[]) {
296 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
300 static struct clk_regmap gxbb_hdmi_pll = {
301 .data = &(struct clk_regmap_div_data){
302 .offset = HHI_HDMI_PLL_CNTL2,
305 .flags = CLK_DIVIDER_POWER_OF_TWO,
307 .hw.init = &(struct clk_init_data){
309 .ops = &clk_regmap_divider_ro_ops,
310 .parent_hws = (const struct clk_hw *[]) {
311 &gxbb_hdmi_pll_od2.hw
314 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
318 static struct clk_regmap gxl_hdmi_pll_od = {
319 .data = &(struct clk_regmap_div_data){
320 .offset = HHI_HDMI_PLL_CNTL + 8,
323 .flags = CLK_DIVIDER_POWER_OF_TWO,
325 .hw.init = &(struct clk_init_data){
326 .name = "hdmi_pll_od",
327 .ops = &clk_regmap_divider_ro_ops,
328 .parent_hws = (const struct clk_hw *[]) {
332 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
336 static struct clk_regmap gxl_hdmi_pll_od2 = {
337 .data = &(struct clk_regmap_div_data){
338 .offset = HHI_HDMI_PLL_CNTL + 8,
341 .flags = CLK_DIVIDER_POWER_OF_TWO,
343 .hw.init = &(struct clk_init_data){
344 .name = "hdmi_pll_od2",
345 .ops = &clk_regmap_divider_ro_ops,
346 .parent_hws = (const struct clk_hw *[]) {
350 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
354 static struct clk_regmap gxl_hdmi_pll = {
355 .data = &(struct clk_regmap_div_data){
356 .offset = HHI_HDMI_PLL_CNTL + 8,
359 .flags = CLK_DIVIDER_POWER_OF_TWO,
361 .hw.init = &(struct clk_init_data){
363 .ops = &clk_regmap_divider_ro_ops,
364 .parent_hws = (const struct clk_hw *[]) {
368 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
372 static struct clk_regmap gxbb_sys_pll_dco = {
373 .data = &(struct meson_clk_pll_data){
375 .reg_off = HHI_SYS_PLL_CNTL,
380 .reg_off = HHI_SYS_PLL_CNTL,
385 .reg_off = HHI_SYS_PLL_CNTL,
390 .reg_off = HHI_SYS_PLL_CNTL,
395 .reg_off = HHI_SYS_PLL_CNTL,
400 .hw.init = &(struct clk_init_data){
401 .name = "sys_pll_dco",
402 .ops = &meson_clk_pll_ro_ops,
403 .parent_data = &(const struct clk_parent_data) {
410 static struct clk_regmap gxbb_sys_pll = {
411 .data = &(struct clk_regmap_div_data){
412 .offset = HHI_SYS_PLL_CNTL,
415 .flags = CLK_DIVIDER_POWER_OF_TWO,
417 .hw.init = &(struct clk_init_data){
419 .ops = &clk_regmap_divider_ro_ops,
420 .parent_hws = (const struct clk_hw *[]) {
424 .flags = CLK_SET_RATE_PARENT,
428 static const struct reg_sequence gxbb_gp0_init_regs[] = {
429 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
430 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
431 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
434 static struct clk_regmap gxbb_gp0_pll_dco = {
435 .data = &(struct meson_clk_pll_data){
437 .reg_off = HHI_GP0_PLL_CNTL,
442 .reg_off = HHI_GP0_PLL_CNTL,
447 .reg_off = HHI_GP0_PLL_CNTL,
452 .reg_off = HHI_GP0_PLL_CNTL,
457 .reg_off = HHI_GP0_PLL_CNTL,
461 .table = gxbb_gp0_pll_params_table,
462 .init_regs = gxbb_gp0_init_regs,
463 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
465 .hw.init = &(struct clk_init_data){
466 .name = "gp0_pll_dco",
467 .ops = &meson_clk_pll_ops,
468 .parent_data = &(const struct clk_parent_data) {
475 static const struct reg_sequence gxl_gp0_init_regs[] = {
476 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
477 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
478 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
479 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
480 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
483 static struct clk_regmap gxl_gp0_pll_dco = {
484 .data = &(struct meson_clk_pll_data){
486 .reg_off = HHI_GP0_PLL_CNTL,
491 .reg_off = HHI_GP0_PLL_CNTL,
496 .reg_off = HHI_GP0_PLL_CNTL,
501 .reg_off = HHI_GP0_PLL_CNTL1,
506 .reg_off = HHI_GP0_PLL_CNTL,
511 .reg_off = HHI_GP0_PLL_CNTL,
515 .table = gxl_gp0_pll_params_table,
516 .init_regs = gxl_gp0_init_regs,
517 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
519 .hw.init = &(struct clk_init_data){
520 .name = "gp0_pll_dco",
521 .ops = &meson_clk_pll_ops,
522 .parent_data = &(const struct clk_parent_data) {
529 static struct clk_regmap gxbb_gp0_pll = {
530 .data = &(struct clk_regmap_div_data){
531 .offset = HHI_GP0_PLL_CNTL,
534 .flags = CLK_DIVIDER_POWER_OF_TWO,
536 .hw.init = &(struct clk_init_data){
538 .ops = &clk_regmap_divider_ops,
539 .parent_data = &(const struct clk_parent_data) {
542 * GXL and GXBB have different gp0_pll_dco (with
543 * different struct clk_hw). We fallback to the global
544 * naming string mechanism so gp0_pll picks up the
547 .name = "gp0_pll_dco",
551 .flags = CLK_SET_RATE_PARENT,
555 static struct clk_fixed_factor gxbb_fclk_div2_div = {
558 .hw.init = &(struct clk_init_data){
559 .name = "fclk_div2_div",
560 .ops = &clk_fixed_factor_ops,
561 .parent_hws = (const struct clk_hw *[]) {
568 static struct clk_regmap gxbb_fclk_div2 = {
569 .data = &(struct clk_regmap_gate_data){
570 .offset = HHI_MPLL_CNTL6,
573 .hw.init = &(struct clk_init_data){
575 .ops = &clk_regmap_gate_ops,
576 .parent_hws = (const struct clk_hw *[]) {
577 &gxbb_fclk_div2_div.hw
580 .flags = CLK_IS_CRITICAL,
584 static struct clk_fixed_factor gxbb_fclk_div3_div = {
587 .hw.init = &(struct clk_init_data){
588 .name = "fclk_div3_div",
589 .ops = &clk_fixed_factor_ops,
590 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
595 static struct clk_regmap gxbb_fclk_div3 = {
596 .data = &(struct clk_regmap_gate_data){
597 .offset = HHI_MPLL_CNTL6,
600 .hw.init = &(struct clk_init_data){
602 .ops = &clk_regmap_gate_ops,
603 .parent_hws = (const struct clk_hw *[]) {
604 &gxbb_fclk_div3_div.hw
609 * This clock, as fdiv2, is used by the SCPI FW and is required
610 * by the platform to operate correctly.
611 * Until the following condition are met, we need this clock to
612 * be marked as critical:
613 * a) The SCPI generic driver claims and enable all the clocks
615 * b) CCF has a clock hand-off mechanism to make the sure the
616 * clock stays on until the proper driver comes along
618 .flags = CLK_IS_CRITICAL,
622 static struct clk_fixed_factor gxbb_fclk_div4_div = {
625 .hw.init = &(struct clk_init_data){
626 .name = "fclk_div4_div",
627 .ops = &clk_fixed_factor_ops,
628 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
633 static struct clk_regmap gxbb_fclk_div4 = {
634 .data = &(struct clk_regmap_gate_data){
635 .offset = HHI_MPLL_CNTL6,
638 .hw.init = &(struct clk_init_data){
640 .ops = &clk_regmap_gate_ops,
641 .parent_hws = (const struct clk_hw *[]) {
642 &gxbb_fclk_div4_div.hw
648 static struct clk_fixed_factor gxbb_fclk_div5_div = {
651 .hw.init = &(struct clk_init_data){
652 .name = "fclk_div5_div",
653 .ops = &clk_fixed_factor_ops,
654 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
659 static struct clk_regmap gxbb_fclk_div5 = {
660 .data = &(struct clk_regmap_gate_data){
661 .offset = HHI_MPLL_CNTL6,
664 .hw.init = &(struct clk_init_data){
666 .ops = &clk_regmap_gate_ops,
667 .parent_hws = (const struct clk_hw *[]) {
668 &gxbb_fclk_div5_div.hw
674 static struct clk_fixed_factor gxbb_fclk_div7_div = {
677 .hw.init = &(struct clk_init_data){
678 .name = "fclk_div7_div",
679 .ops = &clk_fixed_factor_ops,
680 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
685 static struct clk_regmap gxbb_fclk_div7 = {
686 .data = &(struct clk_regmap_gate_data){
687 .offset = HHI_MPLL_CNTL6,
690 .hw.init = &(struct clk_init_data){
692 .ops = &clk_regmap_gate_ops,
693 .parent_hws = (const struct clk_hw *[]) {
694 &gxbb_fclk_div7_div.hw
700 static struct clk_regmap gxbb_mpll_prediv = {
701 .data = &(struct clk_regmap_div_data){
702 .offset = HHI_MPLL_CNTL5,
706 .hw.init = &(struct clk_init_data){
707 .name = "mpll_prediv",
708 .ops = &clk_regmap_divider_ro_ops,
709 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
714 static struct clk_regmap gxbb_mpll0_div = {
715 .data = &(struct meson_clk_mpll_data){
717 .reg_off = HHI_MPLL_CNTL7,
722 .reg_off = HHI_MPLL_CNTL,
727 .reg_off = HHI_MPLL_CNTL7,
731 .lock = &meson_clk_lock,
733 .hw.init = &(struct clk_init_data){
735 .ops = &meson_clk_mpll_ops,
736 .parent_hws = (const struct clk_hw *[]) {
743 static struct clk_regmap gxl_mpll0_div = {
744 .data = &(struct meson_clk_mpll_data){
746 .reg_off = HHI_MPLL_CNTL7,
751 .reg_off = HHI_MPLL_CNTL7,
756 .reg_off = HHI_MPLL_CNTL7,
760 .lock = &meson_clk_lock,
762 .hw.init = &(struct clk_init_data){
764 .ops = &meson_clk_mpll_ops,
765 .parent_hws = (const struct clk_hw *[]) {
772 static struct clk_regmap gxbb_mpll0 = {
773 .data = &(struct clk_regmap_gate_data){
774 .offset = HHI_MPLL_CNTL7,
777 .hw.init = &(struct clk_init_data){
779 .ops = &clk_regmap_gate_ops,
780 .parent_data = &(const struct clk_parent_data) {
783 * GXL and GXBB have different SDM_EN registers. We
784 * fallback to the global naming string mechanism so
785 * mpll0_div picks up the appropriate one.
791 .flags = CLK_SET_RATE_PARENT,
795 static struct clk_regmap gxbb_mpll1_div = {
796 .data = &(struct meson_clk_mpll_data){
798 .reg_off = HHI_MPLL_CNTL8,
803 .reg_off = HHI_MPLL_CNTL8,
808 .reg_off = HHI_MPLL_CNTL8,
812 .lock = &meson_clk_lock,
814 .hw.init = &(struct clk_init_data){
816 .ops = &meson_clk_mpll_ops,
817 .parent_hws = (const struct clk_hw *[]) {
824 static struct clk_regmap gxbb_mpll1 = {
825 .data = &(struct clk_regmap_gate_data){
826 .offset = HHI_MPLL_CNTL8,
829 .hw.init = &(struct clk_init_data){
831 .ops = &clk_regmap_gate_ops,
832 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
834 .flags = CLK_SET_RATE_PARENT,
838 static struct clk_regmap gxbb_mpll2_div = {
839 .data = &(struct meson_clk_mpll_data){
841 .reg_off = HHI_MPLL_CNTL9,
846 .reg_off = HHI_MPLL_CNTL9,
851 .reg_off = HHI_MPLL_CNTL9,
855 .lock = &meson_clk_lock,
857 .hw.init = &(struct clk_init_data){
859 .ops = &meson_clk_mpll_ops,
860 .parent_hws = (const struct clk_hw *[]) {
867 static struct clk_regmap gxbb_mpll2 = {
868 .data = &(struct clk_regmap_gate_data){
869 .offset = HHI_MPLL_CNTL9,
872 .hw.init = &(struct clk_init_data){
874 .ops = &clk_regmap_gate_ops,
875 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
877 .flags = CLK_SET_RATE_PARENT,
881 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
882 static const struct clk_parent_data clk81_parent_data[] = {
883 { .fw_name = "xtal", },
884 { .hw = &gxbb_fclk_div7.hw },
885 { .hw = &gxbb_mpll1.hw },
886 { .hw = &gxbb_mpll2.hw },
887 { .hw = &gxbb_fclk_div4.hw },
888 { .hw = &gxbb_fclk_div3.hw },
889 { .hw = &gxbb_fclk_div5.hw },
892 static struct clk_regmap gxbb_mpeg_clk_sel = {
893 .data = &(struct clk_regmap_mux_data){
894 .offset = HHI_MPEG_CLK_CNTL,
897 .table = mux_table_clk81,
899 .hw.init = &(struct clk_init_data){
900 .name = "mpeg_clk_sel",
901 .ops = &clk_regmap_mux_ro_ops,
903 * bits 14:12 selects from 8 possible parents:
904 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
905 * fclk_div4, fclk_div3, fclk_div5
907 .parent_data = clk81_parent_data,
908 .num_parents = ARRAY_SIZE(clk81_parent_data),
912 static struct clk_regmap gxbb_mpeg_clk_div = {
913 .data = &(struct clk_regmap_div_data){
914 .offset = HHI_MPEG_CLK_CNTL,
918 .hw.init = &(struct clk_init_data){
919 .name = "mpeg_clk_div",
920 .ops = &clk_regmap_divider_ro_ops,
921 .parent_hws = (const struct clk_hw *[]) {
922 &gxbb_mpeg_clk_sel.hw
928 /* the mother of dragons gates */
929 static struct clk_regmap gxbb_clk81 = {
930 .data = &(struct clk_regmap_gate_data){
931 .offset = HHI_MPEG_CLK_CNTL,
934 .hw.init = &(struct clk_init_data){
936 .ops = &clk_regmap_gate_ops,
937 .parent_hws = (const struct clk_hw *[]) {
938 &gxbb_mpeg_clk_div.hw
941 .flags = CLK_IS_CRITICAL,
945 static struct clk_regmap gxbb_sar_adc_clk_sel = {
946 .data = &(struct clk_regmap_mux_data){
947 .offset = HHI_SAR_CLK_CNTL,
951 .hw.init = &(struct clk_init_data){
952 .name = "sar_adc_clk_sel",
953 .ops = &clk_regmap_mux_ops,
954 /* NOTE: The datasheet doesn't list the parents for bit 10 */
955 .parent_data = (const struct clk_parent_data []) {
956 { .fw_name = "xtal", },
957 { .hw = &gxbb_clk81.hw },
963 static struct clk_regmap gxbb_sar_adc_clk_div = {
964 .data = &(struct clk_regmap_div_data){
965 .offset = HHI_SAR_CLK_CNTL,
969 .hw.init = &(struct clk_init_data){
970 .name = "sar_adc_clk_div",
971 .ops = &clk_regmap_divider_ops,
972 .parent_hws = (const struct clk_hw *[]) {
973 &gxbb_sar_adc_clk_sel.hw
976 .flags = CLK_SET_RATE_PARENT,
980 static struct clk_regmap gxbb_sar_adc_clk = {
981 .data = &(struct clk_regmap_gate_data){
982 .offset = HHI_SAR_CLK_CNTL,
985 .hw.init = &(struct clk_init_data){
986 .name = "sar_adc_clk",
987 .ops = &clk_regmap_gate_ops,
988 .parent_hws = (const struct clk_hw *[]) {
989 &gxbb_sar_adc_clk_div.hw
992 .flags = CLK_SET_RATE_PARENT,
997 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
998 * muxed by a glitch-free switch. The CCF can manage this glitch-free
999 * mux because it does top-to-bottom updates the each clock tree and
1000 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1003 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
1004 { .fw_name = "xtal", },
1005 { .hw = &gxbb_gp0_pll.hw },
1006 { .hw = &gxbb_mpll2.hw },
1007 { .hw = &gxbb_mpll1.hw },
1008 { .hw = &gxbb_fclk_div7.hw },
1009 { .hw = &gxbb_fclk_div4.hw },
1010 { .hw = &gxbb_fclk_div3.hw },
1011 { .hw = &gxbb_fclk_div5.hw },
1014 static struct clk_regmap gxbb_mali_0_sel = {
1015 .data = &(struct clk_regmap_mux_data){
1016 .offset = HHI_MALI_CLK_CNTL,
1020 .hw.init = &(struct clk_init_data){
1021 .name = "mali_0_sel",
1022 .ops = &clk_regmap_mux_ops,
1023 .parent_data = gxbb_mali_0_1_parent_data,
1026 * Don't request the parent to change the rate because
1027 * all GPU frequencies can be derived from the fclk_*
1028 * clocks and one special GP0_PLL setting. This is
1029 * important because we need the MPLL clocks for audio.
1035 static struct clk_regmap gxbb_mali_0_div = {
1036 .data = &(struct clk_regmap_div_data){
1037 .offset = HHI_MALI_CLK_CNTL,
1041 .hw.init = &(struct clk_init_data){
1042 .name = "mali_0_div",
1043 .ops = &clk_regmap_divider_ops,
1044 .parent_hws = (const struct clk_hw *[]) {
1048 .flags = CLK_SET_RATE_PARENT,
1052 static struct clk_regmap gxbb_mali_0 = {
1053 .data = &(struct clk_regmap_gate_data){
1054 .offset = HHI_MALI_CLK_CNTL,
1057 .hw.init = &(struct clk_init_data){
1059 .ops = &clk_regmap_gate_ops,
1060 .parent_hws = (const struct clk_hw *[]) {
1064 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1068 static struct clk_regmap gxbb_mali_1_sel = {
1069 .data = &(struct clk_regmap_mux_data){
1070 .offset = HHI_MALI_CLK_CNTL,
1074 .hw.init = &(struct clk_init_data){
1075 .name = "mali_1_sel",
1076 .ops = &clk_regmap_mux_ops,
1077 .parent_data = gxbb_mali_0_1_parent_data,
1080 * Don't request the parent to change the rate because
1081 * all GPU frequencies can be derived from the fclk_*
1082 * clocks and one special GP0_PLL setting. This is
1083 * important because we need the MPLL clocks for audio.
1089 static struct clk_regmap gxbb_mali_1_div = {
1090 .data = &(struct clk_regmap_div_data){
1091 .offset = HHI_MALI_CLK_CNTL,
1095 .hw.init = &(struct clk_init_data){
1096 .name = "mali_1_div",
1097 .ops = &clk_regmap_divider_ops,
1098 .parent_hws = (const struct clk_hw *[]) {
1102 .flags = CLK_SET_RATE_PARENT,
1106 static struct clk_regmap gxbb_mali_1 = {
1107 .data = &(struct clk_regmap_gate_data){
1108 .offset = HHI_MALI_CLK_CNTL,
1111 .hw.init = &(struct clk_init_data){
1113 .ops = &clk_regmap_gate_ops,
1114 .parent_hws = (const struct clk_hw *[]) {
1118 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1122 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1127 static struct clk_regmap gxbb_mali = {
1128 .data = &(struct clk_regmap_mux_data){
1129 .offset = HHI_MALI_CLK_CNTL,
1133 .hw.init = &(struct clk_init_data){
1135 .ops = &clk_regmap_mux_ops,
1136 .parent_hws = gxbb_mali_parent_hws,
1138 .flags = CLK_SET_RATE_PARENT,
1142 static struct clk_regmap gxbb_cts_amclk_sel = {
1143 .data = &(struct clk_regmap_mux_data){
1144 .offset = HHI_AUD_CLK_CNTL,
1147 .table = (u32[]){ 1, 2, 3 },
1148 .flags = CLK_MUX_ROUND_CLOSEST,
1150 .hw.init = &(struct clk_init_data){
1151 .name = "cts_amclk_sel",
1152 .ops = &clk_regmap_mux_ops,
1153 .parent_hws = (const struct clk_hw *[]) {
1162 static struct clk_regmap gxbb_cts_amclk_div = {
1163 .data = &(struct clk_regmap_div_data) {
1164 .offset = HHI_AUD_CLK_CNTL,
1167 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1169 .hw.init = &(struct clk_init_data){
1170 .name = "cts_amclk_div",
1171 .ops = &clk_regmap_divider_ops,
1172 .parent_hws = (const struct clk_hw *[]) {
1173 &gxbb_cts_amclk_sel.hw
1176 .flags = CLK_SET_RATE_PARENT,
1180 static struct clk_regmap gxbb_cts_amclk = {
1181 .data = &(struct clk_regmap_gate_data){
1182 .offset = HHI_AUD_CLK_CNTL,
1185 .hw.init = &(struct clk_init_data){
1186 .name = "cts_amclk",
1187 .ops = &clk_regmap_gate_ops,
1188 .parent_hws = (const struct clk_hw *[]) {
1189 &gxbb_cts_amclk_div.hw
1192 .flags = CLK_SET_RATE_PARENT,
1196 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1197 .data = &(struct clk_regmap_mux_data){
1198 .offset = HHI_AUD_CLK_CNTL2,
1201 .table = (u32[]){ 1, 2, 3 },
1202 .flags = CLK_MUX_ROUND_CLOSEST,
1204 .hw.init = &(struct clk_init_data) {
1205 .name = "cts_mclk_i958_sel",
1206 .ops = &clk_regmap_mux_ops,
1207 .parent_hws = (const struct clk_hw *[]) {
1216 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1217 .data = &(struct clk_regmap_div_data){
1218 .offset = HHI_AUD_CLK_CNTL2,
1221 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1223 .hw.init = &(struct clk_init_data) {
1224 .name = "cts_mclk_i958_div",
1225 .ops = &clk_regmap_divider_ops,
1226 .parent_hws = (const struct clk_hw *[]) {
1227 &gxbb_cts_mclk_i958_sel.hw
1230 .flags = CLK_SET_RATE_PARENT,
1234 static struct clk_regmap gxbb_cts_mclk_i958 = {
1235 .data = &(struct clk_regmap_gate_data){
1236 .offset = HHI_AUD_CLK_CNTL2,
1239 .hw.init = &(struct clk_init_data){
1240 .name = "cts_mclk_i958",
1241 .ops = &clk_regmap_gate_ops,
1242 .parent_hws = (const struct clk_hw *[]) {
1243 &gxbb_cts_mclk_i958_div.hw
1246 .flags = CLK_SET_RATE_PARENT,
1250 static struct clk_regmap gxbb_cts_i958 = {
1251 .data = &(struct clk_regmap_mux_data){
1252 .offset = HHI_AUD_CLK_CNTL2,
1256 .hw.init = &(struct clk_init_data){
1258 .ops = &clk_regmap_mux_ops,
1259 .parent_hws = (const struct clk_hw *[]) {
1261 &gxbb_cts_mclk_i958.hw
1265 *The parent is specific to origin of the audio data. Let the
1266 * consumer choose the appropriate parent
1268 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1272 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1273 { .fw_name = "xtal", },
1275 * FIXME: This clock is provided by the ao clock controller but the
1276 * clock is not yet part of the binding of this controller, so string
1277 * name must be use to set this parent.
1279 { .name = "cts_slow_oscin", .index = -1 },
1280 { .hw = &gxbb_fclk_div3.hw },
1281 { .hw = &gxbb_fclk_div5.hw },
1284 static struct clk_regmap gxbb_32k_clk_sel = {
1285 .data = &(struct clk_regmap_mux_data){
1286 .offset = HHI_32K_CLK_CNTL,
1290 .hw.init = &(struct clk_init_data){
1291 .name = "32k_clk_sel",
1292 .ops = &clk_regmap_mux_ops,
1293 .parent_data = gxbb_32k_clk_parent_data,
1295 .flags = CLK_SET_RATE_PARENT,
1299 static struct clk_regmap gxbb_32k_clk_div = {
1300 .data = &(struct clk_regmap_div_data){
1301 .offset = HHI_32K_CLK_CNTL,
1305 .hw.init = &(struct clk_init_data){
1306 .name = "32k_clk_div",
1307 .ops = &clk_regmap_divider_ops,
1308 .parent_hws = (const struct clk_hw *[]) {
1309 &gxbb_32k_clk_sel.hw
1312 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1316 static struct clk_regmap gxbb_32k_clk = {
1317 .data = &(struct clk_regmap_gate_data){
1318 .offset = HHI_32K_CLK_CNTL,
1321 .hw.init = &(struct clk_init_data){
1323 .ops = &clk_regmap_gate_ops,
1324 .parent_hws = (const struct clk_hw *[]) {
1325 &gxbb_32k_clk_div.hw
1328 .flags = CLK_SET_RATE_PARENT,
1332 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1333 { .fw_name = "xtal", },
1334 { .hw = &gxbb_fclk_div2.hw },
1335 { .hw = &gxbb_fclk_div3.hw },
1336 { .hw = &gxbb_fclk_div5.hw },
1337 { .hw = &gxbb_fclk_div7.hw },
1339 * Following these parent clocks, we should also have had mpll2, mpll3
1340 * and gp0_pll but these clocks are too precious to be used here. All
1341 * the necessary rates for MMC and NAND operation can be acheived using
1342 * xtal or fclk_div clocks
1347 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1348 .data = &(struct clk_regmap_mux_data){
1349 .offset = HHI_SD_EMMC_CLK_CNTL,
1353 .hw.init = &(struct clk_init_data) {
1354 .name = "sd_emmc_a_clk0_sel",
1355 .ops = &clk_regmap_mux_ops,
1356 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1357 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1358 .flags = CLK_SET_RATE_PARENT,
1362 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1363 .data = &(struct clk_regmap_div_data){
1364 .offset = HHI_SD_EMMC_CLK_CNTL,
1367 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1369 .hw.init = &(struct clk_init_data) {
1370 .name = "sd_emmc_a_clk0_div",
1371 .ops = &clk_regmap_divider_ops,
1372 .parent_hws = (const struct clk_hw *[]) {
1373 &gxbb_sd_emmc_a_clk0_sel.hw
1376 .flags = CLK_SET_RATE_PARENT,
1380 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1381 .data = &(struct clk_regmap_gate_data){
1382 .offset = HHI_SD_EMMC_CLK_CNTL,
1385 .hw.init = &(struct clk_init_data){
1386 .name = "sd_emmc_a_clk0",
1387 .ops = &clk_regmap_gate_ops,
1388 .parent_hws = (const struct clk_hw *[]) {
1389 &gxbb_sd_emmc_a_clk0_div.hw
1392 .flags = CLK_SET_RATE_PARENT,
1397 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1398 .data = &(struct clk_regmap_mux_data){
1399 .offset = HHI_SD_EMMC_CLK_CNTL,
1403 .hw.init = &(struct clk_init_data) {
1404 .name = "sd_emmc_b_clk0_sel",
1405 .ops = &clk_regmap_mux_ops,
1406 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1407 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1408 .flags = CLK_SET_RATE_PARENT,
1412 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1413 .data = &(struct clk_regmap_div_data){
1414 .offset = HHI_SD_EMMC_CLK_CNTL,
1417 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1419 .hw.init = &(struct clk_init_data) {
1420 .name = "sd_emmc_b_clk0_div",
1421 .ops = &clk_regmap_divider_ops,
1422 .parent_hws = (const struct clk_hw *[]) {
1423 &gxbb_sd_emmc_b_clk0_sel.hw
1426 .flags = CLK_SET_RATE_PARENT,
1430 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1431 .data = &(struct clk_regmap_gate_data){
1432 .offset = HHI_SD_EMMC_CLK_CNTL,
1435 .hw.init = &(struct clk_init_data){
1436 .name = "sd_emmc_b_clk0",
1437 .ops = &clk_regmap_gate_ops,
1438 .parent_hws = (const struct clk_hw *[]) {
1439 &gxbb_sd_emmc_b_clk0_div.hw
1442 .flags = CLK_SET_RATE_PARENT,
1446 /* EMMC/NAND clock */
1447 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1448 .data = &(struct clk_regmap_mux_data){
1449 .offset = HHI_NAND_CLK_CNTL,
1453 .hw.init = &(struct clk_init_data) {
1454 .name = "sd_emmc_c_clk0_sel",
1455 .ops = &clk_regmap_mux_ops,
1456 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1457 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1458 .flags = CLK_SET_RATE_PARENT,
1462 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1463 .data = &(struct clk_regmap_div_data){
1464 .offset = HHI_NAND_CLK_CNTL,
1467 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1469 .hw.init = &(struct clk_init_data) {
1470 .name = "sd_emmc_c_clk0_div",
1471 .ops = &clk_regmap_divider_ops,
1472 .parent_hws = (const struct clk_hw *[]) {
1473 &gxbb_sd_emmc_c_clk0_sel.hw
1476 .flags = CLK_SET_RATE_PARENT,
1480 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1481 .data = &(struct clk_regmap_gate_data){
1482 .offset = HHI_NAND_CLK_CNTL,
1485 .hw.init = &(struct clk_init_data){
1486 .name = "sd_emmc_c_clk0",
1487 .ops = &clk_regmap_gate_ops,
1488 .parent_hws = (const struct clk_hw *[]) {
1489 &gxbb_sd_emmc_c_clk0_div.hw
1492 .flags = CLK_SET_RATE_PARENT,
1498 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1505 static struct clk_regmap gxbb_vpu_0_sel = {
1506 .data = &(struct clk_regmap_mux_data){
1507 .offset = HHI_VPU_CLK_CNTL,
1511 .hw.init = &(struct clk_init_data){
1512 .name = "vpu_0_sel",
1513 .ops = &clk_regmap_mux_ops,
1515 * bits 9:10 selects from 4 possible parents:
1516 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1518 .parent_hws = gxbb_vpu_parent_hws,
1519 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1520 .flags = CLK_SET_RATE_NO_REPARENT,
1524 static struct clk_regmap gxbb_vpu_0_div = {
1525 .data = &(struct clk_regmap_div_data){
1526 .offset = HHI_VPU_CLK_CNTL,
1530 .hw.init = &(struct clk_init_data){
1531 .name = "vpu_0_div",
1532 .ops = &clk_regmap_divider_ops,
1533 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1535 .flags = CLK_SET_RATE_PARENT,
1539 static struct clk_regmap gxbb_vpu_0 = {
1540 .data = &(struct clk_regmap_gate_data){
1541 .offset = HHI_VPU_CLK_CNTL,
1544 .hw.init = &(struct clk_init_data) {
1546 .ops = &clk_regmap_gate_ops,
1547 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1549 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1553 static struct clk_regmap gxbb_vpu_1_sel = {
1554 .data = &(struct clk_regmap_mux_data){
1555 .offset = HHI_VPU_CLK_CNTL,
1559 .hw.init = &(struct clk_init_data){
1560 .name = "vpu_1_sel",
1561 .ops = &clk_regmap_mux_ops,
1563 * bits 25:26 selects from 4 possible parents:
1564 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1566 .parent_hws = gxbb_vpu_parent_hws,
1567 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1568 .flags = CLK_SET_RATE_NO_REPARENT,
1572 static struct clk_regmap gxbb_vpu_1_div = {
1573 .data = &(struct clk_regmap_div_data){
1574 .offset = HHI_VPU_CLK_CNTL,
1578 .hw.init = &(struct clk_init_data){
1579 .name = "vpu_1_div",
1580 .ops = &clk_regmap_divider_ops,
1581 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1583 .flags = CLK_SET_RATE_PARENT,
1587 static struct clk_regmap gxbb_vpu_1 = {
1588 .data = &(struct clk_regmap_gate_data){
1589 .offset = HHI_VPU_CLK_CNTL,
1592 .hw.init = &(struct clk_init_data) {
1594 .ops = &clk_regmap_gate_ops,
1595 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1597 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1601 static struct clk_regmap gxbb_vpu = {
1602 .data = &(struct clk_regmap_mux_data){
1603 .offset = HHI_VPU_CLK_CNTL,
1607 .hw.init = &(struct clk_init_data){
1609 .ops = &clk_regmap_mux_ops,
1611 * bit 31 selects from 2 possible parents:
1614 .parent_hws = (const struct clk_hw *[]) {
1619 .flags = CLK_SET_RATE_NO_REPARENT,
1625 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1632 static struct clk_regmap gxbb_vapb_0_sel = {
1633 .data = &(struct clk_regmap_mux_data){
1634 .offset = HHI_VAPBCLK_CNTL,
1638 .hw.init = &(struct clk_init_data){
1639 .name = "vapb_0_sel",
1640 .ops = &clk_regmap_mux_ops,
1642 * bits 9:10 selects from 4 possible parents:
1643 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1645 .parent_hws = gxbb_vapb_parent_hws,
1646 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1647 .flags = CLK_SET_RATE_NO_REPARENT,
1651 static struct clk_regmap gxbb_vapb_0_div = {
1652 .data = &(struct clk_regmap_div_data){
1653 .offset = HHI_VAPBCLK_CNTL,
1657 .hw.init = &(struct clk_init_data){
1658 .name = "vapb_0_div",
1659 .ops = &clk_regmap_divider_ops,
1660 .parent_hws = (const struct clk_hw *[]) {
1664 .flags = CLK_SET_RATE_PARENT,
1668 static struct clk_regmap gxbb_vapb_0 = {
1669 .data = &(struct clk_regmap_gate_data){
1670 .offset = HHI_VAPBCLK_CNTL,
1673 .hw.init = &(struct clk_init_data) {
1675 .ops = &clk_regmap_gate_ops,
1676 .parent_hws = (const struct clk_hw *[]) {
1680 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1684 static struct clk_regmap gxbb_vapb_1_sel = {
1685 .data = &(struct clk_regmap_mux_data){
1686 .offset = HHI_VAPBCLK_CNTL,
1690 .hw.init = &(struct clk_init_data){
1691 .name = "vapb_1_sel",
1692 .ops = &clk_regmap_mux_ops,
1694 * bits 25:26 selects from 4 possible parents:
1695 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1697 .parent_hws = gxbb_vapb_parent_hws,
1698 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1699 .flags = CLK_SET_RATE_NO_REPARENT,
1703 static struct clk_regmap gxbb_vapb_1_div = {
1704 .data = &(struct clk_regmap_div_data){
1705 .offset = HHI_VAPBCLK_CNTL,
1709 .hw.init = &(struct clk_init_data){
1710 .name = "vapb_1_div",
1711 .ops = &clk_regmap_divider_ops,
1712 .parent_hws = (const struct clk_hw *[]) {
1716 .flags = CLK_SET_RATE_PARENT,
1720 static struct clk_regmap gxbb_vapb_1 = {
1721 .data = &(struct clk_regmap_gate_data){
1722 .offset = HHI_VAPBCLK_CNTL,
1725 .hw.init = &(struct clk_init_data) {
1727 .ops = &clk_regmap_gate_ops,
1728 .parent_hws = (const struct clk_hw *[]) {
1732 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1736 static struct clk_regmap gxbb_vapb_sel = {
1737 .data = &(struct clk_regmap_mux_data){
1738 .offset = HHI_VAPBCLK_CNTL,
1742 .hw.init = &(struct clk_init_data){
1744 .ops = &clk_regmap_mux_ops,
1746 * bit 31 selects from 2 possible parents:
1749 .parent_hws = (const struct clk_hw *[]) {
1754 .flags = CLK_SET_RATE_NO_REPARENT,
1758 static struct clk_regmap gxbb_vapb = {
1759 .data = &(struct clk_regmap_gate_data){
1760 .offset = HHI_VAPBCLK_CNTL,
1763 .hw.init = &(struct clk_init_data) {
1765 .ops = &clk_regmap_gate_ops,
1766 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1768 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1774 static struct clk_regmap gxbb_vid_pll_div = {
1775 .data = &(struct meson_vid_pll_div_data){
1777 .reg_off = HHI_VID_PLL_CLK_DIV,
1782 .reg_off = HHI_VID_PLL_CLK_DIV,
1787 .hw.init = &(struct clk_init_data) {
1788 .name = "vid_pll_div",
1789 .ops = &meson_vid_pll_div_ro_ops,
1790 .parent_data = &(const struct clk_parent_data) {
1793 * GXL and GXBB have different hdmi_plls (with
1794 * different struct clk_hw). We fallback to the global
1795 * naming string mechanism so vid_pll_div picks up the
1802 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1806 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1807 { .hw = &gxbb_vid_pll_div.hw },
1810 * GXL and GXBB have different hdmi_plls (with
1811 * different struct clk_hw). We fallback to the global
1812 * naming string mechanism so vid_pll_div picks up the
1815 { .name = "hdmi_pll", .index = -1 },
1818 static struct clk_regmap gxbb_vid_pll_sel = {
1819 .data = &(struct clk_regmap_mux_data){
1820 .offset = HHI_VID_PLL_CLK_DIV,
1824 .hw.init = &(struct clk_init_data){
1825 .name = "vid_pll_sel",
1826 .ops = &clk_regmap_mux_ops,
1828 * bit 18 selects from 2 possible parents:
1829 * vid_pll_div or hdmi_pll
1831 .parent_data = gxbb_vid_pll_parent_data,
1832 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1833 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1837 static struct clk_regmap gxbb_vid_pll = {
1838 .data = &(struct clk_regmap_gate_data){
1839 .offset = HHI_VID_PLL_CLK_DIV,
1842 .hw.init = &(struct clk_init_data) {
1844 .ops = &clk_regmap_gate_ops,
1845 .parent_hws = (const struct clk_hw *[]) {
1846 &gxbb_vid_pll_sel.hw
1849 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1853 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1863 static struct clk_regmap gxbb_vclk_sel = {
1864 .data = &(struct clk_regmap_mux_data){
1865 .offset = HHI_VID_CLK_CNTL,
1869 .hw.init = &(struct clk_init_data){
1871 .ops = &clk_regmap_mux_ops,
1873 * bits 16:18 selects from 8 possible parents:
1874 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1875 * vid_pll, fclk_div7, mp1
1877 .parent_hws = gxbb_vclk_parent_hws,
1878 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1879 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1883 static struct clk_regmap gxbb_vclk2_sel = {
1884 .data = &(struct clk_regmap_mux_data){
1885 .offset = HHI_VIID_CLK_CNTL,
1889 .hw.init = &(struct clk_init_data){
1890 .name = "vclk2_sel",
1891 .ops = &clk_regmap_mux_ops,
1893 * bits 16:18 selects from 8 possible parents:
1894 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1895 * vid_pll, fclk_div7, mp1
1897 .parent_hws = gxbb_vclk_parent_hws,
1898 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1899 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1903 static struct clk_regmap gxbb_vclk_input = {
1904 .data = &(struct clk_regmap_gate_data){
1905 .offset = HHI_VID_CLK_DIV,
1908 .hw.init = &(struct clk_init_data) {
1909 .name = "vclk_input",
1910 .ops = &clk_regmap_gate_ops,
1911 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1913 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1917 static struct clk_regmap gxbb_vclk2_input = {
1918 .data = &(struct clk_regmap_gate_data){
1919 .offset = HHI_VIID_CLK_DIV,
1922 .hw.init = &(struct clk_init_data) {
1923 .name = "vclk2_input",
1924 .ops = &clk_regmap_gate_ops,
1925 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1927 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1931 static struct clk_regmap gxbb_vclk_div = {
1932 .data = &(struct clk_regmap_div_data){
1933 .offset = HHI_VID_CLK_DIV,
1937 .hw.init = &(struct clk_init_data){
1939 .ops = &clk_regmap_divider_ops,
1940 .parent_hws = (const struct clk_hw *[]) {
1944 .flags = CLK_GET_RATE_NOCACHE,
1948 static struct clk_regmap gxbb_vclk2_div = {
1949 .data = &(struct clk_regmap_div_data){
1950 .offset = HHI_VIID_CLK_DIV,
1954 .hw.init = &(struct clk_init_data){
1955 .name = "vclk2_div",
1956 .ops = &clk_regmap_divider_ops,
1957 .parent_hws = (const struct clk_hw *[]) {
1958 &gxbb_vclk2_input.hw
1961 .flags = CLK_GET_RATE_NOCACHE,
1965 static struct clk_regmap gxbb_vclk = {
1966 .data = &(struct clk_regmap_gate_data){
1967 .offset = HHI_VID_CLK_CNTL,
1970 .hw.init = &(struct clk_init_data) {
1972 .ops = &clk_regmap_gate_ops,
1973 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1975 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1979 static struct clk_regmap gxbb_vclk2 = {
1980 .data = &(struct clk_regmap_gate_data){
1981 .offset = HHI_VIID_CLK_CNTL,
1984 .hw.init = &(struct clk_init_data) {
1986 .ops = &clk_regmap_gate_ops,
1987 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1989 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1993 static struct clk_regmap gxbb_vclk_div1 = {
1994 .data = &(struct clk_regmap_gate_data){
1995 .offset = HHI_VID_CLK_CNTL,
1998 .hw.init = &(struct clk_init_data) {
1999 .name = "vclk_div1",
2000 .ops = &clk_regmap_gate_ops,
2001 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2003 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2007 static struct clk_regmap gxbb_vclk_div2_en = {
2008 .data = &(struct clk_regmap_gate_data){
2009 .offset = HHI_VID_CLK_CNTL,
2012 .hw.init = &(struct clk_init_data) {
2013 .name = "vclk_div2_en",
2014 .ops = &clk_regmap_gate_ops,
2015 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2017 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2021 static struct clk_regmap gxbb_vclk_div4_en = {
2022 .data = &(struct clk_regmap_gate_data){
2023 .offset = HHI_VID_CLK_CNTL,
2026 .hw.init = &(struct clk_init_data) {
2027 .name = "vclk_div4_en",
2028 .ops = &clk_regmap_gate_ops,
2029 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2031 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2035 static struct clk_regmap gxbb_vclk_div6_en = {
2036 .data = &(struct clk_regmap_gate_data){
2037 .offset = HHI_VID_CLK_CNTL,
2040 .hw.init = &(struct clk_init_data) {
2041 .name = "vclk_div6_en",
2042 .ops = &clk_regmap_gate_ops,
2043 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2045 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2049 static struct clk_regmap gxbb_vclk_div12_en = {
2050 .data = &(struct clk_regmap_gate_data){
2051 .offset = HHI_VID_CLK_CNTL,
2054 .hw.init = &(struct clk_init_data) {
2055 .name = "vclk_div12_en",
2056 .ops = &clk_regmap_gate_ops,
2057 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2059 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2063 static struct clk_regmap gxbb_vclk2_div1 = {
2064 .data = &(struct clk_regmap_gate_data){
2065 .offset = HHI_VIID_CLK_CNTL,
2068 .hw.init = &(struct clk_init_data) {
2069 .name = "vclk2_div1",
2070 .ops = &clk_regmap_gate_ops,
2071 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2073 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2077 static struct clk_regmap gxbb_vclk2_div2_en = {
2078 .data = &(struct clk_regmap_gate_data){
2079 .offset = HHI_VIID_CLK_CNTL,
2082 .hw.init = &(struct clk_init_data) {
2083 .name = "vclk2_div2_en",
2084 .ops = &clk_regmap_gate_ops,
2085 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2087 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2091 static struct clk_regmap gxbb_vclk2_div4_en = {
2092 .data = &(struct clk_regmap_gate_data){
2093 .offset = HHI_VIID_CLK_CNTL,
2096 .hw.init = &(struct clk_init_data) {
2097 .name = "vclk2_div4_en",
2098 .ops = &clk_regmap_gate_ops,
2099 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2101 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2105 static struct clk_regmap gxbb_vclk2_div6_en = {
2106 .data = &(struct clk_regmap_gate_data){
2107 .offset = HHI_VIID_CLK_CNTL,
2110 .hw.init = &(struct clk_init_data) {
2111 .name = "vclk2_div6_en",
2112 .ops = &clk_regmap_gate_ops,
2113 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2115 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2119 static struct clk_regmap gxbb_vclk2_div12_en = {
2120 .data = &(struct clk_regmap_gate_data){
2121 .offset = HHI_VIID_CLK_CNTL,
2124 .hw.init = &(struct clk_init_data) {
2125 .name = "vclk2_div12_en",
2126 .ops = &clk_regmap_gate_ops,
2127 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2129 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2133 static struct clk_fixed_factor gxbb_vclk_div2 = {
2136 .hw.init = &(struct clk_init_data){
2137 .name = "vclk_div2",
2138 .ops = &clk_fixed_factor_ops,
2139 .parent_hws = (const struct clk_hw *[]) {
2140 &gxbb_vclk_div2_en.hw
2146 static struct clk_fixed_factor gxbb_vclk_div4 = {
2149 .hw.init = &(struct clk_init_data){
2150 .name = "vclk_div4",
2151 .ops = &clk_fixed_factor_ops,
2152 .parent_hws = (const struct clk_hw *[]) {
2153 &gxbb_vclk_div4_en.hw
2159 static struct clk_fixed_factor gxbb_vclk_div6 = {
2162 .hw.init = &(struct clk_init_data){
2163 .name = "vclk_div6",
2164 .ops = &clk_fixed_factor_ops,
2165 .parent_hws = (const struct clk_hw *[]) {
2166 &gxbb_vclk_div6_en.hw
2172 static struct clk_fixed_factor gxbb_vclk_div12 = {
2175 .hw.init = &(struct clk_init_data){
2176 .name = "vclk_div12",
2177 .ops = &clk_fixed_factor_ops,
2178 .parent_hws = (const struct clk_hw *[]) {
2179 &gxbb_vclk_div12_en.hw
2185 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2188 .hw.init = &(struct clk_init_data){
2189 .name = "vclk2_div2",
2190 .ops = &clk_fixed_factor_ops,
2191 .parent_hws = (const struct clk_hw *[]) {
2192 &gxbb_vclk2_div2_en.hw
2198 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2201 .hw.init = &(struct clk_init_data){
2202 .name = "vclk2_div4",
2203 .ops = &clk_fixed_factor_ops,
2204 .parent_hws = (const struct clk_hw *[]) {
2205 &gxbb_vclk2_div4_en.hw
2211 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2214 .hw.init = &(struct clk_init_data){
2215 .name = "vclk2_div6",
2216 .ops = &clk_fixed_factor_ops,
2217 .parent_hws = (const struct clk_hw *[]) {
2218 &gxbb_vclk2_div6_en.hw
2224 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2227 .hw.init = &(struct clk_init_data){
2228 .name = "vclk2_div12",
2229 .ops = &clk_fixed_factor_ops,
2230 .parent_hws = (const struct clk_hw *[]) {
2231 &gxbb_vclk2_div12_en.hw
2237 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2238 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2243 &gxbb_vclk_div12.hw,
2244 &gxbb_vclk2_div1.hw,
2245 &gxbb_vclk2_div2.hw,
2246 &gxbb_vclk2_div4.hw,
2247 &gxbb_vclk2_div6.hw,
2248 &gxbb_vclk2_div12.hw,
2251 static struct clk_regmap gxbb_cts_enci_sel = {
2252 .data = &(struct clk_regmap_mux_data){
2253 .offset = HHI_VID_CLK_DIV,
2256 .table = mux_table_cts_sel,
2258 .hw.init = &(struct clk_init_data){
2259 .name = "cts_enci_sel",
2260 .ops = &clk_regmap_mux_ops,
2261 .parent_hws = gxbb_cts_parent_hws,
2262 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2263 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2267 static struct clk_regmap gxbb_cts_encp_sel = {
2268 .data = &(struct clk_regmap_mux_data){
2269 .offset = HHI_VID_CLK_DIV,
2272 .table = mux_table_cts_sel,
2274 .hw.init = &(struct clk_init_data){
2275 .name = "cts_encp_sel",
2276 .ops = &clk_regmap_mux_ops,
2277 .parent_hws = gxbb_cts_parent_hws,
2278 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2279 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2283 static struct clk_regmap gxbb_cts_vdac_sel = {
2284 .data = &(struct clk_regmap_mux_data){
2285 .offset = HHI_VIID_CLK_DIV,
2288 .table = mux_table_cts_sel,
2290 .hw.init = &(struct clk_init_data){
2291 .name = "cts_vdac_sel",
2292 .ops = &clk_regmap_mux_ops,
2293 .parent_hws = gxbb_cts_parent_hws,
2294 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2295 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2299 /* TOFIX: add support for cts_tcon */
2300 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2301 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2306 &gxbb_vclk_div12.hw,
2307 &gxbb_vclk2_div1.hw,
2308 &gxbb_vclk2_div2.hw,
2309 &gxbb_vclk2_div4.hw,
2310 &gxbb_vclk2_div6.hw,
2311 &gxbb_vclk2_div12.hw,
2314 static struct clk_regmap gxbb_hdmi_tx_sel = {
2315 .data = &(struct clk_regmap_mux_data){
2316 .offset = HHI_HDMI_CLK_CNTL,
2319 .table = mux_table_hdmi_tx_sel,
2321 .hw.init = &(struct clk_init_data){
2322 .name = "hdmi_tx_sel",
2323 .ops = &clk_regmap_mux_ops,
2325 * bits 31:28 selects from 12 possible parents:
2326 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2327 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2330 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2331 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2332 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2336 static struct clk_regmap gxbb_cts_enci = {
2337 .data = &(struct clk_regmap_gate_data){
2338 .offset = HHI_VID_CLK_CNTL2,
2341 .hw.init = &(struct clk_init_data) {
2343 .ops = &clk_regmap_gate_ops,
2344 .parent_hws = (const struct clk_hw *[]) {
2345 &gxbb_cts_enci_sel.hw
2348 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2352 static struct clk_regmap gxbb_cts_encp = {
2353 .data = &(struct clk_regmap_gate_data){
2354 .offset = HHI_VID_CLK_CNTL2,
2357 .hw.init = &(struct clk_init_data) {
2359 .ops = &clk_regmap_gate_ops,
2360 .parent_hws = (const struct clk_hw *[]) {
2361 &gxbb_cts_encp_sel.hw
2364 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2368 static struct clk_regmap gxbb_cts_vdac = {
2369 .data = &(struct clk_regmap_gate_data){
2370 .offset = HHI_VID_CLK_CNTL2,
2373 .hw.init = &(struct clk_init_data) {
2375 .ops = &clk_regmap_gate_ops,
2376 .parent_hws = (const struct clk_hw *[]) {
2377 &gxbb_cts_vdac_sel.hw
2380 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2384 static struct clk_regmap gxbb_hdmi_tx = {
2385 .data = &(struct clk_regmap_gate_data){
2386 .offset = HHI_VID_CLK_CNTL2,
2389 .hw.init = &(struct clk_init_data) {
2391 .ops = &clk_regmap_gate_ops,
2392 .parent_hws = (const struct clk_hw *[]) {
2393 &gxbb_hdmi_tx_sel.hw
2396 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2402 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2403 { .fw_name = "xtal", },
2404 { .hw = &gxbb_fclk_div4.hw },
2405 { .hw = &gxbb_fclk_div3.hw },
2406 { .hw = &gxbb_fclk_div5.hw },
2409 static struct clk_regmap gxbb_hdmi_sel = {
2410 .data = &(struct clk_regmap_mux_data){
2411 .offset = HHI_HDMI_CLK_CNTL,
2414 .flags = CLK_MUX_ROUND_CLOSEST,
2416 .hw.init = &(struct clk_init_data){
2418 .ops = &clk_regmap_mux_ops,
2419 .parent_data = gxbb_hdmi_parent_data,
2420 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2421 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2425 static struct clk_regmap gxbb_hdmi_div = {
2426 .data = &(struct clk_regmap_div_data){
2427 .offset = HHI_HDMI_CLK_CNTL,
2431 .hw.init = &(struct clk_init_data){
2433 .ops = &clk_regmap_divider_ops,
2434 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2436 .flags = CLK_GET_RATE_NOCACHE,
2440 static struct clk_regmap gxbb_hdmi = {
2441 .data = &(struct clk_regmap_gate_data){
2442 .offset = HHI_HDMI_CLK_CNTL,
2445 .hw.init = &(struct clk_init_data) {
2447 .ops = &clk_regmap_gate_ops,
2448 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2450 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2456 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2463 static struct clk_regmap gxbb_vdec_1_sel = {
2464 .data = &(struct clk_regmap_mux_data){
2465 .offset = HHI_VDEC_CLK_CNTL,
2468 .flags = CLK_MUX_ROUND_CLOSEST,
2470 .hw.init = &(struct clk_init_data){
2471 .name = "vdec_1_sel",
2472 .ops = &clk_regmap_mux_ops,
2473 .parent_hws = gxbb_vdec_parent_hws,
2474 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2475 .flags = CLK_SET_RATE_PARENT,
2479 static struct clk_regmap gxbb_vdec_1_div = {
2480 .data = &(struct clk_regmap_div_data){
2481 .offset = HHI_VDEC_CLK_CNTL,
2484 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2486 .hw.init = &(struct clk_init_data){
2487 .name = "vdec_1_div",
2488 .ops = &clk_regmap_divider_ops,
2489 .parent_hws = (const struct clk_hw *[]) {
2493 .flags = CLK_SET_RATE_PARENT,
2497 static struct clk_regmap gxbb_vdec_1 = {
2498 .data = &(struct clk_regmap_gate_data){
2499 .offset = HHI_VDEC_CLK_CNTL,
2502 .hw.init = &(struct clk_init_data) {
2504 .ops = &clk_regmap_gate_ops,
2505 .parent_hws = (const struct clk_hw *[]) {
2509 .flags = CLK_SET_RATE_PARENT,
2513 static struct clk_regmap gxbb_vdec_hevc_sel = {
2514 .data = &(struct clk_regmap_mux_data){
2515 .offset = HHI_VDEC2_CLK_CNTL,
2518 .flags = CLK_MUX_ROUND_CLOSEST,
2520 .hw.init = &(struct clk_init_data){
2521 .name = "vdec_hevc_sel",
2522 .ops = &clk_regmap_mux_ops,
2523 .parent_hws = gxbb_vdec_parent_hws,
2524 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2525 .flags = CLK_SET_RATE_PARENT,
2529 static struct clk_regmap gxbb_vdec_hevc_div = {
2530 .data = &(struct clk_regmap_div_data){
2531 .offset = HHI_VDEC2_CLK_CNTL,
2534 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2536 .hw.init = &(struct clk_init_data){
2537 .name = "vdec_hevc_div",
2538 .ops = &clk_regmap_divider_ops,
2539 .parent_hws = (const struct clk_hw *[]) {
2540 &gxbb_vdec_hevc_sel.hw
2543 .flags = CLK_SET_RATE_PARENT,
2547 static struct clk_regmap gxbb_vdec_hevc = {
2548 .data = &(struct clk_regmap_gate_data){
2549 .offset = HHI_VDEC2_CLK_CNTL,
2552 .hw.init = &(struct clk_init_data) {
2553 .name = "vdec_hevc",
2554 .ops = &clk_regmap_gate_ops,
2555 .parent_hws = (const struct clk_hw *[]) {
2556 &gxbb_vdec_hevc_div.hw
2559 .flags = CLK_SET_RATE_PARENT,
2563 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2564 9, 10, 11, 13, 14, };
2565 static const struct clk_parent_data gen_clk_parent_data[] = {
2566 { .fw_name = "xtal", },
2567 { .hw = &gxbb_vdec_1.hw },
2568 { .hw = &gxbb_vdec_hevc.hw },
2569 { .hw = &gxbb_mpll0.hw },
2570 { .hw = &gxbb_mpll1.hw },
2571 { .hw = &gxbb_mpll2.hw },
2572 { .hw = &gxbb_fclk_div4.hw },
2573 { .hw = &gxbb_fclk_div3.hw },
2574 { .hw = &gxbb_fclk_div5.hw },
2575 { .hw = &gxbb_fclk_div7.hw },
2576 { .hw = &gxbb_gp0_pll.hw },
2579 static struct clk_regmap gxbb_gen_clk_sel = {
2580 .data = &(struct clk_regmap_mux_data){
2581 .offset = HHI_GEN_CLK_CNTL,
2584 .table = mux_table_gen_clk,
2586 .hw.init = &(struct clk_init_data){
2587 .name = "gen_clk_sel",
2588 .ops = &clk_regmap_mux_ops,
2590 * bits 15:12 selects from 14 possible parents:
2591 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2592 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2593 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2595 .parent_data = gen_clk_parent_data,
2596 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2600 static struct clk_regmap gxbb_gen_clk_div = {
2601 .data = &(struct clk_regmap_div_data){
2602 .offset = HHI_GEN_CLK_CNTL,
2606 .hw.init = &(struct clk_init_data){
2607 .name = "gen_clk_div",
2608 .ops = &clk_regmap_divider_ops,
2609 .parent_hws = (const struct clk_hw *[]) {
2610 &gxbb_gen_clk_sel.hw
2613 .flags = CLK_SET_RATE_PARENT,
2617 static struct clk_regmap gxbb_gen_clk = {
2618 .data = &(struct clk_regmap_gate_data){
2619 .offset = HHI_GEN_CLK_CNTL,
2622 .hw.init = &(struct clk_init_data){
2624 .ops = &clk_regmap_gate_ops,
2625 .parent_hws = (const struct clk_hw *[]) {
2626 &gxbb_gen_clk_div.hw
2629 .flags = CLK_SET_RATE_PARENT,
2633 #define MESON_GATE(_name, _reg, _bit) \
2634 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2636 /* Everything Else (EE) domain gates */
2637 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2638 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2639 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2640 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2641 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2642 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2643 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2644 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2645 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2646 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2647 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2648 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2649 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2650 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2651 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2652 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2653 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2654 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2655 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2656 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2657 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2658 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2659 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2661 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2662 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2663 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2664 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2665 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2666 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2667 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2668 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2669 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2670 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2671 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2672 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2673 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2674 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2675 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2676 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2677 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2679 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2680 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2681 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2682 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2683 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2684 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2685 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2686 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2687 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2688 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2689 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2690 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2691 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2693 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2694 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2695 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2696 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2697 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2698 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2699 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2700 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2701 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2702 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2703 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2704 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2705 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2706 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2707 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2708 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2710 /* Always On (AO) domain gates */
2712 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2713 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2714 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2715 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2716 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2719 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2720 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2721 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2722 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2723 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2724 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2725 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2726 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2728 /* Array of all clocks provided by this provider */
2730 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2732 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2733 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
2734 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2735 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2736 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2737 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2738 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2739 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2740 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2741 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2742 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2743 [CLKID_CLK81] = &gxbb_clk81.hw,
2744 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2745 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2746 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2747 [CLKID_DDR] = &gxbb_ddr.hw,
2748 [CLKID_DOS] = &gxbb_dos.hw,
2749 [CLKID_ISA] = &gxbb_isa.hw,
2750 [CLKID_PL301] = &gxbb_pl301.hw,
2751 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2752 [CLKID_SPICC] = &gxbb_spicc.hw,
2753 [CLKID_I2C] = &gxbb_i2c.hw,
2754 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2755 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2756 [CLKID_RNG0] = &gxbb_rng0.hw,
2757 [CLKID_UART0] = &gxbb_uart0.hw,
2758 [CLKID_SDHC] = &gxbb_sdhc.hw,
2759 [CLKID_STREAM] = &gxbb_stream.hw,
2760 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2761 [CLKID_SDIO] = &gxbb_sdio.hw,
2762 [CLKID_ABUF] = &gxbb_abuf.hw,
2763 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2764 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2765 [CLKID_SPI] = &gxbb_spi.hw,
2766 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2767 [CLKID_ETH] = &gxbb_eth.hw,
2768 [CLKID_DEMUX] = &gxbb_demux.hw,
2769 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2770 [CLKID_IEC958] = &gxbb_iec958.hw,
2771 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2772 [CLKID_AMCLK] = &gxbb_amclk.hw,
2773 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2774 [CLKID_MIXER] = &gxbb_mixer.hw,
2775 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2776 [CLKID_ADC] = &gxbb_adc.hw,
2777 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2778 [CLKID_AIU] = &gxbb_aiu.hw,
2779 [CLKID_UART1] = &gxbb_uart1.hw,
2780 [CLKID_G2D] = &gxbb_g2d.hw,
2781 [CLKID_USB0] = &gxbb_usb0.hw,
2782 [CLKID_USB1] = &gxbb_usb1.hw,
2783 [CLKID_RESET] = &gxbb_reset.hw,
2784 [CLKID_NAND] = &gxbb_nand.hw,
2785 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2786 [CLKID_USB] = &gxbb_usb.hw,
2787 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2788 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2789 [CLKID_EFUSE] = &gxbb_efuse.hw,
2790 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2791 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2792 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2793 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2794 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2795 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
2796 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
2797 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
2798 [CLKID_DVIN] = &gxbb_dvin.hw,
2799 [CLKID_UART2] = &gxbb_uart2.hw,
2800 [CLKID_SANA] = &gxbb_sana.hw,
2801 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2802 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2803 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2804 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2805 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2806 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2807 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2808 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2809 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2810 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2811 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2812 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2813 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2814 [CLKID_RNG1] = &gxbb_rng1.hw,
2815 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2816 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2817 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2818 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2819 [CLKID_EDP] = &gxbb_edp.hw,
2820 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2821 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2822 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2823 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2824 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2825 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2826 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2827 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2828 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2829 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2830 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2831 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2832 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2833 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2834 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2835 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2836 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2837 [CLKID_MALI] = &gxbb_mali.hw,
2838 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2839 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2840 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2841 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2842 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2843 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2844 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2845 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2846 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2847 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2848 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2849 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2850 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2851 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2852 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2853 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2854 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2855 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2856 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2857 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2858 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2859 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2860 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2861 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2862 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2863 [CLKID_VPU] = &gxbb_vpu.hw,
2864 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2865 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2866 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2867 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2868 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2869 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2870 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2871 [CLKID_VAPB] = &gxbb_vapb.hw,
2872 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
2873 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2874 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2875 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2876 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2877 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2878 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2879 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2880 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2881 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2882 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2883 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2884 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2885 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2886 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2887 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2888 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2889 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2890 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2891 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2892 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2893 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
2894 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
2895 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2896 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
2897 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
2898 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
2899 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
2900 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
2901 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
2902 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
2903 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
2904 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
2905 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
2906 [CLKID_VCLK] = &gxbb_vclk.hw,
2907 [CLKID_VCLK2] = &gxbb_vclk2.hw,
2908 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
2909 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
2910 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
2911 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
2912 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
2913 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
2914 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
2915 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
2916 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
2917 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
2918 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
2919 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
2920 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
2921 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
2922 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
2923 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
2924 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
2925 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
2926 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
2927 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
2928 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
2929 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
2930 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
2931 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
2932 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
2933 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
2934 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
2935 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
2936 [CLKID_HDMI] = &gxbb_hdmi.hw,
2942 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2944 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2945 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
2946 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2947 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2948 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2949 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2950 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2951 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2952 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2953 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2954 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2955 [CLKID_CLK81] = &gxbb_clk81.hw,
2956 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2957 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2958 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2959 [CLKID_DDR] = &gxbb_ddr.hw,
2960 [CLKID_DOS] = &gxbb_dos.hw,
2961 [CLKID_ISA] = &gxbb_isa.hw,
2962 [CLKID_PL301] = &gxbb_pl301.hw,
2963 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2964 [CLKID_SPICC] = &gxbb_spicc.hw,
2965 [CLKID_I2C] = &gxbb_i2c.hw,
2966 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2967 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2968 [CLKID_RNG0] = &gxbb_rng0.hw,
2969 [CLKID_UART0] = &gxbb_uart0.hw,
2970 [CLKID_SDHC] = &gxbb_sdhc.hw,
2971 [CLKID_STREAM] = &gxbb_stream.hw,
2972 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2973 [CLKID_SDIO] = &gxbb_sdio.hw,
2974 [CLKID_ABUF] = &gxbb_abuf.hw,
2975 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2976 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2977 [CLKID_SPI] = &gxbb_spi.hw,
2978 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2979 [CLKID_ETH] = &gxbb_eth.hw,
2980 [CLKID_DEMUX] = &gxbb_demux.hw,
2981 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2982 [CLKID_IEC958] = &gxbb_iec958.hw,
2983 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2984 [CLKID_AMCLK] = &gxbb_amclk.hw,
2985 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2986 [CLKID_MIXER] = &gxbb_mixer.hw,
2987 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2988 [CLKID_ADC] = &gxbb_adc.hw,
2989 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2990 [CLKID_AIU] = &gxbb_aiu.hw,
2991 [CLKID_UART1] = &gxbb_uart1.hw,
2992 [CLKID_G2D] = &gxbb_g2d.hw,
2993 [CLKID_USB0] = &gxbb_usb0.hw,
2994 [CLKID_USB1] = &gxbb_usb1.hw,
2995 [CLKID_RESET] = &gxbb_reset.hw,
2996 [CLKID_NAND] = &gxbb_nand.hw,
2997 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2998 [CLKID_USB] = &gxbb_usb.hw,
2999 [CLKID_VDIN1] = &gxbb_vdin1.hw,
3000 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
3001 [CLKID_EFUSE] = &gxbb_efuse.hw,
3002 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
3003 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
3004 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
3005 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
3006 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
3007 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
3008 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
3009 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
3010 [CLKID_DVIN] = &gxbb_dvin.hw,
3011 [CLKID_UART2] = &gxbb_uart2.hw,
3012 [CLKID_SANA] = &gxbb_sana.hw,
3013 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
3014 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
3015 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
3016 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
3017 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
3018 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
3019 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
3020 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
3021 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
3022 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
3023 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
3024 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
3025 [CLKID_ENC480P] = &gxbb_enc480p.hw,
3026 [CLKID_RNG1] = &gxbb_rng1.hw,
3027 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
3028 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
3029 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
3030 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
3031 [CLKID_EDP] = &gxbb_edp.hw,
3032 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
3033 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
3034 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
3035 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
3036 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
3037 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
3038 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
3039 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
3040 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
3041 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
3042 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
3043 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
3044 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
3045 [CLKID_MALI_0] = &gxbb_mali_0.hw,
3046 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
3047 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
3048 [CLKID_MALI_1] = &gxbb_mali_1.hw,
3049 [CLKID_MALI] = &gxbb_mali.hw,
3050 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
3051 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
3052 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
3053 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
3054 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
3055 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
3056 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
3057 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
3058 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
3059 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
3060 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
3061 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
3062 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
3063 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
3064 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
3065 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
3066 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
3067 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
3068 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
3069 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
3070 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
3071 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
3072 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
3073 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
3074 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
3075 [CLKID_VPU] = &gxbb_vpu.hw,
3076 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
3077 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
3078 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
3079 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
3080 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
3081 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
3082 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
3083 [CLKID_VAPB] = &gxbb_vapb.hw,
3084 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
3085 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
3086 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
3087 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
3088 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
3089 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
3090 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
3091 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
3092 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
3093 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
3094 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
3095 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
3096 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
3097 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
3098 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
3099 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
3100 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
3101 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
3102 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
3103 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
3104 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
3105 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
3106 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
3107 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
3108 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
3109 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
3110 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
3111 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
3112 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
3113 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
3114 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
3115 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
3116 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
3117 [CLKID_VCLK] = &gxbb_vclk.hw,
3118 [CLKID_VCLK2] = &gxbb_vclk2.hw,
3119 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
3120 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
3121 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3122 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
3123 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3124 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
3125 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
3126 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
3127 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
3128 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
3129 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
3130 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
3131 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
3132 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
3133 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
3134 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
3135 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
3136 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
3137 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
3138 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
3139 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
3140 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
3141 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
3142 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
3143 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
3144 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
3145 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
3146 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
3147 [CLKID_HDMI] = &gxbb_hdmi.hw,
3148 [CLKID_ACODEC] = &gxl_acodec.hw,
3154 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3202 &gxbb_hdmi_intr_sync,
3204 &gxbb_usb1_ddr_bridge,
3205 &gxbb_usb0_ddr_bridge,
3211 &gxbb_sec_ahb_ahb3_bridge,
3217 &gxbb_gclk_venci_int0,
3218 &gxbb_gclk_vencp_int,
3224 &gxbb_gclk_venci_int1,
3225 &gxbb_vclk2_venclmcc,
3241 &gxbb_cts_mclk_i958,
3243 &gxbb_sd_emmc_a_clk0,
3244 &gxbb_sd_emmc_b_clk0,
3245 &gxbb_sd_emmc_c_clk0,
3252 &gxbb_sar_adc_clk_div,
3255 &gxbb_cts_mclk_i958_div,
3257 &gxbb_sd_emmc_a_clk0_div,
3258 &gxbb_sd_emmc_b_clk0_div,
3259 &gxbb_sd_emmc_c_clk0_div,
3265 &gxbb_sar_adc_clk_sel,
3269 &gxbb_cts_amclk_sel,
3270 &gxbb_cts_mclk_i958_sel,
3273 &gxbb_sd_emmc_a_clk0_sel,
3274 &gxbb_sd_emmc_b_clk0_sel,
3275 &gxbb_sd_emmc_c_clk0_sel,
3288 &gxbb_cts_amclk_div,
3300 &gxbb_vdec_hevc_sel,
3301 &gxbb_vdec_hevc_div,
3306 &gxbb_fixed_pll_dco,
3320 &gxbb_vclk_div12_en,
3326 &gxbb_vclk2_div2_en,
3327 &gxbb_vclk2_div4_en,
3328 &gxbb_vclk2_div6_en,
3329 &gxbb_vclk2_div12_en,
3348 static struct clk_regmap *const gxl_clk_regmaps[] = {
3396 &gxbb_hdmi_intr_sync,
3398 &gxbb_usb1_ddr_bridge,
3399 &gxbb_usb0_ddr_bridge,
3405 &gxbb_sec_ahb_ahb3_bridge,
3411 &gxbb_gclk_venci_int0,
3412 &gxbb_gclk_vencp_int,
3418 &gxbb_gclk_venci_int1,
3419 &gxbb_vclk2_venclmcc,
3435 &gxbb_cts_mclk_i958,
3437 &gxbb_sd_emmc_a_clk0,
3438 &gxbb_sd_emmc_b_clk0,
3439 &gxbb_sd_emmc_c_clk0,
3446 &gxbb_sar_adc_clk_div,
3449 &gxbb_cts_mclk_i958_div,
3451 &gxbb_sd_emmc_a_clk0_div,
3452 &gxbb_sd_emmc_b_clk0_div,
3453 &gxbb_sd_emmc_c_clk0_div,
3459 &gxbb_sar_adc_clk_sel,
3463 &gxbb_cts_amclk_sel,
3464 &gxbb_cts_mclk_i958_sel,
3467 &gxbb_sd_emmc_a_clk0_sel,
3468 &gxbb_sd_emmc_b_clk0_sel,
3469 &gxbb_sd_emmc_c_clk0_sel,
3482 &gxbb_cts_amclk_div,
3494 &gxbb_vdec_hevc_sel,
3495 &gxbb_vdec_hevc_div,
3500 &gxbb_fixed_pll_dco,
3514 &gxbb_vclk_div12_en,
3520 &gxbb_vclk2_div2_en,
3521 &gxbb_vclk2_div4_en,
3522 &gxbb_vclk2_div6_en,
3523 &gxbb_vclk2_div12_en,
3543 static const struct meson_eeclkc_data gxbb_clkc_data = {
3544 .regmap_clks = gxbb_clk_regmaps,
3545 .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3546 .hw_onecell_data = &gxbb_hw_onecell_data,
3549 static const struct meson_eeclkc_data gxl_clkc_data = {
3550 .regmap_clks = gxl_clk_regmaps,
3551 .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3552 .hw_onecell_data = &gxl_hw_onecell_data,
3555 static const struct of_device_id clkc_match_table[] = {
3556 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3557 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3561 static struct platform_driver gxbb_driver = {
3562 .probe = meson_eeclkc_probe,
3564 .name = "gxbb-clkc",
3565 .of_match_table = clkc_match_table,
3569 builtin_platform_driver(gxbb_driver);