drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/init.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11
  12 #include "gxbb.h"
  13 #include "clk-regmap.h"
  14 #include "clk-pll.h"
  15 #include "clk-mpll.h"
  16 #include "meson-eeclk.h"
  17 #include "vid-pll-div.h"
  18
  19 static DEFINE_SPINLOCK(meson_clk_lock);
  20
  21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  22         PLL_PARAMS(32, 1),
  23         PLL_PARAMS(33, 1),
  24         PLL_PARAMS(34, 1),
  25         PLL_PARAMS(35, 1),
  26         PLL_PARAMS(36, 1),
  27         PLL_PARAMS(37, 1),
  28         PLL_PARAMS(38, 1),
  29         PLL_PARAMS(39, 1),
  30         PLL_PARAMS(40, 1),
  31         PLL_PARAMS(41, 1),
  32         PLL_PARAMS(42, 1),
  33         PLL_PARAMS(43, 1),
  34         PLL_PARAMS(44, 1),
  35         PLL_PARAMS(45, 1),
  36         PLL_PARAMS(46, 1),
  37         PLL_PARAMS(47, 1),
  38         PLL_PARAMS(48, 1),
  39         PLL_PARAMS(49, 1),
  40         PLL_PARAMS(50, 1),
  41         PLL_PARAMS(51, 1),
  42         PLL_PARAMS(52, 1),
  43         PLL_PARAMS(53, 1),
  44         PLL_PARAMS(54, 1),
  45         PLL_PARAMS(55, 1),
  46         PLL_PARAMS(56, 1),
  47         PLL_PARAMS(57, 1),
  48         PLL_PARAMS(58, 1),
  49         PLL_PARAMS(59, 1),
  50         PLL_PARAMS(60, 1),
  51         PLL_PARAMS(61, 1),
  52         PLL_PARAMS(62, 1),
  53         { /* sentinel */ },
  54 };
  55
  56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  57         PLL_PARAMS(42, 1),
  58         PLL_PARAMS(43, 1),
  59         PLL_PARAMS(44, 1),
  60         PLL_PARAMS(45, 1),
  61         PLL_PARAMS(46, 1),
  62         PLL_PARAMS(47, 1),
  63         PLL_PARAMS(48, 1),
  64         PLL_PARAMS(49, 1),
  65         PLL_PARAMS(50, 1),
  66         PLL_PARAMS(51, 1),
  67         PLL_PARAMS(52, 1),
  68         PLL_PARAMS(53, 1),
  69         PLL_PARAMS(54, 1),
  70         PLL_PARAMS(55, 1),
  71         PLL_PARAMS(56, 1),
  72         PLL_PARAMS(57, 1),
  73         PLL_PARAMS(58, 1),
  74         PLL_PARAMS(59, 1),
  75         PLL_PARAMS(60, 1),
  76         PLL_PARAMS(61, 1),
  77         PLL_PARAMS(62, 1),
  78         PLL_PARAMS(63, 1),
  79         PLL_PARAMS(64, 1),
  80         PLL_PARAMS(65, 1),
  81         PLL_PARAMS(66, 1),
  82         { /* sentinel */ },
  83 };
  84
  85 static struct clk_regmap gxbb_fixed_pll_dco = {
  86         .data = &(struct meson_clk_pll_data){
  87                 .en = {
  88                         .reg_off = HHI_MPLL_CNTL,
  89                         .shift   = 30,
  90                         .width   = 1,
  91                 },
  92                 .m = {
  93                         .reg_off = HHI_MPLL_CNTL,
  94                         .shift   = 0,
  95                         .width   = 9,
  96                 },
  97                 .n = {
  98                         .reg_off = HHI_MPLL_CNTL,
  99                         .shift   = 9,
 100                         .width   = 5,
 101                 },
 102                 .frac = {
 103                         .reg_off = HHI_MPLL_CNTL2,
 104                         .shift   = 0,
 105                         .width   = 12,
 106                 },
 107                 .l = {
 108                         .reg_off = HHI_MPLL_CNTL,
 109                         .shift   = 31,
 110                         .width   = 1,
 111                 },
 112                 .rst = {
 113                         .reg_off = HHI_MPLL_CNTL,
 114                         .shift   = 29,
 115                         .width   = 1,
 116                 },
 117         },
 118         .hw.init = &(struct clk_init_data){
 119                 .name = "fixed_pll_dco",
 120                 .ops = &meson_clk_pll_ro_ops,
 121                 .parent_data = &(const struct clk_parent_data) {
 122                         .fw_name = "xtal",
 123                 },
 124                 .num_parents = 1,
 125         },
 126 };
 127
 128 static struct clk_regmap gxbb_fixed_pll = {
 129         .data = &(struct clk_regmap_div_data){
 130                 .offset = HHI_MPLL_CNTL,
 131                 .shift = 16,
 132                 .width = 2,
 133                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 134         },
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "fixed_pll",
 137                 .ops = &clk_regmap_divider_ro_ops,
 138                 .parent_hws = (const struct clk_hw *[]) {
 139                         &gxbb_fixed_pll_dco.hw
 140                 },
 141                 .num_parents = 1,
 142                 /*
 143                  * This clock won't ever change at runtime so
 144                  * CLK_SET_RATE_PARENT is not required
 145                  */
 146         },
 147 };
 148
 149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 150         .mult = 2,
 151         .div = 1,
 152         .hw.init = &(struct clk_init_data){
 153                 .name = "hdmi_pll_pre_mult",
 154                 .ops = &clk_fixed_factor_ops,
 155                 .parent_data = &(const struct clk_parent_data) {
 156                         .fw_name = "xtal",
 157                 },
 158                 .num_parents = 1,
 159         },
 160 };
 161
 162 static struct clk_regmap gxbb_hdmi_pll_dco = {
 163         .data = &(struct meson_clk_pll_data){
 164                 .en = {
 165                         .reg_off = HHI_HDMI_PLL_CNTL,
 166                         .shift   = 30,
 167                         .width   = 1,
 168                 },
 169                 .m = {
 170                         .reg_off = HHI_HDMI_PLL_CNTL,
 171                         .shift   = 0,
 172                         .width   = 9,
 173                 },
 174                 .n = {
 175                         .reg_off = HHI_HDMI_PLL_CNTL,
 176                         .shift   = 9,
 177                         .width   = 5,
 178                 },
 179                 .frac = {
 180                         .reg_off = HHI_HDMI_PLL_CNTL2,
 181                         .shift   = 0,
 182                         .width   = 12,
 183                 },
 184                 .l = {
 185                         .reg_off = HHI_HDMI_PLL_CNTL,
 186                         .shift   = 31,
 187                         .width   = 1,
 188                 },
 189                 .rst = {
 190                         .reg_off = HHI_HDMI_PLL_CNTL,
 191                         .shift   = 28,
 192                         .width   = 1,
 193                 },
 194         },
 195         .hw.init = &(struct clk_init_data){
 196                 .name = "hdmi_pll_dco",
 197                 .ops = &meson_clk_pll_ro_ops,
 198                 .parent_hws = (const struct clk_hw *[]) {
 199                         &gxbb_hdmi_pll_pre_mult.hw
 200                 },
 201                 .num_parents = 1,
 202                 /*
 203                  * Display directly handle hdmi pll registers ATM, we need
 204                  * NOCACHE to keep our view of the clock as accurate as possible
 205                  */
 206                 .flags = CLK_GET_RATE_NOCACHE,
 207         },
 208 };
 209
 210 static struct clk_regmap gxl_hdmi_pll_dco = {
 211         .data = &(struct meson_clk_pll_data){
 212                 .en = {
 213                         .reg_off = HHI_HDMI_PLL_CNTL,
 214                         .shift   = 30,
 215                         .width   = 1,
 216                 },
 217                 .m = {
 218                         .reg_off = HHI_HDMI_PLL_CNTL,
 219                         .shift   = 0,
 220                         .width   = 9,
 221                 },
 222                 .n = {
 223                         .reg_off = HHI_HDMI_PLL_CNTL,
 224                         .shift   = 9,
 225                         .width   = 5,
 226                 },
 227                 /*
 228                  * On gxl, there is a register shift due to
 229                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 230                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 231                  * instead which is defined at the same offset.
 232                  */
 233                 .frac = {
 234                         .reg_off = HHI_HDMI_PLL_CNTL2,
 235                         .shift   = 0,
 236                         .width   = 10,
 237                 },
 238                 .l = {
 239                         .reg_off = HHI_HDMI_PLL_CNTL,
 240                         .shift   = 31,
 241                         .width   = 1,
 242                 },
 243                 .rst = {
 244                         .reg_off = HHI_HDMI_PLL_CNTL,
 245                         .shift   = 28,
 246                         .width   = 1,
 247                 },
 248         },
 249         .hw.init = &(struct clk_init_data){
 250                 .name = "hdmi_pll_dco",
 251                 .ops = &meson_clk_pll_ro_ops,
 252                 .parent_data = &(const struct clk_parent_data) {
 253                         .fw_name = "xtal",
 254                 },
 255                 .num_parents = 1,
 256                 /*
 257                  * Display directly handle hdmi pll registers ATM, we need
 258                  * NOCACHE to keep our view of the clock as accurate as possible
 259                  */
 260                 .flags = CLK_GET_RATE_NOCACHE,
 261         },
 262 };
 263
 264 static struct clk_regmap gxbb_hdmi_pll_od = {
 265         .data = &(struct clk_regmap_div_data){
 266                 .offset = HHI_HDMI_PLL_CNTL2,
 267                 .shift = 16,
 268                 .width = 2,
 269                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 270         },
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "hdmi_pll_od",
 273                 .ops = &clk_regmap_divider_ro_ops,
 274                 .parent_hws = (const struct clk_hw *[]) {
 275                         &gxbb_hdmi_pll_dco.hw
 276                 },
 277                 .num_parents = 1,
 278                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 279         },
 280 };
 281
 282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 283         .data = &(struct clk_regmap_div_data){
 284                 .offset = HHI_HDMI_PLL_CNTL2,
 285                 .shift = 22,
 286                 .width = 2,
 287                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 288         },
 289         .hw.init = &(struct clk_init_data){
 290                 .name = "hdmi_pll_od2",
 291                 .ops = &clk_regmap_divider_ro_ops,
 292                 .parent_hws = (const struct clk_hw *[]) {
 293                         &gxbb_hdmi_pll_od.hw
 294                 },
 295                 .num_parents = 1,
 296                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 297         },
 298 };
 299
 300 static struct clk_regmap gxbb_hdmi_pll = {
 301         .data = &(struct clk_regmap_div_data){
 302                 .offset = HHI_HDMI_PLL_CNTL2,
 303                 .shift = 18,
 304                 .width = 2,
 305                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 306         },
 307         .hw.init = &(struct clk_init_data){
 308                 .name = "hdmi_pll",
 309                 .ops = &clk_regmap_divider_ro_ops,
 310                 .parent_hws = (const struct clk_hw *[]) {
 311                         &gxbb_hdmi_pll_od2.hw
 312                 },
 313                 .num_parents = 1,
 314                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 315         },
 316 };
 317
 318 static struct clk_regmap gxl_hdmi_pll_od = {
 319         .data = &(struct clk_regmap_div_data){
 320                 .offset = HHI_HDMI_PLL_CNTL + 8,
 321                 .shift = 21,
 322                 .width = 2,
 323                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 324         },
 325         .hw.init = &(struct clk_init_data){
 326                 .name = "hdmi_pll_od",
 327                 .ops = &clk_regmap_divider_ro_ops,
 328                 .parent_hws = (const struct clk_hw *[]) {
 329                         &gxl_hdmi_pll_dco.hw
 330                 },
 331                 .num_parents = 1,
 332                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 333         },
 334 };
 335
 336 static struct clk_regmap gxl_hdmi_pll_od2 = {
 337         .data = &(struct clk_regmap_div_data){
 338                 .offset = HHI_HDMI_PLL_CNTL + 8,
 339                 .shift = 23,
 340                 .width = 2,
 341                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 342         },
 343         .hw.init = &(struct clk_init_data){
 344                 .name = "hdmi_pll_od2",
 345                 .ops = &clk_regmap_divider_ro_ops,
 346                 .parent_hws = (const struct clk_hw *[]) {
 347                         &gxl_hdmi_pll_od.hw
 348                 },
 349                 .num_parents = 1,
 350                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 351         },
 352 };
 353
 354 static struct clk_regmap gxl_hdmi_pll = {
 355         .data = &(struct clk_regmap_div_data){
 356                 .offset = HHI_HDMI_PLL_CNTL + 8,
 357                 .shift = 19,
 358                 .width = 2,
 359                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 360         },
 361         .hw.init = &(struct clk_init_data){
 362                 .name = "hdmi_pll",
 363                 .ops = &clk_regmap_divider_ro_ops,
 364                 .parent_hws = (const struct clk_hw *[]) {
 365                         &gxl_hdmi_pll_od2.hw
 366                 },
 367                 .num_parents = 1,
 368                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 369         },
 370 };
 371
 372 static struct clk_regmap gxbb_sys_pll_dco = {
 373         .data = &(struct meson_clk_pll_data){
 374                 .en = {
 375                         .reg_off = HHI_SYS_PLL_CNTL,
 376                         .shift   = 30,
 377                         .width   = 1,
 378                 },
 379                 .m = {
 380                         .reg_off = HHI_SYS_PLL_CNTL,
 381                         .shift   = 0,
 382                         .width   = 9,
 383                 },
 384                 .n = {
 385                         .reg_off = HHI_SYS_PLL_CNTL,
 386                         .shift   = 9,
 387                         .width   = 5,
 388                 },
 389                 .l = {
 390                         .reg_off = HHI_SYS_PLL_CNTL,
 391                         .shift   = 31,
 392                         .width   = 1,
 393                 },
 394                 .rst = {
 395                         .reg_off = HHI_SYS_PLL_CNTL,
 396                         .shift   = 29,
 397                         .width   = 1,
 398                 },
 399         },
 400         .hw.init = &(struct clk_init_data){
 401                 .name = "sys_pll_dco",
 402                 .ops = &meson_clk_pll_ro_ops,
 403                 .parent_data = &(const struct clk_parent_data) {
 404                         .fw_name = "xtal",
 405                 },
 406                 .num_parents = 1,
 407         },
 408 };
 409
 410 static struct clk_regmap gxbb_sys_pll = {
 411         .data = &(struct clk_regmap_div_data){
 412                 .offset = HHI_SYS_PLL_CNTL,
 413                 .shift = 10,
 414                 .width = 2,
 415                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 416         },
 417         .hw.init = &(struct clk_init_data){
 418                 .name = "sys_pll",
 419                 .ops = &clk_regmap_divider_ro_ops,
 420                 .parent_hws = (const struct clk_hw *[]) {
 421                         &gxbb_sys_pll_dco.hw
 422                 },
 423                 .num_parents = 1,
 424                 .flags = CLK_SET_RATE_PARENT,
 425         },
 426 };
 427
 428 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 429         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 430         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 431         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 432 };
 433
 434 static struct clk_regmap gxbb_gp0_pll_dco = {
 435         .data = &(struct meson_clk_pll_data){
 436                 .en = {
 437                         .reg_off = HHI_GP0_PLL_CNTL,
 438                         .shift   = 30,
 439                         .width   = 1,
 440                 },
 441                 .m = {
 442                         .reg_off = HHI_GP0_PLL_CNTL,
 443                         .shift   = 0,
 444                         .width   = 9,
 445                 },
 446                 .n = {
 447                         .reg_off = HHI_GP0_PLL_CNTL,
 448                         .shift   = 9,
 449                         .width   = 5,
 450                 },
 451                 .l = {
 452                         .reg_off = HHI_GP0_PLL_CNTL,
 453                         .shift   = 31,
 454                         .width   = 1,
 455                 },
 456                 .rst = {
 457                         .reg_off = HHI_GP0_PLL_CNTL,
 458                         .shift   = 29,
 459                         .width   = 1,
 460                 },
 461                 .table = gxbb_gp0_pll_params_table,
 462                 .init_regs = gxbb_gp0_init_regs,
 463                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 464         },
 465         .hw.init = &(struct clk_init_data){
 466                 .name = "gp0_pll_dco",
 467                 .ops = &meson_clk_pll_ops,
 468                 .parent_data = &(const struct clk_parent_data) {
 469                         .fw_name = "xtal",
 470                 },
 471                 .num_parents = 1,
 472         },
 473 };
 474
 475 static const struct reg_sequence gxl_gp0_init_regs[] = {
 476         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 477         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 478         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 479         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 480         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 481 };
 482
 483 static struct clk_regmap gxl_gp0_pll_dco = {
 484         .data = &(struct meson_clk_pll_data){
 485                 .en = {
 486                         .reg_off = HHI_GP0_PLL_CNTL,
 487                         .shift   = 30,
 488                         .width   = 1,
 489                 },
 490                 .m = {
 491                         .reg_off = HHI_GP0_PLL_CNTL,
 492                         .shift   = 0,
 493                         .width   = 9,
 494                 },
 495                 .n = {
 496                         .reg_off = HHI_GP0_PLL_CNTL,
 497                         .shift   = 9,
 498                         .width   = 5,
 499                 },
 500                 .frac = {
 501                         .reg_off = HHI_GP0_PLL_CNTL1,
 502                         .shift   = 0,
 503                         .width   = 10,
 504                 },
 505                 .l = {
 506                         .reg_off = HHI_GP0_PLL_CNTL,
 507                         .shift   = 31,
 508                         .width   = 1,
 509                 },
 510                 .rst = {
 511                         .reg_off = HHI_GP0_PLL_CNTL,
 512                         .shift   = 29,
 513                         .width   = 1,
 514                 },
 515                 .table = gxl_gp0_pll_params_table,
 516                 .init_regs = gxl_gp0_init_regs,
 517                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 518         },
 519         .hw.init = &(struct clk_init_data){
 520                 .name = "gp0_pll_dco",
 521                 .ops = &meson_clk_pll_ops,
 522                 .parent_data = &(const struct clk_parent_data) {
 523                         .fw_name = "xtal",
 524                 },
 525                 .num_parents = 1,
 526         },
 527 };
 528
 529 static struct clk_regmap gxbb_gp0_pll = {
 530         .data = &(struct clk_regmap_div_data){
 531                 .offset = HHI_GP0_PLL_CNTL,
 532                 .shift = 16,
 533                 .width = 2,
 534                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 535         },
 536         .hw.init = &(struct clk_init_data){
 537                 .name = "gp0_pll",
 538                 .ops = &clk_regmap_divider_ops,
 539                 .parent_data = &(const struct clk_parent_data) {
 540                         /*
 541                          * Note:
 542                          * GXL and GXBB have different gp0_pll_dco (with
 543                          * different struct clk_hw). We fallback to the global
 544                          * naming string mechanism so gp0_pll picks up the
 545                          * appropriate one.
 546                          */
 547                         .name = "gp0_pll_dco",
 548                         .index = -1,
 549                 },
 550                 .num_parents = 1,
 551                 .flags = CLK_SET_RATE_PARENT,
 552         },
 553 };
 554
 555 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 556         .mult = 1,
 557         .div = 2,
 558         .hw.init = &(struct clk_init_data){
 559                 .name = "fclk_div2_div",
 560                 .ops = &clk_fixed_factor_ops,
 561                 .parent_hws = (const struct clk_hw *[]) {
 562                         &gxbb_fixed_pll.hw
 563                 },
 564                 .num_parents = 1,
 565         },
 566 };
 567
 568 static struct clk_regmap gxbb_fclk_div2 = {
 569         .data = &(struct clk_regmap_gate_data){
 570                 .offset = HHI_MPLL_CNTL6,
 571                 .bit_idx = 27,
 572         },
 573         .hw.init = &(struct clk_init_data){
 574                 .name = "fclk_div2",
 575                 .ops = &clk_regmap_gate_ops,
 576                 .parent_hws = (const struct clk_hw *[]) {
 577                         &gxbb_fclk_div2_div.hw
 578                 },
 579                 .num_parents = 1,
 580                 .flags = CLK_IS_CRITICAL,
 581         },
 582 };
 583
 584 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 585         .mult = 1,
 586         .div = 3,
 587         .hw.init = &(struct clk_init_data){
 588                 .name = "fclk_div3_div",
 589                 .ops = &clk_fixed_factor_ops,
 590                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 591                 .num_parents = 1,
 592         },
 593 };
 594
 595 static struct clk_regmap gxbb_fclk_div3 = {
 596         .data = &(struct clk_regmap_gate_data){
 597                 .offset = HHI_MPLL_CNTL6,
 598                 .bit_idx = 28,
 599         },
 600         .hw.init = &(struct clk_init_data){
 601                 .name = "fclk_div3",
 602                 .ops = &clk_regmap_gate_ops,
 603                 .parent_hws = (const struct clk_hw *[]) {
 604                         &gxbb_fclk_div3_div.hw
 605                 },
 606                 .num_parents = 1,
 607                 /*
 608                  * FIXME:
 609                  * This clock, as fdiv2, is used by the SCPI FW and is required
 610                  * by the platform to operate correctly.
 611                  * Until the following condition are met, we need this clock to
 612                  * be marked as critical:
 613                  * a) The SCPI generic driver claims and enable all the clocks
 614                  *    it needs
 615                  * b) CCF has a clock hand-off mechanism to make the sure the
 616                  *    clock stays on until the proper driver comes along
 617                  */
 618                 .flags = CLK_IS_CRITICAL,
 619         },
 620 };
 621
 622 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 623         .mult = 1,
 624         .div = 4,
 625         .hw.init = &(struct clk_init_data){
 626                 .name = "fclk_div4_div",
 627                 .ops = &clk_fixed_factor_ops,
 628                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 629                 .num_parents = 1,
 630         },
 631 };
 632
 633 static struct clk_regmap gxbb_fclk_div4 = {
 634         .data = &(struct clk_regmap_gate_data){
 635                 .offset = HHI_MPLL_CNTL6,
 636                 .bit_idx = 29,
 637         },
 638         .hw.init = &(struct clk_init_data){
 639                 .name = "fclk_div4",
 640                 .ops = &clk_regmap_gate_ops,
 641                 .parent_hws = (const struct clk_hw *[]) {
 642                         &gxbb_fclk_div4_div.hw
 643                 },
 644                 .num_parents = 1,
 645         },
 646 };
 647
 648 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 649         .mult = 1,
 650         .div = 5,
 651         .hw.init = &(struct clk_init_data){
 652                 .name = "fclk_div5_div",
 653                 .ops = &clk_fixed_factor_ops,
 654                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 655                 .num_parents = 1,
 656         },
 657 };
 658
 659 static struct clk_regmap gxbb_fclk_div5 = {
 660         .data = &(struct clk_regmap_gate_data){
 661                 .offset = HHI_MPLL_CNTL6,
 662                 .bit_idx = 30,
 663         },
 664         .hw.init = &(struct clk_init_data){
 665                 .name = "fclk_div5",
 666                 .ops = &clk_regmap_gate_ops,
 667                 .parent_hws = (const struct clk_hw *[]) {
 668                         &gxbb_fclk_div5_div.hw
 669                 },
 670                 .num_parents = 1,
 671         },
 672 };
 673
 674 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 675         .mult = 1,
 676         .div = 7,
 677         .hw.init = &(struct clk_init_data){
 678                 .name = "fclk_div7_div",
 679                 .ops = &clk_fixed_factor_ops,
 680                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 681                 .num_parents = 1,
 682         },
 683 };
 684
 685 static struct clk_regmap gxbb_fclk_div7 = {
 686         .data = &(struct clk_regmap_gate_data){
 687                 .offset = HHI_MPLL_CNTL6,
 688                 .bit_idx = 31,
 689         },
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "fclk_div7",
 692                 .ops = &clk_regmap_gate_ops,
 693                 .parent_hws = (const struct clk_hw *[]) {
 694                         &gxbb_fclk_div7_div.hw
 695                 },
 696                 .num_parents = 1,
 697         },
 698 };
 699
 700 static struct clk_regmap gxbb_mpll_prediv = {
 701         .data = &(struct clk_regmap_div_data){
 702                 .offset = HHI_MPLL_CNTL5,
 703                 .shift = 12,
 704                 .width = 1,
 705         },
 706         .hw.init = &(struct clk_init_data){
 707                 .name = "mpll_prediv",
 708                 .ops = &clk_regmap_divider_ro_ops,
 709                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 710                 .num_parents = 1,
 711         },
 712 };
 713
 714 static struct clk_regmap gxbb_mpll0_div = {
 715         .data = &(struct meson_clk_mpll_data){
 716                 .sdm = {
 717                         .reg_off = HHI_MPLL_CNTL7,
 718                         .shift   = 0,
 719                         .width   = 14,
 720                 },
 721                 .sdm_en = {
 722                         .reg_off = HHI_MPLL_CNTL,
 723                         .shift   = 25,
 724                         .width   = 1,
 725                 },
 726                 .n2 = {
 727                         .reg_off = HHI_MPLL_CNTL7,
 728                         .shift   = 16,
 729                         .width   = 9,
 730                 },
 731                 .lock = &meson_clk_lock,
 732         },
 733         .hw.init = &(struct clk_init_data){
 734                 .name = "mpll0_div",
 735                 .ops = &meson_clk_mpll_ops,
 736                 .parent_hws = (const struct clk_hw *[]) {
 737                         &gxbb_mpll_prediv.hw
 738                 },
 739                 .num_parents = 1,
 740         },
 741 };
 742
 743 static struct clk_regmap gxl_mpll0_div = {
 744         .data = &(struct meson_clk_mpll_data){
 745                 .sdm = {
 746                         .reg_off = HHI_MPLL_CNTL7,
 747                         .shift   = 0,
 748                         .width   = 14,
 749                 },
 750                 .sdm_en = {
 751                         .reg_off = HHI_MPLL_CNTL7,
 752                         .shift   = 15,
 753                         .width   = 1,
 754                 },
 755                 .n2 = {
 756                         .reg_off = HHI_MPLL_CNTL7,
 757                         .shift   = 16,
 758                         .width   = 9,
 759                 },
 760                 .lock = &meson_clk_lock,
 761         },
 762         .hw.init = &(struct clk_init_data){
 763                 .name = "mpll0_div",
 764                 .ops = &meson_clk_mpll_ops,
 765                 .parent_hws = (const struct clk_hw *[]) {
 766                         &gxbb_mpll_prediv.hw
 767                 },
 768                 .num_parents = 1,
 769         },
 770 };
 771
 772 static struct clk_regmap gxbb_mpll0 = {
 773         .data = &(struct clk_regmap_gate_data){
 774                 .offset = HHI_MPLL_CNTL7,
 775                 .bit_idx = 14,
 776         },
 777         .hw.init = &(struct clk_init_data){
 778                 .name = "mpll0",
 779                 .ops = &clk_regmap_gate_ops,
 780                 .parent_data = &(const struct clk_parent_data) {
 781                         /*
 782                          * Note:
 783                          * GXL and GXBB have different SDM_EN registers. We
 784                          * fallback to the global naming string mechanism so
 785                          * mpll0_div picks up the appropriate one.
 786                          */
 787                         .name = "mpll0_div",
 788                         .index = -1,
 789                 },
 790                 .num_parents = 1,
 791                 .flags = CLK_SET_RATE_PARENT,
 792         },
 793 };
 794
 795 static struct clk_regmap gxbb_mpll1_div = {
 796         .data = &(struct meson_clk_mpll_data){
 797                 .sdm = {
 798                         .reg_off = HHI_MPLL_CNTL8,
 799                         .shift   = 0,
 800                         .width   = 14,
 801                 },
 802                 .sdm_en = {
 803                         .reg_off = HHI_MPLL_CNTL8,
 804                         .shift   = 15,
 805                         .width   = 1,
 806                 },
 807                 .n2 = {
 808                         .reg_off = HHI_MPLL_CNTL8,
 809                         .shift   = 16,
 810                         .width   = 9,
 811                 },
 812                 .lock = &meson_clk_lock,
 813         },
 814         .hw.init = &(struct clk_init_data){
 815                 .name = "mpll1_div",
 816                 .ops = &meson_clk_mpll_ops,
 817                 .parent_hws = (const struct clk_hw *[]) {
 818                         &gxbb_mpll_prediv.hw
 819                 },
 820                 .num_parents = 1,
 821         },
 822 };
 823
 824 static struct clk_regmap gxbb_mpll1 = {
 825         .data = &(struct clk_regmap_gate_data){
 826                 .offset = HHI_MPLL_CNTL8,
 827                 .bit_idx = 14,
 828         },
 829         .hw.init = &(struct clk_init_data){
 830                 .name = "mpll1",
 831                 .ops = &clk_regmap_gate_ops,
 832                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
 833                 .num_parents = 1,
 834                 .flags = CLK_SET_RATE_PARENT,
 835         },
 836 };
 837
 838 static struct clk_regmap gxbb_mpll2_div = {
 839         .data = &(struct meson_clk_mpll_data){
 840                 .sdm = {
 841                         .reg_off = HHI_MPLL_CNTL9,
 842                         .shift   = 0,
 843                         .width   = 14,
 844                 },
 845                 .sdm_en = {
 846                         .reg_off = HHI_MPLL_CNTL9,
 847                         .shift   = 15,
 848                         .width   = 1,
 849                 },
 850                 .n2 = {
 851                         .reg_off = HHI_MPLL_CNTL9,
 852                         .shift   = 16,
 853                         .width   = 9,
 854                 },
 855                 .lock = &meson_clk_lock,
 856         },
 857         .hw.init = &(struct clk_init_data){
 858                 .name = "mpll2_div",
 859                 .ops = &meson_clk_mpll_ops,
 860                 .parent_hws = (const struct clk_hw *[]) {
 861                         &gxbb_mpll_prediv.hw
 862                 },
 863                 .num_parents = 1,
 864         },
 865 };
 866
 867 static struct clk_regmap gxbb_mpll2 = {
 868         .data = &(struct clk_regmap_gate_data){
 869                 .offset = HHI_MPLL_CNTL9,
 870                 .bit_idx = 14,
 871         },
 872         .hw.init = &(struct clk_init_data){
 873                 .name = "mpll2",
 874                 .ops = &clk_regmap_gate_ops,
 875                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
 876                 .num_parents = 1,
 877                 .flags = CLK_SET_RATE_PARENT,
 878         },
 879 };
 880
 881 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 882 static const struct clk_parent_data clk81_parent_data[] = {
 883         { .fw_name = "xtal", },
 884         { .hw = &gxbb_fclk_div7.hw },
 885         { .hw = &gxbb_mpll1.hw },
 886         { .hw = &gxbb_mpll2.hw },
 887         { .hw = &gxbb_fclk_div4.hw },
 888         { .hw = &gxbb_fclk_div3.hw },
 889         { .hw = &gxbb_fclk_div5.hw },
 890 };
 891
 892 static struct clk_regmap gxbb_mpeg_clk_sel = {
 893         .data = &(struct clk_regmap_mux_data){
 894                 .offset = HHI_MPEG_CLK_CNTL,
 895                 .mask = 0x7,
 896                 .shift = 12,
 897                 .table = mux_table_clk81,
 898         },
 899         .hw.init = &(struct clk_init_data){
 900                 .name = "mpeg_clk_sel",
 901                 .ops = &clk_regmap_mux_ro_ops,
 902                 /*
 903                  * bits 14:12 selects from 8 possible parents:
 904                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 905                  * fclk_div4, fclk_div3, fclk_div5
 906                  */
 907                 .parent_data = clk81_parent_data,
 908                 .num_parents = ARRAY_SIZE(clk81_parent_data),
 909         },
 910 };
 911
 912 static struct clk_regmap gxbb_mpeg_clk_div = {
 913         .data = &(struct clk_regmap_div_data){
 914                 .offset = HHI_MPEG_CLK_CNTL,
 915                 .shift = 0,
 916                 .width = 7,
 917         },
 918         .hw.init = &(struct clk_init_data){
 919                 .name = "mpeg_clk_div",
 920                 .ops = &clk_regmap_divider_ro_ops,
 921                 .parent_hws = (const struct clk_hw *[]) {
 922                         &gxbb_mpeg_clk_sel.hw
 923                 },
 924                 .num_parents = 1,
 925         },
 926 };
 927
 928 /* the mother of dragons gates */
 929 static struct clk_regmap gxbb_clk81 = {
 930         .data = &(struct clk_regmap_gate_data){
 931                 .offset = HHI_MPEG_CLK_CNTL,
 932                 .bit_idx = 7,
 933         },
 934         .hw.init = &(struct clk_init_data){
 935                 .name = "clk81",
 936                 .ops = &clk_regmap_gate_ops,
 937                 .parent_hws = (const struct clk_hw *[]) {
 938                         &gxbb_mpeg_clk_div.hw
 939                 },
 940                 .num_parents = 1,
 941                 .flags = CLK_IS_CRITICAL,
 942         },
 943 };
 944
 945 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 946         .data = &(struct clk_regmap_mux_data){
 947                 .offset = HHI_SAR_CLK_CNTL,
 948                 .mask = 0x3,
 949                 .shift = 9,
 950         },
 951         .hw.init = &(struct clk_init_data){
 952                 .name = "sar_adc_clk_sel",
 953                 .ops = &clk_regmap_mux_ops,
 954                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 955                 .parent_data = (const struct clk_parent_data []) {
 956                         { .fw_name = "xtal", },
 957                         { .hw = &gxbb_clk81.hw },
 958                 },
 959                 .num_parents = 2,
 960         },
 961 };
 962
 963 static struct clk_regmap gxbb_sar_adc_clk_div = {
 964         .data = &(struct clk_regmap_div_data){
 965                 .offset = HHI_SAR_CLK_CNTL,
 966                 .shift = 0,
 967                 .width = 8,
 968         },
 969         .hw.init = &(struct clk_init_data){
 970                 .name = "sar_adc_clk_div",
 971                 .ops = &clk_regmap_divider_ops,
 972                 .parent_hws = (const struct clk_hw *[]) {
 973                         &gxbb_sar_adc_clk_sel.hw
 974                 },
 975                 .num_parents = 1,
 976                 .flags = CLK_SET_RATE_PARENT,
 977         },
 978 };
 979
 980 static struct clk_regmap gxbb_sar_adc_clk = {
 981         .data = &(struct clk_regmap_gate_data){
 982                 .offset = HHI_SAR_CLK_CNTL,
 983                 .bit_idx = 8,
 984         },
 985         .hw.init = &(struct clk_init_data){
 986                 .name = "sar_adc_clk",
 987                 .ops = &clk_regmap_gate_ops,
 988                 .parent_hws = (const struct clk_hw *[]) {
 989                         &gxbb_sar_adc_clk_div.hw
 990                 },
 991                 .num_parents = 1,
 992                 .flags = CLK_SET_RATE_PARENT,
 993         },
 994 };
 995
 996 /*
 997  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 998  * muxed by a glitch-free switch. The CCF can manage this glitch-free
 999  * mux because it does top-to-bottom updates the each clock tree and
1000  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1001  */
1002
1003 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
1004         { .fw_name = "xtal", },
1005         { .hw = &gxbb_gp0_pll.hw },
1006         { .hw = &gxbb_mpll2.hw },
1007         { .hw = &gxbb_mpll1.hw },
1008         { .hw = &gxbb_fclk_div7.hw },
1009         { .hw = &gxbb_fclk_div4.hw },
1010         { .hw = &gxbb_fclk_div3.hw },
1011         { .hw = &gxbb_fclk_div5.hw },
1012 };
1013
1014 static struct clk_regmap gxbb_mali_0_sel = {
1015         .data = &(struct clk_regmap_mux_data){
1016                 .offset = HHI_MALI_CLK_CNTL,
1017                 .mask = 0x7,
1018                 .shift = 9,
1019         },
1020         .hw.init = &(struct clk_init_data){
1021                 .name = "mali_0_sel",
1022                 .ops = &clk_regmap_mux_ops,
1023                 .parent_data = gxbb_mali_0_1_parent_data,
1024                 .num_parents = 8,
1025                 /*
1026                  * Don't request the parent to change the rate because
1027                  * all GPU frequencies can be derived from the fclk_*
1028                  * clocks and one special GP0_PLL setting. This is
1029                  * important because we need the MPLL clocks for audio.
1030                  */
1031                 .flags = 0,
1032         },
1033 };
1034
1035 static struct clk_regmap gxbb_mali_0_div = {
1036         .data = &(struct clk_regmap_div_data){
1037                 .offset = HHI_MALI_CLK_CNTL,
1038                 .shift = 0,
1039                 .width = 7,
1040         },
1041         .hw.init = &(struct clk_init_data){
1042                 .name = "mali_0_div",
1043                 .ops = &clk_regmap_divider_ops,
1044                 .parent_hws = (const struct clk_hw *[]) {
1045                         &gxbb_mali_0_sel.hw
1046                 },
1047                 .num_parents = 1,
1048                 .flags = CLK_SET_RATE_PARENT,
1049         },
1050 };
1051
1052 static struct clk_regmap gxbb_mali_0 = {
1053         .data = &(struct clk_regmap_gate_data){
1054                 .offset = HHI_MALI_CLK_CNTL,
1055                 .bit_idx = 8,
1056         },
1057         .hw.init = &(struct clk_init_data){
1058                 .name = "mali_0",
1059                 .ops = &clk_regmap_gate_ops,
1060                 .parent_hws = (const struct clk_hw *[]) {
1061                         &gxbb_mali_0_div.hw
1062                 },
1063                 .num_parents = 1,
1064                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1065         },
1066 };
1067
1068 static struct clk_regmap gxbb_mali_1_sel = {
1069         .data = &(struct clk_regmap_mux_data){
1070                 .offset = HHI_MALI_CLK_CNTL,
1071                 .mask = 0x7,
1072                 .shift = 25,
1073         },
1074         .hw.init = &(struct clk_init_data){
1075                 .name = "mali_1_sel",
1076                 .ops = &clk_regmap_mux_ops,
1077                 .parent_data = gxbb_mali_0_1_parent_data,
1078                 .num_parents = 8,
1079                 /*
1080                  * Don't request the parent to change the rate because
1081                  * all GPU frequencies can be derived from the fclk_*
1082                  * clocks and one special GP0_PLL setting. This is
1083                  * important because we need the MPLL clocks for audio.
1084                  */
1085                 .flags = 0,
1086         },
1087 };
1088
1089 static struct clk_regmap gxbb_mali_1_div = {
1090         .data = &(struct clk_regmap_div_data){
1091                 .offset = HHI_MALI_CLK_CNTL,
1092                 .shift = 16,
1093                 .width = 7,
1094         },
1095         .hw.init = &(struct clk_init_data){
1096                 .name = "mali_1_div",
1097                 .ops = &clk_regmap_divider_ops,
1098                 .parent_hws = (const struct clk_hw *[]) {
1099                         &gxbb_mali_1_sel.hw
1100                 },
1101                 .num_parents = 1,
1102                 .flags = CLK_SET_RATE_PARENT,
1103         },
1104 };
1105
1106 static struct clk_regmap gxbb_mali_1 = {
1107         .data = &(struct clk_regmap_gate_data){
1108                 .offset = HHI_MALI_CLK_CNTL,
1109                 .bit_idx = 24,
1110         },
1111         .hw.init = &(struct clk_init_data){
1112                 .name = "mali_1",
1113                 .ops = &clk_regmap_gate_ops,
1114                 .parent_hws = (const struct clk_hw *[]) {
1115                         &gxbb_mali_1_div.hw
1116                 },
1117                 .num_parents = 1,
1118                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1119         },
1120 };
1121
1122 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1123         &gxbb_mali_0.hw,
1124         &gxbb_mali_1.hw,
1125 };
1126
1127 static struct clk_regmap gxbb_mali = {
1128         .data = &(struct clk_regmap_mux_data){
1129                 .offset = HHI_MALI_CLK_CNTL,
1130                 .mask = 1,
1131                 .shift = 31,
1132         },
1133         .hw.init = &(struct clk_init_data){
1134                 .name = "mali",
1135                 .ops = &clk_regmap_mux_ops,
1136                 .parent_hws = gxbb_mali_parent_hws,
1137                 .num_parents = 2,
1138                 .flags = CLK_SET_RATE_PARENT,
1139         },
1140 };
1141
1142 static struct clk_regmap gxbb_cts_amclk_sel = {
1143         .data = &(struct clk_regmap_mux_data){
1144                 .offset = HHI_AUD_CLK_CNTL,
1145                 .mask = 0x3,
1146                 .shift = 9,
1147                 .table = (u32[]){ 1, 2, 3 },
1148                 .flags = CLK_MUX_ROUND_CLOSEST,
1149         },
1150         .hw.init = &(struct clk_init_data){
1151                 .name = "cts_amclk_sel",
1152                 .ops = &clk_regmap_mux_ops,
1153                 .parent_hws = (const struct clk_hw *[]) {
1154                         &gxbb_mpll0.hw,
1155                         &gxbb_mpll1.hw,
1156                         &gxbb_mpll2.hw,
1157                 },
1158                 .num_parents = 3,
1159         },
1160 };
1161
1162 static struct clk_regmap gxbb_cts_amclk_div = {
1163         .data = &(struct clk_regmap_div_data) {
1164                 .offset = HHI_AUD_CLK_CNTL,
1165                 .shift = 0,
1166                 .width = 8,
1167                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1168         },
1169         .hw.init = &(struct clk_init_data){
1170                 .name = "cts_amclk_div",
1171                 .ops = &clk_regmap_divider_ops,
1172                 .parent_hws = (const struct clk_hw *[]) {
1173                         &gxbb_cts_amclk_sel.hw
1174                 },
1175                 .num_parents = 1,
1176                 .flags = CLK_SET_RATE_PARENT,
1177         },
1178 };
1179
1180 static struct clk_regmap gxbb_cts_amclk = {
1181         .data = &(struct clk_regmap_gate_data){
1182                 .offset = HHI_AUD_CLK_CNTL,
1183                 .bit_idx = 8,
1184         },
1185         .hw.init = &(struct clk_init_data){
1186                 .name = "cts_amclk",
1187                 .ops = &clk_regmap_gate_ops,
1188                 .parent_hws = (const struct clk_hw *[]) {
1189                         &gxbb_cts_amclk_div.hw
1190                 },
1191                 .num_parents = 1,
1192                 .flags = CLK_SET_RATE_PARENT,
1193         },
1194 };
1195
1196 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1197         .data = &(struct clk_regmap_mux_data){
1198                 .offset = HHI_AUD_CLK_CNTL2,
1199                 .mask = 0x3,
1200                 .shift = 25,
1201                 .table = (u32[]){ 1, 2, 3 },
1202                 .flags = CLK_MUX_ROUND_CLOSEST,
1203         },
1204         .hw.init = &(struct clk_init_data) {
1205                 .name = "cts_mclk_i958_sel",
1206                 .ops = &clk_regmap_mux_ops,
1207                 .parent_hws = (const struct clk_hw *[]) {
1208                         &gxbb_mpll0.hw,
1209                         &gxbb_mpll1.hw,
1210                         &gxbb_mpll2.hw,
1211                 },
1212                 .num_parents = 3,
1213         },
1214 };
1215
1216 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1217         .data = &(struct clk_regmap_div_data){
1218                 .offset = HHI_AUD_CLK_CNTL2,
1219                 .shift = 16,
1220                 .width = 8,
1221                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1222         },
1223         .hw.init = &(struct clk_init_data) {
1224                 .name = "cts_mclk_i958_div",
1225                 .ops = &clk_regmap_divider_ops,
1226                 .parent_hws = (const struct clk_hw *[]) {
1227                         &gxbb_cts_mclk_i958_sel.hw
1228                 },
1229                 .num_parents = 1,
1230                 .flags = CLK_SET_RATE_PARENT,
1231         },
1232 };
1233
1234 static struct clk_regmap gxbb_cts_mclk_i958 = {
1235         .data = &(struct clk_regmap_gate_data){
1236                 .offset = HHI_AUD_CLK_CNTL2,
1237                 .bit_idx = 24,
1238         },
1239         .hw.init = &(struct clk_init_data){
1240                 .name = "cts_mclk_i958",
1241                 .ops = &clk_regmap_gate_ops,
1242                 .parent_hws = (const struct clk_hw *[]) {
1243                         &gxbb_cts_mclk_i958_div.hw
1244                 },
1245                 .num_parents = 1,
1246                 .flags = CLK_SET_RATE_PARENT,
1247         },
1248 };
1249
1250 static struct clk_regmap gxbb_cts_i958 = {
1251         .data = &(struct clk_regmap_mux_data){
1252                 .offset = HHI_AUD_CLK_CNTL2,
1253                 .mask = 0x1,
1254                 .shift = 27,
1255                 },
1256         .hw.init = &(struct clk_init_data){
1257                 .name = "cts_i958",
1258                 .ops = &clk_regmap_mux_ops,
1259                 .parent_hws = (const struct clk_hw *[]) {
1260                         &gxbb_cts_amclk.hw,
1261                         &gxbb_cts_mclk_i958.hw
1262                 },
1263                 .num_parents = 2,
1264                 /*
1265                  *The parent is specific to origin of the audio data. Let the
1266                  * consumer choose the appropriate parent
1267                  */
1268                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1269         },
1270 };
1271
1272 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1273         { .fw_name = "xtal", },
1274         /*
1275          * FIXME: This clock is provided by the ao clock controller but the
1276          * clock is not yet part of the binding of this controller, so string
1277          * name must be use to set this parent.
1278          */
1279         { .name = "cts_slow_oscin", .index = -1 },
1280         { .hw = &gxbb_fclk_div3.hw },
1281         { .hw = &gxbb_fclk_div5.hw },
1282 };
1283
1284 static struct clk_regmap gxbb_32k_clk_sel = {
1285         .data = &(struct clk_regmap_mux_data){
1286                 .offset = HHI_32K_CLK_CNTL,
1287                 .mask = 0x3,
1288                 .shift = 16,
1289                 },
1290         .hw.init = &(struct clk_init_data){
1291                 .name = "32k_clk_sel",
1292                 .ops = &clk_regmap_mux_ops,
1293                 .parent_data = gxbb_32k_clk_parent_data,
1294                 .num_parents = 4,
1295                 .flags = CLK_SET_RATE_PARENT,
1296         },
1297 };
1298
1299 static struct clk_regmap gxbb_32k_clk_div = {
1300         .data = &(struct clk_regmap_div_data){
1301                 .offset = HHI_32K_CLK_CNTL,
1302                 .shift = 0,
1303                 .width = 14,
1304         },
1305         .hw.init = &(struct clk_init_data){
1306                 .name = "32k_clk_div",
1307                 .ops = &clk_regmap_divider_ops,
1308                 .parent_hws = (const struct clk_hw *[]) {
1309                         &gxbb_32k_clk_sel.hw
1310                 },
1311                 .num_parents = 1,
1312                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1313         },
1314 };
1315
1316 static struct clk_regmap gxbb_32k_clk = {
1317         .data = &(struct clk_regmap_gate_data){
1318                 .offset = HHI_32K_CLK_CNTL,
1319                 .bit_idx = 15,
1320         },
1321         .hw.init = &(struct clk_init_data){
1322                 .name = "32k_clk",
1323                 .ops = &clk_regmap_gate_ops,
1324                 .parent_hws = (const struct clk_hw *[]) {
1325                         &gxbb_32k_clk_div.hw
1326                 },
1327                 .num_parents = 1,
1328                 .flags = CLK_SET_RATE_PARENT,
1329         },
1330 };
1331
1332 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1333         { .fw_name = "xtal", },
1334         { .hw = &gxbb_fclk_div2.hw },
1335         { .hw = &gxbb_fclk_div3.hw },
1336         { .hw = &gxbb_fclk_div5.hw },
1337         { .hw = &gxbb_fclk_div7.hw },
1338         /*
1339          * Following these parent clocks, we should also have had mpll2, mpll3
1340          * and gp0_pll but these clocks are too precious to be used here. All
1341          * the necessary rates for MMC and NAND operation can be acheived using
1342          * xtal or fclk_div clocks
1343          */
1344 };
1345
1346 /* SDIO clock */
1347 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1348         .data = &(struct clk_regmap_mux_data){
1349                 .offset = HHI_SD_EMMC_CLK_CNTL,
1350                 .mask = 0x7,
1351                 .shift = 9,
1352         },
1353         .hw.init = &(struct clk_init_data) {
1354                 .name = "sd_emmc_a_clk0_sel",
1355                 .ops = &clk_regmap_mux_ops,
1356                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1357                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1358                 .flags = CLK_SET_RATE_PARENT,
1359         },
1360 };
1361
1362 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1363         .data = &(struct clk_regmap_div_data){
1364                 .offset = HHI_SD_EMMC_CLK_CNTL,
1365                 .shift = 0,
1366                 .width = 7,
1367                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1368         },
1369         .hw.init = &(struct clk_init_data) {
1370                 .name = "sd_emmc_a_clk0_div",
1371                 .ops = &clk_regmap_divider_ops,
1372                 .parent_hws = (const struct clk_hw *[]) {
1373                         &gxbb_sd_emmc_a_clk0_sel.hw
1374                 },
1375                 .num_parents = 1,
1376                 .flags = CLK_SET_RATE_PARENT,
1377         },
1378 };
1379
1380 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1381         .data = &(struct clk_regmap_gate_data){
1382                 .offset = HHI_SD_EMMC_CLK_CNTL,
1383                 .bit_idx = 7,
1384         },
1385         .hw.init = &(struct clk_init_data){
1386                 .name = "sd_emmc_a_clk0",
1387                 .ops = &clk_regmap_gate_ops,
1388                 .parent_hws = (const struct clk_hw *[]) {
1389                         &gxbb_sd_emmc_a_clk0_div.hw
1390                 },
1391                 .num_parents = 1,
1392                 .flags = CLK_SET_RATE_PARENT,
1393         },
1394 };
1395
1396 /* SDcard clock */
1397 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1398         .data = &(struct clk_regmap_mux_data){
1399                 .offset = HHI_SD_EMMC_CLK_CNTL,
1400                 .mask = 0x7,
1401                 .shift = 25,
1402         },
1403         .hw.init = &(struct clk_init_data) {
1404                 .name = "sd_emmc_b_clk0_sel",
1405                 .ops = &clk_regmap_mux_ops,
1406                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1407                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1408                 .flags = CLK_SET_RATE_PARENT,
1409         },
1410 };
1411
1412 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1413         .data = &(struct clk_regmap_div_data){
1414                 .offset = HHI_SD_EMMC_CLK_CNTL,
1415                 .shift = 16,
1416                 .width = 7,
1417                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1418         },
1419         .hw.init = &(struct clk_init_data) {
1420                 .name = "sd_emmc_b_clk0_div",
1421                 .ops = &clk_regmap_divider_ops,
1422                 .parent_hws = (const struct clk_hw *[]) {
1423                         &gxbb_sd_emmc_b_clk0_sel.hw
1424                 },
1425                 .num_parents = 1,
1426                 .flags = CLK_SET_RATE_PARENT,
1427         },
1428 };
1429
1430 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1431         .data = &(struct clk_regmap_gate_data){
1432                 .offset = HHI_SD_EMMC_CLK_CNTL,
1433                 .bit_idx = 23,
1434         },
1435         .hw.init = &(struct clk_init_data){
1436                 .name = "sd_emmc_b_clk0",
1437                 .ops = &clk_regmap_gate_ops,
1438                 .parent_hws = (const struct clk_hw *[]) {
1439                         &gxbb_sd_emmc_b_clk0_div.hw
1440                 },
1441                 .num_parents = 1,
1442                 .flags = CLK_SET_RATE_PARENT,
1443         },
1444 };
1445
1446 /* EMMC/NAND clock */
1447 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1448         .data = &(struct clk_regmap_mux_data){
1449                 .offset = HHI_NAND_CLK_CNTL,
1450                 .mask = 0x7,
1451                 .shift = 9,
1452         },
1453         .hw.init = &(struct clk_init_data) {
1454                 .name = "sd_emmc_c_clk0_sel",
1455                 .ops = &clk_regmap_mux_ops,
1456                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1457                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1458                 .flags = CLK_SET_RATE_PARENT,
1459         },
1460 };
1461
1462 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1463         .data = &(struct clk_regmap_div_data){
1464                 .offset = HHI_NAND_CLK_CNTL,
1465                 .shift = 0,
1466                 .width = 7,
1467                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1468         },
1469         .hw.init = &(struct clk_init_data) {
1470                 .name = "sd_emmc_c_clk0_div",
1471                 .ops = &clk_regmap_divider_ops,
1472                 .parent_hws = (const struct clk_hw *[]) {
1473                         &gxbb_sd_emmc_c_clk0_sel.hw
1474                 },
1475                 .num_parents = 1,
1476                 .flags = CLK_SET_RATE_PARENT,
1477         },
1478 };
1479
1480 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1481         .data = &(struct clk_regmap_gate_data){
1482                 .offset = HHI_NAND_CLK_CNTL,
1483                 .bit_idx = 7,
1484         },
1485         .hw.init = &(struct clk_init_data){
1486                 .name = "sd_emmc_c_clk0",
1487                 .ops = &clk_regmap_gate_ops,
1488                 .parent_hws = (const struct clk_hw *[]) {
1489                         &gxbb_sd_emmc_c_clk0_div.hw
1490                 },
1491                 .num_parents = 1,
1492                 .flags = CLK_SET_RATE_PARENT,
1493         },
1494 };
1495
1496 /* VPU Clock */
1497
1498 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1499         &gxbb_fclk_div4.hw,
1500         &gxbb_fclk_div3.hw,
1501         &gxbb_fclk_div5.hw,
1502         &gxbb_fclk_div7.hw,
1503 };
1504
1505 static struct clk_regmap gxbb_vpu_0_sel = {
1506         .data = &(struct clk_regmap_mux_data){
1507                 .offset = HHI_VPU_CLK_CNTL,
1508                 .mask = 0x3,
1509                 .shift = 9,
1510         },
1511         .hw.init = &(struct clk_init_data){
1512                 .name = "vpu_0_sel",
1513                 .ops = &clk_regmap_mux_ops,
1514                 /*
1515                  * bits 9:10 selects from 4 possible parents:
1516                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1517                  */
1518                 .parent_hws = gxbb_vpu_parent_hws,
1519                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1520                 .flags = CLK_SET_RATE_NO_REPARENT,
1521         },
1522 };
1523
1524 static struct clk_regmap gxbb_vpu_0_div = {
1525         .data = &(struct clk_regmap_div_data){
1526                 .offset = HHI_VPU_CLK_CNTL,
1527                 .shift = 0,
1528                 .width = 7,
1529         },
1530         .hw.init = &(struct clk_init_data){
1531                 .name = "vpu_0_div",
1532                 .ops = &clk_regmap_divider_ops,
1533                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1534                 .num_parents = 1,
1535                 .flags = CLK_SET_RATE_PARENT,
1536         },
1537 };
1538
1539 static struct clk_regmap gxbb_vpu_0 = {
1540         .data = &(struct clk_regmap_gate_data){
1541                 .offset = HHI_VPU_CLK_CNTL,
1542                 .bit_idx = 8,
1543         },
1544         .hw.init = &(struct clk_init_data) {
1545                 .name = "vpu_0",
1546                 .ops = &clk_regmap_gate_ops,
1547                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1548                 .num_parents = 1,
1549                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1550         },
1551 };
1552
1553 static struct clk_regmap gxbb_vpu_1_sel = {
1554         .data = &(struct clk_regmap_mux_data){
1555                 .offset = HHI_VPU_CLK_CNTL,
1556                 .mask = 0x3,
1557                 .shift = 25,
1558         },
1559         .hw.init = &(struct clk_init_data){
1560                 .name = "vpu_1_sel",
1561                 .ops = &clk_regmap_mux_ops,
1562                 /*
1563                  * bits 25:26 selects from 4 possible parents:
1564                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1565                  */
1566                 .parent_hws = gxbb_vpu_parent_hws,
1567                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1568                 .flags = CLK_SET_RATE_NO_REPARENT,
1569         },
1570 };
1571
1572 static struct clk_regmap gxbb_vpu_1_div = {
1573         .data = &(struct clk_regmap_div_data){
1574                 .offset = HHI_VPU_CLK_CNTL,
1575                 .shift = 16,
1576                 .width = 7,
1577         },
1578         .hw.init = &(struct clk_init_data){
1579                 .name = "vpu_1_div",
1580                 .ops = &clk_regmap_divider_ops,
1581                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1582                 .num_parents = 1,
1583                 .flags = CLK_SET_RATE_PARENT,
1584         },
1585 };
1586
1587 static struct clk_regmap gxbb_vpu_1 = {
1588         .data = &(struct clk_regmap_gate_data){
1589                 .offset = HHI_VPU_CLK_CNTL,
1590                 .bit_idx = 24,
1591         },
1592         .hw.init = &(struct clk_init_data) {
1593                 .name = "vpu_1",
1594                 .ops = &clk_regmap_gate_ops,
1595                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1596                 .num_parents = 1,
1597                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1598         },
1599 };
1600
1601 static struct clk_regmap gxbb_vpu = {
1602         .data = &(struct clk_regmap_mux_data){
1603                 .offset = HHI_VPU_CLK_CNTL,
1604                 .mask = 1,
1605                 .shift = 31,
1606         },
1607         .hw.init = &(struct clk_init_data){
1608                 .name = "vpu",
1609                 .ops = &clk_regmap_mux_ops,
1610                 /*
1611                  * bit 31 selects from 2 possible parents:
1612                  * vpu_0 or vpu_1
1613                  */
1614                 .parent_hws = (const struct clk_hw *[]) {
1615                         &gxbb_vpu_0.hw,
1616                         &gxbb_vpu_1.hw
1617                 },
1618                 .num_parents = 2,
1619                 .flags = CLK_SET_RATE_NO_REPARENT,
1620         },
1621 };
1622
1623 /* VAPB Clock */
1624
1625 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1626         &gxbb_fclk_div4.hw,
1627         &gxbb_fclk_div3.hw,
1628         &gxbb_fclk_div5.hw,
1629         &gxbb_fclk_div7.hw,
1630 };
1631
1632 static struct clk_regmap gxbb_vapb_0_sel = {
1633         .data = &(struct clk_regmap_mux_data){
1634                 .offset = HHI_VAPBCLK_CNTL,
1635                 .mask = 0x3,
1636                 .shift = 9,
1637         },
1638         .hw.init = &(struct clk_init_data){
1639                 .name = "vapb_0_sel",
1640                 .ops = &clk_regmap_mux_ops,
1641                 /*
1642                  * bits 9:10 selects from 4 possible parents:
1643                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1644                  */
1645                 .parent_hws = gxbb_vapb_parent_hws,
1646                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1647                 .flags = CLK_SET_RATE_NO_REPARENT,
1648         },
1649 };
1650
1651 static struct clk_regmap gxbb_vapb_0_div = {
1652         .data = &(struct clk_regmap_div_data){
1653                 .offset = HHI_VAPBCLK_CNTL,
1654                 .shift = 0,
1655                 .width = 7,
1656         },
1657         .hw.init = &(struct clk_init_data){
1658                 .name = "vapb_0_div",
1659                 .ops = &clk_regmap_divider_ops,
1660                 .parent_hws = (const struct clk_hw *[]) {
1661                         &gxbb_vapb_0_sel.hw
1662                 },
1663                 .num_parents = 1,
1664                 .flags = CLK_SET_RATE_PARENT,
1665         },
1666 };
1667
1668 static struct clk_regmap gxbb_vapb_0 = {
1669         .data = &(struct clk_regmap_gate_data){
1670                 .offset = HHI_VAPBCLK_CNTL,
1671                 .bit_idx = 8,
1672         },
1673         .hw.init = &(struct clk_init_data) {
1674                 .name = "vapb_0",
1675                 .ops = &clk_regmap_gate_ops,
1676                 .parent_hws = (const struct clk_hw *[]) {
1677                         &gxbb_vapb_0_div.hw
1678                 },
1679                 .num_parents = 1,
1680                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1681         },
1682 };
1683
1684 static struct clk_regmap gxbb_vapb_1_sel = {
1685         .data = &(struct clk_regmap_mux_data){
1686                 .offset = HHI_VAPBCLK_CNTL,
1687                 .mask = 0x3,
1688                 .shift = 25,
1689         },
1690         .hw.init = &(struct clk_init_data){
1691                 .name = "vapb_1_sel",
1692                 .ops = &clk_regmap_mux_ops,
1693                 /*
1694                  * bits 25:26 selects from 4 possible parents:
1695                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1696                  */
1697                 .parent_hws = gxbb_vapb_parent_hws,
1698                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1699                 .flags = CLK_SET_RATE_NO_REPARENT,
1700         },
1701 };
1702
1703 static struct clk_regmap gxbb_vapb_1_div = {
1704         .data = &(struct clk_regmap_div_data){
1705                 .offset = HHI_VAPBCLK_CNTL,
1706                 .shift = 16,
1707                 .width = 7,
1708         },
1709         .hw.init = &(struct clk_init_data){
1710                 .name = "vapb_1_div",
1711                 .ops = &clk_regmap_divider_ops,
1712                 .parent_hws = (const struct clk_hw *[]) {
1713                         &gxbb_vapb_1_sel.hw
1714                 },
1715                 .num_parents = 1,
1716                 .flags = CLK_SET_RATE_PARENT,
1717         },
1718 };
1719
1720 static struct clk_regmap gxbb_vapb_1 = {
1721         .data = &(struct clk_regmap_gate_data){
1722                 .offset = HHI_VAPBCLK_CNTL,
1723                 .bit_idx = 24,
1724         },
1725         .hw.init = &(struct clk_init_data) {
1726                 .name = "vapb_1",
1727                 .ops = &clk_regmap_gate_ops,
1728                 .parent_hws = (const struct clk_hw *[]) {
1729                         &gxbb_vapb_1_div.hw
1730                 },
1731                 .num_parents = 1,
1732                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1733         },
1734 };
1735
1736 static struct clk_regmap gxbb_vapb_sel = {
1737         .data = &(struct clk_regmap_mux_data){
1738                 .offset = HHI_VAPBCLK_CNTL,
1739                 .mask = 1,
1740                 .shift = 31,
1741         },
1742         .hw.init = &(struct clk_init_data){
1743                 .name = "vapb_sel",
1744                 .ops = &clk_regmap_mux_ops,
1745                 /*
1746                  * bit 31 selects from 2 possible parents:
1747                  * vapb_0 or vapb_1
1748                  */
1749                 .parent_hws = (const struct clk_hw *[]) {
1750                         &gxbb_vapb_0.hw,
1751                         &gxbb_vapb_1.hw
1752                 },
1753                 .num_parents = 2,
1754                 .flags = CLK_SET_RATE_NO_REPARENT,
1755         },
1756 };
1757
1758 static struct clk_regmap gxbb_vapb = {
1759         .data = &(struct clk_regmap_gate_data){
1760                 .offset = HHI_VAPBCLK_CNTL,
1761                 .bit_idx = 30,
1762         },
1763         .hw.init = &(struct clk_init_data) {
1764                 .name = "vapb",
1765                 .ops = &clk_regmap_gate_ops,
1766                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1767                 .num_parents = 1,
1768                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1769         },
1770 };
1771
1772 /* Video Clocks */
1773
1774 static struct clk_regmap gxbb_vid_pll_div = {
1775         .data = &(struct meson_vid_pll_div_data){
1776                 .val = {
1777                         .reg_off = HHI_VID_PLL_CLK_DIV,
1778                         .shift   = 0,
1779                         .width   = 15,
1780                 },
1781                 .sel = {
1782                         .reg_off = HHI_VID_PLL_CLK_DIV,
1783                         .shift   = 16,
1784                         .width   = 2,
1785                 },
1786         },
1787         .hw.init = &(struct clk_init_data) {
1788                 .name = "vid_pll_div",
1789                 .ops = &meson_vid_pll_div_ro_ops,
1790                 .parent_data = &(const struct clk_parent_data) {
1791                         /*
1792                          * Note:
1793                          * GXL and GXBB have different hdmi_plls (with
1794                          * different struct clk_hw). We fallback to the global
1795                          * naming string mechanism so vid_pll_div picks up the
1796                          * appropriate one.
1797                          */
1798                         .name = "hdmi_pll",
1799                         .index = -1,
1800                 },
1801                 .num_parents = 1,
1802                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1803         },
1804 };
1805
1806 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1807         { .hw = &gxbb_vid_pll_div.hw },
1808         /*
1809          * Note:
1810          * GXL and GXBB have different hdmi_plls (with
1811          * different struct clk_hw). We fallback to the global
1812          * naming string mechanism so vid_pll_div picks up the
1813          * appropriate one.
1814          */
1815         { .name = "hdmi_pll", .index = -1 },
1816 };
1817
1818 static struct clk_regmap gxbb_vid_pll_sel = {
1819         .data = &(struct clk_regmap_mux_data){
1820                 .offset = HHI_VID_PLL_CLK_DIV,
1821                 .mask = 0x1,
1822                 .shift = 18,
1823         },
1824         .hw.init = &(struct clk_init_data){
1825                 .name = "vid_pll_sel",
1826                 .ops = &clk_regmap_mux_ops,
1827                 /*
1828                  * bit 18 selects from 2 possible parents:
1829                  * vid_pll_div or hdmi_pll
1830                  */
1831                 .parent_data = gxbb_vid_pll_parent_data,
1832                 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1833                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1834         },
1835 };
1836
1837 static struct clk_regmap gxbb_vid_pll = {
1838         .data = &(struct clk_regmap_gate_data){
1839                 .offset = HHI_VID_PLL_CLK_DIV,
1840                 .bit_idx = 19,
1841         },
1842         .hw.init = &(struct clk_init_data) {
1843                 .name = "vid_pll",
1844                 .ops = &clk_regmap_gate_ops,
1845                 .parent_hws = (const struct clk_hw *[]) {
1846                         &gxbb_vid_pll_sel.hw
1847                 },
1848                 .num_parents = 1,
1849                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1850         },
1851 };
1852
1853 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1854         &gxbb_vid_pll.hw,
1855         &gxbb_fclk_div4.hw,
1856         &gxbb_fclk_div3.hw,
1857         &gxbb_fclk_div5.hw,
1858         &gxbb_vid_pll.hw,
1859         &gxbb_fclk_div7.hw,
1860         &gxbb_mpll1.hw,
1861 };
1862
1863 static struct clk_regmap gxbb_vclk_sel = {
1864         .data = &(struct clk_regmap_mux_data){
1865                 .offset = HHI_VID_CLK_CNTL,
1866                 .mask = 0x7,
1867                 .shift = 16,
1868         },
1869         .hw.init = &(struct clk_init_data){
1870                 .name = "vclk_sel",
1871                 .ops = &clk_regmap_mux_ops,
1872                 /*
1873                  * bits 16:18 selects from 8 possible parents:
1874                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1875                  * vid_pll, fclk_div7, mp1
1876                  */
1877                 .parent_hws = gxbb_vclk_parent_hws,
1878                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1879                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1880         },
1881 };
1882
1883 static struct clk_regmap gxbb_vclk2_sel = {
1884         .data = &(struct clk_regmap_mux_data){
1885                 .offset = HHI_VIID_CLK_CNTL,
1886                 .mask = 0x7,
1887                 .shift = 16,
1888         },
1889         .hw.init = &(struct clk_init_data){
1890                 .name = "vclk2_sel",
1891                 .ops = &clk_regmap_mux_ops,
1892                 /*
1893                  * bits 16:18 selects from 8 possible parents:
1894                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1895                  * vid_pll, fclk_div7, mp1
1896                  */
1897                 .parent_hws = gxbb_vclk_parent_hws,
1898                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1899                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1900         },
1901 };
1902
1903 static struct clk_regmap gxbb_vclk_input = {
1904         .data = &(struct clk_regmap_gate_data){
1905                 .offset = HHI_VID_CLK_DIV,
1906                 .bit_idx = 16,
1907         },
1908         .hw.init = &(struct clk_init_data) {
1909                 .name = "vclk_input",
1910                 .ops = &clk_regmap_gate_ops,
1911                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1912                 .num_parents = 1,
1913                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1914         },
1915 };
1916
1917 static struct clk_regmap gxbb_vclk2_input = {
1918         .data = &(struct clk_regmap_gate_data){
1919                 .offset = HHI_VIID_CLK_DIV,
1920                 .bit_idx = 16,
1921         },
1922         .hw.init = &(struct clk_init_data) {
1923                 .name = "vclk2_input",
1924                 .ops = &clk_regmap_gate_ops,
1925                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1926                 .num_parents = 1,
1927                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1928         },
1929 };
1930
1931 static struct clk_regmap gxbb_vclk_div = {
1932         .data = &(struct clk_regmap_div_data){
1933                 .offset = HHI_VID_CLK_DIV,
1934                 .shift = 0,
1935                 .width = 8,
1936         },
1937         .hw.init = &(struct clk_init_data){
1938                 .name = "vclk_div",
1939                 .ops = &clk_regmap_divider_ops,
1940                 .parent_hws = (const struct clk_hw *[]) {
1941                         &gxbb_vclk_input.hw
1942                 },
1943                 .num_parents = 1,
1944                 .flags = CLK_GET_RATE_NOCACHE,
1945         },
1946 };
1947
1948 static struct clk_regmap gxbb_vclk2_div = {
1949         .data = &(struct clk_regmap_div_data){
1950                 .offset = HHI_VIID_CLK_DIV,
1951                 .shift = 0,
1952                 .width = 8,
1953         },
1954         .hw.init = &(struct clk_init_data){
1955                 .name = "vclk2_div",
1956                 .ops = &clk_regmap_divider_ops,
1957                 .parent_hws = (const struct clk_hw *[]) {
1958                         &gxbb_vclk2_input.hw
1959                 },
1960                 .num_parents = 1,
1961                 .flags = CLK_GET_RATE_NOCACHE,
1962         },
1963 };
1964
1965 static struct clk_regmap gxbb_vclk = {
1966         .data = &(struct clk_regmap_gate_data){
1967                 .offset = HHI_VID_CLK_CNTL,
1968                 .bit_idx = 19,
1969         },
1970         .hw.init = &(struct clk_init_data) {
1971                 .name = "vclk",
1972                 .ops = &clk_regmap_gate_ops,
1973                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1974                 .num_parents = 1,
1975                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1976         },
1977 };
1978
1979 static struct clk_regmap gxbb_vclk2 = {
1980         .data = &(struct clk_regmap_gate_data){
1981                 .offset = HHI_VIID_CLK_CNTL,
1982                 .bit_idx = 19,
1983         },
1984         .hw.init = &(struct clk_init_data) {
1985                 .name = "vclk2",
1986                 .ops = &clk_regmap_gate_ops,
1987                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1988                 .num_parents = 1,
1989                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1990         },
1991 };
1992
1993 static struct clk_regmap gxbb_vclk_div1 = {
1994         .data = &(struct clk_regmap_gate_data){
1995                 .offset = HHI_VID_CLK_CNTL,
1996                 .bit_idx = 0,
1997         },
1998         .hw.init = &(struct clk_init_data) {
1999                 .name = "vclk_div1",
2000                 .ops = &clk_regmap_gate_ops,
2001                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2002                 .num_parents = 1,
2003                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2004         },
2005 };
2006
2007 static struct clk_regmap gxbb_vclk_div2_en = {
2008         .data = &(struct clk_regmap_gate_data){
2009                 .offset = HHI_VID_CLK_CNTL,
2010                 .bit_idx = 1,
2011         },
2012         .hw.init = &(struct clk_init_data) {
2013                 .name = "vclk_div2_en",
2014                 .ops = &clk_regmap_gate_ops,
2015                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2016                 .num_parents = 1,
2017                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2018         },
2019 };
2020
2021 static struct clk_regmap gxbb_vclk_div4_en = {
2022         .data = &(struct clk_regmap_gate_data){
2023                 .offset = HHI_VID_CLK_CNTL,
2024                 .bit_idx = 2,
2025         },
2026         .hw.init = &(struct clk_init_data) {
2027                 .name = "vclk_div4_en",
2028                 .ops = &clk_regmap_gate_ops,
2029                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2030                 .num_parents = 1,
2031                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2032         },
2033 };
2034
2035 static struct clk_regmap gxbb_vclk_div6_en = {
2036         .data = &(struct clk_regmap_gate_data){
2037                 .offset = HHI_VID_CLK_CNTL,
2038                 .bit_idx = 3,
2039         },
2040         .hw.init = &(struct clk_init_data) {
2041                 .name = "vclk_div6_en",
2042                 .ops = &clk_regmap_gate_ops,
2043                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2044                 .num_parents = 1,
2045                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2046         },
2047 };
2048
2049 static struct clk_regmap gxbb_vclk_div12_en = {
2050         .data = &(struct clk_regmap_gate_data){
2051                 .offset = HHI_VID_CLK_CNTL,
2052                 .bit_idx = 4,
2053         },
2054         .hw.init = &(struct clk_init_data) {
2055                 .name = "vclk_div12_en",
2056                 .ops = &clk_regmap_gate_ops,
2057                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2058                 .num_parents = 1,
2059                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2060         },
2061 };
2062
2063 static struct clk_regmap gxbb_vclk2_div1 = {
2064         .data = &(struct clk_regmap_gate_data){
2065                 .offset = HHI_VIID_CLK_CNTL,
2066                 .bit_idx = 0,
2067         },
2068         .hw.init = &(struct clk_init_data) {
2069                 .name = "vclk2_div1",
2070                 .ops = &clk_regmap_gate_ops,
2071                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2072                 .num_parents = 1,
2073                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2074         },
2075 };
2076
2077 static struct clk_regmap gxbb_vclk2_div2_en = {
2078         .data = &(struct clk_regmap_gate_data){
2079                 .offset = HHI_VIID_CLK_CNTL,
2080                 .bit_idx = 1,
2081         },
2082         .hw.init = &(struct clk_init_data) {
2083                 .name = "vclk2_div2_en",
2084                 .ops = &clk_regmap_gate_ops,
2085                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2086                 .num_parents = 1,
2087                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2088         },
2089 };
2090
2091 static struct clk_regmap gxbb_vclk2_div4_en = {
2092         .data = &(struct clk_regmap_gate_data){
2093                 .offset = HHI_VIID_CLK_CNTL,
2094                 .bit_idx = 2,
2095         },
2096         .hw.init = &(struct clk_init_data) {
2097                 .name = "vclk2_div4_en",
2098                 .ops = &clk_regmap_gate_ops,
2099                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2100                 .num_parents = 1,
2101                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2102         },
2103 };
2104
2105 static struct clk_regmap gxbb_vclk2_div6_en = {
2106         .data = &(struct clk_regmap_gate_data){
2107                 .offset = HHI_VIID_CLK_CNTL,
2108                 .bit_idx = 3,
2109         },
2110         .hw.init = &(struct clk_init_data) {
2111                 .name = "vclk2_div6_en",
2112                 .ops = &clk_regmap_gate_ops,
2113                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2114                 .num_parents = 1,
2115                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2116         },
2117 };
2118
2119 static struct clk_regmap gxbb_vclk2_div12_en = {
2120         .data = &(struct clk_regmap_gate_data){
2121                 .offset = HHI_VIID_CLK_CNTL,
2122                 .bit_idx = 4,
2123         },
2124         .hw.init = &(struct clk_init_data) {
2125                 .name = "vclk2_div12_en",
2126                 .ops = &clk_regmap_gate_ops,
2127                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2128                 .num_parents = 1,
2129                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2130         },
2131 };
2132
2133 static struct clk_fixed_factor gxbb_vclk_div2 = {
2134         .mult = 1,
2135         .div = 2,
2136         .hw.init = &(struct clk_init_data){
2137                 .name = "vclk_div2",
2138                 .ops = &clk_fixed_factor_ops,
2139                 .parent_hws = (const struct clk_hw *[]) {
2140                         &gxbb_vclk_div2_en.hw
2141                 },
2142                 .num_parents = 1,
2143         },
2144 };
2145
2146 static struct clk_fixed_factor gxbb_vclk_div4 = {
2147         .mult = 1,
2148         .div = 4,
2149         .hw.init = &(struct clk_init_data){
2150                 .name = "vclk_div4",
2151                 .ops = &clk_fixed_factor_ops,
2152                 .parent_hws = (const struct clk_hw *[]) {
2153                         &gxbb_vclk_div4_en.hw
2154                 },
2155                 .num_parents = 1,
2156         },
2157 };
2158
2159 static struct clk_fixed_factor gxbb_vclk_div6 = {
2160         .mult = 1,
2161         .div = 6,
2162         .hw.init = &(struct clk_init_data){
2163                 .name = "vclk_div6",
2164                 .ops = &clk_fixed_factor_ops,
2165                 .parent_hws = (const struct clk_hw *[]) {
2166                         &gxbb_vclk_div6_en.hw
2167                 },
2168                 .num_parents = 1,
2169         },
2170 };
2171
2172 static struct clk_fixed_factor gxbb_vclk_div12 = {
2173         .mult = 1,
2174         .div = 12,
2175         .hw.init = &(struct clk_init_data){
2176                 .name = "vclk_div12",
2177                 .ops = &clk_fixed_factor_ops,
2178                 .parent_hws = (const struct clk_hw *[]) {
2179                         &gxbb_vclk_div12_en.hw
2180                 },
2181                 .num_parents = 1,
2182         },
2183 };
2184
2185 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2186         .mult = 1,
2187         .div = 2,
2188         .hw.init = &(struct clk_init_data){
2189                 .name = "vclk2_div2",
2190                 .ops = &clk_fixed_factor_ops,
2191                 .parent_hws = (const struct clk_hw *[]) {
2192                         &gxbb_vclk2_div2_en.hw
2193                 },
2194                 .num_parents = 1,
2195         },
2196 };
2197
2198 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2199         .mult = 1,
2200         .div = 4,
2201         .hw.init = &(struct clk_init_data){
2202                 .name = "vclk2_div4",
2203                 .ops = &clk_fixed_factor_ops,
2204                 .parent_hws = (const struct clk_hw *[]) {
2205                         &gxbb_vclk2_div4_en.hw
2206                 },
2207                 .num_parents = 1,
2208         },
2209 };
2210
2211 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2212         .mult = 1,
2213         .div = 6,
2214         .hw.init = &(struct clk_init_data){
2215                 .name = "vclk2_div6",
2216                 .ops = &clk_fixed_factor_ops,
2217                 .parent_hws = (const struct clk_hw *[]) {
2218                         &gxbb_vclk2_div6_en.hw
2219                 },
2220                 .num_parents = 1,
2221         },
2222 };
2223
2224 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2225         .mult = 1,
2226         .div = 12,
2227         .hw.init = &(struct clk_init_data){
2228                 .name = "vclk2_div12",
2229                 .ops = &clk_fixed_factor_ops,
2230                 .parent_hws = (const struct clk_hw *[]) {
2231                         &gxbb_vclk2_div12_en.hw
2232                 },
2233                 .num_parents = 1,
2234         },
2235 };
2236
2237 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2238 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2239         &gxbb_vclk_div1.hw,
2240         &gxbb_vclk_div2.hw,
2241         &gxbb_vclk_div4.hw,
2242         &gxbb_vclk_div6.hw,
2243         &gxbb_vclk_div12.hw,
2244         &gxbb_vclk2_div1.hw,
2245         &gxbb_vclk2_div2.hw,
2246         &gxbb_vclk2_div4.hw,
2247         &gxbb_vclk2_div6.hw,
2248         &gxbb_vclk2_div12.hw,
2249 };
2250
2251 static struct clk_regmap gxbb_cts_enci_sel = {
2252         .data = &(struct clk_regmap_mux_data){
2253                 .offset = HHI_VID_CLK_DIV,
2254                 .mask = 0xf,
2255                 .shift = 28,
2256                 .table = mux_table_cts_sel,
2257         },
2258         .hw.init = &(struct clk_init_data){
2259                 .name = "cts_enci_sel",
2260                 .ops = &clk_regmap_mux_ops,
2261                 .parent_hws = gxbb_cts_parent_hws,
2262                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2263                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2264         },
2265 };
2266
2267 static struct clk_regmap gxbb_cts_encp_sel = {
2268         .data = &(struct clk_regmap_mux_data){
2269                 .offset = HHI_VID_CLK_DIV,
2270                 .mask = 0xf,
2271                 .shift = 20,
2272                 .table = mux_table_cts_sel,
2273         },
2274         .hw.init = &(struct clk_init_data){
2275                 .name = "cts_encp_sel",
2276                 .ops = &clk_regmap_mux_ops,
2277                 .parent_hws = gxbb_cts_parent_hws,
2278                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2279                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2280         },
2281 };
2282
2283 static struct clk_regmap gxbb_cts_vdac_sel = {
2284         .data = &(struct clk_regmap_mux_data){
2285                 .offset = HHI_VIID_CLK_DIV,
2286                 .mask = 0xf,
2287                 .shift = 28,
2288                 .table = mux_table_cts_sel,
2289         },
2290         .hw.init = &(struct clk_init_data){
2291                 .name = "cts_vdac_sel",
2292                 .ops = &clk_regmap_mux_ops,
2293                 .parent_hws = gxbb_cts_parent_hws,
2294                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2295                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2296         },
2297 };
2298
2299 /* TOFIX: add support for cts_tcon */
2300 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2301 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2302         &gxbb_vclk_div1.hw,
2303         &gxbb_vclk_div2.hw,
2304         &gxbb_vclk_div4.hw,
2305         &gxbb_vclk_div6.hw,
2306         &gxbb_vclk_div12.hw,
2307         &gxbb_vclk2_div1.hw,
2308         &gxbb_vclk2_div2.hw,
2309         &gxbb_vclk2_div4.hw,
2310         &gxbb_vclk2_div6.hw,
2311         &gxbb_vclk2_div12.hw,
2312 };
2313
2314 static struct clk_regmap gxbb_hdmi_tx_sel = {
2315         .data = &(struct clk_regmap_mux_data){
2316                 .offset = HHI_HDMI_CLK_CNTL,
2317                 .mask = 0xf,
2318                 .shift = 16,
2319                 .table = mux_table_hdmi_tx_sel,
2320         },
2321         .hw.init = &(struct clk_init_data){
2322                 .name = "hdmi_tx_sel",
2323                 .ops = &clk_regmap_mux_ops,
2324                 /*
2325                  * bits 31:28 selects from 12 possible parents:
2326                  * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2327                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2328                  * cts_tcon
2329                  */
2330                 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2331                 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2332                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2333         },
2334 };
2335
2336 static struct clk_regmap gxbb_cts_enci = {
2337         .data = &(struct clk_regmap_gate_data){
2338                 .offset = HHI_VID_CLK_CNTL2,
2339                 .bit_idx = 0,
2340         },
2341         .hw.init = &(struct clk_init_data) {
2342                 .name = "cts_enci",
2343                 .ops = &clk_regmap_gate_ops,
2344                 .parent_hws = (const struct clk_hw *[]) {
2345                         &gxbb_cts_enci_sel.hw
2346                 },
2347                 .num_parents = 1,
2348                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2349         },
2350 };
2351
2352 static struct clk_regmap gxbb_cts_encp = {
2353         .data = &(struct clk_regmap_gate_data){
2354                 .offset = HHI_VID_CLK_CNTL2,
2355                 .bit_idx = 2,
2356         },
2357         .hw.init = &(struct clk_init_data) {
2358                 .name = "cts_encp",
2359                 .ops = &clk_regmap_gate_ops,
2360                 .parent_hws = (const struct clk_hw *[]) {
2361                         &gxbb_cts_encp_sel.hw
2362                 },
2363                 .num_parents = 1,
2364                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2365         },
2366 };
2367
2368 static struct clk_regmap gxbb_cts_vdac = {
2369         .data = &(struct clk_regmap_gate_data){
2370                 .offset = HHI_VID_CLK_CNTL2,
2371                 .bit_idx = 4,
2372         },
2373         .hw.init = &(struct clk_init_data) {
2374                 .name = "cts_vdac",
2375                 .ops = &clk_regmap_gate_ops,
2376                 .parent_hws = (const struct clk_hw *[]) {
2377                         &gxbb_cts_vdac_sel.hw
2378                 },
2379                 .num_parents = 1,
2380                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2381         },
2382 };
2383
2384 static struct clk_regmap gxbb_hdmi_tx = {
2385         .data = &(struct clk_regmap_gate_data){
2386                 .offset = HHI_VID_CLK_CNTL2,
2387                 .bit_idx = 5,
2388         },
2389         .hw.init = &(struct clk_init_data) {
2390                 .name = "hdmi_tx",
2391                 .ops = &clk_regmap_gate_ops,
2392                 .parent_hws = (const struct clk_hw *[]) {
2393                         &gxbb_hdmi_tx_sel.hw
2394                 },
2395                 .num_parents = 1,
2396                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2397         },
2398 };
2399
2400 /* HDMI Clocks */
2401
2402 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2403         { .fw_name = "xtal", },
2404         { .hw = &gxbb_fclk_div4.hw },
2405         { .hw = &gxbb_fclk_div3.hw },
2406         { .hw = &gxbb_fclk_div5.hw },
2407 };
2408
2409 static struct clk_regmap gxbb_hdmi_sel = {
2410         .data = &(struct clk_regmap_mux_data){
2411                 .offset = HHI_HDMI_CLK_CNTL,
2412                 .mask = 0x3,
2413                 .shift = 9,
2414                 .flags = CLK_MUX_ROUND_CLOSEST,
2415         },
2416         .hw.init = &(struct clk_init_data){
2417                 .name = "hdmi_sel",
2418                 .ops = &clk_regmap_mux_ops,
2419                 .parent_data = gxbb_hdmi_parent_data,
2420                 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2421                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2422         },
2423 };
2424
2425 static struct clk_regmap gxbb_hdmi_div = {
2426         .data = &(struct clk_regmap_div_data){
2427                 .offset = HHI_HDMI_CLK_CNTL,
2428                 .shift = 0,
2429                 .width = 7,
2430         },
2431         .hw.init = &(struct clk_init_data){
2432                 .name = "hdmi_div",
2433                 .ops = &clk_regmap_divider_ops,
2434                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2435                 .num_parents = 1,
2436                 .flags = CLK_GET_RATE_NOCACHE,
2437         },
2438 };
2439
2440 static struct clk_regmap gxbb_hdmi = {
2441         .data = &(struct clk_regmap_gate_data){
2442                 .offset = HHI_HDMI_CLK_CNTL,
2443                 .bit_idx = 8,
2444         },
2445         .hw.init = &(struct clk_init_data) {
2446                 .name = "hdmi",
2447                 .ops = &clk_regmap_gate_ops,
2448                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2449                 .num_parents = 1,
2450                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2451         },
2452 };
2453
2454 /* VDEC clocks */
2455
2456 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2457         &gxbb_fclk_div4.hw,
2458         &gxbb_fclk_div3.hw,
2459         &gxbb_fclk_div5.hw,
2460         &gxbb_fclk_div7.hw,
2461 };
2462
2463 static struct clk_regmap gxbb_vdec_1_sel = {
2464         .data = &(struct clk_regmap_mux_data){
2465                 .offset = HHI_VDEC_CLK_CNTL,
2466                 .mask = 0x3,
2467                 .shift = 9,
2468                 .flags = CLK_MUX_ROUND_CLOSEST,
2469         },
2470         .hw.init = &(struct clk_init_data){
2471                 .name = "vdec_1_sel",
2472                 .ops = &clk_regmap_mux_ops,
2473                 .parent_hws = gxbb_vdec_parent_hws,
2474                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2475                 .flags = CLK_SET_RATE_PARENT,
2476         },
2477 };
2478
2479 static struct clk_regmap gxbb_vdec_1_div = {
2480         .data = &(struct clk_regmap_div_data){
2481                 .offset = HHI_VDEC_CLK_CNTL,
2482                 .shift = 0,
2483                 .width = 7,
2484                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2485         },
2486         .hw.init = &(struct clk_init_data){
2487                 .name = "vdec_1_div",
2488                 .ops = &clk_regmap_divider_ops,
2489                 .parent_hws = (const struct clk_hw *[]) {
2490                         &gxbb_vdec_1_sel.hw
2491                 },
2492                 .num_parents = 1,
2493                 .flags = CLK_SET_RATE_PARENT,
2494         },
2495 };
2496
2497 static struct clk_regmap gxbb_vdec_1 = {
2498         .data = &(struct clk_regmap_gate_data){
2499                 .offset = HHI_VDEC_CLK_CNTL,
2500                 .bit_idx = 8,
2501         },
2502         .hw.init = &(struct clk_init_data) {
2503                 .name = "vdec_1",
2504                 .ops = &clk_regmap_gate_ops,
2505                 .parent_hws = (const struct clk_hw *[]) {
2506                         &gxbb_vdec_1_div.hw
2507                 },
2508                 .num_parents = 1,
2509                 .flags = CLK_SET_RATE_PARENT,
2510         },
2511 };
2512
2513 static struct clk_regmap gxbb_vdec_hevc_sel = {
2514         .data = &(struct clk_regmap_mux_data){
2515                 .offset = HHI_VDEC2_CLK_CNTL,
2516                 .mask = 0x3,
2517                 .shift = 25,
2518                 .flags = CLK_MUX_ROUND_CLOSEST,
2519         },
2520         .hw.init = &(struct clk_init_data){
2521                 .name = "vdec_hevc_sel",
2522                 .ops = &clk_regmap_mux_ops,
2523                 .parent_hws = gxbb_vdec_parent_hws,
2524                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2525                 .flags = CLK_SET_RATE_PARENT,
2526         },
2527 };
2528
2529 static struct clk_regmap gxbb_vdec_hevc_div = {
2530         .data = &(struct clk_regmap_div_data){
2531                 .offset = HHI_VDEC2_CLK_CNTL,
2532                 .shift = 16,
2533                 .width = 7,
2534                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2535         },
2536         .hw.init = &(struct clk_init_data){
2537                 .name = "vdec_hevc_div",
2538                 .ops = &clk_regmap_divider_ops,
2539                 .parent_hws = (const struct clk_hw *[]) {
2540                         &gxbb_vdec_hevc_sel.hw
2541                 },
2542                 .num_parents = 1,
2543                 .flags = CLK_SET_RATE_PARENT,
2544         },
2545 };
2546
2547 static struct clk_regmap gxbb_vdec_hevc = {
2548         .data = &(struct clk_regmap_gate_data){
2549                 .offset = HHI_VDEC2_CLK_CNTL,
2550                 .bit_idx = 24,
2551         },
2552         .hw.init = &(struct clk_init_data) {
2553                 .name = "vdec_hevc",
2554                 .ops = &clk_regmap_gate_ops,
2555                 .parent_hws = (const struct clk_hw *[]) {
2556                         &gxbb_vdec_hevc_div.hw
2557                 },
2558                 .num_parents = 1,
2559                 .flags = CLK_SET_RATE_PARENT,
2560         },
2561 };
2562
2563 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
2564                                     9, 10, 11, 13, 14, };
2565 static const struct clk_parent_data gen_clk_parent_data[] = {
2566         { .fw_name = "xtal", },
2567         { .hw = &gxbb_vdec_1.hw },
2568         { .hw = &gxbb_vdec_hevc.hw },
2569         { .hw = &gxbb_mpll0.hw },
2570         { .hw = &gxbb_mpll1.hw },
2571         { .hw = &gxbb_mpll2.hw },
2572         { .hw = &gxbb_fclk_div4.hw },
2573         { .hw = &gxbb_fclk_div3.hw },
2574         { .hw = &gxbb_fclk_div5.hw },
2575         { .hw = &gxbb_fclk_div7.hw },
2576         { .hw = &gxbb_gp0_pll.hw },
2577 };
2578
2579 static struct clk_regmap gxbb_gen_clk_sel = {
2580         .data = &(struct clk_regmap_mux_data){
2581                 .offset = HHI_GEN_CLK_CNTL,
2582                 .mask = 0xf,
2583                 .shift = 12,
2584                 .table = mux_table_gen_clk,
2585         },
2586         .hw.init = &(struct clk_init_data){
2587                 .name = "gen_clk_sel",
2588                 .ops = &clk_regmap_mux_ops,
2589                 /*
2590                  * bits 15:12 selects from 14 possible parents:
2591                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2592                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2593                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2594                  */
2595                 .parent_data = gen_clk_parent_data,
2596                 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2597         },
2598 };
2599
2600 static struct clk_regmap gxbb_gen_clk_div = {
2601         .data = &(struct clk_regmap_div_data){
2602                 .offset = HHI_GEN_CLK_CNTL,
2603                 .shift = 0,
2604                 .width = 11,
2605         },
2606         .hw.init = &(struct clk_init_data){
2607                 .name = "gen_clk_div",
2608                 .ops = &clk_regmap_divider_ops,
2609                 .parent_hws = (const struct clk_hw *[]) {
2610                         &gxbb_gen_clk_sel.hw
2611                 },
2612                 .num_parents = 1,
2613                 .flags = CLK_SET_RATE_PARENT,
2614         },
2615 };
2616
2617 static struct clk_regmap gxbb_gen_clk = {
2618         .data = &(struct clk_regmap_gate_data){
2619                 .offset = HHI_GEN_CLK_CNTL,
2620                 .bit_idx = 7,
2621         },
2622         .hw.init = &(struct clk_init_data){
2623                 .name = "gen_clk",
2624                 .ops = &clk_regmap_gate_ops,
2625                 .parent_hws = (const struct clk_hw *[]) {
2626                         &gxbb_gen_clk_div.hw
2627                 },
2628                 .num_parents = 1,
2629                 .flags = CLK_SET_RATE_PARENT,
2630         },
2631 };
2632
2633 #define MESON_GATE(_name, _reg, _bit) \
2634         MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2635
2636 /* Everything Else (EE) domain gates */
2637 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2638 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2639 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2640 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2641 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2642 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2643 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2644 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2645 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2646 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2647 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2648 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2649 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2650 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2651 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2652 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2653 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2654 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2655 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2656 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2657 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2658 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2659 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2660
2661 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2662 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2663 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2664 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2665 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2666 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2667 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2668 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2669 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2670 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2671 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2672 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2673 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2674 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2675 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2676 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2677 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2678
2679 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2680 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2681 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2682 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2683 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2684 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2685 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2686 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2687 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2688 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2689 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2690 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2691 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2692
2693 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2694 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2695 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2696 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2697 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2698 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2699 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2700 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2701 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2702 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2703 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2704 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2705 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2706 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2707 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2708 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2709
2710 /* Always On (AO) domain gates */
2711
2712 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2713 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2714 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2715 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2716 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2717
2718 /* AIU gates */
2719 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2720 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2721 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2722 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2723 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2724 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2725 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2726 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2727
2728 /* Array of all clocks provided by this provider */
2729
2730 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2731         .hws = {
2732                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2733                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
2734                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2735                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2736                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2737                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2738                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2739                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2740                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2741                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2742                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2743                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2744                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2745                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2746                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2747                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2748                 [CLKID_DOS]                 = &gxbb_dos.hw,
2749                 [CLKID_ISA]                 = &gxbb_isa.hw,
2750                 [CLKID_PL301]               = &gxbb_pl301.hw,
2751                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2752                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2753                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2754                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2755                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2756                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2757                 [CLKID_UART0]               = &gxbb_uart0.hw,
2758                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2759                 [CLKID_STREAM]              = &gxbb_stream.hw,
2760                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2761                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2762                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2763                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2764                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2765                 [CLKID_SPI]                 = &gxbb_spi.hw,
2766                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2767                 [CLKID_ETH]                 = &gxbb_eth.hw,
2768                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2769                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2770                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2771                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2772                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2773                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2774                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2775                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2776                 [CLKID_ADC]                 = &gxbb_adc.hw,
2777                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2778                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2779                 [CLKID_UART1]               = &gxbb_uart1.hw,
2780                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2781                 [CLKID_USB0]                = &gxbb_usb0.hw,
2782                 [CLKID_USB1]                = &gxbb_usb1.hw,
2783                 [CLKID_RESET]               = &gxbb_reset.hw,
2784                 [CLKID_NAND]                = &gxbb_nand.hw,
2785                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2786                 [CLKID_USB]                 = &gxbb_usb.hw,
2787                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2788                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2789                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2790                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2791                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2792                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2793                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2794                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2795                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2796                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2797                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2798                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2799                 [CLKID_UART2]               = &gxbb_uart2.hw,
2800                 [CLKID_SANA]                = &gxbb_sana.hw,
2801                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2802                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2803                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2804                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2805                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2806                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2807                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2808                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2809                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2810                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2811                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2812                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2813                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2814                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2815                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2816                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2817                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2818                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2819                 [CLKID_EDP]                 = &gxbb_edp.hw,
2820                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2821                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2822                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2823                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2824                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2825                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2826                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2827                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2828                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2829                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2830                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2831                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2832                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2833                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2834                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2835                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2836                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2837                 [CLKID_MALI]                = &gxbb_mali.hw,
2838                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2839                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2840                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2841                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2842                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2843                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2844                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2845                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2846                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2847                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2848                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2849                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2850                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2851                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2852                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2853                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2854                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2855                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2856                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2857                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2858                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2859                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2860                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2861                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2862                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2863                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2864                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2865                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2866                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2867                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2868                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2869                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2870                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2871                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2872                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2873                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2874                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2875                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2876                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2877                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2878                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2879                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2880                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2881                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2882                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2883                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2884                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2885                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2886                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2887                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2888                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2889                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2890                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2891                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2892                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2893                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
2894                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
2895                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2896                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
2897                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
2898                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
2899                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
2900                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
2901                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
2902                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
2903                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
2904                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
2905                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
2906                 [CLKID_VCLK]                = &gxbb_vclk.hw,
2907                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
2908                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
2909                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
2910                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
2911                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
2912                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
2913                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
2914                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
2915                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
2916                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
2917                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
2918                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
2919                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
2920                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
2921                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
2922                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
2923                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
2924                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
2925                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
2926                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
2927                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
2928                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
2929                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
2930                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
2931                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
2932                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
2933                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
2934                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
2935                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
2936                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
2937                 [NR_CLKS]                   = NULL,
2938         },
2939         .num = NR_CLKS,
2940 };
2941
2942 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2943         .hws = {
2944                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2945                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
2946                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2947                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2948                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2949                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2950                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2951                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2952                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2953                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2954                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2955                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2956                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2957                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2958                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2959                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2960                 [CLKID_DOS]                 = &gxbb_dos.hw,
2961                 [CLKID_ISA]                 = &gxbb_isa.hw,
2962                 [CLKID_PL301]               = &gxbb_pl301.hw,
2963                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2964                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2965                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2966                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2967                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2968                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2969                 [CLKID_UART0]               = &gxbb_uart0.hw,
2970                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2971                 [CLKID_STREAM]              = &gxbb_stream.hw,
2972                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2973                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2974                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2975                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2976                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2977                 [CLKID_SPI]                 = &gxbb_spi.hw,
2978                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2979                 [CLKID_ETH]                 = &gxbb_eth.hw,
2980                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2981                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2982                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2983                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2984                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2985                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2986                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2987                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2988                 [CLKID_ADC]                 = &gxbb_adc.hw,
2989                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2990                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2991                 [CLKID_UART1]               = &gxbb_uart1.hw,
2992                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2993                 [CLKID_USB0]                = &gxbb_usb0.hw,
2994                 [CLKID_USB1]                = &gxbb_usb1.hw,
2995                 [CLKID_RESET]               = &gxbb_reset.hw,
2996                 [CLKID_NAND]                = &gxbb_nand.hw,
2997                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2998                 [CLKID_USB]                 = &gxbb_usb.hw,
2999                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
3000                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
3001                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
3002                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
3003                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
3004                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
3005                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
3006                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
3007                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
3008                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
3009                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
3010                 [CLKID_DVIN]                = &gxbb_dvin.hw,
3011                 [CLKID_UART2]               = &gxbb_uart2.hw,
3012                 [CLKID_SANA]                = &gxbb_sana.hw,
3013                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
3014                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
3015                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
3016                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
3017                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
3018                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
3019                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
3020                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
3021                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
3022                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
3023                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
3024                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
3025                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
3026                 [CLKID_RNG1]                = &gxbb_rng1.hw,
3027                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
3028                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
3029                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
3030                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
3031                 [CLKID_EDP]                 = &gxbb_edp.hw,
3032                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
3033                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
3034                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
3035                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
3036                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
3037                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
3038                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
3039                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
3040                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
3041                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
3042                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
3043                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
3044                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
3045                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
3046                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
3047                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
3048                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
3049                 [CLKID_MALI]                = &gxbb_mali.hw,
3050                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
3051                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
3052                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
3053                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
3054                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3055                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3056                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
3057                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
3058                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
3059                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
3060                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3061                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3062                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
3063                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3064                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3065                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
3066                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3067                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3068                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
3069                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
3070                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
3071                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
3072                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
3073                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
3074                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
3075                 [CLKID_VPU]                 = &gxbb_vpu.hw,
3076                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
3077                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
3078                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
3079                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
3080                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
3081                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
3082                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
3083                 [CLKID_VAPB]                = &gxbb_vapb.hw,
3084                 [CLKID_MPLL0_DIV]           = &gxl_mpll0_div.hw,
3085                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
3086                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
3087                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
3088                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
3089                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
3090                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
3091                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
3092                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
3093                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
3094                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
3095                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
3096                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
3097                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
3098                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
3099                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
3100                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
3101                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
3102                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
3103                 [CLKID_HDMI_PLL_DCO]        = &gxl_hdmi_pll_dco.hw,
3104                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
3105                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
3106                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
3107                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
3108                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
3109                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
3110                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
3111                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
3112                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
3113                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
3114                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
3115                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
3116                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
3117                 [CLKID_VCLK]                = &gxbb_vclk.hw,
3118                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
3119                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
3120                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
3121                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
3122                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
3123                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
3124                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
3125                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
3126                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
3127                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
3128                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
3129                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
3130                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
3131                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
3132                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
3133                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
3134                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
3135                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
3136                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
3137                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
3138                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
3139                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
3140                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
3141                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
3142                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
3143                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
3144                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
3145                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
3146                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
3147                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
3148                 [CLKID_ACODEC]              = &gxl_acodec.hw,
3149                 [NR_CLKS]                   = NULL,
3150         },
3151         .num = NR_CLKS,
3152 };
3153
3154 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3155         &gxbb_clk81,
3156         &gxbb_ddr,
3157         &gxbb_dos,
3158         &gxbb_isa,
3159         &gxbb_pl301,
3160         &gxbb_periphs,
3161         &gxbb_spicc,
3162         &gxbb_i2c,
3163         &gxbb_sar_adc,
3164         &gxbb_smart_card,
3165         &gxbb_rng0,
3166         &gxbb_uart0,
3167         &gxbb_sdhc,
3168         &gxbb_stream,
3169         &gxbb_async_fifo,
3170         &gxbb_sdio,
3171         &gxbb_abuf,
3172         &gxbb_hiu_iface,
3173         &gxbb_assist_misc,
3174         &gxbb_spi,
3175         &gxbb_i2s_spdif,
3176         &gxbb_eth,
3177         &gxbb_demux,
3178         &gxbb_aiu_glue,
3179         &gxbb_iec958,
3180         &gxbb_i2s_out,
3181         &gxbb_amclk,
3182         &gxbb_aififo2,
3183         &gxbb_mixer,
3184         &gxbb_mixer_iface,
3185         &gxbb_adc,
3186         &gxbb_blkmv,
3187         &gxbb_aiu,
3188         &gxbb_uart1,
3189         &gxbb_g2d,
3190         &gxbb_usb0,
3191         &gxbb_usb1,
3192         &gxbb_reset,
3193         &gxbb_nand,
3194         &gxbb_dos_parser,
3195         &gxbb_usb,
3196         &gxbb_vdin1,
3197         &gxbb_ahb_arb0,
3198         &gxbb_efuse,
3199         &gxbb_boot_rom,
3200         &gxbb_ahb_data_bus,
3201         &gxbb_ahb_ctrl_bus,
3202         &gxbb_hdmi_intr_sync,
3203         &gxbb_hdmi_pclk,
3204         &gxbb_usb1_ddr_bridge,
3205         &gxbb_usb0_ddr_bridge,
3206         &gxbb_mmc_pclk,
3207         &gxbb_dvin,
3208         &gxbb_uart2,
3209         &gxbb_sana,
3210         &gxbb_vpu_intr,
3211         &gxbb_sec_ahb_ahb3_bridge,
3212         &gxbb_clk81_a53,
3213         &gxbb_vclk2_venci0,
3214         &gxbb_vclk2_venci1,
3215         &gxbb_vclk2_vencp0,
3216         &gxbb_vclk2_vencp1,
3217         &gxbb_gclk_venci_int0,
3218         &gxbb_gclk_vencp_int,
3219         &gxbb_dac_clk,
3220         &gxbb_aoclk_gate,
3221         &gxbb_iec958_gate,
3222         &gxbb_enc480p,
3223         &gxbb_rng1,
3224         &gxbb_gclk_venci_int1,
3225         &gxbb_vclk2_venclmcc,
3226         &gxbb_vclk2_vencl,
3227         &gxbb_vclk_other,
3228         &gxbb_edp,
3229         &gxbb_ao_media_cpu,
3230         &gxbb_ao_ahb_sram,
3231         &gxbb_ao_ahb_bus,
3232         &gxbb_ao_iface,
3233         &gxbb_ao_i2c,
3234         &gxbb_emmc_a,
3235         &gxbb_emmc_b,
3236         &gxbb_emmc_c,
3237         &gxbb_sar_adc_clk,
3238         &gxbb_mali_0,
3239         &gxbb_mali_1,
3240         &gxbb_cts_amclk,
3241         &gxbb_cts_mclk_i958,
3242         &gxbb_32k_clk,
3243         &gxbb_sd_emmc_a_clk0,
3244         &gxbb_sd_emmc_b_clk0,
3245         &gxbb_sd_emmc_c_clk0,
3246         &gxbb_vpu_0,
3247         &gxbb_vpu_1,
3248         &gxbb_vapb_0,
3249         &gxbb_vapb_1,
3250         &gxbb_vapb,
3251         &gxbb_mpeg_clk_div,
3252         &gxbb_sar_adc_clk_div,
3253         &gxbb_mali_0_div,
3254         &gxbb_mali_1_div,
3255         &gxbb_cts_mclk_i958_div,
3256         &gxbb_32k_clk_div,
3257         &gxbb_sd_emmc_a_clk0_div,
3258         &gxbb_sd_emmc_b_clk0_div,
3259         &gxbb_sd_emmc_c_clk0_div,
3260         &gxbb_vpu_0_div,
3261         &gxbb_vpu_1_div,
3262         &gxbb_vapb_0_div,
3263         &gxbb_vapb_1_div,
3264         &gxbb_mpeg_clk_sel,
3265         &gxbb_sar_adc_clk_sel,
3266         &gxbb_mali_0_sel,
3267         &gxbb_mali_1_sel,
3268         &gxbb_mali,
3269         &gxbb_cts_amclk_sel,
3270         &gxbb_cts_mclk_i958_sel,
3271         &gxbb_cts_i958,
3272         &gxbb_32k_clk_sel,
3273         &gxbb_sd_emmc_a_clk0_sel,
3274         &gxbb_sd_emmc_b_clk0_sel,
3275         &gxbb_sd_emmc_c_clk0_sel,
3276         &gxbb_vpu_0_sel,
3277         &gxbb_vpu_1_sel,
3278         &gxbb_vpu,
3279         &gxbb_vapb_0_sel,
3280         &gxbb_vapb_1_sel,
3281         &gxbb_vapb_sel,
3282         &gxbb_mpll0,
3283         &gxbb_mpll1,
3284         &gxbb_mpll2,
3285         &gxbb_mpll0_div,
3286         &gxbb_mpll1_div,
3287         &gxbb_mpll2_div,
3288         &gxbb_cts_amclk_div,
3289         &gxbb_fixed_pll,
3290         &gxbb_sys_pll,
3291         &gxbb_mpll_prediv,
3292         &gxbb_fclk_div2,
3293         &gxbb_fclk_div3,
3294         &gxbb_fclk_div4,
3295         &gxbb_fclk_div5,
3296         &gxbb_fclk_div7,
3297         &gxbb_vdec_1_sel,
3298         &gxbb_vdec_1_div,
3299         &gxbb_vdec_1,
3300         &gxbb_vdec_hevc_sel,
3301         &gxbb_vdec_hevc_div,
3302         &gxbb_vdec_hevc,
3303         &gxbb_gen_clk_sel,
3304         &gxbb_gen_clk_div,
3305         &gxbb_gen_clk,
3306         &gxbb_fixed_pll_dco,
3307         &gxbb_sys_pll_dco,
3308         &gxbb_gp0_pll,
3309         &gxbb_vid_pll,
3310         &gxbb_vid_pll_sel,
3311         &gxbb_vid_pll_div,
3312         &gxbb_vclk,
3313         &gxbb_vclk_sel,
3314         &gxbb_vclk_div,
3315         &gxbb_vclk_input,
3316         &gxbb_vclk_div1,
3317         &gxbb_vclk_div2_en,
3318         &gxbb_vclk_div4_en,
3319         &gxbb_vclk_div6_en,
3320         &gxbb_vclk_div12_en,
3321         &gxbb_vclk2,
3322         &gxbb_vclk2_sel,
3323         &gxbb_vclk2_div,
3324         &gxbb_vclk2_input,
3325         &gxbb_vclk2_div1,
3326         &gxbb_vclk2_div2_en,
3327         &gxbb_vclk2_div4_en,
3328         &gxbb_vclk2_div6_en,
3329         &gxbb_vclk2_div12_en,
3330         &gxbb_cts_enci,
3331         &gxbb_cts_enci_sel,
3332         &gxbb_cts_encp,
3333         &gxbb_cts_encp_sel,
3334         &gxbb_cts_vdac,
3335         &gxbb_cts_vdac_sel,
3336         &gxbb_hdmi_tx,
3337         &gxbb_hdmi_tx_sel,
3338         &gxbb_hdmi_sel,
3339         &gxbb_hdmi_div,
3340         &gxbb_hdmi,
3341         &gxbb_gp0_pll_dco,
3342         &gxbb_hdmi_pll,
3343         &gxbb_hdmi_pll_od,
3344         &gxbb_hdmi_pll_od2,
3345         &gxbb_hdmi_pll_dco,
3346 };
3347
3348 static struct clk_regmap *const gxl_clk_regmaps[] = {
3349         &gxbb_clk81,
3350         &gxbb_ddr,
3351         &gxbb_dos,
3352         &gxbb_isa,
3353         &gxbb_pl301,
3354         &gxbb_periphs,
3355         &gxbb_spicc,
3356         &gxbb_i2c,
3357         &gxbb_sar_adc,
3358         &gxbb_smart_card,
3359         &gxbb_rng0,
3360         &gxbb_uart0,
3361         &gxbb_sdhc,
3362         &gxbb_stream,
3363         &gxbb_async_fifo,
3364         &gxbb_sdio,
3365         &gxbb_abuf,
3366         &gxbb_hiu_iface,
3367         &gxbb_assist_misc,
3368         &gxbb_spi,
3369         &gxbb_i2s_spdif,
3370         &gxbb_eth,
3371         &gxbb_demux,
3372         &gxbb_aiu_glue,
3373         &gxbb_iec958,
3374         &gxbb_i2s_out,
3375         &gxbb_amclk,
3376         &gxbb_aififo2,
3377         &gxbb_mixer,
3378         &gxbb_mixer_iface,
3379         &gxbb_adc,
3380         &gxbb_blkmv,
3381         &gxbb_aiu,
3382         &gxbb_uart1,
3383         &gxbb_g2d,
3384         &gxbb_usb0,
3385         &gxbb_usb1,
3386         &gxbb_reset,
3387         &gxbb_nand,
3388         &gxbb_dos_parser,
3389         &gxbb_usb,
3390         &gxbb_vdin1,
3391         &gxbb_ahb_arb0,
3392         &gxbb_efuse,
3393         &gxbb_boot_rom,
3394         &gxbb_ahb_data_bus,
3395         &gxbb_ahb_ctrl_bus,
3396         &gxbb_hdmi_intr_sync,
3397         &gxbb_hdmi_pclk,
3398         &gxbb_usb1_ddr_bridge,
3399         &gxbb_usb0_ddr_bridge,
3400         &gxbb_mmc_pclk,
3401         &gxbb_dvin,
3402         &gxbb_uart2,
3403         &gxbb_sana,
3404         &gxbb_vpu_intr,
3405         &gxbb_sec_ahb_ahb3_bridge,
3406         &gxbb_clk81_a53,
3407         &gxbb_vclk2_venci0,
3408         &gxbb_vclk2_venci1,
3409         &gxbb_vclk2_vencp0,
3410         &gxbb_vclk2_vencp1,
3411         &gxbb_gclk_venci_int0,
3412         &gxbb_gclk_vencp_int,
3413         &gxbb_dac_clk,
3414         &gxbb_aoclk_gate,
3415         &gxbb_iec958_gate,
3416         &gxbb_enc480p,
3417         &gxbb_rng1,
3418         &gxbb_gclk_venci_int1,
3419         &gxbb_vclk2_venclmcc,
3420         &gxbb_vclk2_vencl,
3421         &gxbb_vclk_other,
3422         &gxbb_edp,
3423         &gxbb_ao_media_cpu,
3424         &gxbb_ao_ahb_sram,
3425         &gxbb_ao_ahb_bus,
3426         &gxbb_ao_iface,
3427         &gxbb_ao_i2c,
3428         &gxbb_emmc_a,
3429         &gxbb_emmc_b,
3430         &gxbb_emmc_c,
3431         &gxbb_sar_adc_clk,
3432         &gxbb_mali_0,
3433         &gxbb_mali_1,
3434         &gxbb_cts_amclk,
3435         &gxbb_cts_mclk_i958,
3436         &gxbb_32k_clk,
3437         &gxbb_sd_emmc_a_clk0,
3438         &gxbb_sd_emmc_b_clk0,
3439         &gxbb_sd_emmc_c_clk0,
3440         &gxbb_vpu_0,
3441         &gxbb_vpu_1,
3442         &gxbb_vapb_0,
3443         &gxbb_vapb_1,
3444         &gxbb_vapb,
3445         &gxbb_mpeg_clk_div,
3446         &gxbb_sar_adc_clk_div,
3447         &gxbb_mali_0_div,
3448         &gxbb_mali_1_div,
3449         &gxbb_cts_mclk_i958_div,
3450         &gxbb_32k_clk_div,
3451         &gxbb_sd_emmc_a_clk0_div,
3452         &gxbb_sd_emmc_b_clk0_div,
3453         &gxbb_sd_emmc_c_clk0_div,
3454         &gxbb_vpu_0_div,
3455         &gxbb_vpu_1_div,
3456         &gxbb_vapb_0_div,
3457         &gxbb_vapb_1_div,
3458         &gxbb_mpeg_clk_sel,
3459         &gxbb_sar_adc_clk_sel,
3460         &gxbb_mali_0_sel,
3461         &gxbb_mali_1_sel,
3462         &gxbb_mali,
3463         &gxbb_cts_amclk_sel,
3464         &gxbb_cts_mclk_i958_sel,
3465         &gxbb_cts_i958,
3466         &gxbb_32k_clk_sel,
3467         &gxbb_sd_emmc_a_clk0_sel,
3468         &gxbb_sd_emmc_b_clk0_sel,
3469         &gxbb_sd_emmc_c_clk0_sel,
3470         &gxbb_vpu_0_sel,
3471         &gxbb_vpu_1_sel,
3472         &gxbb_vpu,
3473         &gxbb_vapb_0_sel,
3474         &gxbb_vapb_1_sel,
3475         &gxbb_vapb_sel,
3476         &gxbb_mpll0,
3477         &gxbb_mpll1,
3478         &gxbb_mpll2,
3479         &gxl_mpll0_div,
3480         &gxbb_mpll1_div,
3481         &gxbb_mpll2_div,
3482         &gxbb_cts_amclk_div,
3483         &gxbb_fixed_pll,
3484         &gxbb_sys_pll,
3485         &gxbb_mpll_prediv,
3486         &gxbb_fclk_div2,
3487         &gxbb_fclk_div3,
3488         &gxbb_fclk_div4,
3489         &gxbb_fclk_div5,
3490         &gxbb_fclk_div7,
3491         &gxbb_vdec_1_sel,
3492         &gxbb_vdec_1_div,
3493         &gxbb_vdec_1,
3494         &gxbb_vdec_hevc_sel,
3495         &gxbb_vdec_hevc_div,
3496         &gxbb_vdec_hevc,
3497         &gxbb_gen_clk_sel,
3498         &gxbb_gen_clk_div,
3499         &gxbb_gen_clk,
3500         &gxbb_fixed_pll_dco,
3501         &gxbb_sys_pll_dco,
3502         &gxbb_gp0_pll,
3503         &gxbb_vid_pll,
3504         &gxbb_vid_pll_sel,
3505         &gxbb_vid_pll_div,
3506         &gxbb_vclk,
3507         &gxbb_vclk_sel,
3508         &gxbb_vclk_div,
3509         &gxbb_vclk_input,
3510         &gxbb_vclk_div1,
3511         &gxbb_vclk_div2_en,
3512         &gxbb_vclk_div4_en,
3513         &gxbb_vclk_div6_en,
3514         &gxbb_vclk_div12_en,
3515         &gxbb_vclk2,
3516         &gxbb_vclk2_sel,
3517         &gxbb_vclk2_div,
3518         &gxbb_vclk2_input,
3519         &gxbb_vclk2_div1,
3520         &gxbb_vclk2_div2_en,
3521         &gxbb_vclk2_div4_en,
3522         &gxbb_vclk2_div6_en,
3523         &gxbb_vclk2_div12_en,
3524         &gxbb_cts_enci,
3525         &gxbb_cts_enci_sel,
3526         &gxbb_cts_encp,
3527         &gxbb_cts_encp_sel,
3528         &gxbb_cts_vdac,
3529         &gxbb_cts_vdac_sel,
3530         &gxbb_hdmi_tx,
3531         &gxbb_hdmi_tx_sel,
3532         &gxbb_hdmi_sel,
3533         &gxbb_hdmi_div,
3534         &gxbb_hdmi,
3535         &gxl_gp0_pll_dco,
3536         &gxl_hdmi_pll,
3537         &gxl_hdmi_pll_od,
3538         &gxl_hdmi_pll_od2,
3539         &gxl_hdmi_pll_dco,
3540         &gxl_acodec,
3541 };
3542
3543 static const struct meson_eeclkc_data gxbb_clkc_data = {
3544         .regmap_clks = gxbb_clk_regmaps,
3545         .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3546         .hw_onecell_data = &gxbb_hw_onecell_data,
3547 };
3548
3549 static const struct meson_eeclkc_data gxl_clkc_data = {
3550         .regmap_clks = gxl_clk_regmaps,
3551         .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3552         .hw_onecell_data = &gxl_hw_onecell_data,
3553 };
3554
3555 static const struct of_device_id clkc_match_table[] = {
3556         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3557         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3558         {},
3559 };
3560
3561 static struct platform_driver gxbb_driver = {
3562         .probe          = meson_eeclkc_probe,
3563         .driver         = {
3564                 .name   = "gxbb-clkc",
3565                 .of_match_table = clkc_match_table,
3566         },
3567 };
3568
3569 builtin_platform_driver(gxbb_driver);