drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/init.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/module.h>
  12
  13 #include "gxbb.h"
  14 #include "clk-regmap.h"
  15 #include "clk-pll.h"
  16 #include "clk-mpll.h"
  17 #include "meson-eeclk.h"
  18 #include "vid-pll-div.h"
  19
  20 static DEFINE_SPINLOCK(meson_clk_lock);
  21
  22 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  23         PLL_PARAMS(32, 1),
  24         PLL_PARAMS(33, 1),
  25         PLL_PARAMS(34, 1),
  26         PLL_PARAMS(35, 1),
  27         PLL_PARAMS(36, 1),
  28         PLL_PARAMS(37, 1),
  29         PLL_PARAMS(38, 1),
  30         PLL_PARAMS(39, 1),
  31         PLL_PARAMS(40, 1),
  32         PLL_PARAMS(41, 1),
  33         PLL_PARAMS(42, 1),
  34         PLL_PARAMS(43, 1),
  35         PLL_PARAMS(44, 1),
  36         PLL_PARAMS(45, 1),
  37         PLL_PARAMS(46, 1),
  38         PLL_PARAMS(47, 1),
  39         PLL_PARAMS(48, 1),
  40         PLL_PARAMS(49, 1),
  41         PLL_PARAMS(50, 1),
  42         PLL_PARAMS(51, 1),
  43         PLL_PARAMS(52, 1),
  44         PLL_PARAMS(53, 1),
  45         PLL_PARAMS(54, 1),
  46         PLL_PARAMS(55, 1),
  47         PLL_PARAMS(56, 1),
  48         PLL_PARAMS(57, 1),
  49         PLL_PARAMS(58, 1),
  50         PLL_PARAMS(59, 1),
  51         PLL_PARAMS(60, 1),
  52         PLL_PARAMS(61, 1),
  53         PLL_PARAMS(62, 1),
  54         { /* sentinel */ },
  55 };
  56
  57 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  58         PLL_PARAMS(42, 1),
  59         PLL_PARAMS(43, 1),
  60         PLL_PARAMS(44, 1),
  61         PLL_PARAMS(45, 1),
  62         PLL_PARAMS(46, 1),
  63         PLL_PARAMS(47, 1),
  64         PLL_PARAMS(48, 1),
  65         PLL_PARAMS(49, 1),
  66         PLL_PARAMS(50, 1),
  67         PLL_PARAMS(51, 1),
  68         PLL_PARAMS(52, 1),
  69         PLL_PARAMS(53, 1),
  70         PLL_PARAMS(54, 1),
  71         PLL_PARAMS(55, 1),
  72         PLL_PARAMS(56, 1),
  73         PLL_PARAMS(57, 1),
  74         PLL_PARAMS(58, 1),
  75         PLL_PARAMS(59, 1),
  76         PLL_PARAMS(60, 1),
  77         PLL_PARAMS(61, 1),
  78         PLL_PARAMS(62, 1),
  79         PLL_PARAMS(63, 1),
  80         PLL_PARAMS(64, 1),
  81         PLL_PARAMS(65, 1),
  82         PLL_PARAMS(66, 1),
  83         { /* sentinel */ },
  84 };
  85
  86 static struct clk_regmap gxbb_fixed_pll_dco = {
  87         .data = &(struct meson_clk_pll_data){
  88                 .en = {
  89                         .reg_off = HHI_MPLL_CNTL,
  90                         .shift   = 30,
  91                         .width   = 1,
  92                 },
  93                 .m = {
  94                         .reg_off = HHI_MPLL_CNTL,
  95                         .shift   = 0,
  96                         .width   = 9,
  97                 },
  98                 .n = {
  99                         .reg_off = HHI_MPLL_CNTL,
 100                         .shift   = 9,
 101                         .width   = 5,
 102                 },
 103                 .frac = {
 104                         .reg_off = HHI_MPLL_CNTL2,
 105                         .shift   = 0,
 106                         .width   = 12,
 107                 },
 108                 .l = {
 109                         .reg_off = HHI_MPLL_CNTL,
 110                         .shift   = 31,
 111                         .width   = 1,
 112                 },
 113                 .rst = {
 114                         .reg_off = HHI_MPLL_CNTL,
 115                         .shift   = 29,
 116                         .width   = 1,
 117                 },
 118         },
 119         .hw.init = &(struct clk_init_data){
 120                 .name = "fixed_pll_dco",
 121                 .ops = &meson_clk_pll_ro_ops,
 122                 .parent_data = &(const struct clk_parent_data) {
 123                         .fw_name = "xtal",
 124                 },
 125                 .num_parents = 1,
 126         },
 127 };
 128
 129 static struct clk_regmap gxbb_fixed_pll = {
 130         .data = &(struct clk_regmap_div_data){
 131                 .offset = HHI_MPLL_CNTL,
 132                 .shift = 16,
 133                 .width = 2,
 134                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 135         },
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "fixed_pll",
 138                 .ops = &clk_regmap_divider_ro_ops,
 139                 .parent_hws = (const struct clk_hw *[]) {
 140                         &gxbb_fixed_pll_dco.hw
 141                 },
 142                 .num_parents = 1,
 143                 /*
 144                  * This clock won't ever change at runtime so
 145                  * CLK_SET_RATE_PARENT is not required
 146                  */
 147         },
 148 };
 149
 150 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 151         .mult = 2,
 152         .div = 1,
 153         .hw.init = &(struct clk_init_data){
 154                 .name = "hdmi_pll_pre_mult",
 155                 .ops = &clk_fixed_factor_ops,
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xtal",
 158                 },
 159                 .num_parents = 1,
 160         },
 161 };
 162
 163 static struct clk_regmap gxbb_hdmi_pll_dco = {
 164         .data = &(struct meson_clk_pll_data){
 165                 .en = {
 166                         .reg_off = HHI_HDMI_PLL_CNTL,
 167                         .shift   = 30,
 168                         .width   = 1,
 169                 },
 170                 .m = {
 171                         .reg_off = HHI_HDMI_PLL_CNTL,
 172                         .shift   = 0,
 173                         .width   = 9,
 174                 },
 175                 .n = {
 176                         .reg_off = HHI_HDMI_PLL_CNTL,
 177                         .shift   = 9,
 178                         .width   = 5,
 179                 },
 180                 .frac = {
 181                         .reg_off = HHI_HDMI_PLL_CNTL2,
 182                         .shift   = 0,
 183                         .width   = 12,
 184                 },
 185                 .l = {
 186                         .reg_off = HHI_HDMI_PLL_CNTL,
 187                         .shift   = 31,
 188                         .width   = 1,
 189                 },
 190                 .rst = {
 191                         .reg_off = HHI_HDMI_PLL_CNTL,
 192                         .shift   = 28,
 193                         .width   = 1,
 194                 },
 195         },
 196         .hw.init = &(struct clk_init_data){
 197                 .name = "hdmi_pll_dco",
 198                 .ops = &meson_clk_pll_ro_ops,
 199                 .parent_hws = (const struct clk_hw *[]) {
 200                         &gxbb_hdmi_pll_pre_mult.hw
 201                 },
 202                 .num_parents = 1,
 203                 /*
 204                  * Display directly handle hdmi pll registers ATM, we need
 205                  * NOCACHE to keep our view of the clock as accurate as possible
 206                  */
 207                 .flags = CLK_GET_RATE_NOCACHE,
 208         },
 209 };
 210
 211 static struct clk_regmap gxl_hdmi_pll_dco = {
 212         .data = &(struct meson_clk_pll_data){
 213                 .en = {
 214                         .reg_off = HHI_HDMI_PLL_CNTL,
 215                         .shift   = 30,
 216                         .width   = 1,
 217                 },
 218                 .m = {
 219                         .reg_off = HHI_HDMI_PLL_CNTL,
 220                         .shift   = 0,
 221                         .width   = 9,
 222                 },
 223                 .n = {
 224                         .reg_off = HHI_HDMI_PLL_CNTL,
 225                         .shift   = 9,
 226                         .width   = 5,
 227                 },
 228                 /*
 229                  * On gxl, there is a register shift due to
 230                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 231                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 232                  * instead which is defined at the same offset.
 233                  */
 234                 .frac = {
 235                         .reg_off = HHI_HDMI_PLL_CNTL2,
 236                         .shift   = 0,
 237                         .width   = 10,
 238                 },
 239                 .l = {
 240                         .reg_off = HHI_HDMI_PLL_CNTL,
 241                         .shift   = 31,
 242                         .width   = 1,
 243                 },
 244                 .rst = {
 245                         .reg_off = HHI_HDMI_PLL_CNTL,
 246                         .shift   = 28,
 247                         .width   = 1,
 248                 },
 249         },
 250         .hw.init = &(struct clk_init_data){
 251                 .name = "hdmi_pll_dco",
 252                 .ops = &meson_clk_pll_ro_ops,
 253                 .parent_data = &(const struct clk_parent_data) {
 254                         .fw_name = "xtal",
 255                 },
 256                 .num_parents = 1,
 257                 /*
 258                  * Display directly handle hdmi pll registers ATM, we need
 259                  * NOCACHE to keep our view of the clock as accurate as possible
 260                  */
 261                 .flags = CLK_GET_RATE_NOCACHE,
 262         },
 263 };
 264
 265 static struct clk_regmap gxbb_hdmi_pll_od = {
 266         .data = &(struct clk_regmap_div_data){
 267                 .offset = HHI_HDMI_PLL_CNTL2,
 268                 .shift = 16,
 269                 .width = 2,
 270                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 271         },
 272         .hw.init = &(struct clk_init_data){
 273                 .name = "hdmi_pll_od",
 274                 .ops = &clk_regmap_divider_ro_ops,
 275                 .parent_hws = (const struct clk_hw *[]) {
 276                         &gxbb_hdmi_pll_dco.hw
 277                 },
 278                 .num_parents = 1,
 279                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 280         },
 281 };
 282
 283 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 284         .data = &(struct clk_regmap_div_data){
 285                 .offset = HHI_HDMI_PLL_CNTL2,
 286                 .shift = 22,
 287                 .width = 2,
 288                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 289         },
 290         .hw.init = &(struct clk_init_data){
 291                 .name = "hdmi_pll_od2",
 292                 .ops = &clk_regmap_divider_ro_ops,
 293                 .parent_hws = (const struct clk_hw *[]) {
 294                         &gxbb_hdmi_pll_od.hw
 295                 },
 296                 .num_parents = 1,
 297                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 298         },
 299 };
 300
 301 static struct clk_regmap gxbb_hdmi_pll = {
 302         .data = &(struct clk_regmap_div_data){
 303                 .offset = HHI_HDMI_PLL_CNTL2,
 304                 .shift = 18,
 305                 .width = 2,
 306                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 307         },
 308         .hw.init = &(struct clk_init_data){
 309                 .name = "hdmi_pll",
 310                 .ops = &clk_regmap_divider_ro_ops,
 311                 .parent_hws = (const struct clk_hw *[]) {
 312                         &gxbb_hdmi_pll_od2.hw
 313                 },
 314                 .num_parents = 1,
 315                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 316         },
 317 };
 318
 319 static struct clk_regmap gxl_hdmi_pll_od = {
 320         .data = &(struct clk_regmap_div_data){
 321                 .offset = HHI_HDMI_PLL_CNTL + 8,
 322                 .shift = 21,
 323                 .width = 2,
 324                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 325         },
 326         .hw.init = &(struct clk_init_data){
 327                 .name = "hdmi_pll_od",
 328                 .ops = &clk_regmap_divider_ro_ops,
 329                 .parent_hws = (const struct clk_hw *[]) {
 330                         &gxl_hdmi_pll_dco.hw
 331                 },
 332                 .num_parents = 1,
 333                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 334         },
 335 };
 336
 337 static struct clk_regmap gxl_hdmi_pll_od2 = {
 338         .data = &(struct clk_regmap_div_data){
 339                 .offset = HHI_HDMI_PLL_CNTL + 8,
 340                 .shift = 23,
 341                 .width = 2,
 342                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 343         },
 344         .hw.init = &(struct clk_init_data){
 345                 .name = "hdmi_pll_od2",
 346                 .ops = &clk_regmap_divider_ro_ops,
 347                 .parent_hws = (const struct clk_hw *[]) {
 348                         &gxl_hdmi_pll_od.hw
 349                 },
 350                 .num_parents = 1,
 351                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 352         },
 353 };
 354
 355 static struct clk_regmap gxl_hdmi_pll = {
 356         .data = &(struct clk_regmap_div_data){
 357                 .offset = HHI_HDMI_PLL_CNTL + 8,
 358                 .shift = 19,
 359                 .width = 2,
 360                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 361         },
 362         .hw.init = &(struct clk_init_data){
 363                 .name = "hdmi_pll",
 364                 .ops = &clk_regmap_divider_ro_ops,
 365                 .parent_hws = (const struct clk_hw *[]) {
 366                         &gxl_hdmi_pll_od2.hw
 367                 },
 368                 .num_parents = 1,
 369                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 370         },
 371 };
 372
 373 static struct clk_regmap gxbb_sys_pll_dco = {
 374         .data = &(struct meson_clk_pll_data){
 375                 .en = {
 376                         .reg_off = HHI_SYS_PLL_CNTL,
 377                         .shift   = 30,
 378                         .width   = 1,
 379                 },
 380                 .m = {
 381                         .reg_off = HHI_SYS_PLL_CNTL,
 382                         .shift   = 0,
 383                         .width   = 9,
 384                 },
 385                 .n = {
 386                         .reg_off = HHI_SYS_PLL_CNTL,
 387                         .shift   = 9,
 388                         .width   = 5,
 389                 },
 390                 .l = {
 391                         .reg_off = HHI_SYS_PLL_CNTL,
 392                         .shift   = 31,
 393                         .width   = 1,
 394                 },
 395                 .rst = {
 396                         .reg_off = HHI_SYS_PLL_CNTL,
 397                         .shift   = 29,
 398                         .width   = 1,
 399                 },
 400         },
 401         .hw.init = &(struct clk_init_data){
 402                 .name = "sys_pll_dco",
 403                 .ops = &meson_clk_pll_ro_ops,
 404                 .parent_data = &(const struct clk_parent_data) {
 405                         .fw_name = "xtal",
 406                 },
 407                 .num_parents = 1,
 408         },
 409 };
 410
 411 static struct clk_regmap gxbb_sys_pll = {
 412         .data = &(struct clk_regmap_div_data){
 413                 .offset = HHI_SYS_PLL_CNTL,
 414                 .shift = 10,
 415                 .width = 2,
 416                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 417         },
 418         .hw.init = &(struct clk_init_data){
 419                 .name = "sys_pll",
 420                 .ops = &clk_regmap_divider_ro_ops,
 421                 .parent_hws = (const struct clk_hw *[]) {
 422                         &gxbb_sys_pll_dco.hw
 423                 },
 424                 .num_parents = 1,
 425                 .flags = CLK_SET_RATE_PARENT,
 426         },
 427 };
 428
 429 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 430         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 431         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 432         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 433 };
 434
 435 static struct clk_regmap gxbb_gp0_pll_dco = {
 436         .data = &(struct meson_clk_pll_data){
 437                 .en = {
 438                         .reg_off = HHI_GP0_PLL_CNTL,
 439                         .shift   = 30,
 440                         .width   = 1,
 441                 },
 442                 .m = {
 443                         .reg_off = HHI_GP0_PLL_CNTL,
 444                         .shift   = 0,
 445                         .width   = 9,
 446                 },
 447                 .n = {
 448                         .reg_off = HHI_GP0_PLL_CNTL,
 449                         .shift   = 9,
 450                         .width   = 5,
 451                 },
 452                 .l = {
 453                         .reg_off = HHI_GP0_PLL_CNTL,
 454                         .shift   = 31,
 455                         .width   = 1,
 456                 },
 457                 .rst = {
 458                         .reg_off = HHI_GP0_PLL_CNTL,
 459                         .shift   = 29,
 460                         .width   = 1,
 461                 },
 462                 .table = gxbb_gp0_pll_params_table,
 463                 .init_regs = gxbb_gp0_init_regs,
 464                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 465         },
 466         .hw.init = &(struct clk_init_data){
 467                 .name = "gp0_pll_dco",
 468                 .ops = &meson_clk_pll_ops,
 469                 .parent_data = &(const struct clk_parent_data) {
 470                         .fw_name = "xtal",
 471                 },
 472                 .num_parents = 1,
 473         },
 474 };
 475
 476 static const struct reg_sequence gxl_gp0_init_regs[] = {
 477         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 478         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 479         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 480         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 481         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 482 };
 483
 484 static struct clk_regmap gxl_gp0_pll_dco = {
 485         .data = &(struct meson_clk_pll_data){
 486                 .en = {
 487                         .reg_off = HHI_GP0_PLL_CNTL,
 488                         .shift   = 30,
 489                         .width   = 1,
 490                 },
 491                 .m = {
 492                         .reg_off = HHI_GP0_PLL_CNTL,
 493                         .shift   = 0,
 494                         .width   = 9,
 495                 },
 496                 .n = {
 497                         .reg_off = HHI_GP0_PLL_CNTL,
 498                         .shift   = 9,
 499                         .width   = 5,
 500                 },
 501                 .frac = {
 502                         .reg_off = HHI_GP0_PLL_CNTL1,
 503                         .shift   = 0,
 504                         .width   = 10,
 505                 },
 506                 .l = {
 507                         .reg_off = HHI_GP0_PLL_CNTL,
 508                         .shift   = 31,
 509                         .width   = 1,
 510                 },
 511                 .rst = {
 512                         .reg_off = HHI_GP0_PLL_CNTL,
 513                         .shift   = 29,
 514                         .width   = 1,
 515                 },
 516                 .table = gxl_gp0_pll_params_table,
 517                 .init_regs = gxl_gp0_init_regs,
 518                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 519         },
 520         .hw.init = &(struct clk_init_data){
 521                 .name = "gp0_pll_dco",
 522                 .ops = &meson_clk_pll_ops,
 523                 .parent_data = &(const struct clk_parent_data) {
 524                         .fw_name = "xtal",
 525                 },
 526                 .num_parents = 1,
 527         },
 528 };
 529
 530 static struct clk_regmap gxbb_gp0_pll = {
 531         .data = &(struct clk_regmap_div_data){
 532                 .offset = HHI_GP0_PLL_CNTL,
 533                 .shift = 16,
 534                 .width = 2,
 535                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 536         },
 537         .hw.init = &(struct clk_init_data){
 538                 .name = "gp0_pll",
 539                 .ops = &clk_regmap_divider_ops,
 540                 .parent_data = &(const struct clk_parent_data) {
 541                         /*
 542                          * Note:
 543                          * GXL and GXBB have different gp0_pll_dco (with
 544                          * different struct clk_hw). We fallback to the global
 545                          * naming string mechanism so gp0_pll picks up the
 546                          * appropriate one.
 547                          */
 548                         .name = "gp0_pll_dco",
 549                         .index = -1,
 550                 },
 551                 .num_parents = 1,
 552                 .flags = CLK_SET_RATE_PARENT,
 553         },
 554 };
 555
 556 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 557         .mult = 1,
 558         .div = 2,
 559         .hw.init = &(struct clk_init_data){
 560                 .name = "fclk_div2_div",
 561                 .ops = &clk_fixed_factor_ops,
 562                 .parent_hws = (const struct clk_hw *[]) {
 563                         &gxbb_fixed_pll.hw
 564                 },
 565                 .num_parents = 1,
 566         },
 567 };
 568
 569 static struct clk_regmap gxbb_fclk_div2 = {
 570         .data = &(struct clk_regmap_gate_data){
 571                 .offset = HHI_MPLL_CNTL6,
 572                 .bit_idx = 27,
 573         },
 574         .hw.init = &(struct clk_init_data){
 575                 .name = "fclk_div2",
 576                 .ops = &clk_regmap_gate_ops,
 577                 .parent_hws = (const struct clk_hw *[]) {
 578                         &gxbb_fclk_div2_div.hw
 579                 },
 580                 .num_parents = 1,
 581                 .flags = CLK_IS_CRITICAL,
 582         },
 583 };
 584
 585 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 586         .mult = 1,
 587         .div = 3,
 588         .hw.init = &(struct clk_init_data){
 589                 .name = "fclk_div3_div",
 590                 .ops = &clk_fixed_factor_ops,
 591                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 592                 .num_parents = 1,
 593         },
 594 };
 595
 596 static struct clk_regmap gxbb_fclk_div3 = {
 597         .data = &(struct clk_regmap_gate_data){
 598                 .offset = HHI_MPLL_CNTL6,
 599                 .bit_idx = 28,
 600         },
 601         .hw.init = &(struct clk_init_data){
 602                 .name = "fclk_div3",
 603                 .ops = &clk_regmap_gate_ops,
 604                 .parent_hws = (const struct clk_hw *[]) {
 605                         &gxbb_fclk_div3_div.hw
 606                 },
 607                 .num_parents = 1,
 608                 /*
 609                  * FIXME:
 610                  * This clock, as fdiv2, is used by the SCPI FW and is required
 611                  * by the platform to operate correctly.
 612                  * Until the following condition are met, we need this clock to
 613                  * be marked as critical:
 614                  * a) The SCPI generic driver claims and enable all the clocks
 615                  *    it needs
 616                  * b) CCF has a clock hand-off mechanism to make the sure the
 617                  *    clock stays on until the proper driver comes along
 618                  */
 619                 .flags = CLK_IS_CRITICAL,
 620         },
 621 };
 622
 623 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 624         .mult = 1,
 625         .div = 4,
 626         .hw.init = &(struct clk_init_data){
 627                 .name = "fclk_div4_div",
 628                 .ops = &clk_fixed_factor_ops,
 629                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 630                 .num_parents = 1,
 631         },
 632 };
 633
 634 static struct clk_regmap gxbb_fclk_div4 = {
 635         .data = &(struct clk_regmap_gate_data){
 636                 .offset = HHI_MPLL_CNTL6,
 637                 .bit_idx = 29,
 638         },
 639         .hw.init = &(struct clk_init_data){
 640                 .name = "fclk_div4",
 641                 .ops = &clk_regmap_gate_ops,
 642                 .parent_hws = (const struct clk_hw *[]) {
 643                         &gxbb_fclk_div4_div.hw
 644                 },
 645                 .num_parents = 1,
 646         },
 647 };
 648
 649 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 650         .mult = 1,
 651         .div = 5,
 652         .hw.init = &(struct clk_init_data){
 653                 .name = "fclk_div5_div",
 654                 .ops = &clk_fixed_factor_ops,
 655                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 656                 .num_parents = 1,
 657         },
 658 };
 659
 660 static struct clk_regmap gxbb_fclk_div5 = {
 661         .data = &(struct clk_regmap_gate_data){
 662                 .offset = HHI_MPLL_CNTL6,
 663                 .bit_idx = 30,
 664         },
 665         .hw.init = &(struct clk_init_data){
 666                 .name = "fclk_div5",
 667                 .ops = &clk_regmap_gate_ops,
 668                 .parent_hws = (const struct clk_hw *[]) {
 669                         &gxbb_fclk_div5_div.hw
 670                 },
 671                 .num_parents = 1,
 672         },
 673 };
 674
 675 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 676         .mult = 1,
 677         .div = 7,
 678         .hw.init = &(struct clk_init_data){
 679                 .name = "fclk_div7_div",
 680                 .ops = &clk_fixed_factor_ops,
 681                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 682                 .num_parents = 1,
 683         },
 684 };
 685
 686 static struct clk_regmap gxbb_fclk_div7 = {
 687         .data = &(struct clk_regmap_gate_data){
 688                 .offset = HHI_MPLL_CNTL6,
 689                 .bit_idx = 31,
 690         },
 691         .hw.init = &(struct clk_init_data){
 692                 .name = "fclk_div7",
 693                 .ops = &clk_regmap_gate_ops,
 694                 .parent_hws = (const struct clk_hw *[]) {
 695                         &gxbb_fclk_div7_div.hw
 696                 },
 697                 .num_parents = 1,
 698         },
 699 };
 700
 701 static struct clk_regmap gxbb_mpll_prediv = {
 702         .data = &(struct clk_regmap_div_data){
 703                 .offset = HHI_MPLL_CNTL5,
 704                 .shift = 12,
 705                 .width = 1,
 706         },
 707         .hw.init = &(struct clk_init_data){
 708                 .name = "mpll_prediv",
 709                 .ops = &clk_regmap_divider_ro_ops,
 710                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 711                 .num_parents = 1,
 712         },
 713 };
 714
 715 static struct clk_regmap gxbb_mpll0_div = {
 716         .data = &(struct meson_clk_mpll_data){
 717                 .sdm = {
 718                         .reg_off = HHI_MPLL_CNTL7,
 719                         .shift   = 0,
 720                         .width   = 14,
 721                 },
 722                 .sdm_en = {
 723                         .reg_off = HHI_MPLL_CNTL,
 724                         .shift   = 25,
 725                         .width   = 1,
 726                 },
 727                 .n2 = {
 728                         .reg_off = HHI_MPLL_CNTL7,
 729                         .shift   = 16,
 730                         .width   = 9,
 731                 },
 732                 .lock = &meson_clk_lock,
 733         },
 734         .hw.init = &(struct clk_init_data){
 735                 .name = "mpll0_div",
 736                 .ops = &meson_clk_mpll_ops,
 737                 .parent_hws = (const struct clk_hw *[]) {
 738                         &gxbb_mpll_prediv.hw
 739                 },
 740                 .num_parents = 1,
 741         },
 742 };
 743
 744 static struct clk_regmap gxl_mpll0_div = {
 745         .data = &(struct meson_clk_mpll_data){
 746                 .sdm = {
 747                         .reg_off = HHI_MPLL_CNTL7,
 748                         .shift   = 0,
 749                         .width   = 14,
 750                 },
 751                 .sdm_en = {
 752                         .reg_off = HHI_MPLL_CNTL7,
 753                         .shift   = 15,
 754                         .width   = 1,
 755                 },
 756                 .n2 = {
 757                         .reg_off = HHI_MPLL_CNTL7,
 758                         .shift   = 16,
 759                         .width   = 9,
 760                 },
 761                 .lock = &meson_clk_lock,
 762         },
 763         .hw.init = &(struct clk_init_data){
 764                 .name = "mpll0_div",
 765                 .ops = &meson_clk_mpll_ops,
 766                 .parent_hws = (const struct clk_hw *[]) {
 767                         &gxbb_mpll_prediv.hw
 768                 },
 769                 .num_parents = 1,
 770         },
 771 };
 772
 773 static struct clk_regmap gxbb_mpll0 = {
 774         .data = &(struct clk_regmap_gate_data){
 775                 .offset = HHI_MPLL_CNTL7,
 776                 .bit_idx = 14,
 777         },
 778         .hw.init = &(struct clk_init_data){
 779                 .name = "mpll0",
 780                 .ops = &clk_regmap_gate_ops,
 781                 .parent_data = &(const struct clk_parent_data) {
 782                         /*
 783                          * Note:
 784                          * GXL and GXBB have different SDM_EN registers. We
 785                          * fallback to the global naming string mechanism so
 786                          * mpll0_div picks up the appropriate one.
 787                          */
 788                         .name = "mpll0_div",
 789                         .index = -1,
 790                 },
 791                 .num_parents = 1,
 792                 .flags = CLK_SET_RATE_PARENT,
 793         },
 794 };
 795
 796 static struct clk_regmap gxbb_mpll1_div = {
 797         .data = &(struct meson_clk_mpll_data){
 798                 .sdm = {
 799                         .reg_off = HHI_MPLL_CNTL8,
 800                         .shift   = 0,
 801                         .width   = 14,
 802                 },
 803                 .sdm_en = {
 804                         .reg_off = HHI_MPLL_CNTL8,
 805                         .shift   = 15,
 806                         .width   = 1,
 807                 },
 808                 .n2 = {
 809                         .reg_off = HHI_MPLL_CNTL8,
 810                         .shift   = 16,
 811                         .width   = 9,
 812                 },
 813                 .lock = &meson_clk_lock,
 814         },
 815         .hw.init = &(struct clk_init_data){
 816                 .name = "mpll1_div",
 817                 .ops = &meson_clk_mpll_ops,
 818                 .parent_hws = (const struct clk_hw *[]) {
 819                         &gxbb_mpll_prediv.hw
 820                 },
 821                 .num_parents = 1,
 822         },
 823 };
 824
 825 static struct clk_regmap gxbb_mpll1 = {
 826         .data = &(struct clk_regmap_gate_data){
 827                 .offset = HHI_MPLL_CNTL8,
 828                 .bit_idx = 14,
 829         },
 830         .hw.init = &(struct clk_init_data){
 831                 .name = "mpll1",
 832                 .ops = &clk_regmap_gate_ops,
 833                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
 834                 .num_parents = 1,
 835                 .flags = CLK_SET_RATE_PARENT,
 836         },
 837 };
 838
 839 static struct clk_regmap gxbb_mpll2_div = {
 840         .data = &(struct meson_clk_mpll_data){
 841                 .sdm = {
 842                         .reg_off = HHI_MPLL_CNTL9,
 843                         .shift   = 0,
 844                         .width   = 14,
 845                 },
 846                 .sdm_en = {
 847                         .reg_off = HHI_MPLL_CNTL9,
 848                         .shift   = 15,
 849                         .width   = 1,
 850                 },
 851                 .n2 = {
 852                         .reg_off = HHI_MPLL_CNTL9,
 853                         .shift   = 16,
 854                         .width   = 9,
 855                 },
 856                 .lock = &meson_clk_lock,
 857         },
 858         .hw.init = &(struct clk_init_data){
 859                 .name = "mpll2_div",
 860                 .ops = &meson_clk_mpll_ops,
 861                 .parent_hws = (const struct clk_hw *[]) {
 862                         &gxbb_mpll_prediv.hw
 863                 },
 864                 .num_parents = 1,
 865         },
 866 };
 867
 868 static struct clk_regmap gxbb_mpll2 = {
 869         .data = &(struct clk_regmap_gate_data){
 870                 .offset = HHI_MPLL_CNTL9,
 871                 .bit_idx = 14,
 872         },
 873         .hw.init = &(struct clk_init_data){
 874                 .name = "mpll2",
 875                 .ops = &clk_regmap_gate_ops,
 876                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
 877                 .num_parents = 1,
 878                 .flags = CLK_SET_RATE_PARENT,
 879         },
 880 };
 881
 882 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 883 static const struct clk_parent_data clk81_parent_data[] = {
 884         { .fw_name = "xtal", },
 885         { .hw = &gxbb_fclk_div7.hw },
 886         { .hw = &gxbb_mpll1.hw },
 887         { .hw = &gxbb_mpll2.hw },
 888         { .hw = &gxbb_fclk_div4.hw },
 889         { .hw = &gxbb_fclk_div3.hw },
 890         { .hw = &gxbb_fclk_div5.hw },
 891 };
 892
 893 static struct clk_regmap gxbb_mpeg_clk_sel = {
 894         .data = &(struct clk_regmap_mux_data){
 895                 .offset = HHI_MPEG_CLK_CNTL,
 896                 .mask = 0x7,
 897                 .shift = 12,
 898                 .table = mux_table_clk81,
 899         },
 900         .hw.init = &(struct clk_init_data){
 901                 .name = "mpeg_clk_sel",
 902                 .ops = &clk_regmap_mux_ro_ops,
 903                 /*
 904                  * bits 14:12 selects from 8 possible parents:
 905                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 906                  * fclk_div4, fclk_div3, fclk_div5
 907                  */
 908                 .parent_data = clk81_parent_data,
 909                 .num_parents = ARRAY_SIZE(clk81_parent_data),
 910         },
 911 };
 912
 913 static struct clk_regmap gxbb_mpeg_clk_div = {
 914         .data = &(struct clk_regmap_div_data){
 915                 .offset = HHI_MPEG_CLK_CNTL,
 916                 .shift = 0,
 917                 .width = 7,
 918         },
 919         .hw.init = &(struct clk_init_data){
 920                 .name = "mpeg_clk_div",
 921                 .ops = &clk_regmap_divider_ro_ops,
 922                 .parent_hws = (const struct clk_hw *[]) {
 923                         &gxbb_mpeg_clk_sel.hw
 924                 },
 925                 .num_parents = 1,
 926         },
 927 };
 928
 929 /* the mother of dragons gates */
 930 static struct clk_regmap gxbb_clk81 = {
 931         .data = &(struct clk_regmap_gate_data){
 932                 .offset = HHI_MPEG_CLK_CNTL,
 933                 .bit_idx = 7,
 934         },
 935         .hw.init = &(struct clk_init_data){
 936                 .name = "clk81",
 937                 .ops = &clk_regmap_gate_ops,
 938                 .parent_hws = (const struct clk_hw *[]) {
 939                         &gxbb_mpeg_clk_div.hw
 940                 },
 941                 .num_parents = 1,
 942                 .flags = CLK_IS_CRITICAL,
 943         },
 944 };
 945
 946 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 947         .data = &(struct clk_regmap_mux_data){
 948                 .offset = HHI_SAR_CLK_CNTL,
 949                 .mask = 0x3,
 950                 .shift = 9,
 951         },
 952         .hw.init = &(struct clk_init_data){
 953                 .name = "sar_adc_clk_sel",
 954                 .ops = &clk_regmap_mux_ops,
 955                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 956                 .parent_data = (const struct clk_parent_data []) {
 957                         { .fw_name = "xtal", },
 958                         { .hw = &gxbb_clk81.hw },
 959                 },
 960                 .num_parents = 2,
 961         },
 962 };
 963
 964 static struct clk_regmap gxbb_sar_adc_clk_div = {
 965         .data = &(struct clk_regmap_div_data){
 966                 .offset = HHI_SAR_CLK_CNTL,
 967                 .shift = 0,
 968                 .width = 8,
 969         },
 970         .hw.init = &(struct clk_init_data){
 971                 .name = "sar_adc_clk_div",
 972                 .ops = &clk_regmap_divider_ops,
 973                 .parent_hws = (const struct clk_hw *[]) {
 974                         &gxbb_sar_adc_clk_sel.hw
 975                 },
 976                 .num_parents = 1,
 977                 .flags = CLK_SET_RATE_PARENT,
 978         },
 979 };
 980
 981 static struct clk_regmap gxbb_sar_adc_clk = {
 982         .data = &(struct clk_regmap_gate_data){
 983                 .offset = HHI_SAR_CLK_CNTL,
 984                 .bit_idx = 8,
 985         },
 986         .hw.init = &(struct clk_init_data){
 987                 .name = "sar_adc_clk",
 988                 .ops = &clk_regmap_gate_ops,
 989                 .parent_hws = (const struct clk_hw *[]) {
 990                         &gxbb_sar_adc_clk_div.hw
 991                 },
 992                 .num_parents = 1,
 993                 .flags = CLK_SET_RATE_PARENT,
 994         },
 995 };
 996
 997 /*
 998  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 999  * muxed by a glitch-free switch. The CCF can manage this glitch-free
1000  * mux because it does top-to-bottom updates the each clock tree and
1001  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1002  */
1003
1004 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
1005         { .fw_name = "xtal", },
1006         { .hw = &gxbb_gp0_pll.hw },
1007         { .hw = &gxbb_mpll2.hw },
1008         { .hw = &gxbb_mpll1.hw },
1009         { .hw = &gxbb_fclk_div7.hw },
1010         { .hw = &gxbb_fclk_div4.hw },
1011         { .hw = &gxbb_fclk_div3.hw },
1012         { .hw = &gxbb_fclk_div5.hw },
1013 };
1014
1015 static struct clk_regmap gxbb_mali_0_sel = {
1016         .data = &(struct clk_regmap_mux_data){
1017                 .offset = HHI_MALI_CLK_CNTL,
1018                 .mask = 0x7,
1019                 .shift = 9,
1020         },
1021         .hw.init = &(struct clk_init_data){
1022                 .name = "mali_0_sel",
1023                 .ops = &clk_regmap_mux_ops,
1024                 .parent_data = gxbb_mali_0_1_parent_data,
1025                 .num_parents = 8,
1026                 /*
1027                  * Don't request the parent to change the rate because
1028                  * all GPU frequencies can be derived from the fclk_*
1029                  * clocks and one special GP0_PLL setting. This is
1030                  * important because we need the MPLL clocks for audio.
1031                  */
1032                 .flags = 0,
1033         },
1034 };
1035
1036 static struct clk_regmap gxbb_mali_0_div = {
1037         .data = &(struct clk_regmap_div_data){
1038                 .offset = HHI_MALI_CLK_CNTL,
1039                 .shift = 0,
1040                 .width = 7,
1041         },
1042         .hw.init = &(struct clk_init_data){
1043                 .name = "mali_0_div",
1044                 .ops = &clk_regmap_divider_ops,
1045                 .parent_hws = (const struct clk_hw *[]) {
1046                         &gxbb_mali_0_sel.hw
1047                 },
1048                 .num_parents = 1,
1049                 .flags = CLK_SET_RATE_PARENT,
1050         },
1051 };
1052
1053 static struct clk_regmap gxbb_mali_0 = {
1054         .data = &(struct clk_regmap_gate_data){
1055                 .offset = HHI_MALI_CLK_CNTL,
1056                 .bit_idx = 8,
1057         },
1058         .hw.init = &(struct clk_init_data){
1059                 .name = "mali_0",
1060                 .ops = &clk_regmap_gate_ops,
1061                 .parent_hws = (const struct clk_hw *[]) {
1062                         &gxbb_mali_0_div.hw
1063                 },
1064                 .num_parents = 1,
1065                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1066         },
1067 };
1068
1069 static struct clk_regmap gxbb_mali_1_sel = {
1070         .data = &(struct clk_regmap_mux_data){
1071                 .offset = HHI_MALI_CLK_CNTL,
1072                 .mask = 0x7,
1073                 .shift = 25,
1074         },
1075         .hw.init = &(struct clk_init_data){
1076                 .name = "mali_1_sel",
1077                 .ops = &clk_regmap_mux_ops,
1078                 .parent_data = gxbb_mali_0_1_parent_data,
1079                 .num_parents = 8,
1080                 /*
1081                  * Don't request the parent to change the rate because
1082                  * all GPU frequencies can be derived from the fclk_*
1083                  * clocks and one special GP0_PLL setting. This is
1084                  * important because we need the MPLL clocks for audio.
1085                  */
1086                 .flags = 0,
1087         },
1088 };
1089
1090 static struct clk_regmap gxbb_mali_1_div = {
1091         .data = &(struct clk_regmap_div_data){
1092                 .offset = HHI_MALI_CLK_CNTL,
1093                 .shift = 16,
1094                 .width = 7,
1095         },
1096         .hw.init = &(struct clk_init_data){
1097                 .name = "mali_1_div",
1098                 .ops = &clk_regmap_divider_ops,
1099                 .parent_hws = (const struct clk_hw *[]) {
1100                         &gxbb_mali_1_sel.hw
1101                 },
1102                 .num_parents = 1,
1103                 .flags = CLK_SET_RATE_PARENT,
1104         },
1105 };
1106
1107 static struct clk_regmap gxbb_mali_1 = {
1108         .data = &(struct clk_regmap_gate_data){
1109                 .offset = HHI_MALI_CLK_CNTL,
1110                 .bit_idx = 24,
1111         },
1112         .hw.init = &(struct clk_init_data){
1113                 .name = "mali_1",
1114                 .ops = &clk_regmap_gate_ops,
1115                 .parent_hws = (const struct clk_hw *[]) {
1116                         &gxbb_mali_1_div.hw
1117                 },
1118                 .num_parents = 1,
1119                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1120         },
1121 };
1122
1123 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1124         &gxbb_mali_0.hw,
1125         &gxbb_mali_1.hw,
1126 };
1127
1128 static struct clk_regmap gxbb_mali = {
1129         .data = &(struct clk_regmap_mux_data){
1130                 .offset = HHI_MALI_CLK_CNTL,
1131                 .mask = 1,
1132                 .shift = 31,
1133         },
1134         .hw.init = &(struct clk_init_data){
1135                 .name = "mali",
1136                 .ops = &clk_regmap_mux_ops,
1137                 .parent_hws = gxbb_mali_parent_hws,
1138                 .num_parents = 2,
1139                 .flags = CLK_SET_RATE_PARENT,
1140         },
1141 };
1142
1143 static struct clk_regmap gxbb_cts_amclk_sel = {
1144         .data = &(struct clk_regmap_mux_data){
1145                 .offset = HHI_AUD_CLK_CNTL,
1146                 .mask = 0x3,
1147                 .shift = 9,
1148                 .table = (u32[]){ 1, 2, 3 },
1149                 .flags = CLK_MUX_ROUND_CLOSEST,
1150         },
1151         .hw.init = &(struct clk_init_data){
1152                 .name = "cts_amclk_sel",
1153                 .ops = &clk_regmap_mux_ops,
1154                 .parent_hws = (const struct clk_hw *[]) {
1155                         &gxbb_mpll0.hw,
1156                         &gxbb_mpll1.hw,
1157                         &gxbb_mpll2.hw,
1158                 },
1159                 .num_parents = 3,
1160         },
1161 };
1162
1163 static struct clk_regmap gxbb_cts_amclk_div = {
1164         .data = &(struct clk_regmap_div_data) {
1165                 .offset = HHI_AUD_CLK_CNTL,
1166                 .shift = 0,
1167                 .width = 8,
1168                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1169         },
1170         .hw.init = &(struct clk_init_data){
1171                 .name = "cts_amclk_div",
1172                 .ops = &clk_regmap_divider_ops,
1173                 .parent_hws = (const struct clk_hw *[]) {
1174                         &gxbb_cts_amclk_sel.hw
1175                 },
1176                 .num_parents = 1,
1177                 .flags = CLK_SET_RATE_PARENT,
1178         },
1179 };
1180
1181 static struct clk_regmap gxbb_cts_amclk = {
1182         .data = &(struct clk_regmap_gate_data){
1183                 .offset = HHI_AUD_CLK_CNTL,
1184                 .bit_idx = 8,
1185         },
1186         .hw.init = &(struct clk_init_data){
1187                 .name = "cts_amclk",
1188                 .ops = &clk_regmap_gate_ops,
1189                 .parent_hws = (const struct clk_hw *[]) {
1190                         &gxbb_cts_amclk_div.hw
1191                 },
1192                 .num_parents = 1,
1193                 .flags = CLK_SET_RATE_PARENT,
1194         },
1195 };
1196
1197 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1198         .data = &(struct clk_regmap_mux_data){
1199                 .offset = HHI_AUD_CLK_CNTL2,
1200                 .mask = 0x3,
1201                 .shift = 25,
1202                 .table = (u32[]){ 1, 2, 3 },
1203                 .flags = CLK_MUX_ROUND_CLOSEST,
1204         },
1205         .hw.init = &(struct clk_init_data) {
1206                 .name = "cts_mclk_i958_sel",
1207                 .ops = &clk_regmap_mux_ops,
1208                 .parent_hws = (const struct clk_hw *[]) {
1209                         &gxbb_mpll0.hw,
1210                         &gxbb_mpll1.hw,
1211                         &gxbb_mpll2.hw,
1212                 },
1213                 .num_parents = 3,
1214         },
1215 };
1216
1217 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1218         .data = &(struct clk_regmap_div_data){
1219                 .offset = HHI_AUD_CLK_CNTL2,
1220                 .shift = 16,
1221                 .width = 8,
1222                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1223         },
1224         .hw.init = &(struct clk_init_data) {
1225                 .name = "cts_mclk_i958_div",
1226                 .ops = &clk_regmap_divider_ops,
1227                 .parent_hws = (const struct clk_hw *[]) {
1228                         &gxbb_cts_mclk_i958_sel.hw
1229                 },
1230                 .num_parents = 1,
1231                 .flags = CLK_SET_RATE_PARENT,
1232         },
1233 };
1234
1235 static struct clk_regmap gxbb_cts_mclk_i958 = {
1236         .data = &(struct clk_regmap_gate_data){
1237                 .offset = HHI_AUD_CLK_CNTL2,
1238                 .bit_idx = 24,
1239         },
1240         .hw.init = &(struct clk_init_data){
1241                 .name = "cts_mclk_i958",
1242                 .ops = &clk_regmap_gate_ops,
1243                 .parent_hws = (const struct clk_hw *[]) {
1244                         &gxbb_cts_mclk_i958_div.hw
1245                 },
1246                 .num_parents = 1,
1247                 .flags = CLK_SET_RATE_PARENT,
1248         },
1249 };
1250
1251 static struct clk_regmap gxbb_cts_i958 = {
1252         .data = &(struct clk_regmap_mux_data){
1253                 .offset = HHI_AUD_CLK_CNTL2,
1254                 .mask = 0x1,
1255                 .shift = 27,
1256                 },
1257         .hw.init = &(struct clk_init_data){
1258                 .name = "cts_i958",
1259                 .ops = &clk_regmap_mux_ops,
1260                 .parent_hws = (const struct clk_hw *[]) {
1261                         &gxbb_cts_amclk.hw,
1262                         &gxbb_cts_mclk_i958.hw
1263                 },
1264                 .num_parents = 2,
1265                 /*
1266                  *The parent is specific to origin of the audio data. Let the
1267                  * consumer choose the appropriate parent
1268                  */
1269                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1270         },
1271 };
1272
1273 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1274         { .fw_name = "xtal", },
1275         /*
1276          * FIXME: This clock is provided by the ao clock controller but the
1277          * clock is not yet part of the binding of this controller, so string
1278          * name must be use to set this parent.
1279          */
1280         { .name = "cts_slow_oscin", .index = -1 },
1281         { .hw = &gxbb_fclk_div3.hw },
1282         { .hw = &gxbb_fclk_div5.hw },
1283 };
1284
1285 static struct clk_regmap gxbb_32k_clk_sel = {
1286         .data = &(struct clk_regmap_mux_data){
1287                 .offset = HHI_32K_CLK_CNTL,
1288                 .mask = 0x3,
1289                 .shift = 16,
1290                 },
1291         .hw.init = &(struct clk_init_data){
1292                 .name = "32k_clk_sel",
1293                 .ops = &clk_regmap_mux_ops,
1294                 .parent_data = gxbb_32k_clk_parent_data,
1295                 .num_parents = 4,
1296                 .flags = CLK_SET_RATE_PARENT,
1297         },
1298 };
1299
1300 static struct clk_regmap gxbb_32k_clk_div = {
1301         .data = &(struct clk_regmap_div_data){
1302                 .offset = HHI_32K_CLK_CNTL,
1303                 .shift = 0,
1304                 .width = 14,
1305         },
1306         .hw.init = &(struct clk_init_data){
1307                 .name = "32k_clk_div",
1308                 .ops = &clk_regmap_divider_ops,
1309                 .parent_hws = (const struct clk_hw *[]) {
1310                         &gxbb_32k_clk_sel.hw
1311                 },
1312                 .num_parents = 1,
1313                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1314         },
1315 };
1316
1317 static struct clk_regmap gxbb_32k_clk = {
1318         .data = &(struct clk_regmap_gate_data){
1319                 .offset = HHI_32K_CLK_CNTL,
1320                 .bit_idx = 15,
1321         },
1322         .hw.init = &(struct clk_init_data){
1323                 .name = "32k_clk",
1324                 .ops = &clk_regmap_gate_ops,
1325                 .parent_hws = (const struct clk_hw *[]) {
1326                         &gxbb_32k_clk_div.hw
1327                 },
1328                 .num_parents = 1,
1329                 .flags = CLK_SET_RATE_PARENT,
1330         },
1331 };
1332
1333 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1334         { .fw_name = "xtal", },
1335         { .hw = &gxbb_fclk_div2.hw },
1336         { .hw = &gxbb_fclk_div3.hw },
1337         { .hw = &gxbb_fclk_div5.hw },
1338         { .hw = &gxbb_fclk_div7.hw },
1339         /*
1340          * Following these parent clocks, we should also have had mpll2, mpll3
1341          * and gp0_pll but these clocks are too precious to be used here. All
1342          * the necessary rates for MMC and NAND operation can be acheived using
1343          * xtal or fclk_div clocks
1344          */
1345 };
1346
1347 /* SDIO clock */
1348 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1349         .data = &(struct clk_regmap_mux_data){
1350                 .offset = HHI_SD_EMMC_CLK_CNTL,
1351                 .mask = 0x7,
1352                 .shift = 9,
1353         },
1354         .hw.init = &(struct clk_init_data) {
1355                 .name = "sd_emmc_a_clk0_sel",
1356                 .ops = &clk_regmap_mux_ops,
1357                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1358                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1359                 .flags = CLK_SET_RATE_PARENT,
1360         },
1361 };
1362
1363 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1364         .data = &(struct clk_regmap_div_data){
1365                 .offset = HHI_SD_EMMC_CLK_CNTL,
1366                 .shift = 0,
1367                 .width = 7,
1368                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1369         },
1370         .hw.init = &(struct clk_init_data) {
1371                 .name = "sd_emmc_a_clk0_div",
1372                 .ops = &clk_regmap_divider_ops,
1373                 .parent_hws = (const struct clk_hw *[]) {
1374                         &gxbb_sd_emmc_a_clk0_sel.hw
1375                 },
1376                 .num_parents = 1,
1377                 .flags = CLK_SET_RATE_PARENT,
1378         },
1379 };
1380
1381 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1382         .data = &(struct clk_regmap_gate_data){
1383                 .offset = HHI_SD_EMMC_CLK_CNTL,
1384                 .bit_idx = 7,
1385         },
1386         .hw.init = &(struct clk_init_data){
1387                 .name = "sd_emmc_a_clk0",
1388                 .ops = &clk_regmap_gate_ops,
1389                 .parent_hws = (const struct clk_hw *[]) {
1390                         &gxbb_sd_emmc_a_clk0_div.hw
1391                 },
1392                 .num_parents = 1,
1393                 .flags = CLK_SET_RATE_PARENT,
1394         },
1395 };
1396
1397 /* SDcard clock */
1398 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1399         .data = &(struct clk_regmap_mux_data){
1400                 .offset = HHI_SD_EMMC_CLK_CNTL,
1401                 .mask = 0x7,
1402                 .shift = 25,
1403         },
1404         .hw.init = &(struct clk_init_data) {
1405                 .name = "sd_emmc_b_clk0_sel",
1406                 .ops = &clk_regmap_mux_ops,
1407                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1408                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1409                 .flags = CLK_SET_RATE_PARENT,
1410         },
1411 };
1412
1413 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1414         .data = &(struct clk_regmap_div_data){
1415                 .offset = HHI_SD_EMMC_CLK_CNTL,
1416                 .shift = 16,
1417                 .width = 7,
1418                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1419         },
1420         .hw.init = &(struct clk_init_data) {
1421                 .name = "sd_emmc_b_clk0_div",
1422                 .ops = &clk_regmap_divider_ops,
1423                 .parent_hws = (const struct clk_hw *[]) {
1424                         &gxbb_sd_emmc_b_clk0_sel.hw
1425                 },
1426                 .num_parents = 1,
1427                 .flags = CLK_SET_RATE_PARENT,
1428         },
1429 };
1430
1431 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1432         .data = &(struct clk_regmap_gate_data){
1433                 .offset = HHI_SD_EMMC_CLK_CNTL,
1434                 .bit_idx = 23,
1435         },
1436         .hw.init = &(struct clk_init_data){
1437                 .name = "sd_emmc_b_clk0",
1438                 .ops = &clk_regmap_gate_ops,
1439                 .parent_hws = (const struct clk_hw *[]) {
1440                         &gxbb_sd_emmc_b_clk0_div.hw
1441                 },
1442                 .num_parents = 1,
1443                 .flags = CLK_SET_RATE_PARENT,
1444         },
1445 };
1446
1447 /* EMMC/NAND clock */
1448 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1449         .data = &(struct clk_regmap_mux_data){
1450                 .offset = HHI_NAND_CLK_CNTL,
1451                 .mask = 0x7,
1452                 .shift = 9,
1453         },
1454         .hw.init = &(struct clk_init_data) {
1455                 .name = "sd_emmc_c_clk0_sel",
1456                 .ops = &clk_regmap_mux_ops,
1457                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1458                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1459                 .flags = CLK_SET_RATE_PARENT,
1460         },
1461 };
1462
1463 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1464         .data = &(struct clk_regmap_div_data){
1465                 .offset = HHI_NAND_CLK_CNTL,
1466                 .shift = 0,
1467                 .width = 7,
1468                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1469         },
1470         .hw.init = &(struct clk_init_data) {
1471                 .name = "sd_emmc_c_clk0_div",
1472                 .ops = &clk_regmap_divider_ops,
1473                 .parent_hws = (const struct clk_hw *[]) {
1474                         &gxbb_sd_emmc_c_clk0_sel.hw
1475                 },
1476                 .num_parents = 1,
1477                 .flags = CLK_SET_RATE_PARENT,
1478         },
1479 };
1480
1481 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1482         .data = &(struct clk_regmap_gate_data){
1483                 .offset = HHI_NAND_CLK_CNTL,
1484                 .bit_idx = 7,
1485         },
1486         .hw.init = &(struct clk_init_data){
1487                 .name = "sd_emmc_c_clk0",
1488                 .ops = &clk_regmap_gate_ops,
1489                 .parent_hws = (const struct clk_hw *[]) {
1490                         &gxbb_sd_emmc_c_clk0_div.hw
1491                 },
1492                 .num_parents = 1,
1493                 .flags = CLK_SET_RATE_PARENT,
1494         },
1495 };
1496
1497 /* VPU Clock */
1498
1499 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1500         &gxbb_fclk_div4.hw,
1501         &gxbb_fclk_div3.hw,
1502         &gxbb_fclk_div5.hw,
1503         &gxbb_fclk_div7.hw,
1504 };
1505
1506 static struct clk_regmap gxbb_vpu_0_sel = {
1507         .data = &(struct clk_regmap_mux_data){
1508                 .offset = HHI_VPU_CLK_CNTL,
1509                 .mask = 0x3,
1510                 .shift = 9,
1511         },
1512         .hw.init = &(struct clk_init_data){
1513                 .name = "vpu_0_sel",
1514                 .ops = &clk_regmap_mux_ops,
1515                 /*
1516                  * bits 9:10 selects from 4 possible parents:
1517                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1518                  */
1519                 .parent_hws = gxbb_vpu_parent_hws,
1520                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1521                 .flags = CLK_SET_RATE_NO_REPARENT,
1522         },
1523 };
1524
1525 static struct clk_regmap gxbb_vpu_0_div = {
1526         .data = &(struct clk_regmap_div_data){
1527                 .offset = HHI_VPU_CLK_CNTL,
1528                 .shift = 0,
1529                 .width = 7,
1530         },
1531         .hw.init = &(struct clk_init_data){
1532                 .name = "vpu_0_div",
1533                 .ops = &clk_regmap_divider_ops,
1534                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1535                 .num_parents = 1,
1536                 .flags = CLK_SET_RATE_PARENT,
1537         },
1538 };
1539
1540 static struct clk_regmap gxbb_vpu_0 = {
1541         .data = &(struct clk_regmap_gate_data){
1542                 .offset = HHI_VPU_CLK_CNTL,
1543                 .bit_idx = 8,
1544         },
1545         .hw.init = &(struct clk_init_data) {
1546                 .name = "vpu_0",
1547                 .ops = &clk_regmap_gate_ops,
1548                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1549                 .num_parents = 1,
1550                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1551         },
1552 };
1553
1554 static struct clk_regmap gxbb_vpu_1_sel = {
1555         .data = &(struct clk_regmap_mux_data){
1556                 .offset = HHI_VPU_CLK_CNTL,
1557                 .mask = 0x3,
1558                 .shift = 25,
1559         },
1560         .hw.init = &(struct clk_init_data){
1561                 .name = "vpu_1_sel",
1562                 .ops = &clk_regmap_mux_ops,
1563                 /*
1564                  * bits 25:26 selects from 4 possible parents:
1565                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1566                  */
1567                 .parent_hws = gxbb_vpu_parent_hws,
1568                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1569                 .flags = CLK_SET_RATE_NO_REPARENT,
1570         },
1571 };
1572
1573 static struct clk_regmap gxbb_vpu_1_div = {
1574         .data = &(struct clk_regmap_div_data){
1575                 .offset = HHI_VPU_CLK_CNTL,
1576                 .shift = 16,
1577                 .width = 7,
1578         },
1579         .hw.init = &(struct clk_init_data){
1580                 .name = "vpu_1_div",
1581                 .ops = &clk_regmap_divider_ops,
1582                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1583                 .num_parents = 1,
1584                 .flags = CLK_SET_RATE_PARENT,
1585         },
1586 };
1587
1588 static struct clk_regmap gxbb_vpu_1 = {
1589         .data = &(struct clk_regmap_gate_data){
1590                 .offset = HHI_VPU_CLK_CNTL,
1591                 .bit_idx = 24,
1592         },
1593         .hw.init = &(struct clk_init_data) {
1594                 .name = "vpu_1",
1595                 .ops = &clk_regmap_gate_ops,
1596                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1597                 .num_parents = 1,
1598                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1599         },
1600 };
1601
1602 static struct clk_regmap gxbb_vpu = {
1603         .data = &(struct clk_regmap_mux_data){
1604                 .offset = HHI_VPU_CLK_CNTL,
1605                 .mask = 1,
1606                 .shift = 31,
1607         },
1608         .hw.init = &(struct clk_init_data){
1609                 .name = "vpu",
1610                 .ops = &clk_regmap_mux_ops,
1611                 /*
1612                  * bit 31 selects from 2 possible parents:
1613                  * vpu_0 or vpu_1
1614                  */
1615                 .parent_hws = (const struct clk_hw *[]) {
1616                         &gxbb_vpu_0.hw,
1617                         &gxbb_vpu_1.hw
1618                 },
1619                 .num_parents = 2,
1620                 .flags = CLK_SET_RATE_NO_REPARENT,
1621         },
1622 };
1623
1624 /* VAPB Clock */
1625
1626 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1627         &gxbb_fclk_div4.hw,
1628         &gxbb_fclk_div3.hw,
1629         &gxbb_fclk_div5.hw,
1630         &gxbb_fclk_div7.hw,
1631 };
1632
1633 static struct clk_regmap gxbb_vapb_0_sel = {
1634         .data = &(struct clk_regmap_mux_data){
1635                 .offset = HHI_VAPBCLK_CNTL,
1636                 .mask = 0x3,
1637                 .shift = 9,
1638         },
1639         .hw.init = &(struct clk_init_data){
1640                 .name = "vapb_0_sel",
1641                 .ops = &clk_regmap_mux_ops,
1642                 /*
1643                  * bits 9:10 selects from 4 possible parents:
1644                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1645                  */
1646                 .parent_hws = gxbb_vapb_parent_hws,
1647                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1648                 .flags = CLK_SET_RATE_NO_REPARENT,
1649         },
1650 };
1651
1652 static struct clk_regmap gxbb_vapb_0_div = {
1653         .data = &(struct clk_regmap_div_data){
1654                 .offset = HHI_VAPBCLK_CNTL,
1655                 .shift = 0,
1656                 .width = 7,
1657         },
1658         .hw.init = &(struct clk_init_data){
1659                 .name = "vapb_0_div",
1660                 .ops = &clk_regmap_divider_ops,
1661                 .parent_hws = (const struct clk_hw *[]) {
1662                         &gxbb_vapb_0_sel.hw
1663                 },
1664                 .num_parents = 1,
1665                 .flags = CLK_SET_RATE_PARENT,
1666         },
1667 };
1668
1669 static struct clk_regmap gxbb_vapb_0 = {
1670         .data = &(struct clk_regmap_gate_data){
1671                 .offset = HHI_VAPBCLK_CNTL,
1672                 .bit_idx = 8,
1673         },
1674         .hw.init = &(struct clk_init_data) {
1675                 .name = "vapb_0",
1676                 .ops = &clk_regmap_gate_ops,
1677                 .parent_hws = (const struct clk_hw *[]) {
1678                         &gxbb_vapb_0_div.hw
1679                 },
1680                 .num_parents = 1,
1681                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1682         },
1683 };
1684
1685 static struct clk_regmap gxbb_vapb_1_sel = {
1686         .data = &(struct clk_regmap_mux_data){
1687                 .offset = HHI_VAPBCLK_CNTL,
1688                 .mask = 0x3,
1689                 .shift = 25,
1690         },
1691         .hw.init = &(struct clk_init_data){
1692                 .name = "vapb_1_sel",
1693                 .ops = &clk_regmap_mux_ops,
1694                 /*
1695                  * bits 25:26 selects from 4 possible parents:
1696                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1697                  */
1698                 .parent_hws = gxbb_vapb_parent_hws,
1699                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1700                 .flags = CLK_SET_RATE_NO_REPARENT,
1701         },
1702 };
1703
1704 static struct clk_regmap gxbb_vapb_1_div = {
1705         .data = &(struct clk_regmap_div_data){
1706                 .offset = HHI_VAPBCLK_CNTL,
1707                 .shift = 16,
1708                 .width = 7,
1709         },
1710         .hw.init = &(struct clk_init_data){
1711                 .name = "vapb_1_div",
1712                 .ops = &clk_regmap_divider_ops,
1713                 .parent_hws = (const struct clk_hw *[]) {
1714                         &gxbb_vapb_1_sel.hw
1715                 },
1716                 .num_parents = 1,
1717                 .flags = CLK_SET_RATE_PARENT,
1718         },
1719 };
1720
1721 static struct clk_regmap gxbb_vapb_1 = {
1722         .data = &(struct clk_regmap_gate_data){
1723                 .offset = HHI_VAPBCLK_CNTL,
1724                 .bit_idx = 24,
1725         },
1726         .hw.init = &(struct clk_init_data) {
1727                 .name = "vapb_1",
1728                 .ops = &clk_regmap_gate_ops,
1729                 .parent_hws = (const struct clk_hw *[]) {
1730                         &gxbb_vapb_1_div.hw
1731                 },
1732                 .num_parents = 1,
1733                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1734         },
1735 };
1736
1737 static struct clk_regmap gxbb_vapb_sel = {
1738         .data = &(struct clk_regmap_mux_data){
1739                 .offset = HHI_VAPBCLK_CNTL,
1740                 .mask = 1,
1741                 .shift = 31,
1742         },
1743         .hw.init = &(struct clk_init_data){
1744                 .name = "vapb_sel",
1745                 .ops = &clk_regmap_mux_ops,
1746                 /*
1747                  * bit 31 selects from 2 possible parents:
1748                  * vapb_0 or vapb_1
1749                  */
1750                 .parent_hws = (const struct clk_hw *[]) {
1751                         &gxbb_vapb_0.hw,
1752                         &gxbb_vapb_1.hw
1753                 },
1754                 .num_parents = 2,
1755                 .flags = CLK_SET_RATE_NO_REPARENT,
1756         },
1757 };
1758
1759 static struct clk_regmap gxbb_vapb = {
1760         .data = &(struct clk_regmap_gate_data){
1761                 .offset = HHI_VAPBCLK_CNTL,
1762                 .bit_idx = 30,
1763         },
1764         .hw.init = &(struct clk_init_data) {
1765                 .name = "vapb",
1766                 .ops = &clk_regmap_gate_ops,
1767                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1768                 .num_parents = 1,
1769                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1770         },
1771 };
1772
1773 /* Video Clocks */
1774
1775 static struct clk_regmap gxbb_vid_pll_div = {
1776         .data = &(struct meson_vid_pll_div_data){
1777                 .val = {
1778                         .reg_off = HHI_VID_PLL_CLK_DIV,
1779                         .shift   = 0,
1780                         .width   = 15,
1781                 },
1782                 .sel = {
1783                         .reg_off = HHI_VID_PLL_CLK_DIV,
1784                         .shift   = 16,
1785                         .width   = 2,
1786                 },
1787         },
1788         .hw.init = &(struct clk_init_data) {
1789                 .name = "vid_pll_div",
1790                 .ops = &meson_vid_pll_div_ro_ops,
1791                 .parent_data = &(const struct clk_parent_data) {
1792                         /*
1793                          * Note:
1794                          * GXL and GXBB have different hdmi_plls (with
1795                          * different struct clk_hw). We fallback to the global
1796                          * naming string mechanism so vid_pll_div picks up the
1797                          * appropriate one.
1798                          */
1799                         .name = "hdmi_pll",
1800                         .index = -1,
1801                 },
1802                 .num_parents = 1,
1803                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1804         },
1805 };
1806
1807 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1808         { .hw = &gxbb_vid_pll_div.hw },
1809         /*
1810          * Note:
1811          * GXL and GXBB have different hdmi_plls (with
1812          * different struct clk_hw). We fallback to the global
1813          * naming string mechanism so vid_pll_div picks up the
1814          * appropriate one.
1815          */
1816         { .name = "hdmi_pll", .index = -1 },
1817 };
1818
1819 static struct clk_regmap gxbb_vid_pll_sel = {
1820         .data = &(struct clk_regmap_mux_data){
1821                 .offset = HHI_VID_PLL_CLK_DIV,
1822                 .mask = 0x1,
1823                 .shift = 18,
1824         },
1825         .hw.init = &(struct clk_init_data){
1826                 .name = "vid_pll_sel",
1827                 .ops = &clk_regmap_mux_ops,
1828                 /*
1829                  * bit 18 selects from 2 possible parents:
1830                  * vid_pll_div or hdmi_pll
1831                  */
1832                 .parent_data = gxbb_vid_pll_parent_data,
1833                 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1834                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1835         },
1836 };
1837
1838 static struct clk_regmap gxbb_vid_pll = {
1839         .data = &(struct clk_regmap_gate_data){
1840                 .offset = HHI_VID_PLL_CLK_DIV,
1841                 .bit_idx = 19,
1842         },
1843         .hw.init = &(struct clk_init_data) {
1844                 .name = "vid_pll",
1845                 .ops = &clk_regmap_gate_ops,
1846                 .parent_hws = (const struct clk_hw *[]) {
1847                         &gxbb_vid_pll_sel.hw
1848                 },
1849                 .num_parents = 1,
1850                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1851         },
1852 };
1853
1854 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1855         &gxbb_vid_pll.hw,
1856         &gxbb_fclk_div4.hw,
1857         &gxbb_fclk_div3.hw,
1858         &gxbb_fclk_div5.hw,
1859         &gxbb_vid_pll.hw,
1860         &gxbb_fclk_div7.hw,
1861         &gxbb_mpll1.hw,
1862 };
1863
1864 static struct clk_regmap gxbb_vclk_sel = {
1865         .data = &(struct clk_regmap_mux_data){
1866                 .offset = HHI_VID_CLK_CNTL,
1867                 .mask = 0x7,
1868                 .shift = 16,
1869         },
1870         .hw.init = &(struct clk_init_data){
1871                 .name = "vclk_sel",
1872                 .ops = &clk_regmap_mux_ops,
1873                 /*
1874                  * bits 16:18 selects from 8 possible parents:
1875                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1876                  * vid_pll, fclk_div7, mp1
1877                  */
1878                 .parent_hws = gxbb_vclk_parent_hws,
1879                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1880                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1881         },
1882 };
1883
1884 static struct clk_regmap gxbb_vclk2_sel = {
1885         .data = &(struct clk_regmap_mux_data){
1886                 .offset = HHI_VIID_CLK_CNTL,
1887                 .mask = 0x7,
1888                 .shift = 16,
1889         },
1890         .hw.init = &(struct clk_init_data){
1891                 .name = "vclk2_sel",
1892                 .ops = &clk_regmap_mux_ops,
1893                 /*
1894                  * bits 16:18 selects from 8 possible parents:
1895                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1896                  * vid_pll, fclk_div7, mp1
1897                  */
1898                 .parent_hws = gxbb_vclk_parent_hws,
1899                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1900                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1901         },
1902 };
1903
1904 static struct clk_regmap gxbb_vclk_input = {
1905         .data = &(struct clk_regmap_gate_data){
1906                 .offset = HHI_VID_CLK_DIV,
1907                 .bit_idx = 16,
1908         },
1909         .hw.init = &(struct clk_init_data) {
1910                 .name = "vclk_input",
1911                 .ops = &clk_regmap_gate_ops,
1912                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1913                 .num_parents = 1,
1914                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1915         },
1916 };
1917
1918 static struct clk_regmap gxbb_vclk2_input = {
1919         .data = &(struct clk_regmap_gate_data){
1920                 .offset = HHI_VIID_CLK_DIV,
1921                 .bit_idx = 16,
1922         },
1923         .hw.init = &(struct clk_init_data) {
1924                 .name = "vclk2_input",
1925                 .ops = &clk_regmap_gate_ops,
1926                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1927                 .num_parents = 1,
1928                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1929         },
1930 };
1931
1932 static struct clk_regmap gxbb_vclk_div = {
1933         .data = &(struct clk_regmap_div_data){
1934                 .offset = HHI_VID_CLK_DIV,
1935                 .shift = 0,
1936                 .width = 8,
1937         },
1938         .hw.init = &(struct clk_init_data){
1939                 .name = "vclk_div",
1940                 .ops = &clk_regmap_divider_ops,
1941                 .parent_hws = (const struct clk_hw *[]) {
1942                         &gxbb_vclk_input.hw
1943                 },
1944                 .num_parents = 1,
1945                 .flags = CLK_GET_RATE_NOCACHE,
1946         },
1947 };
1948
1949 static struct clk_regmap gxbb_vclk2_div = {
1950         .data = &(struct clk_regmap_div_data){
1951                 .offset = HHI_VIID_CLK_DIV,
1952                 .shift = 0,
1953                 .width = 8,
1954         },
1955         .hw.init = &(struct clk_init_data){
1956                 .name = "vclk2_div",
1957                 .ops = &clk_regmap_divider_ops,
1958                 .parent_hws = (const struct clk_hw *[]) {
1959                         &gxbb_vclk2_input.hw
1960                 },
1961                 .num_parents = 1,
1962                 .flags = CLK_GET_RATE_NOCACHE,
1963         },
1964 };
1965
1966 static struct clk_regmap gxbb_vclk = {
1967         .data = &(struct clk_regmap_gate_data){
1968                 .offset = HHI_VID_CLK_CNTL,
1969                 .bit_idx = 19,
1970         },
1971         .hw.init = &(struct clk_init_data) {
1972                 .name = "vclk",
1973                 .ops = &clk_regmap_gate_ops,
1974                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1975                 .num_parents = 1,
1976                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1977         },
1978 };
1979
1980 static struct clk_regmap gxbb_vclk2 = {
1981         .data = &(struct clk_regmap_gate_data){
1982                 .offset = HHI_VIID_CLK_CNTL,
1983                 .bit_idx = 19,
1984         },
1985         .hw.init = &(struct clk_init_data) {
1986                 .name = "vclk2",
1987                 .ops = &clk_regmap_gate_ops,
1988                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1989                 .num_parents = 1,
1990                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1991         },
1992 };
1993
1994 static struct clk_regmap gxbb_vclk_div1 = {
1995         .data = &(struct clk_regmap_gate_data){
1996                 .offset = HHI_VID_CLK_CNTL,
1997                 .bit_idx = 0,
1998         },
1999         .hw.init = &(struct clk_init_data) {
2000                 .name = "vclk_div1",
2001                 .ops = &clk_regmap_gate_ops,
2002                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2003                 .num_parents = 1,
2004                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2005         },
2006 };
2007
2008 static struct clk_regmap gxbb_vclk_div2_en = {
2009         .data = &(struct clk_regmap_gate_data){
2010                 .offset = HHI_VID_CLK_CNTL,
2011                 .bit_idx = 1,
2012         },
2013         .hw.init = &(struct clk_init_data) {
2014                 .name = "vclk_div2_en",
2015                 .ops = &clk_regmap_gate_ops,
2016                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2017                 .num_parents = 1,
2018                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2019         },
2020 };
2021
2022 static struct clk_regmap gxbb_vclk_div4_en = {
2023         .data = &(struct clk_regmap_gate_data){
2024                 .offset = HHI_VID_CLK_CNTL,
2025                 .bit_idx = 2,
2026         },
2027         .hw.init = &(struct clk_init_data) {
2028                 .name = "vclk_div4_en",
2029                 .ops = &clk_regmap_gate_ops,
2030                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2031                 .num_parents = 1,
2032                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2033         },
2034 };
2035
2036 static struct clk_regmap gxbb_vclk_div6_en = {
2037         .data = &(struct clk_regmap_gate_data){
2038                 .offset = HHI_VID_CLK_CNTL,
2039                 .bit_idx = 3,
2040         },
2041         .hw.init = &(struct clk_init_data) {
2042                 .name = "vclk_div6_en",
2043                 .ops = &clk_regmap_gate_ops,
2044                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2045                 .num_parents = 1,
2046                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2047         },
2048 };
2049
2050 static struct clk_regmap gxbb_vclk_div12_en = {
2051         .data = &(struct clk_regmap_gate_data){
2052                 .offset = HHI_VID_CLK_CNTL,
2053                 .bit_idx = 4,
2054         },
2055         .hw.init = &(struct clk_init_data) {
2056                 .name = "vclk_div12_en",
2057                 .ops = &clk_regmap_gate_ops,
2058                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2059                 .num_parents = 1,
2060                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2061         },
2062 };
2063
2064 static struct clk_regmap gxbb_vclk2_div1 = {
2065         .data = &(struct clk_regmap_gate_data){
2066                 .offset = HHI_VIID_CLK_CNTL,
2067                 .bit_idx = 0,
2068         },
2069         .hw.init = &(struct clk_init_data) {
2070                 .name = "vclk2_div1",
2071                 .ops = &clk_regmap_gate_ops,
2072                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2073                 .num_parents = 1,
2074                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2075         },
2076 };
2077
2078 static struct clk_regmap gxbb_vclk2_div2_en = {
2079         .data = &(struct clk_regmap_gate_data){
2080                 .offset = HHI_VIID_CLK_CNTL,
2081                 .bit_idx = 1,
2082         },
2083         .hw.init = &(struct clk_init_data) {
2084                 .name = "vclk2_div2_en",
2085                 .ops = &clk_regmap_gate_ops,
2086                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2087                 .num_parents = 1,
2088                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2089         },
2090 };
2091
2092 static struct clk_regmap gxbb_vclk2_div4_en = {
2093         .data = &(struct clk_regmap_gate_data){
2094                 .offset = HHI_VIID_CLK_CNTL,
2095                 .bit_idx = 2,
2096         },
2097         .hw.init = &(struct clk_init_data) {
2098                 .name = "vclk2_div4_en",
2099                 .ops = &clk_regmap_gate_ops,
2100                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2101                 .num_parents = 1,
2102                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2103         },
2104 };
2105
2106 static struct clk_regmap gxbb_vclk2_div6_en = {
2107         .data = &(struct clk_regmap_gate_data){
2108                 .offset = HHI_VIID_CLK_CNTL,
2109                 .bit_idx = 3,
2110         },
2111         .hw.init = &(struct clk_init_data) {
2112                 .name = "vclk2_div6_en",
2113                 .ops = &clk_regmap_gate_ops,
2114                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2115                 .num_parents = 1,
2116                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2117         },
2118 };
2119
2120 static struct clk_regmap gxbb_vclk2_div12_en = {
2121         .data = &(struct clk_regmap_gate_data){
2122                 .offset = HHI_VIID_CLK_CNTL,
2123                 .bit_idx = 4,
2124         },
2125         .hw.init = &(struct clk_init_data) {
2126                 .name = "vclk2_div12_en",
2127                 .ops = &clk_regmap_gate_ops,
2128                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2129                 .num_parents = 1,
2130                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2131         },
2132 };
2133
2134 static struct clk_fixed_factor gxbb_vclk_div2 = {
2135         .mult = 1,
2136         .div = 2,
2137         .hw.init = &(struct clk_init_data){
2138                 .name = "vclk_div2",
2139                 .ops = &clk_fixed_factor_ops,
2140                 .parent_hws = (const struct clk_hw *[]) {
2141                         &gxbb_vclk_div2_en.hw
2142                 },
2143                 .num_parents = 1,
2144         },
2145 };
2146
2147 static struct clk_fixed_factor gxbb_vclk_div4 = {
2148         .mult = 1,
2149         .div = 4,
2150         .hw.init = &(struct clk_init_data){
2151                 .name = "vclk_div4",
2152                 .ops = &clk_fixed_factor_ops,
2153                 .parent_hws = (const struct clk_hw *[]) {
2154                         &gxbb_vclk_div4_en.hw
2155                 },
2156                 .num_parents = 1,
2157         },
2158 };
2159
2160 static struct clk_fixed_factor gxbb_vclk_div6 = {
2161         .mult = 1,
2162         .div = 6,
2163         .hw.init = &(struct clk_init_data){
2164                 .name = "vclk_div6",
2165                 .ops = &clk_fixed_factor_ops,
2166                 .parent_hws = (const struct clk_hw *[]) {
2167                         &gxbb_vclk_div6_en.hw
2168                 },
2169                 .num_parents = 1,
2170         },
2171 };
2172
2173 static struct clk_fixed_factor gxbb_vclk_div12 = {
2174         .mult = 1,
2175         .div = 12,
2176         .hw.init = &(struct clk_init_data){
2177                 .name = "vclk_div12",
2178                 .ops = &clk_fixed_factor_ops,
2179                 .parent_hws = (const struct clk_hw *[]) {
2180                         &gxbb_vclk_div12_en.hw
2181                 },
2182                 .num_parents = 1,
2183         },
2184 };
2185
2186 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2187         .mult = 1,
2188         .div = 2,
2189         .hw.init = &(struct clk_init_data){
2190                 .name = "vclk2_div2",
2191                 .ops = &clk_fixed_factor_ops,
2192                 .parent_hws = (const struct clk_hw *[]) {
2193                         &gxbb_vclk2_div2_en.hw
2194                 },
2195                 .num_parents = 1,
2196         },
2197 };
2198
2199 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2200         .mult = 1,
2201         .div = 4,
2202         .hw.init = &(struct clk_init_data){
2203                 .name = "vclk2_div4",
2204                 .ops = &clk_fixed_factor_ops,
2205                 .parent_hws = (const struct clk_hw *[]) {
2206                         &gxbb_vclk2_div4_en.hw
2207                 },
2208                 .num_parents = 1,
2209         },
2210 };
2211
2212 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2213         .mult = 1,
2214         .div = 6,
2215         .hw.init = &(struct clk_init_data){
2216                 .name = "vclk2_div6",
2217                 .ops = &clk_fixed_factor_ops,
2218                 .parent_hws = (const struct clk_hw *[]) {
2219                         &gxbb_vclk2_div6_en.hw
2220                 },
2221                 .num_parents = 1,
2222         },
2223 };
2224
2225 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2226         .mult = 1,
2227         .div = 12,
2228         .hw.init = &(struct clk_init_data){
2229                 .name = "vclk2_div12",
2230                 .ops = &clk_fixed_factor_ops,
2231                 .parent_hws = (const struct clk_hw *[]) {
2232                         &gxbb_vclk2_div12_en.hw
2233                 },
2234                 .num_parents = 1,
2235         },
2236 };
2237
2238 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2239 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2240         &gxbb_vclk_div1.hw,
2241         &gxbb_vclk_div2.hw,
2242         &gxbb_vclk_div4.hw,
2243         &gxbb_vclk_div6.hw,
2244         &gxbb_vclk_div12.hw,
2245         &gxbb_vclk2_div1.hw,
2246         &gxbb_vclk2_div2.hw,
2247         &gxbb_vclk2_div4.hw,
2248         &gxbb_vclk2_div6.hw,
2249         &gxbb_vclk2_div12.hw,
2250 };
2251
2252 static struct clk_regmap gxbb_cts_enci_sel = {
2253         .data = &(struct clk_regmap_mux_data){
2254                 .offset = HHI_VID_CLK_DIV,
2255                 .mask = 0xf,
2256                 .shift = 28,
2257                 .table = mux_table_cts_sel,
2258         },
2259         .hw.init = &(struct clk_init_data){
2260                 .name = "cts_enci_sel",
2261                 .ops = &clk_regmap_mux_ops,
2262                 .parent_hws = gxbb_cts_parent_hws,
2263                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2264                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2265         },
2266 };
2267
2268 static struct clk_regmap gxbb_cts_encp_sel = {
2269         .data = &(struct clk_regmap_mux_data){
2270                 .offset = HHI_VID_CLK_DIV,
2271                 .mask = 0xf,
2272                 .shift = 20,
2273                 .table = mux_table_cts_sel,
2274         },
2275         .hw.init = &(struct clk_init_data){
2276                 .name = "cts_encp_sel",
2277                 .ops = &clk_regmap_mux_ops,
2278                 .parent_hws = gxbb_cts_parent_hws,
2279                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2280                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2281         },
2282 };
2283
2284 static struct clk_regmap gxbb_cts_vdac_sel = {
2285         .data = &(struct clk_regmap_mux_data){
2286                 .offset = HHI_VIID_CLK_DIV,
2287                 .mask = 0xf,
2288                 .shift = 28,
2289                 .table = mux_table_cts_sel,
2290         },
2291         .hw.init = &(struct clk_init_data){
2292                 .name = "cts_vdac_sel",
2293                 .ops = &clk_regmap_mux_ops,
2294                 .parent_hws = gxbb_cts_parent_hws,
2295                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2296                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2297         },
2298 };
2299
2300 /* TOFIX: add support for cts_tcon */
2301 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2302 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2303         &gxbb_vclk_div1.hw,
2304         &gxbb_vclk_div2.hw,
2305         &gxbb_vclk_div4.hw,
2306         &gxbb_vclk_div6.hw,
2307         &gxbb_vclk_div12.hw,
2308         &gxbb_vclk2_div1.hw,
2309         &gxbb_vclk2_div2.hw,
2310         &gxbb_vclk2_div4.hw,
2311         &gxbb_vclk2_div6.hw,
2312         &gxbb_vclk2_div12.hw,
2313 };
2314
2315 static struct clk_regmap gxbb_hdmi_tx_sel = {
2316         .data = &(struct clk_regmap_mux_data){
2317                 .offset = HHI_HDMI_CLK_CNTL,
2318                 .mask = 0xf,
2319                 .shift = 16,
2320                 .table = mux_table_hdmi_tx_sel,
2321         },
2322         .hw.init = &(struct clk_init_data){
2323                 .name = "hdmi_tx_sel",
2324                 .ops = &clk_regmap_mux_ops,
2325                 /*
2326                  * bits 31:28 selects from 12 possible parents:
2327                  * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2328                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2329                  * cts_tcon
2330                  */
2331                 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2332                 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2333                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2334         },
2335 };
2336
2337 static struct clk_regmap gxbb_cts_enci = {
2338         .data = &(struct clk_regmap_gate_data){
2339                 .offset = HHI_VID_CLK_CNTL2,
2340                 .bit_idx = 0,
2341         },
2342         .hw.init = &(struct clk_init_data) {
2343                 .name = "cts_enci",
2344                 .ops = &clk_regmap_gate_ops,
2345                 .parent_hws = (const struct clk_hw *[]) {
2346                         &gxbb_cts_enci_sel.hw
2347                 },
2348                 .num_parents = 1,
2349                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2350         },
2351 };
2352
2353 static struct clk_regmap gxbb_cts_encp = {
2354         .data = &(struct clk_regmap_gate_data){
2355                 .offset = HHI_VID_CLK_CNTL2,
2356                 .bit_idx = 2,
2357         },
2358         .hw.init = &(struct clk_init_data) {
2359                 .name = "cts_encp",
2360                 .ops = &clk_regmap_gate_ops,
2361                 .parent_hws = (const struct clk_hw *[]) {
2362                         &gxbb_cts_encp_sel.hw
2363                 },
2364                 .num_parents = 1,
2365                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2366         },
2367 };
2368
2369 static struct clk_regmap gxbb_cts_vdac = {
2370         .data = &(struct clk_regmap_gate_data){
2371                 .offset = HHI_VID_CLK_CNTL2,
2372                 .bit_idx = 4,
2373         },
2374         .hw.init = &(struct clk_init_data) {
2375                 .name = "cts_vdac",
2376                 .ops = &clk_regmap_gate_ops,
2377                 .parent_hws = (const struct clk_hw *[]) {
2378                         &gxbb_cts_vdac_sel.hw
2379                 },
2380                 .num_parents = 1,
2381                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2382         },
2383 };
2384
2385 static struct clk_regmap gxbb_hdmi_tx = {
2386         .data = &(struct clk_regmap_gate_data){
2387                 .offset = HHI_VID_CLK_CNTL2,
2388                 .bit_idx = 5,
2389         },
2390         .hw.init = &(struct clk_init_data) {
2391                 .name = "hdmi_tx",
2392                 .ops = &clk_regmap_gate_ops,
2393                 .parent_hws = (const struct clk_hw *[]) {
2394                         &gxbb_hdmi_tx_sel.hw
2395                 },
2396                 .num_parents = 1,
2397                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2398         },
2399 };
2400
2401 /* HDMI Clocks */
2402
2403 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2404         { .fw_name = "xtal", },
2405         { .hw = &gxbb_fclk_div4.hw },
2406         { .hw = &gxbb_fclk_div3.hw },
2407         { .hw = &gxbb_fclk_div5.hw },
2408 };
2409
2410 static struct clk_regmap gxbb_hdmi_sel = {
2411         .data = &(struct clk_regmap_mux_data){
2412                 .offset = HHI_HDMI_CLK_CNTL,
2413                 .mask = 0x3,
2414                 .shift = 9,
2415                 .flags = CLK_MUX_ROUND_CLOSEST,
2416         },
2417         .hw.init = &(struct clk_init_data){
2418                 .name = "hdmi_sel",
2419                 .ops = &clk_regmap_mux_ops,
2420                 .parent_data = gxbb_hdmi_parent_data,
2421                 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2422                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2423         },
2424 };
2425
2426 static struct clk_regmap gxbb_hdmi_div = {
2427         .data = &(struct clk_regmap_div_data){
2428                 .offset = HHI_HDMI_CLK_CNTL,
2429                 .shift = 0,
2430                 .width = 7,
2431         },
2432         .hw.init = &(struct clk_init_data){
2433                 .name = "hdmi_div",
2434                 .ops = &clk_regmap_divider_ops,
2435                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2436                 .num_parents = 1,
2437                 .flags = CLK_GET_RATE_NOCACHE,
2438         },
2439 };
2440
2441 static struct clk_regmap gxbb_hdmi = {
2442         .data = &(struct clk_regmap_gate_data){
2443                 .offset = HHI_HDMI_CLK_CNTL,
2444                 .bit_idx = 8,
2445         },
2446         .hw.init = &(struct clk_init_data) {
2447                 .name = "hdmi",
2448                 .ops = &clk_regmap_gate_ops,
2449                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2450                 .num_parents = 1,
2451                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2452         },
2453 };
2454
2455 /* VDEC clocks */
2456
2457 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2458         &gxbb_fclk_div4.hw,
2459         &gxbb_fclk_div3.hw,
2460         &gxbb_fclk_div5.hw,
2461         &gxbb_fclk_div7.hw,
2462 };
2463
2464 static struct clk_regmap gxbb_vdec_1_sel = {
2465         .data = &(struct clk_regmap_mux_data){
2466                 .offset = HHI_VDEC_CLK_CNTL,
2467                 .mask = 0x3,
2468                 .shift = 9,
2469                 .flags = CLK_MUX_ROUND_CLOSEST,
2470         },
2471         .hw.init = &(struct clk_init_data){
2472                 .name = "vdec_1_sel",
2473                 .ops = &clk_regmap_mux_ops,
2474                 .parent_hws = gxbb_vdec_parent_hws,
2475                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2476                 .flags = CLK_SET_RATE_PARENT,
2477         },
2478 };
2479
2480 static struct clk_regmap gxbb_vdec_1_div = {
2481         .data = &(struct clk_regmap_div_data){
2482                 .offset = HHI_VDEC_CLK_CNTL,
2483                 .shift = 0,
2484                 .width = 7,
2485                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2486         },
2487         .hw.init = &(struct clk_init_data){
2488                 .name = "vdec_1_div",
2489                 .ops = &clk_regmap_divider_ops,
2490                 .parent_hws = (const struct clk_hw *[]) {
2491                         &gxbb_vdec_1_sel.hw
2492                 },
2493                 .num_parents = 1,
2494                 .flags = CLK_SET_RATE_PARENT,
2495         },
2496 };
2497
2498 static struct clk_regmap gxbb_vdec_1 = {
2499         .data = &(struct clk_regmap_gate_data){
2500                 .offset = HHI_VDEC_CLK_CNTL,
2501                 .bit_idx = 8,
2502         },
2503         .hw.init = &(struct clk_init_data) {
2504                 .name = "vdec_1",
2505                 .ops = &clk_regmap_gate_ops,
2506                 .parent_hws = (const struct clk_hw *[]) {
2507                         &gxbb_vdec_1_div.hw
2508                 },
2509                 .num_parents = 1,
2510                 .flags = CLK_SET_RATE_PARENT,
2511         },
2512 };
2513
2514 static struct clk_regmap gxbb_vdec_hevc_sel = {
2515         .data = &(struct clk_regmap_mux_data){
2516                 .offset = HHI_VDEC2_CLK_CNTL,
2517                 .mask = 0x3,
2518                 .shift = 25,
2519                 .flags = CLK_MUX_ROUND_CLOSEST,
2520         },
2521         .hw.init = &(struct clk_init_data){
2522                 .name = "vdec_hevc_sel",
2523                 .ops = &clk_regmap_mux_ops,
2524                 .parent_hws = gxbb_vdec_parent_hws,
2525                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2526                 .flags = CLK_SET_RATE_PARENT,
2527         },
2528 };
2529
2530 static struct clk_regmap gxbb_vdec_hevc_div = {
2531         .data = &(struct clk_regmap_div_data){
2532                 .offset = HHI_VDEC2_CLK_CNTL,
2533                 .shift = 16,
2534                 .width = 7,
2535                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2536         },
2537         .hw.init = &(struct clk_init_data){
2538                 .name = "vdec_hevc_div",
2539                 .ops = &clk_regmap_divider_ops,
2540                 .parent_hws = (const struct clk_hw *[]) {
2541                         &gxbb_vdec_hevc_sel.hw
2542                 },
2543                 .num_parents = 1,
2544                 .flags = CLK_SET_RATE_PARENT,
2545         },
2546 };
2547
2548 static struct clk_regmap gxbb_vdec_hevc = {
2549         .data = &(struct clk_regmap_gate_data){
2550                 .offset = HHI_VDEC2_CLK_CNTL,
2551                 .bit_idx = 24,
2552         },
2553         .hw.init = &(struct clk_init_data) {
2554                 .name = "vdec_hevc",
2555                 .ops = &clk_regmap_gate_ops,
2556                 .parent_hws = (const struct clk_hw *[]) {
2557                         &gxbb_vdec_hevc_div.hw
2558                 },
2559                 .num_parents = 1,
2560                 .flags = CLK_SET_RATE_PARENT,
2561         },
2562 };
2563
2564 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
2565                                     9, 10, 11, 13, 14, };
2566 static const struct clk_parent_data gen_clk_parent_data[] = {
2567         { .fw_name = "xtal", },
2568         { .hw = &gxbb_vdec_1.hw },
2569         { .hw = &gxbb_vdec_hevc.hw },
2570         { .hw = &gxbb_mpll0.hw },
2571         { .hw = &gxbb_mpll1.hw },
2572         { .hw = &gxbb_mpll2.hw },
2573         { .hw = &gxbb_fclk_div4.hw },
2574         { .hw = &gxbb_fclk_div3.hw },
2575         { .hw = &gxbb_fclk_div5.hw },
2576         { .hw = &gxbb_fclk_div7.hw },
2577         { .hw = &gxbb_gp0_pll.hw },
2578 };
2579
2580 static struct clk_regmap gxbb_gen_clk_sel = {
2581         .data = &(struct clk_regmap_mux_data){
2582                 .offset = HHI_GEN_CLK_CNTL,
2583                 .mask = 0xf,
2584                 .shift = 12,
2585                 .table = mux_table_gen_clk,
2586         },
2587         .hw.init = &(struct clk_init_data){
2588                 .name = "gen_clk_sel",
2589                 .ops = &clk_regmap_mux_ops,
2590                 /*
2591                  * bits 15:12 selects from 14 possible parents:
2592                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2593                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2594                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2595                  */
2596                 .parent_data = gen_clk_parent_data,
2597                 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2598         },
2599 };
2600
2601 static struct clk_regmap gxbb_gen_clk_div = {
2602         .data = &(struct clk_regmap_div_data){
2603                 .offset = HHI_GEN_CLK_CNTL,
2604                 .shift = 0,
2605                 .width = 11,
2606         },
2607         .hw.init = &(struct clk_init_data){
2608                 .name = "gen_clk_div",
2609                 .ops = &clk_regmap_divider_ops,
2610                 .parent_hws = (const struct clk_hw *[]) {
2611                         &gxbb_gen_clk_sel.hw
2612                 },
2613                 .num_parents = 1,
2614                 .flags = CLK_SET_RATE_PARENT,
2615         },
2616 };
2617
2618 static struct clk_regmap gxbb_gen_clk = {
2619         .data = &(struct clk_regmap_gate_data){
2620                 .offset = HHI_GEN_CLK_CNTL,
2621                 .bit_idx = 7,
2622         },
2623         .hw.init = &(struct clk_init_data){
2624                 .name = "gen_clk",
2625                 .ops = &clk_regmap_gate_ops,
2626                 .parent_hws = (const struct clk_hw *[]) {
2627                         &gxbb_gen_clk_div.hw
2628                 },
2629                 .num_parents = 1,
2630                 .flags = CLK_SET_RATE_PARENT,
2631         },
2632 };
2633
2634 #define MESON_GATE(_name, _reg, _bit) \
2635         MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2636
2637 /* Everything Else (EE) domain gates */
2638 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2639 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2640 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2641 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2642 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2643 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2644 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2645 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2646 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2647 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2648 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2649 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2650 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2651 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2652 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2653 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2654 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2655 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2656 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2657 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2658 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2659 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2660 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2661
2662 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2663 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2664 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2665 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2666 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2667 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2668 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2669 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2670 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2671 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2672 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2673 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2674 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2675 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2676 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2677 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2678 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2679
2680 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2681 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2682 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2683 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2684 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2685 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2686 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2687 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2688 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2689 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2690 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2691 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2692 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2693
2694 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2695 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2696 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2697 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2698 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2699 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2700 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2701 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2702 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2703 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2704 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2705 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2706 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2707 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2708 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2709 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2710
2711 /* Always On (AO) domain gates */
2712
2713 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2714 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2715 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2716 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2717 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2718
2719 /* AIU gates */
2720 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2721 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2722 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2723 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2724 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2725 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2726 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2727 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2728
2729 /* Array of all clocks provided by this provider */
2730
2731 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2732         .hws = {
2733                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2734                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
2735                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2736                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2737                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2738                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2739                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2740                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2741                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2742                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2743                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2744                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2745                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2746                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2747                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2748                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2749                 [CLKID_DOS]                 = &gxbb_dos.hw,
2750                 [CLKID_ISA]                 = &gxbb_isa.hw,
2751                 [CLKID_PL301]               = &gxbb_pl301.hw,
2752                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2753                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2754                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2755                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2756                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2757                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2758                 [CLKID_UART0]               = &gxbb_uart0.hw,
2759                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2760                 [CLKID_STREAM]              = &gxbb_stream.hw,
2761                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2762                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2763                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2764                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2765                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2766                 [CLKID_SPI]                 = &gxbb_spi.hw,
2767                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2768                 [CLKID_ETH]                 = &gxbb_eth.hw,
2769                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2770                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2771                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2772                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2773                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2774                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2775                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2776                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2777                 [CLKID_ADC]                 = &gxbb_adc.hw,
2778                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2779                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2780                 [CLKID_UART1]               = &gxbb_uart1.hw,
2781                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2782                 [CLKID_USB0]                = &gxbb_usb0.hw,
2783                 [CLKID_USB1]                = &gxbb_usb1.hw,
2784                 [CLKID_RESET]               = &gxbb_reset.hw,
2785                 [CLKID_NAND]                = &gxbb_nand.hw,
2786                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2787                 [CLKID_USB]                 = &gxbb_usb.hw,
2788                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2789                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2790                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2791                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2792                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2793                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2794                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2795                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2796                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2797                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2798                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2799                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2800                 [CLKID_UART2]               = &gxbb_uart2.hw,
2801                 [CLKID_SANA]                = &gxbb_sana.hw,
2802                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2803                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2804                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2805                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2806                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2807                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2808                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2809                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2810                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2811                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2812                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2813                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2814                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2815                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2816                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2817                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2818                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2819                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2820                 [CLKID_EDP]                 = &gxbb_edp.hw,
2821                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2822                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2823                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2824                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2825                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2826                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2827                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2828                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2829                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2830                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2831                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2832                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2833                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2834                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2835                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2836                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2837                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2838                 [CLKID_MALI]                = &gxbb_mali.hw,
2839                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2840                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2841                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2842                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2843                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2844                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2845                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2846                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2847                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2848                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2849                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2850                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2851                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2852                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2853                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2854                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2855                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2856                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2857                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2858                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2859                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2860                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2861                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2862                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2863                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2864                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2865                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2866                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2867                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2868                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2869                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2870                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2871                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2872                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2873                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2874                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2875                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2876                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2877                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2878                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2879                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2880                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2881                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2882                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2883                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2884                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2885                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2886                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2887                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2888                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2889                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2890                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2891                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2892                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2893                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2894                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
2895                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
2896                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2897                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
2898                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
2899                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
2900                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
2901                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
2902                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
2903                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
2904                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
2905                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
2906                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
2907                 [CLKID_VCLK]                = &gxbb_vclk.hw,
2908                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
2909                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
2910                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
2911                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
2912                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
2913                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
2914                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
2915                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
2916                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
2917                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
2918                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
2919                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
2920                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
2921                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
2922                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
2923                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
2924                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
2925                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
2926                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
2927                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
2928                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
2929                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
2930                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
2931                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
2932                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
2933                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
2934                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
2935                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
2936                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
2937                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
2938                 [NR_CLKS]                   = NULL,
2939         },
2940         .num = NR_CLKS,
2941 };
2942
2943 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2944         .hws = {
2945                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2946                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
2947                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2948                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2949                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2950                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2951                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2952                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2953                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2954                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2955                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2956                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2957                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2958                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2959                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2960                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2961                 [CLKID_DOS]                 = &gxbb_dos.hw,
2962                 [CLKID_ISA]                 = &gxbb_isa.hw,
2963                 [CLKID_PL301]               = &gxbb_pl301.hw,
2964                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2965                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2966                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2967                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2968                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2969                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2970                 [CLKID_UART0]               = &gxbb_uart0.hw,
2971                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2972                 [CLKID_STREAM]              = &gxbb_stream.hw,
2973                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2974                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2975                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2976                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2977                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2978                 [CLKID_SPI]                 = &gxbb_spi.hw,
2979                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2980                 [CLKID_ETH]                 = &gxbb_eth.hw,
2981                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2982                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2983                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2984                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2985                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2986                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2987                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2988                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2989                 [CLKID_ADC]                 = &gxbb_adc.hw,
2990                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2991                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2992                 [CLKID_UART1]               = &gxbb_uart1.hw,
2993                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2994                 [CLKID_USB0]                = &gxbb_usb0.hw,
2995                 [CLKID_USB1]                = &gxbb_usb1.hw,
2996                 [CLKID_RESET]               = &gxbb_reset.hw,
2997                 [CLKID_NAND]                = &gxbb_nand.hw,
2998                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2999                 [CLKID_USB]                 = &gxbb_usb.hw,
3000                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
3001                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
3002                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
3003                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
3004                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
3005                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
3006                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
3007                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
3008                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
3009                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
3010                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
3011                 [CLKID_DVIN]                = &gxbb_dvin.hw,
3012                 [CLKID_UART2]               = &gxbb_uart2.hw,
3013                 [CLKID_SANA]                = &gxbb_sana.hw,
3014                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
3015                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
3016                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
3017                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
3018                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
3019                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
3020                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
3021                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
3022                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
3023                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
3024                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
3025                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
3026                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
3027                 [CLKID_RNG1]                = &gxbb_rng1.hw,
3028                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
3029                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
3030                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
3031                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
3032                 [CLKID_EDP]                 = &gxbb_edp.hw,
3033                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
3034                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
3035                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
3036                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
3037                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
3038                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
3039                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
3040                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
3041                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
3042                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
3043                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
3044                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
3045                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
3046                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
3047                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
3048                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
3049                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
3050                 [CLKID_MALI]                = &gxbb_mali.hw,
3051                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
3052                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
3053                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
3054                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
3055                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3056                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3057                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
3058                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
3059                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
3060                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
3061                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3062                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3063                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
3064                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3065                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3066                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
3067                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3068                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3069                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
3070                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
3071                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
3072                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
3073                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
3074                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
3075                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
3076                 [CLKID_VPU]                 = &gxbb_vpu.hw,
3077                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
3078                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
3079                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
3080                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
3081                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
3082                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
3083                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
3084                 [CLKID_VAPB]                = &gxbb_vapb.hw,
3085                 [CLKID_MPLL0_DIV]           = &gxl_mpll0_div.hw,
3086                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
3087                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
3088                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
3089                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
3090                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
3091                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
3092                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
3093                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
3094                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
3095                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
3096                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
3097                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
3098                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
3099                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
3100                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
3101                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
3102                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
3103                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
3104                 [CLKID_HDMI_PLL_DCO]        = &gxl_hdmi_pll_dco.hw,
3105                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
3106                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
3107                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
3108                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
3109                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
3110                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
3111                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
3112                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
3113                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
3114                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
3115                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
3116                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
3117                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
3118                 [CLKID_VCLK]                = &gxbb_vclk.hw,
3119                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
3120                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
3121                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
3122                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
3123                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
3124                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
3125                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
3126                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
3127                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
3128                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
3129                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
3130                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
3131                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
3132                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
3133                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
3134                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
3135                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
3136                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
3137                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
3138                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
3139                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
3140                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
3141                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
3142                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
3143                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
3144                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
3145                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
3146                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
3147                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
3148                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
3149                 [CLKID_ACODEC]              = &gxl_acodec.hw,
3150                 [NR_CLKS]                   = NULL,
3151         },
3152         .num = NR_CLKS,
3153 };
3154
3155 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3156         &gxbb_clk81,
3157         &gxbb_ddr,
3158         &gxbb_dos,
3159         &gxbb_isa,
3160         &gxbb_pl301,
3161         &gxbb_periphs,
3162         &gxbb_spicc,
3163         &gxbb_i2c,
3164         &gxbb_sar_adc,
3165         &gxbb_smart_card,
3166         &gxbb_rng0,
3167         &gxbb_uart0,
3168         &gxbb_sdhc,
3169         &gxbb_stream,
3170         &gxbb_async_fifo,
3171         &gxbb_sdio,
3172         &gxbb_abuf,
3173         &gxbb_hiu_iface,
3174         &gxbb_assist_misc,
3175         &gxbb_spi,
3176         &gxbb_i2s_spdif,
3177         &gxbb_eth,
3178         &gxbb_demux,
3179         &gxbb_aiu_glue,
3180         &gxbb_iec958,
3181         &gxbb_i2s_out,
3182         &gxbb_amclk,
3183         &gxbb_aififo2,
3184         &gxbb_mixer,
3185         &gxbb_mixer_iface,
3186         &gxbb_adc,
3187         &gxbb_blkmv,
3188         &gxbb_aiu,
3189         &gxbb_uart1,
3190         &gxbb_g2d,
3191         &gxbb_usb0,
3192         &gxbb_usb1,
3193         &gxbb_reset,
3194         &gxbb_nand,
3195         &gxbb_dos_parser,
3196         &gxbb_usb,
3197         &gxbb_vdin1,
3198         &gxbb_ahb_arb0,
3199         &gxbb_efuse,
3200         &gxbb_boot_rom,
3201         &gxbb_ahb_data_bus,
3202         &gxbb_ahb_ctrl_bus,
3203         &gxbb_hdmi_intr_sync,
3204         &gxbb_hdmi_pclk,
3205         &gxbb_usb1_ddr_bridge,
3206         &gxbb_usb0_ddr_bridge,
3207         &gxbb_mmc_pclk,
3208         &gxbb_dvin,
3209         &gxbb_uart2,
3210         &gxbb_sana,
3211         &gxbb_vpu_intr,
3212         &gxbb_sec_ahb_ahb3_bridge,
3213         &gxbb_clk81_a53,
3214         &gxbb_vclk2_venci0,
3215         &gxbb_vclk2_venci1,
3216         &gxbb_vclk2_vencp0,
3217         &gxbb_vclk2_vencp1,
3218         &gxbb_gclk_venci_int0,
3219         &gxbb_gclk_vencp_int,
3220         &gxbb_dac_clk,
3221         &gxbb_aoclk_gate,
3222         &gxbb_iec958_gate,
3223         &gxbb_enc480p,
3224         &gxbb_rng1,
3225         &gxbb_gclk_venci_int1,
3226         &gxbb_vclk2_venclmcc,
3227         &gxbb_vclk2_vencl,
3228         &gxbb_vclk_other,
3229         &gxbb_edp,
3230         &gxbb_ao_media_cpu,
3231         &gxbb_ao_ahb_sram,
3232         &gxbb_ao_ahb_bus,
3233         &gxbb_ao_iface,
3234         &gxbb_ao_i2c,
3235         &gxbb_emmc_a,
3236         &gxbb_emmc_b,
3237         &gxbb_emmc_c,
3238         &gxbb_sar_adc_clk,
3239         &gxbb_mali_0,
3240         &gxbb_mali_1,
3241         &gxbb_cts_amclk,
3242         &gxbb_cts_mclk_i958,
3243         &gxbb_32k_clk,
3244         &gxbb_sd_emmc_a_clk0,
3245         &gxbb_sd_emmc_b_clk0,
3246         &gxbb_sd_emmc_c_clk0,
3247         &gxbb_vpu_0,
3248         &gxbb_vpu_1,
3249         &gxbb_vapb_0,
3250         &gxbb_vapb_1,
3251         &gxbb_vapb,
3252         &gxbb_mpeg_clk_div,
3253         &gxbb_sar_adc_clk_div,
3254         &gxbb_mali_0_div,
3255         &gxbb_mali_1_div,
3256         &gxbb_cts_mclk_i958_div,
3257         &gxbb_32k_clk_div,
3258         &gxbb_sd_emmc_a_clk0_div,
3259         &gxbb_sd_emmc_b_clk0_div,
3260         &gxbb_sd_emmc_c_clk0_div,
3261         &gxbb_vpu_0_div,
3262         &gxbb_vpu_1_div,
3263         &gxbb_vapb_0_div,
3264         &gxbb_vapb_1_div,
3265         &gxbb_mpeg_clk_sel,
3266         &gxbb_sar_adc_clk_sel,
3267         &gxbb_mali_0_sel,
3268         &gxbb_mali_1_sel,
3269         &gxbb_mali,
3270         &gxbb_cts_amclk_sel,
3271         &gxbb_cts_mclk_i958_sel,
3272         &gxbb_cts_i958,
3273         &gxbb_32k_clk_sel,
3274         &gxbb_sd_emmc_a_clk0_sel,
3275         &gxbb_sd_emmc_b_clk0_sel,
3276         &gxbb_sd_emmc_c_clk0_sel,
3277         &gxbb_vpu_0_sel,
3278         &gxbb_vpu_1_sel,
3279         &gxbb_vpu,
3280         &gxbb_vapb_0_sel,
3281         &gxbb_vapb_1_sel,
3282         &gxbb_vapb_sel,
3283         &gxbb_mpll0,
3284         &gxbb_mpll1,
3285         &gxbb_mpll2,
3286         &gxbb_mpll0_div,
3287         &gxbb_mpll1_div,
3288         &gxbb_mpll2_div,
3289         &gxbb_cts_amclk_div,
3290         &gxbb_fixed_pll,
3291         &gxbb_sys_pll,
3292         &gxbb_mpll_prediv,
3293         &gxbb_fclk_div2,
3294         &gxbb_fclk_div3,
3295         &gxbb_fclk_div4,
3296         &gxbb_fclk_div5,
3297         &gxbb_fclk_div7,
3298         &gxbb_vdec_1_sel,
3299         &gxbb_vdec_1_div,
3300         &gxbb_vdec_1,
3301         &gxbb_vdec_hevc_sel,
3302         &gxbb_vdec_hevc_div,
3303         &gxbb_vdec_hevc,
3304         &gxbb_gen_clk_sel,
3305         &gxbb_gen_clk_div,
3306         &gxbb_gen_clk,
3307         &gxbb_fixed_pll_dco,
3308         &gxbb_sys_pll_dco,
3309         &gxbb_gp0_pll,
3310         &gxbb_vid_pll,
3311         &gxbb_vid_pll_sel,
3312         &gxbb_vid_pll_div,
3313         &gxbb_vclk,
3314         &gxbb_vclk_sel,
3315         &gxbb_vclk_div,
3316         &gxbb_vclk_input,
3317         &gxbb_vclk_div1,
3318         &gxbb_vclk_div2_en,
3319         &gxbb_vclk_div4_en,
3320         &gxbb_vclk_div6_en,
3321         &gxbb_vclk_div12_en,
3322         &gxbb_vclk2,
3323         &gxbb_vclk2_sel,
3324         &gxbb_vclk2_div,
3325         &gxbb_vclk2_input,
3326         &gxbb_vclk2_div1,
3327         &gxbb_vclk2_div2_en,
3328         &gxbb_vclk2_div4_en,
3329         &gxbb_vclk2_div6_en,
3330         &gxbb_vclk2_div12_en,
3331         &gxbb_cts_enci,
3332         &gxbb_cts_enci_sel,
3333         &gxbb_cts_encp,
3334         &gxbb_cts_encp_sel,
3335         &gxbb_cts_vdac,
3336         &gxbb_cts_vdac_sel,
3337         &gxbb_hdmi_tx,
3338         &gxbb_hdmi_tx_sel,
3339         &gxbb_hdmi_sel,
3340         &gxbb_hdmi_div,
3341         &gxbb_hdmi,
3342         &gxbb_gp0_pll_dco,
3343         &gxbb_hdmi_pll,
3344         &gxbb_hdmi_pll_od,
3345         &gxbb_hdmi_pll_od2,
3346         &gxbb_hdmi_pll_dco,
3347 };
3348
3349 static struct clk_regmap *const gxl_clk_regmaps[] = {
3350         &gxbb_clk81,
3351         &gxbb_ddr,
3352         &gxbb_dos,
3353         &gxbb_isa,
3354         &gxbb_pl301,
3355         &gxbb_periphs,
3356         &gxbb_spicc,
3357         &gxbb_i2c,
3358         &gxbb_sar_adc,
3359         &gxbb_smart_card,
3360         &gxbb_rng0,
3361         &gxbb_uart0,
3362         &gxbb_sdhc,
3363         &gxbb_stream,
3364         &gxbb_async_fifo,
3365         &gxbb_sdio,
3366         &gxbb_abuf,
3367         &gxbb_hiu_iface,
3368         &gxbb_assist_misc,
3369         &gxbb_spi,
3370         &gxbb_i2s_spdif,
3371         &gxbb_eth,
3372         &gxbb_demux,
3373         &gxbb_aiu_glue,
3374         &gxbb_iec958,
3375         &gxbb_i2s_out,
3376         &gxbb_amclk,
3377         &gxbb_aififo2,
3378         &gxbb_mixer,
3379         &gxbb_mixer_iface,
3380         &gxbb_adc,
3381         &gxbb_blkmv,
3382         &gxbb_aiu,
3383         &gxbb_uart1,
3384         &gxbb_g2d,
3385         &gxbb_usb0,
3386         &gxbb_usb1,
3387         &gxbb_reset,
3388         &gxbb_nand,
3389         &gxbb_dos_parser,
3390         &gxbb_usb,
3391         &gxbb_vdin1,
3392         &gxbb_ahb_arb0,
3393         &gxbb_efuse,
3394         &gxbb_boot_rom,
3395         &gxbb_ahb_data_bus,
3396         &gxbb_ahb_ctrl_bus,
3397         &gxbb_hdmi_intr_sync,
3398         &gxbb_hdmi_pclk,
3399         &gxbb_usb1_ddr_bridge,
3400         &gxbb_usb0_ddr_bridge,
3401         &gxbb_mmc_pclk,
3402         &gxbb_dvin,
3403         &gxbb_uart2,
3404         &gxbb_sana,
3405         &gxbb_vpu_intr,
3406         &gxbb_sec_ahb_ahb3_bridge,
3407         &gxbb_clk81_a53,
3408         &gxbb_vclk2_venci0,
3409         &gxbb_vclk2_venci1,
3410         &gxbb_vclk2_vencp0,
3411         &gxbb_vclk2_vencp1,
3412         &gxbb_gclk_venci_int0,
3413         &gxbb_gclk_vencp_int,
3414         &gxbb_dac_clk,
3415         &gxbb_aoclk_gate,
3416         &gxbb_iec958_gate,
3417         &gxbb_enc480p,
3418         &gxbb_rng1,
3419         &gxbb_gclk_venci_int1,
3420         &gxbb_vclk2_venclmcc,
3421         &gxbb_vclk2_vencl,
3422         &gxbb_vclk_other,
3423         &gxbb_edp,
3424         &gxbb_ao_media_cpu,
3425         &gxbb_ao_ahb_sram,
3426         &gxbb_ao_ahb_bus,
3427         &gxbb_ao_iface,
3428         &gxbb_ao_i2c,
3429         &gxbb_emmc_a,
3430         &gxbb_emmc_b,
3431         &gxbb_emmc_c,
3432         &gxbb_sar_adc_clk,
3433         &gxbb_mali_0,
3434         &gxbb_mali_1,
3435         &gxbb_cts_amclk,
3436         &gxbb_cts_mclk_i958,
3437         &gxbb_32k_clk,
3438         &gxbb_sd_emmc_a_clk0,
3439         &gxbb_sd_emmc_b_clk0,
3440         &gxbb_sd_emmc_c_clk0,
3441         &gxbb_vpu_0,
3442         &gxbb_vpu_1,
3443         &gxbb_vapb_0,
3444         &gxbb_vapb_1,
3445         &gxbb_vapb,
3446         &gxbb_mpeg_clk_div,
3447         &gxbb_sar_adc_clk_div,
3448         &gxbb_mali_0_div,
3449         &gxbb_mali_1_div,
3450         &gxbb_cts_mclk_i958_div,
3451         &gxbb_32k_clk_div,
3452         &gxbb_sd_emmc_a_clk0_div,
3453         &gxbb_sd_emmc_b_clk0_div,
3454         &gxbb_sd_emmc_c_clk0_div,
3455         &gxbb_vpu_0_div,
3456         &gxbb_vpu_1_div,
3457         &gxbb_vapb_0_div,
3458         &gxbb_vapb_1_div,
3459         &gxbb_mpeg_clk_sel,
3460         &gxbb_sar_adc_clk_sel,
3461         &gxbb_mali_0_sel,
3462         &gxbb_mali_1_sel,
3463         &gxbb_mali,
3464         &gxbb_cts_amclk_sel,
3465         &gxbb_cts_mclk_i958_sel,
3466         &gxbb_cts_i958,
3467         &gxbb_32k_clk_sel,
3468         &gxbb_sd_emmc_a_clk0_sel,
3469         &gxbb_sd_emmc_b_clk0_sel,
3470         &gxbb_sd_emmc_c_clk0_sel,
3471         &gxbb_vpu_0_sel,
3472         &gxbb_vpu_1_sel,
3473         &gxbb_vpu,
3474         &gxbb_vapb_0_sel,
3475         &gxbb_vapb_1_sel,
3476         &gxbb_vapb_sel,
3477         &gxbb_mpll0,
3478         &gxbb_mpll1,
3479         &gxbb_mpll2,
3480         &gxl_mpll0_div,
3481         &gxbb_mpll1_div,
3482         &gxbb_mpll2_div,
3483         &gxbb_cts_amclk_div,
3484         &gxbb_fixed_pll,
3485         &gxbb_sys_pll,
3486         &gxbb_mpll_prediv,
3487         &gxbb_fclk_div2,
3488         &gxbb_fclk_div3,
3489         &gxbb_fclk_div4,
3490         &gxbb_fclk_div5,
3491         &gxbb_fclk_div7,
3492         &gxbb_vdec_1_sel,
3493         &gxbb_vdec_1_div,
3494         &gxbb_vdec_1,
3495         &gxbb_vdec_hevc_sel,
3496         &gxbb_vdec_hevc_div,
3497         &gxbb_vdec_hevc,
3498         &gxbb_gen_clk_sel,
3499         &gxbb_gen_clk_div,
3500         &gxbb_gen_clk,
3501         &gxbb_fixed_pll_dco,
3502         &gxbb_sys_pll_dco,
3503         &gxbb_gp0_pll,
3504         &gxbb_vid_pll,
3505         &gxbb_vid_pll_sel,
3506         &gxbb_vid_pll_div,
3507         &gxbb_vclk,
3508         &gxbb_vclk_sel,
3509         &gxbb_vclk_div,
3510         &gxbb_vclk_input,
3511         &gxbb_vclk_div1,
3512         &gxbb_vclk_div2_en,
3513         &gxbb_vclk_div4_en,
3514         &gxbb_vclk_div6_en,
3515         &gxbb_vclk_div12_en,
3516         &gxbb_vclk2,
3517         &gxbb_vclk2_sel,
3518         &gxbb_vclk2_div,
3519         &gxbb_vclk2_input,
3520         &gxbb_vclk2_div1,
3521         &gxbb_vclk2_div2_en,
3522         &gxbb_vclk2_div4_en,
3523         &gxbb_vclk2_div6_en,
3524         &gxbb_vclk2_div12_en,
3525         &gxbb_cts_enci,
3526         &gxbb_cts_enci_sel,
3527         &gxbb_cts_encp,
3528         &gxbb_cts_encp_sel,
3529         &gxbb_cts_vdac,
3530         &gxbb_cts_vdac_sel,
3531         &gxbb_hdmi_tx,
3532         &gxbb_hdmi_tx_sel,
3533         &gxbb_hdmi_sel,
3534         &gxbb_hdmi_div,
3535         &gxbb_hdmi,
3536         &gxl_gp0_pll_dco,
3537         &gxl_hdmi_pll,
3538         &gxl_hdmi_pll_od,
3539         &gxl_hdmi_pll_od2,
3540         &gxl_hdmi_pll_dco,
3541         &gxl_acodec,
3542 };
3543
3544 static const struct meson_eeclkc_data gxbb_clkc_data = {
3545         .regmap_clks = gxbb_clk_regmaps,
3546         .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3547         .hw_onecell_data = &gxbb_hw_onecell_data,
3548 };
3549
3550 static const struct meson_eeclkc_data gxl_clkc_data = {
3551         .regmap_clks = gxl_clk_regmaps,
3552         .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3553         .hw_onecell_data = &gxl_hw_onecell_data,
3554 };
3555
3556 static const struct of_device_id clkc_match_table[] = {
3557         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3558         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3559         {},
3560 };
3561 MODULE_DEVICE_TABLE(of, clkc_match_table);
3562
3563 static struct platform_driver gxbb_driver = {
3564         .probe          = meson_eeclkc_probe,
3565         .driver         = {
3566                 .name   = "gxbb-clkc",
3567                 .of_match_table = clkc_match_table,
3568         },
3569 };
3570
3571 module_platform_driver(gxbb_driver);
3572 MODULE_LICENSE("GPL v2");