1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
21 #include "clk-regmap.h"
22 #include "clk-cpu-dyndiv.h"
23 #include "vid-pll-div.h"
24 #include "meson-eeclk.h"
27 static DEFINE_SPINLOCK(meson_clk_lock);
29 static struct clk_regmap g12a_fixed_pll_dco = {
30 .data = &(struct meson_clk_pll_data){
32 .reg_off = HHI_FIX_PLL_CNTL0,
37 .reg_off = HHI_FIX_PLL_CNTL0,
42 .reg_off = HHI_FIX_PLL_CNTL0,
47 .reg_off = HHI_FIX_PLL_CNTL1,
52 .reg_off = HHI_FIX_PLL_CNTL0,
57 .reg_off = HHI_FIX_PLL_CNTL0,
62 .hw.init = &(struct clk_init_data){
63 .name = "fixed_pll_dco",
64 .ops = &meson_clk_pll_ro_ops,
65 .parent_data = &(const struct clk_parent_data) {
72 static struct clk_regmap g12a_fixed_pll = {
73 .data = &(struct clk_regmap_div_data){
74 .offset = HHI_FIX_PLL_CNTL0,
77 .flags = CLK_DIVIDER_POWER_OF_TWO,
79 .hw.init = &(struct clk_init_data){
81 .ops = &clk_regmap_divider_ro_ops,
82 .parent_hws = (const struct clk_hw *[]) {
83 &g12a_fixed_pll_dco.hw
87 * This clock won't ever change at runtime so
88 * CLK_SET_RATE_PARENT is not required
93 static const struct pll_mult_range g12a_sys_pll_mult_range = {
98 static struct clk_regmap g12a_sys_pll_dco = {
99 .data = &(struct meson_clk_pll_data){
101 .reg_off = HHI_SYS_PLL_CNTL0,
106 .reg_off = HHI_SYS_PLL_CNTL0,
111 .reg_off = HHI_SYS_PLL_CNTL0,
116 .reg_off = HHI_SYS_PLL_CNTL0,
121 .reg_off = HHI_SYS_PLL_CNTL0,
125 .range = &g12a_sys_pll_mult_range,
127 .hw.init = &(struct clk_init_data){
128 .name = "sys_pll_dco",
129 .ops = &meson_clk_pll_ops,
130 .parent_data = &(const struct clk_parent_data) {
134 /* This clock feeds the CPU, avoid disabling it */
135 .flags = CLK_IS_CRITICAL,
139 static struct clk_regmap g12a_sys_pll = {
140 .data = &(struct clk_regmap_div_data){
141 .offset = HHI_SYS_PLL_CNTL0,
144 .flags = CLK_DIVIDER_POWER_OF_TWO,
146 .hw.init = &(struct clk_init_data){
148 .ops = &clk_regmap_divider_ops,
149 .parent_hws = (const struct clk_hw *[]) {
153 .flags = CLK_SET_RATE_PARENT,
157 static struct clk_regmap g12b_sys1_pll_dco = {
158 .data = &(struct meson_clk_pll_data){
160 .reg_off = HHI_SYS1_PLL_CNTL0,
165 .reg_off = HHI_SYS1_PLL_CNTL0,
170 .reg_off = HHI_SYS1_PLL_CNTL0,
175 .reg_off = HHI_SYS1_PLL_CNTL0,
180 .reg_off = HHI_SYS1_PLL_CNTL0,
184 .range = &g12a_sys_pll_mult_range,
186 .hw.init = &(struct clk_init_data){
187 .name = "sys1_pll_dco",
188 .ops = &meson_clk_pll_ops,
189 .parent_data = &(const struct clk_parent_data) {
193 /* This clock feeds the CPU, avoid disabling it */
194 .flags = CLK_IS_CRITICAL,
198 static struct clk_regmap g12b_sys1_pll = {
199 .data = &(struct clk_regmap_div_data){
200 .offset = HHI_SYS1_PLL_CNTL0,
203 .flags = CLK_DIVIDER_POWER_OF_TWO,
205 .hw.init = &(struct clk_init_data){
207 .ops = &clk_regmap_divider_ops,
208 .parent_hws = (const struct clk_hw *[]) {
209 &g12b_sys1_pll_dco.hw
212 .flags = CLK_SET_RATE_PARENT,
216 static struct clk_regmap g12a_sys_pll_div16_en = {
217 .data = &(struct clk_regmap_gate_data){
218 .offset = HHI_SYS_CPU_CLK_CNTL1,
221 .hw.init = &(struct clk_init_data) {
222 .name = "sys_pll_div16_en",
223 .ops = &clk_regmap_gate_ro_ops,
224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
227 * This clock is used to debug the sys_pll range
228 * Linux should not change it at runtime
233 static struct clk_regmap g12b_sys1_pll_div16_en = {
234 .data = &(struct clk_regmap_gate_data){
235 .offset = HHI_SYS_CPUB_CLK_CNTL1,
238 .hw.init = &(struct clk_init_data) {
239 .name = "sys1_pll_div16_en",
240 .ops = &clk_regmap_gate_ro_ops,
241 .parent_hws = (const struct clk_hw *[]) {
246 * This clock is used to debug the sys_pll range
247 * Linux should not change it at runtime
252 static struct clk_fixed_factor g12a_sys_pll_div16 = {
255 .hw.init = &(struct clk_init_data){
256 .name = "sys_pll_div16",
257 .ops = &clk_fixed_factor_ops,
258 .parent_hws = (const struct clk_hw *[]) {
259 &g12a_sys_pll_div16_en.hw
265 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
268 .hw.init = &(struct clk_init_data){
269 .name = "sys1_pll_div16",
270 .ops = &clk_fixed_factor_ops,
271 .parent_hws = (const struct clk_hw *[]) {
272 &g12b_sys1_pll_div16_en.hw
278 static struct clk_fixed_factor g12a_fclk_div2_div = {
281 .hw.init = &(struct clk_init_data){
282 .name = "fclk_div2_div",
283 .ops = &clk_fixed_factor_ops,
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
289 static struct clk_regmap g12a_fclk_div2 = {
290 .data = &(struct clk_regmap_gate_data){
291 .offset = HHI_FIX_PLL_CNTL1,
294 .hw.init = &(struct clk_init_data){
296 .ops = &clk_regmap_gate_ops,
297 .parent_hws = (const struct clk_hw *[]) {
298 &g12a_fclk_div2_div.hw
302 * Similar to fclk_div3, it seems that this clock is used by
303 * the resident firmware and is required by the platform to
305 * Until the following condition are met, we need this clock to
306 * be marked as critical:
307 * a) Mark the clock used by a firmware resource, if possible
308 * b) CCF has a clock hand-off mechanism to make the sure the
309 * clock stays on until the proper driver comes along
311 .flags = CLK_IS_CRITICAL,
315 static struct clk_fixed_factor g12a_fclk_div3_div = {
318 .hw.init = &(struct clk_init_data){
319 .name = "fclk_div3_div",
320 .ops = &clk_fixed_factor_ops,
321 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
326 static struct clk_regmap g12a_fclk_div3 = {
327 .data = &(struct clk_regmap_gate_data){
328 .offset = HHI_FIX_PLL_CNTL1,
331 .hw.init = &(struct clk_init_data){
333 .ops = &clk_regmap_gate_ops,
334 .parent_hws = (const struct clk_hw *[]) {
335 &g12a_fclk_div3_div.hw
339 * This clock is used by the resident firmware and is required
340 * by the platform to operate correctly.
341 * Until the following condition are met, we need this clock to
342 * be marked as critical:
343 * a) Mark the clock used by a firmware resource, if possible
344 * b) CCF has a clock hand-off mechanism to make the sure the
345 * clock stays on until the proper driver comes along
347 .flags = CLK_IS_CRITICAL,
351 /* Datasheet names this field as "premux0" */
352 static struct clk_regmap g12a_cpu_clk_premux0 = {
353 .data = &(struct clk_regmap_mux_data){
354 .offset = HHI_SYS_CPU_CLK_CNTL0,
357 .flags = CLK_MUX_ROUND_CLOSEST,
359 .hw.init = &(struct clk_init_data){
360 .name = "cpu_clk_dyn0_sel",
361 .ops = &clk_regmap_mux_ops,
362 .parent_data = (const struct clk_parent_data []) {
363 { .fw_name = "xtal", },
364 { .hw = &g12a_fclk_div2.hw },
365 { .hw = &g12a_fclk_div3.hw },
368 .flags = CLK_SET_RATE_PARENT,
372 /* Datasheet names this field as "premux1" */
373 static struct clk_regmap g12a_cpu_clk_premux1 = {
374 .data = &(struct clk_regmap_mux_data){
375 .offset = HHI_SYS_CPU_CLK_CNTL0,
379 .hw.init = &(struct clk_init_data){
380 .name = "cpu_clk_dyn1_sel",
381 .ops = &clk_regmap_mux_ops,
382 .parent_data = (const struct clk_parent_data []) {
383 { .fw_name = "xtal", },
384 { .hw = &g12a_fclk_div2.hw },
385 { .hw = &g12a_fclk_div3.hw },
388 /* This sub-tree is used a parking clock */
389 .flags = CLK_SET_RATE_NO_REPARENT
393 /* Datasheet names this field as "mux0_divn_tcnt" */
394 static struct clk_regmap g12a_cpu_clk_mux0_div = {
395 .data = &(struct meson_clk_cpu_dyndiv_data){
397 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
402 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
407 .hw.init = &(struct clk_init_data){
408 .name = "cpu_clk_dyn0_div",
409 .ops = &meson_clk_cpu_dyndiv_ops,
410 .parent_hws = (const struct clk_hw *[]) {
411 &g12a_cpu_clk_premux0.hw
414 .flags = CLK_SET_RATE_PARENT,
418 /* Datasheet names this field as "postmux0" */
419 static struct clk_regmap g12a_cpu_clk_postmux0 = {
420 .data = &(struct clk_regmap_mux_data){
421 .offset = HHI_SYS_CPU_CLK_CNTL0,
424 .flags = CLK_MUX_ROUND_CLOSEST,
426 .hw.init = &(struct clk_init_data){
427 .name = "cpu_clk_dyn0",
428 .ops = &clk_regmap_mux_ops,
429 .parent_hws = (const struct clk_hw *[]) {
430 &g12a_cpu_clk_premux0.hw,
431 &g12a_cpu_clk_mux0_div.hw,
434 .flags = CLK_SET_RATE_PARENT,
438 /* Datasheet names this field as "Mux1_divn_tcnt" */
439 static struct clk_regmap g12a_cpu_clk_mux1_div = {
440 .data = &(struct clk_regmap_div_data){
441 .offset = HHI_SYS_CPU_CLK_CNTL0,
445 .hw.init = &(struct clk_init_data){
446 .name = "cpu_clk_dyn1_div",
447 .ops = &clk_regmap_divider_ro_ops,
448 .parent_hws = (const struct clk_hw *[]) {
449 &g12a_cpu_clk_premux1.hw
455 /* Datasheet names this field as "postmux1" */
456 static struct clk_regmap g12a_cpu_clk_postmux1 = {
457 .data = &(struct clk_regmap_mux_data){
458 .offset = HHI_SYS_CPU_CLK_CNTL0,
462 .hw.init = &(struct clk_init_data){
463 .name = "cpu_clk_dyn1",
464 .ops = &clk_regmap_mux_ops,
465 .parent_hws = (const struct clk_hw *[]) {
466 &g12a_cpu_clk_premux1.hw,
467 &g12a_cpu_clk_mux1_div.hw,
470 /* This sub-tree is used a parking clock */
471 .flags = CLK_SET_RATE_NO_REPARENT,
475 /* Datasheet names this field as "Final_dyn_mux_sel" */
476 static struct clk_regmap g12a_cpu_clk_dyn = {
477 .data = &(struct clk_regmap_mux_data){
478 .offset = HHI_SYS_CPU_CLK_CNTL0,
481 .flags = CLK_MUX_ROUND_CLOSEST,
483 .hw.init = &(struct clk_init_data){
484 .name = "cpu_clk_dyn",
485 .ops = &clk_regmap_mux_ops,
486 .parent_hws = (const struct clk_hw *[]) {
487 &g12a_cpu_clk_postmux0.hw,
488 &g12a_cpu_clk_postmux1.hw,
491 .flags = CLK_SET_RATE_PARENT,
495 /* Datasheet names this field as "Final_mux_sel" */
496 static struct clk_regmap g12a_cpu_clk = {
497 .data = &(struct clk_regmap_mux_data){
498 .offset = HHI_SYS_CPU_CLK_CNTL0,
501 .flags = CLK_MUX_ROUND_CLOSEST,
503 .hw.init = &(struct clk_init_data){
505 .ops = &clk_regmap_mux_ops,
506 .parent_hws = (const struct clk_hw *[]) {
507 &g12a_cpu_clk_dyn.hw,
511 .flags = CLK_SET_RATE_PARENT,
515 /* Datasheet names this field as "Final_mux_sel" */
516 static struct clk_regmap g12b_cpu_clk = {
517 .data = &(struct clk_regmap_mux_data){
518 .offset = HHI_SYS_CPU_CLK_CNTL0,
521 .flags = CLK_MUX_ROUND_CLOSEST,
523 .hw.init = &(struct clk_init_data){
525 .ops = &clk_regmap_mux_ops,
526 .parent_hws = (const struct clk_hw *[]) {
527 &g12a_cpu_clk_dyn.hw,
531 .flags = CLK_SET_RATE_PARENT,
535 /* Datasheet names this field as "premux0" */
536 static struct clk_regmap g12b_cpub_clk_premux0 = {
537 .data = &(struct clk_regmap_mux_data){
538 .offset = HHI_SYS_CPUB_CLK_CNTL,
541 .flags = CLK_MUX_ROUND_CLOSEST,
543 .hw.init = &(struct clk_init_data){
544 .name = "cpub_clk_dyn0_sel",
545 .ops = &clk_regmap_mux_ops,
546 .parent_data = (const struct clk_parent_data []) {
547 { .fw_name = "xtal", },
548 { .hw = &g12a_fclk_div2.hw },
549 { .hw = &g12a_fclk_div3.hw },
552 .flags = CLK_SET_RATE_PARENT,
556 /* Datasheet names this field as "mux0_divn_tcnt" */
557 static struct clk_regmap g12b_cpub_clk_mux0_div = {
558 .data = &(struct meson_clk_cpu_dyndiv_data){
560 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
565 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
570 .hw.init = &(struct clk_init_data){
571 .name = "cpub_clk_dyn0_div",
572 .ops = &meson_clk_cpu_dyndiv_ops,
573 .parent_hws = (const struct clk_hw *[]) {
574 &g12b_cpub_clk_premux0.hw
577 .flags = CLK_SET_RATE_PARENT,
581 /* Datasheet names this field as "postmux0" */
582 static struct clk_regmap g12b_cpub_clk_postmux0 = {
583 .data = &(struct clk_regmap_mux_data){
584 .offset = HHI_SYS_CPUB_CLK_CNTL,
587 .flags = CLK_MUX_ROUND_CLOSEST,
589 .hw.init = &(struct clk_init_data){
590 .name = "cpub_clk_dyn0",
591 .ops = &clk_regmap_mux_ops,
592 .parent_hws = (const struct clk_hw *[]) {
593 &g12b_cpub_clk_premux0.hw,
594 &g12b_cpub_clk_mux0_div.hw
597 .flags = CLK_SET_RATE_PARENT,
601 /* Datasheet names this field as "premux1" */
602 static struct clk_regmap g12b_cpub_clk_premux1 = {
603 .data = &(struct clk_regmap_mux_data){
604 .offset = HHI_SYS_CPUB_CLK_CNTL,
608 .hw.init = &(struct clk_init_data){
609 .name = "cpub_clk_dyn1_sel",
610 .ops = &clk_regmap_mux_ops,
611 .parent_data = (const struct clk_parent_data []) {
612 { .fw_name = "xtal", },
613 { .hw = &g12a_fclk_div2.hw },
614 { .hw = &g12a_fclk_div3.hw },
617 /* This sub-tree is used a parking clock */
618 .flags = CLK_SET_RATE_NO_REPARENT,
622 /* Datasheet names this field as "Mux1_divn_tcnt" */
623 static struct clk_regmap g12b_cpub_clk_mux1_div = {
624 .data = &(struct clk_regmap_div_data){
625 .offset = HHI_SYS_CPUB_CLK_CNTL,
629 .hw.init = &(struct clk_init_data){
630 .name = "cpub_clk_dyn1_div",
631 .ops = &clk_regmap_divider_ro_ops,
632 .parent_hws = (const struct clk_hw *[]) {
633 &g12b_cpub_clk_premux1.hw
639 /* Datasheet names this field as "postmux1" */
640 static struct clk_regmap g12b_cpub_clk_postmux1 = {
641 .data = &(struct clk_regmap_mux_data){
642 .offset = HHI_SYS_CPUB_CLK_CNTL,
646 .hw.init = &(struct clk_init_data){
647 .name = "cpub_clk_dyn1",
648 .ops = &clk_regmap_mux_ops,
649 .parent_hws = (const struct clk_hw *[]) {
650 &g12b_cpub_clk_premux1.hw,
651 &g12b_cpub_clk_mux1_div.hw
654 /* This sub-tree is used a parking clock */
655 .flags = CLK_SET_RATE_NO_REPARENT,
659 /* Datasheet names this field as "Final_dyn_mux_sel" */
660 static struct clk_regmap g12b_cpub_clk_dyn = {
661 .data = &(struct clk_regmap_mux_data){
662 .offset = HHI_SYS_CPUB_CLK_CNTL,
665 .flags = CLK_MUX_ROUND_CLOSEST,
667 .hw.init = &(struct clk_init_data){
668 .name = "cpub_clk_dyn",
669 .ops = &clk_regmap_mux_ops,
670 .parent_hws = (const struct clk_hw *[]) {
671 &g12b_cpub_clk_postmux0.hw,
672 &g12b_cpub_clk_postmux1.hw
675 .flags = CLK_SET_RATE_PARENT,
679 /* Datasheet names this field as "Final_mux_sel" */
680 static struct clk_regmap g12b_cpub_clk = {
681 .data = &(struct clk_regmap_mux_data){
682 .offset = HHI_SYS_CPUB_CLK_CNTL,
685 .flags = CLK_MUX_ROUND_CLOSEST,
687 .hw.init = &(struct clk_init_data){
689 .ops = &clk_regmap_mux_ops,
690 .parent_hws = (const struct clk_hw *[]) {
691 &g12b_cpub_clk_dyn.hw,
695 .flags = CLK_SET_RATE_PARENT,
699 static struct clk_regmap sm1_gp1_pll;
701 /* Datasheet names this field as "premux0" */
702 static struct clk_regmap sm1_dsu_clk_premux0 = {
703 .data = &(struct clk_regmap_mux_data){
704 .offset = HHI_SYS_CPU_CLK_CNTL5,
708 .hw.init = &(struct clk_init_data){
709 .name = "dsu_clk_dyn0_sel",
710 .ops = &clk_regmap_mux_ro_ops,
711 .parent_data = (const struct clk_parent_data []) {
712 { .fw_name = "xtal", },
713 { .hw = &g12a_fclk_div2.hw },
714 { .hw = &g12a_fclk_div3.hw },
715 { .hw = &sm1_gp1_pll.hw },
721 /* Datasheet names this field as "premux1" */
722 static struct clk_regmap sm1_dsu_clk_premux1 = {
723 .data = &(struct clk_regmap_mux_data){
724 .offset = HHI_SYS_CPU_CLK_CNTL5,
728 .hw.init = &(struct clk_init_data){
729 .name = "dsu_clk_dyn1_sel",
730 .ops = &clk_regmap_mux_ro_ops,
731 .parent_data = (const struct clk_parent_data []) {
732 { .fw_name = "xtal", },
733 { .hw = &g12a_fclk_div2.hw },
734 { .hw = &g12a_fclk_div3.hw },
735 { .hw = &sm1_gp1_pll.hw },
741 /* Datasheet names this field as "Mux0_divn_tcnt" */
742 static struct clk_regmap sm1_dsu_clk_mux0_div = {
743 .data = &(struct clk_regmap_div_data){
744 .offset = HHI_SYS_CPU_CLK_CNTL5,
748 .hw.init = &(struct clk_init_data){
749 .name = "dsu_clk_dyn0_div",
750 .ops = &clk_regmap_divider_ro_ops,
751 .parent_hws = (const struct clk_hw *[]) {
752 &sm1_dsu_clk_premux0.hw
758 /* Datasheet names this field as "postmux0" */
759 static struct clk_regmap sm1_dsu_clk_postmux0 = {
760 .data = &(struct clk_regmap_mux_data){
761 .offset = HHI_SYS_CPU_CLK_CNTL5,
765 .hw.init = &(struct clk_init_data){
766 .name = "dsu_clk_dyn0",
767 .ops = &clk_regmap_mux_ro_ops,
768 .parent_hws = (const struct clk_hw *[]) {
769 &sm1_dsu_clk_premux0.hw,
770 &sm1_dsu_clk_mux0_div.hw,
776 /* Datasheet names this field as "Mux1_divn_tcnt" */
777 static struct clk_regmap sm1_dsu_clk_mux1_div = {
778 .data = &(struct clk_regmap_div_data){
779 .offset = HHI_SYS_CPU_CLK_CNTL5,
783 .hw.init = &(struct clk_init_data){
784 .name = "dsu_clk_dyn1_div",
785 .ops = &clk_regmap_divider_ro_ops,
786 .parent_hws = (const struct clk_hw *[]) {
787 &sm1_dsu_clk_premux1.hw
793 /* Datasheet names this field as "postmux1" */
794 static struct clk_regmap sm1_dsu_clk_postmux1 = {
795 .data = &(struct clk_regmap_mux_data){
796 .offset = HHI_SYS_CPU_CLK_CNTL5,
800 .hw.init = &(struct clk_init_data){
801 .name = "dsu_clk_dyn1",
802 .ops = &clk_regmap_mux_ro_ops,
803 .parent_hws = (const struct clk_hw *[]) {
804 &sm1_dsu_clk_premux1.hw,
805 &sm1_dsu_clk_mux1_div.hw,
811 /* Datasheet names this field as "Final_dyn_mux_sel" */
812 static struct clk_regmap sm1_dsu_clk_dyn = {
813 .data = &(struct clk_regmap_mux_data){
814 .offset = HHI_SYS_CPU_CLK_CNTL5,
818 .hw.init = &(struct clk_init_data){
819 .name = "dsu_clk_dyn",
820 .ops = &clk_regmap_mux_ro_ops,
821 .parent_hws = (const struct clk_hw *[]) {
822 &sm1_dsu_clk_postmux0.hw,
823 &sm1_dsu_clk_postmux1.hw,
829 /* Datasheet names this field as "Final_mux_sel" */
830 static struct clk_regmap sm1_dsu_final_clk = {
831 .data = &(struct clk_regmap_mux_data){
832 .offset = HHI_SYS_CPU_CLK_CNTL5,
836 .hw.init = &(struct clk_init_data){
837 .name = "dsu_clk_final",
838 .ops = &clk_regmap_mux_ro_ops,
839 .parent_hws = (const struct clk_hw *[]) {
847 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
848 static struct clk_regmap sm1_cpu1_clk = {
849 .data = &(struct clk_regmap_mux_data){
850 .offset = HHI_SYS_CPU_CLK_CNTL6,
854 .hw.init = &(struct clk_init_data){
856 .ops = &clk_regmap_mux_ro_ops,
857 .parent_hws = (const struct clk_hw *[]) {
859 /* This CPU also have a dedicated clock tree */
865 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
866 static struct clk_regmap sm1_cpu2_clk = {
867 .data = &(struct clk_regmap_mux_data){
868 .offset = HHI_SYS_CPU_CLK_CNTL6,
872 .hw.init = &(struct clk_init_data){
874 .ops = &clk_regmap_mux_ro_ops,
875 .parent_hws = (const struct clk_hw *[]) {
877 /* This CPU also have a dedicated clock tree */
883 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
884 static struct clk_regmap sm1_cpu3_clk = {
885 .data = &(struct clk_regmap_mux_data){
886 .offset = HHI_SYS_CPU_CLK_CNTL6,
890 .hw.init = &(struct clk_init_data){
892 .ops = &clk_regmap_mux_ro_ops,
893 .parent_hws = (const struct clk_hw *[]) {
895 /* This CPU also have a dedicated clock tree */
901 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
902 static struct clk_regmap sm1_dsu_clk = {
903 .data = &(struct clk_regmap_mux_data){
904 .offset = HHI_SYS_CPU_CLK_CNTL6,
908 .hw.init = &(struct clk_init_data){
910 .ops = &clk_regmap_mux_ro_ops,
911 .parent_hws = (const struct clk_hw *[]) {
913 &sm1_dsu_final_clk.hw,
919 static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
920 unsigned long event, void *data)
922 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
923 /* Wait for clock propagation before/after changing the mux */
931 static struct notifier_block g12a_cpu_clk_mux_nb = {
932 .notifier_call = g12a_cpu_clk_mux_notifier_cb,
935 struct g12a_cpu_clk_postmux_nb_data {
936 struct notifier_block nb;
938 struct clk_hw *cpu_clk_dyn;
939 struct clk_hw *cpu_clk_postmux0;
940 struct clk_hw *cpu_clk_postmux1;
941 struct clk_hw *cpu_clk_premux1;
944 static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
945 unsigned long event, void *data)
947 struct g12a_cpu_clk_postmux_nb_data *nb_data =
948 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
951 case PRE_RATE_CHANGE:
953 * This notifier means cpu_clk_postmux0 clock will be changed
954 * to feed cpu_clk, this is the current path :
957 * \- cpu_clk_postmux0
958 * \- cpu_clk_muxX_div
960 * \- fclk_div3 or fclk_div2
963 * \- fclk_div3 or fclk_div2
966 /* Setup cpu_clk_premux1 to xtal */
967 clk_hw_set_parent(nb_data->cpu_clk_premux1,
970 /* Setup cpu_clk_postmux1 to bypass divider */
971 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
972 nb_data->cpu_clk_premux1);
974 /* Switch to parking clk on cpu_clk_postmux1 */
975 clk_hw_set_parent(nb_data->cpu_clk_dyn,
976 nb_data->cpu_clk_postmux1);
979 * Now, cpu_clk is 24MHz in the current path :
982 * \- cpu_clk_postmux1
991 case POST_RATE_CHANGE:
993 * The cpu_clk_postmux0 has ben updated, now switch back
994 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
998 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
999 clk_hw_set_parent(nb_data->cpu_clk_dyn,
1000 nb_data->cpu_clk_postmux0);
1006 * \- cpu_clk_postmux0
1007 * \- cpu_clk_muxX_div
1008 * \- cpu_clk_premux0
1009 * \- fclk_div3 or fclk_div2
1011 * \- cpu_clk_premux0
1012 * \- fclk_div3 or fclk_div2
1024 static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1025 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1026 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1027 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1028 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1029 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1032 static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1033 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1034 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1035 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1036 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1037 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1040 struct g12a_sys_pll_nb_data {
1041 struct notifier_block nb;
1042 struct clk_hw *sys_pll;
1043 struct clk_hw *cpu_clk;
1044 struct clk_hw *cpu_clk_dyn;
1047 static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1048 unsigned long event, void *data)
1050 struct g12a_sys_pll_nb_data *nb_data =
1051 container_of(nb, struct g12a_sys_pll_nb_data, nb);
1054 case PRE_RATE_CHANGE:
1056 * This notifier means sys_pll clock will be changed
1057 * to feed cpu_clk, this the current path :
1063 /* Configure cpu_clk to use cpu_clk_dyn */
1064 clk_hw_set_parent(nb_data->cpu_clk,
1065 nb_data->cpu_clk_dyn);
1068 * Now, cpu_clk uses the dyn path
1072 * \- cpu_clk_dynX_sel
1073 * \- cpu_clk_dynX_div
1074 * \- xtal/fclk_div2/fclk_div3
1075 * \- xtal/fclk_div2/fclk_div3
1082 case POST_RATE_CHANGE:
1084 * The sys_pll has ben updated, now switch back cpu_clk to
1088 /* Configure cpu_clk to use sys_pll */
1089 clk_hw_set_parent(nb_data->cpu_clk,
1107 static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1108 .sys_pll = &g12a_sys_pll.hw,
1109 .cpu_clk = &g12a_cpu_clk.hw,
1110 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1111 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1114 /* G12B first CPU cluster uses sys1_pll */
1115 static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1116 .sys_pll = &g12b_sys1_pll.hw,
1117 .cpu_clk = &g12b_cpu_clk.hw,
1118 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1119 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1122 /* G12B second CPU cluster uses sys_pll */
1123 static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1124 .sys_pll = &g12a_sys_pll.hw,
1125 .cpu_clk = &g12b_cpub_clk.hw,
1126 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1127 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1130 static struct clk_regmap g12a_cpu_clk_div16_en = {
1131 .data = &(struct clk_regmap_gate_data){
1132 .offset = HHI_SYS_CPU_CLK_CNTL1,
1135 .hw.init = &(struct clk_init_data) {
1136 .name = "cpu_clk_div16_en",
1137 .ops = &clk_regmap_gate_ro_ops,
1138 .parent_hws = (const struct clk_hw *[]) {
1143 * This clock is used to debug the cpu_clk range
1144 * Linux should not change it at runtime
1149 static struct clk_regmap g12b_cpub_clk_div16_en = {
1150 .data = &(struct clk_regmap_gate_data){
1151 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1154 .hw.init = &(struct clk_init_data) {
1155 .name = "cpub_clk_div16_en",
1156 .ops = &clk_regmap_gate_ro_ops,
1157 .parent_hws = (const struct clk_hw *[]) {
1162 * This clock is used to debug the cpu_clk range
1163 * Linux should not change it at runtime
1168 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1171 .hw.init = &(struct clk_init_data){
1172 .name = "cpu_clk_div16",
1173 .ops = &clk_fixed_factor_ops,
1174 .parent_hws = (const struct clk_hw *[]) {
1175 &g12a_cpu_clk_div16_en.hw
1181 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1184 .hw.init = &(struct clk_init_data){
1185 .name = "cpub_clk_div16",
1186 .ops = &clk_fixed_factor_ops,
1187 .parent_hws = (const struct clk_hw *[]) {
1188 &g12b_cpub_clk_div16_en.hw
1194 static struct clk_regmap g12a_cpu_clk_apb_div = {
1195 .data = &(struct clk_regmap_div_data){
1196 .offset = HHI_SYS_CPU_CLK_CNTL1,
1199 .flags = CLK_DIVIDER_POWER_OF_TWO,
1201 .hw.init = &(struct clk_init_data){
1202 .name = "cpu_clk_apb_div",
1203 .ops = &clk_regmap_divider_ro_ops,
1204 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1209 static struct clk_regmap g12a_cpu_clk_apb = {
1210 .data = &(struct clk_regmap_gate_data){
1211 .offset = HHI_SYS_CPU_CLK_CNTL1,
1214 .hw.init = &(struct clk_init_data) {
1215 .name = "cpu_clk_apb",
1216 .ops = &clk_regmap_gate_ro_ops,
1217 .parent_hws = (const struct clk_hw *[]) {
1218 &g12a_cpu_clk_apb_div.hw
1222 * This clock is set by the ROM monitor code,
1223 * Linux should not change it at runtime
1228 static struct clk_regmap g12a_cpu_clk_atb_div = {
1229 .data = &(struct clk_regmap_div_data){
1230 .offset = HHI_SYS_CPU_CLK_CNTL1,
1233 .flags = CLK_DIVIDER_POWER_OF_TWO,
1235 .hw.init = &(struct clk_init_data){
1236 .name = "cpu_clk_atb_div",
1237 .ops = &clk_regmap_divider_ro_ops,
1238 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1243 static struct clk_regmap g12a_cpu_clk_atb = {
1244 .data = &(struct clk_regmap_gate_data){
1245 .offset = HHI_SYS_CPU_CLK_CNTL1,
1248 .hw.init = &(struct clk_init_data) {
1249 .name = "cpu_clk_atb",
1250 .ops = &clk_regmap_gate_ro_ops,
1251 .parent_hws = (const struct clk_hw *[]) {
1252 &g12a_cpu_clk_atb_div.hw
1256 * This clock is set by the ROM monitor code,
1257 * Linux should not change it at runtime
1262 static struct clk_regmap g12a_cpu_clk_axi_div = {
1263 .data = &(struct clk_regmap_div_data){
1264 .offset = HHI_SYS_CPU_CLK_CNTL1,
1267 .flags = CLK_DIVIDER_POWER_OF_TWO,
1269 .hw.init = &(struct clk_init_data){
1270 .name = "cpu_clk_axi_div",
1271 .ops = &clk_regmap_divider_ro_ops,
1272 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1277 static struct clk_regmap g12a_cpu_clk_axi = {
1278 .data = &(struct clk_regmap_gate_data){
1279 .offset = HHI_SYS_CPU_CLK_CNTL1,
1282 .hw.init = &(struct clk_init_data) {
1283 .name = "cpu_clk_axi",
1284 .ops = &clk_regmap_gate_ro_ops,
1285 .parent_hws = (const struct clk_hw *[]) {
1286 &g12a_cpu_clk_axi_div.hw
1290 * This clock is set by the ROM monitor code,
1291 * Linux should not change it at runtime
1296 static struct clk_regmap g12a_cpu_clk_trace_div = {
1297 .data = &(struct clk_regmap_div_data){
1298 .offset = HHI_SYS_CPU_CLK_CNTL1,
1301 .flags = CLK_DIVIDER_POWER_OF_TWO,
1303 .hw.init = &(struct clk_init_data){
1304 .name = "cpu_clk_trace_div",
1305 .ops = &clk_regmap_divider_ro_ops,
1306 .parent_data = &(const struct clk_parent_data) {
1309 * G12A and G12B have different cpu_clks (with
1310 * different struct clk_hw). We fallback to the global
1311 * naming string mechanism so cpu_clk_trace_div picks
1312 * up the appropriate one.
1321 static struct clk_regmap g12a_cpu_clk_trace = {
1322 .data = &(struct clk_regmap_gate_data){
1323 .offset = HHI_SYS_CPU_CLK_CNTL1,
1326 .hw.init = &(struct clk_init_data) {
1327 .name = "cpu_clk_trace",
1328 .ops = &clk_regmap_gate_ro_ops,
1329 .parent_hws = (const struct clk_hw *[]) {
1330 &g12a_cpu_clk_trace_div.hw
1334 * This clock is set by the ROM monitor code,
1335 * Linux should not change it at runtime
1340 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1343 .hw.init = &(struct clk_init_data){
1344 .name = "cpub_clk_div2",
1345 .ops = &clk_fixed_factor_ops,
1346 .parent_hws = (const struct clk_hw *[]) {
1353 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1356 .hw.init = &(struct clk_init_data){
1357 .name = "cpub_clk_div3",
1358 .ops = &clk_fixed_factor_ops,
1359 .parent_hws = (const struct clk_hw *[]) {
1366 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1369 .hw.init = &(struct clk_init_data){
1370 .name = "cpub_clk_div4",
1371 .ops = &clk_fixed_factor_ops,
1372 .parent_hws = (const struct clk_hw *[]) {
1379 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1382 .hw.init = &(struct clk_init_data){
1383 .name = "cpub_clk_div5",
1384 .ops = &clk_fixed_factor_ops,
1385 .parent_hws = (const struct clk_hw *[]) {
1392 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1395 .hw.init = &(struct clk_init_data){
1396 .name = "cpub_clk_div6",
1397 .ops = &clk_fixed_factor_ops,
1398 .parent_hws = (const struct clk_hw *[]) {
1405 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1408 .hw.init = &(struct clk_init_data){
1409 .name = "cpub_clk_div7",
1410 .ops = &clk_fixed_factor_ops,
1411 .parent_hws = (const struct clk_hw *[]) {
1418 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1421 .hw.init = &(struct clk_init_data){
1422 .name = "cpub_clk_div8",
1423 .ops = &clk_fixed_factor_ops,
1424 .parent_hws = (const struct clk_hw *[]) {
1431 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1432 static struct clk_regmap g12b_cpub_clk_apb_sel = {
1433 .data = &(struct clk_regmap_mux_data){
1434 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1437 .table = mux_table_cpub,
1439 .hw.init = &(struct clk_init_data){
1440 .name = "cpub_clk_apb_sel",
1441 .ops = &clk_regmap_mux_ro_ops,
1442 .parent_hws = (const struct clk_hw *[]) {
1443 &g12b_cpub_clk_div2.hw,
1444 &g12b_cpub_clk_div3.hw,
1445 &g12b_cpub_clk_div4.hw,
1446 &g12b_cpub_clk_div5.hw,
1447 &g12b_cpub_clk_div6.hw,
1448 &g12b_cpub_clk_div7.hw,
1449 &g12b_cpub_clk_div8.hw
1455 static struct clk_regmap g12b_cpub_clk_apb = {
1456 .data = &(struct clk_regmap_gate_data){
1457 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1459 .flags = CLK_GATE_SET_TO_DISABLE,
1461 .hw.init = &(struct clk_init_data) {
1462 .name = "cpub_clk_apb",
1463 .ops = &clk_regmap_gate_ro_ops,
1464 .parent_hws = (const struct clk_hw *[]) {
1465 &g12b_cpub_clk_apb_sel.hw
1469 * This clock is set by the ROM monitor code,
1470 * Linux should not change it at runtime
1475 static struct clk_regmap g12b_cpub_clk_atb_sel = {
1476 .data = &(struct clk_regmap_mux_data){
1477 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1480 .table = mux_table_cpub,
1482 .hw.init = &(struct clk_init_data){
1483 .name = "cpub_clk_atb_sel",
1484 .ops = &clk_regmap_mux_ro_ops,
1485 .parent_hws = (const struct clk_hw *[]) {
1486 &g12b_cpub_clk_div2.hw,
1487 &g12b_cpub_clk_div3.hw,
1488 &g12b_cpub_clk_div4.hw,
1489 &g12b_cpub_clk_div5.hw,
1490 &g12b_cpub_clk_div6.hw,
1491 &g12b_cpub_clk_div7.hw,
1492 &g12b_cpub_clk_div8.hw
1498 static struct clk_regmap g12b_cpub_clk_atb = {
1499 .data = &(struct clk_regmap_gate_data){
1500 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1502 .flags = CLK_GATE_SET_TO_DISABLE,
1504 .hw.init = &(struct clk_init_data) {
1505 .name = "cpub_clk_atb",
1506 .ops = &clk_regmap_gate_ro_ops,
1507 .parent_hws = (const struct clk_hw *[]) {
1508 &g12b_cpub_clk_atb_sel.hw
1512 * This clock is set by the ROM monitor code,
1513 * Linux should not change it at runtime
1518 static struct clk_regmap g12b_cpub_clk_axi_sel = {
1519 .data = &(struct clk_regmap_mux_data){
1520 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1523 .table = mux_table_cpub,
1525 .hw.init = &(struct clk_init_data){
1526 .name = "cpub_clk_axi_sel",
1527 .ops = &clk_regmap_mux_ro_ops,
1528 .parent_hws = (const struct clk_hw *[]) {
1529 &g12b_cpub_clk_div2.hw,
1530 &g12b_cpub_clk_div3.hw,
1531 &g12b_cpub_clk_div4.hw,
1532 &g12b_cpub_clk_div5.hw,
1533 &g12b_cpub_clk_div6.hw,
1534 &g12b_cpub_clk_div7.hw,
1535 &g12b_cpub_clk_div8.hw
1541 static struct clk_regmap g12b_cpub_clk_axi = {
1542 .data = &(struct clk_regmap_gate_data){
1543 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1545 .flags = CLK_GATE_SET_TO_DISABLE,
1547 .hw.init = &(struct clk_init_data) {
1548 .name = "cpub_clk_axi",
1549 .ops = &clk_regmap_gate_ro_ops,
1550 .parent_hws = (const struct clk_hw *[]) {
1551 &g12b_cpub_clk_axi_sel.hw
1555 * This clock is set by the ROM monitor code,
1556 * Linux should not change it at runtime
1561 static struct clk_regmap g12b_cpub_clk_trace_sel = {
1562 .data = &(struct clk_regmap_mux_data){
1563 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1566 .table = mux_table_cpub,
1568 .hw.init = &(struct clk_init_data){
1569 .name = "cpub_clk_trace_sel",
1570 .ops = &clk_regmap_mux_ro_ops,
1571 .parent_hws = (const struct clk_hw *[]) {
1572 &g12b_cpub_clk_div2.hw,
1573 &g12b_cpub_clk_div3.hw,
1574 &g12b_cpub_clk_div4.hw,
1575 &g12b_cpub_clk_div5.hw,
1576 &g12b_cpub_clk_div6.hw,
1577 &g12b_cpub_clk_div7.hw,
1578 &g12b_cpub_clk_div8.hw
1584 static struct clk_regmap g12b_cpub_clk_trace = {
1585 .data = &(struct clk_regmap_gate_data){
1586 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1588 .flags = CLK_GATE_SET_TO_DISABLE,
1590 .hw.init = &(struct clk_init_data) {
1591 .name = "cpub_clk_trace",
1592 .ops = &clk_regmap_gate_ro_ops,
1593 .parent_hws = (const struct clk_hw *[]) {
1594 &g12b_cpub_clk_trace_sel.hw
1598 * This clock is set by the ROM monitor code,
1599 * Linux should not change it at runtime
1604 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1610 * Internal gp0 pll emulation configuration parameters
1612 static const struct reg_sequence g12a_gp0_init_regs[] = {
1613 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
1614 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
1615 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
1616 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
1617 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
1618 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
1621 static struct clk_regmap g12a_gp0_pll_dco = {
1622 .data = &(struct meson_clk_pll_data){
1624 .reg_off = HHI_GP0_PLL_CNTL0,
1629 .reg_off = HHI_GP0_PLL_CNTL0,
1634 .reg_off = HHI_GP0_PLL_CNTL0,
1639 .reg_off = HHI_GP0_PLL_CNTL1,
1644 .reg_off = HHI_GP0_PLL_CNTL0,
1649 .reg_off = HHI_GP0_PLL_CNTL0,
1653 .range = &g12a_gp0_pll_mult_range,
1654 .init_regs = g12a_gp0_init_regs,
1655 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "gp0_pll_dco",
1659 .ops = &meson_clk_pll_ops,
1660 .parent_data = &(const struct clk_parent_data) {
1667 static struct clk_regmap g12a_gp0_pll = {
1668 .data = &(struct clk_regmap_div_data){
1669 .offset = HHI_GP0_PLL_CNTL0,
1672 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1673 CLK_DIVIDER_ROUND_CLOSEST),
1675 .hw.init = &(struct clk_init_data){
1677 .ops = &clk_regmap_divider_ops,
1678 .parent_hws = (const struct clk_hw *[]) {
1679 &g12a_gp0_pll_dco.hw
1682 .flags = CLK_SET_RATE_PARENT,
1686 static struct clk_regmap sm1_gp1_pll_dco = {
1687 .data = &(struct meson_clk_pll_data){
1689 .reg_off = HHI_GP1_PLL_CNTL0,
1694 .reg_off = HHI_GP1_PLL_CNTL0,
1699 .reg_off = HHI_GP1_PLL_CNTL0,
1704 .reg_off = HHI_GP1_PLL_CNTL1,
1709 .reg_off = HHI_GP1_PLL_CNTL0,
1714 .reg_off = HHI_GP1_PLL_CNTL0,
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gp1_pll_dco",
1721 .ops = &meson_clk_pll_ro_ops,
1722 .parent_data = &(const struct clk_parent_data) {
1726 /* This clock feeds the DSU, avoid disabling it */
1727 .flags = CLK_IS_CRITICAL,
1731 static struct clk_regmap sm1_gp1_pll = {
1732 .data = &(struct clk_regmap_div_data){
1733 .offset = HHI_GP1_PLL_CNTL0,
1736 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1737 CLK_DIVIDER_ROUND_CLOSEST),
1739 .hw.init = &(struct clk_init_data){
1741 .ops = &clk_regmap_divider_ro_ops,
1742 .parent_hws = (const struct clk_hw *[]) {
1750 * Internal hifi pll emulation configuration parameters
1752 static const struct reg_sequence g12a_hifi_init_regs[] = {
1753 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
1754 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
1755 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
1756 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
1757 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
1758 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
1761 static struct clk_regmap g12a_hifi_pll_dco = {
1762 .data = &(struct meson_clk_pll_data){
1764 .reg_off = HHI_HIFI_PLL_CNTL0,
1769 .reg_off = HHI_HIFI_PLL_CNTL0,
1774 .reg_off = HHI_HIFI_PLL_CNTL0,
1779 .reg_off = HHI_HIFI_PLL_CNTL1,
1784 .reg_off = HHI_HIFI_PLL_CNTL0,
1789 .reg_off = HHI_HIFI_PLL_CNTL0,
1793 .range = &g12a_gp0_pll_mult_range,
1794 .init_regs = g12a_hifi_init_regs,
1795 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1796 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
1798 .hw.init = &(struct clk_init_data){
1799 .name = "hifi_pll_dco",
1800 .ops = &meson_clk_pll_ops,
1801 .parent_data = &(const struct clk_parent_data) {
1808 static struct clk_regmap g12a_hifi_pll = {
1809 .data = &(struct clk_regmap_div_data){
1810 .offset = HHI_HIFI_PLL_CNTL0,
1813 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1814 CLK_DIVIDER_ROUND_CLOSEST),
1816 .hw.init = &(struct clk_init_data){
1818 .ops = &clk_regmap_divider_ops,
1819 .parent_hws = (const struct clk_hw *[]) {
1820 &g12a_hifi_pll_dco.hw
1823 .flags = CLK_SET_RATE_PARENT,
1828 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1829 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1830 * a strict register sequence to enable the PLL.
1832 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1833 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
1834 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
1835 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
1836 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
1837 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
1838 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
1839 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
1840 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
1841 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
1842 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
1843 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
1844 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
1847 /* Keep a single entry table for recalc/round_rate() ops */
1848 static const struct pll_params_table g12a_pcie_pll_table[] = {
1853 static struct clk_regmap g12a_pcie_pll_dco = {
1854 .data = &(struct meson_clk_pll_data){
1856 .reg_off = HHI_PCIE_PLL_CNTL0,
1861 .reg_off = HHI_PCIE_PLL_CNTL0,
1866 .reg_off = HHI_PCIE_PLL_CNTL0,
1871 .reg_off = HHI_PCIE_PLL_CNTL1,
1876 .reg_off = HHI_PCIE_PLL_CNTL0,
1881 .reg_off = HHI_PCIE_PLL_CNTL0,
1885 .table = g12a_pcie_pll_table,
1886 .init_regs = g12a_pcie_pll_init_regs,
1887 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "pcie_pll_dco",
1891 .ops = &meson_clk_pcie_pll_ops,
1892 .parent_data = &(const struct clk_parent_data) {
1899 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1902 .hw.init = &(struct clk_init_data){
1903 .name = "pcie_pll_dco_div2",
1904 .ops = &clk_fixed_factor_ops,
1905 .parent_hws = (const struct clk_hw *[]) {
1906 &g12a_pcie_pll_dco.hw
1909 .flags = CLK_SET_RATE_PARENT,
1913 static struct clk_regmap g12a_pcie_pll_od = {
1914 .data = &(struct clk_regmap_div_data){
1915 .offset = HHI_PCIE_PLL_CNTL0,
1918 .flags = CLK_DIVIDER_ROUND_CLOSEST |
1919 CLK_DIVIDER_ONE_BASED |
1920 CLK_DIVIDER_ALLOW_ZERO,
1922 .hw.init = &(struct clk_init_data){
1923 .name = "pcie_pll_od",
1924 .ops = &clk_regmap_divider_ops,
1925 .parent_hws = (const struct clk_hw *[]) {
1926 &g12a_pcie_pll_dco_div2.hw
1929 .flags = CLK_SET_RATE_PARENT,
1933 static struct clk_fixed_factor g12a_pcie_pll = {
1936 .hw.init = &(struct clk_init_data){
1937 .name = "pcie_pll_pll",
1938 .ops = &clk_fixed_factor_ops,
1939 .parent_hws = (const struct clk_hw *[]) {
1940 &g12a_pcie_pll_od.hw
1943 .flags = CLK_SET_RATE_PARENT,
1947 static struct clk_regmap g12a_hdmi_pll_dco = {
1948 .data = &(struct meson_clk_pll_data){
1950 .reg_off = HHI_HDMI_PLL_CNTL0,
1955 .reg_off = HHI_HDMI_PLL_CNTL0,
1960 .reg_off = HHI_HDMI_PLL_CNTL0,
1965 .reg_off = HHI_HDMI_PLL_CNTL1,
1970 .reg_off = HHI_HDMI_PLL_CNTL0,
1975 .reg_off = HHI_HDMI_PLL_CNTL0,
1980 .hw.init = &(struct clk_init_data){
1981 .name = "hdmi_pll_dco",
1982 .ops = &meson_clk_pll_ro_ops,
1983 .parent_data = &(const struct clk_parent_data) {
1988 * Display directly handle hdmi pll registers ATM, we need
1989 * NOCACHE to keep our view of the clock as accurate as possible
1991 .flags = CLK_GET_RATE_NOCACHE,
1995 static struct clk_regmap g12a_hdmi_pll_od = {
1996 .data = &(struct clk_regmap_div_data){
1997 .offset = HHI_HDMI_PLL_CNTL0,
2000 .flags = CLK_DIVIDER_POWER_OF_TWO,
2002 .hw.init = &(struct clk_init_data){
2003 .name = "hdmi_pll_od",
2004 .ops = &clk_regmap_divider_ro_ops,
2005 .parent_hws = (const struct clk_hw *[]) {
2006 &g12a_hdmi_pll_dco.hw
2009 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2013 static struct clk_regmap g12a_hdmi_pll_od2 = {
2014 .data = &(struct clk_regmap_div_data){
2015 .offset = HHI_HDMI_PLL_CNTL0,
2018 .flags = CLK_DIVIDER_POWER_OF_TWO,
2020 .hw.init = &(struct clk_init_data){
2021 .name = "hdmi_pll_od2",
2022 .ops = &clk_regmap_divider_ro_ops,
2023 .parent_hws = (const struct clk_hw *[]) {
2024 &g12a_hdmi_pll_od.hw
2027 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2031 static struct clk_regmap g12a_hdmi_pll = {
2032 .data = &(struct clk_regmap_div_data){
2033 .offset = HHI_HDMI_PLL_CNTL0,
2036 .flags = CLK_DIVIDER_POWER_OF_TWO,
2038 .hw.init = &(struct clk_init_data){
2040 .ops = &clk_regmap_divider_ro_ops,
2041 .parent_hws = (const struct clk_hw *[]) {
2042 &g12a_hdmi_pll_od2.hw
2045 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2049 static struct clk_fixed_factor g12a_fclk_div4_div = {
2052 .hw.init = &(struct clk_init_data){
2053 .name = "fclk_div4_div",
2054 .ops = &clk_fixed_factor_ops,
2055 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2060 static struct clk_regmap g12a_fclk_div4 = {
2061 .data = &(struct clk_regmap_gate_data){
2062 .offset = HHI_FIX_PLL_CNTL1,
2065 .hw.init = &(struct clk_init_data){
2066 .name = "fclk_div4",
2067 .ops = &clk_regmap_gate_ops,
2068 .parent_hws = (const struct clk_hw *[]) {
2069 &g12a_fclk_div4_div.hw
2075 static struct clk_fixed_factor g12a_fclk_div5_div = {
2078 .hw.init = &(struct clk_init_data){
2079 .name = "fclk_div5_div",
2080 .ops = &clk_fixed_factor_ops,
2081 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2086 static struct clk_regmap g12a_fclk_div5 = {
2087 .data = &(struct clk_regmap_gate_data){
2088 .offset = HHI_FIX_PLL_CNTL1,
2091 .hw.init = &(struct clk_init_data){
2092 .name = "fclk_div5",
2093 .ops = &clk_regmap_gate_ops,
2094 .parent_hws = (const struct clk_hw *[]) {
2095 &g12a_fclk_div5_div.hw
2101 static struct clk_fixed_factor g12a_fclk_div7_div = {
2104 .hw.init = &(struct clk_init_data){
2105 .name = "fclk_div7_div",
2106 .ops = &clk_fixed_factor_ops,
2107 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2112 static struct clk_regmap g12a_fclk_div7 = {
2113 .data = &(struct clk_regmap_gate_data){
2114 .offset = HHI_FIX_PLL_CNTL1,
2117 .hw.init = &(struct clk_init_data){
2118 .name = "fclk_div7",
2119 .ops = &clk_regmap_gate_ops,
2120 .parent_hws = (const struct clk_hw *[]) {
2121 &g12a_fclk_div7_div.hw
2127 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2130 .hw.init = &(struct clk_init_data){
2131 .name = "fclk_div2p5_div",
2132 .ops = &clk_fixed_factor_ops,
2133 .parent_hws = (const struct clk_hw *[]) {
2134 &g12a_fixed_pll_dco.hw
2140 static struct clk_regmap g12a_fclk_div2p5 = {
2141 .data = &(struct clk_regmap_gate_data){
2142 .offset = HHI_FIX_PLL_CNTL1,
2145 .hw.init = &(struct clk_init_data){
2146 .name = "fclk_div2p5",
2147 .ops = &clk_regmap_gate_ops,
2148 .parent_hws = (const struct clk_hw *[]) {
2149 &g12a_fclk_div2p5_div.hw
2155 static struct clk_fixed_factor g12a_mpll_50m_div = {
2158 .hw.init = &(struct clk_init_data){
2159 .name = "mpll_50m_div",
2160 .ops = &clk_fixed_factor_ops,
2161 .parent_hws = (const struct clk_hw *[]) {
2162 &g12a_fixed_pll_dco.hw
2168 static struct clk_regmap g12a_mpll_50m = {
2169 .data = &(struct clk_regmap_mux_data){
2170 .offset = HHI_FIX_PLL_CNTL3,
2174 .hw.init = &(struct clk_init_data){
2176 .ops = &clk_regmap_mux_ro_ops,
2177 .parent_data = (const struct clk_parent_data []) {
2178 { .fw_name = "xtal", },
2179 { .hw = &g12a_mpll_50m_div.hw },
2185 static struct clk_fixed_factor g12a_mpll_prediv = {
2188 .hw.init = &(struct clk_init_data){
2189 .name = "mpll_prediv",
2190 .ops = &clk_fixed_factor_ops,
2191 .parent_hws = (const struct clk_hw *[]) {
2192 &g12a_fixed_pll_dco.hw
2198 static const struct reg_sequence g12a_mpll0_init_regs[] = {
2199 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
2202 static struct clk_regmap g12a_mpll0_div = {
2203 .data = &(struct meson_clk_mpll_data){
2205 .reg_off = HHI_MPLL_CNTL1,
2210 .reg_off = HHI_MPLL_CNTL1,
2215 .reg_off = HHI_MPLL_CNTL1,
2220 .reg_off = HHI_MPLL_CNTL1,
2224 .lock = &meson_clk_lock,
2225 .init_regs = g12a_mpll0_init_regs,
2226 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2228 .hw.init = &(struct clk_init_data){
2229 .name = "mpll0_div",
2230 .ops = &meson_clk_mpll_ops,
2231 .parent_hws = (const struct clk_hw *[]) {
2232 &g12a_mpll_prediv.hw
2238 static struct clk_regmap g12a_mpll0 = {
2239 .data = &(struct clk_regmap_gate_data){
2240 .offset = HHI_MPLL_CNTL1,
2243 .hw.init = &(struct clk_init_data){
2245 .ops = &clk_regmap_gate_ops,
2246 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2248 .flags = CLK_SET_RATE_PARENT,
2252 static const struct reg_sequence g12a_mpll1_init_regs[] = {
2253 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
2256 static struct clk_regmap g12a_mpll1_div = {
2257 .data = &(struct meson_clk_mpll_data){
2259 .reg_off = HHI_MPLL_CNTL3,
2264 .reg_off = HHI_MPLL_CNTL3,
2269 .reg_off = HHI_MPLL_CNTL3,
2274 .reg_off = HHI_MPLL_CNTL3,
2278 .lock = &meson_clk_lock,
2279 .init_regs = g12a_mpll1_init_regs,
2280 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "mpll1_div",
2284 .ops = &meson_clk_mpll_ops,
2285 .parent_hws = (const struct clk_hw *[]) {
2286 &g12a_mpll_prediv.hw
2292 static struct clk_regmap g12a_mpll1 = {
2293 .data = &(struct clk_regmap_gate_data){
2294 .offset = HHI_MPLL_CNTL3,
2297 .hw.init = &(struct clk_init_data){
2299 .ops = &clk_regmap_gate_ops,
2300 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2302 .flags = CLK_SET_RATE_PARENT,
2306 static const struct reg_sequence g12a_mpll2_init_regs[] = {
2307 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
2310 static struct clk_regmap g12a_mpll2_div = {
2311 .data = &(struct meson_clk_mpll_data){
2313 .reg_off = HHI_MPLL_CNTL5,
2318 .reg_off = HHI_MPLL_CNTL5,
2323 .reg_off = HHI_MPLL_CNTL5,
2328 .reg_off = HHI_MPLL_CNTL5,
2332 .lock = &meson_clk_lock,
2333 .init_regs = g12a_mpll2_init_regs,
2334 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "mpll2_div",
2338 .ops = &meson_clk_mpll_ops,
2339 .parent_hws = (const struct clk_hw *[]) {
2340 &g12a_mpll_prediv.hw
2346 static struct clk_regmap g12a_mpll2 = {
2347 .data = &(struct clk_regmap_gate_data){
2348 .offset = HHI_MPLL_CNTL5,
2351 .hw.init = &(struct clk_init_data){
2353 .ops = &clk_regmap_gate_ops,
2354 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2356 .flags = CLK_SET_RATE_PARENT,
2360 static const struct reg_sequence g12a_mpll3_init_regs[] = {
2361 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
2364 static struct clk_regmap g12a_mpll3_div = {
2365 .data = &(struct meson_clk_mpll_data){
2367 .reg_off = HHI_MPLL_CNTL7,
2372 .reg_off = HHI_MPLL_CNTL7,
2377 .reg_off = HHI_MPLL_CNTL7,
2382 .reg_off = HHI_MPLL_CNTL7,
2386 .lock = &meson_clk_lock,
2387 .init_regs = g12a_mpll3_init_regs,
2388 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "mpll3_div",
2392 .ops = &meson_clk_mpll_ops,
2393 .parent_hws = (const struct clk_hw *[]) {
2394 &g12a_mpll_prediv.hw
2400 static struct clk_regmap g12a_mpll3 = {
2401 .data = &(struct clk_regmap_gate_data){
2402 .offset = HHI_MPLL_CNTL7,
2405 .hw.init = &(struct clk_init_data){
2407 .ops = &clk_regmap_gate_ops,
2408 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2410 .flags = CLK_SET_RATE_PARENT,
2414 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
2415 static const struct clk_parent_data clk81_parent_data[] = {
2416 { .fw_name = "xtal", },
2417 { .hw = &g12a_fclk_div7.hw },
2418 { .hw = &g12a_mpll1.hw },
2419 { .hw = &g12a_mpll2.hw },
2420 { .hw = &g12a_fclk_div4.hw },
2421 { .hw = &g12a_fclk_div3.hw },
2422 { .hw = &g12a_fclk_div5.hw },
2425 static struct clk_regmap g12a_mpeg_clk_sel = {
2426 .data = &(struct clk_regmap_mux_data){
2427 .offset = HHI_MPEG_CLK_CNTL,
2430 .table = mux_table_clk81,
2432 .hw.init = &(struct clk_init_data){
2433 .name = "mpeg_clk_sel",
2434 .ops = &clk_regmap_mux_ro_ops,
2435 .parent_data = clk81_parent_data,
2436 .num_parents = ARRAY_SIZE(clk81_parent_data),
2440 static struct clk_regmap g12a_mpeg_clk_div = {
2441 .data = &(struct clk_regmap_div_data){
2442 .offset = HHI_MPEG_CLK_CNTL,
2446 .hw.init = &(struct clk_init_data){
2447 .name = "mpeg_clk_div",
2448 .ops = &clk_regmap_divider_ops,
2449 .parent_hws = (const struct clk_hw *[]) {
2450 &g12a_mpeg_clk_sel.hw
2453 .flags = CLK_SET_RATE_PARENT,
2457 static struct clk_regmap g12a_clk81 = {
2458 .data = &(struct clk_regmap_gate_data){
2459 .offset = HHI_MPEG_CLK_CNTL,
2462 .hw.init = &(struct clk_init_data){
2464 .ops = &clk_regmap_gate_ops,
2465 .parent_hws = (const struct clk_hw *[]) {
2466 &g12a_mpeg_clk_div.hw
2469 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2473 static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2474 { .fw_name = "xtal", },
2475 { .hw = &g12a_fclk_div2.hw },
2476 { .hw = &g12a_fclk_div3.hw },
2477 { .hw = &g12a_fclk_div5.hw },
2478 { .hw = &g12a_fclk_div7.hw },
2480 * Following these parent clocks, we should also have had mpll2, mpll3
2481 * and gp0_pll but these clocks are too precious to be used here. All
2482 * the necessary rates for MMC and NAND operation can be acheived using
2483 * g12a_ee_core or fclk_div clocks
2488 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2489 .data = &(struct clk_regmap_mux_data){
2490 .offset = HHI_SD_EMMC_CLK_CNTL,
2494 .hw.init = &(struct clk_init_data) {
2495 .name = "sd_emmc_a_clk0_sel",
2496 .ops = &clk_regmap_mux_ops,
2497 .parent_data = g12a_sd_emmc_clk0_parent_data,
2498 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2499 .flags = CLK_SET_RATE_PARENT,
2503 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2504 .data = &(struct clk_regmap_div_data){
2505 .offset = HHI_SD_EMMC_CLK_CNTL,
2509 .hw.init = &(struct clk_init_data) {
2510 .name = "sd_emmc_a_clk0_div",
2511 .ops = &clk_regmap_divider_ops,
2512 .parent_hws = (const struct clk_hw *[]) {
2513 &g12a_sd_emmc_a_clk0_sel.hw
2516 .flags = CLK_SET_RATE_PARENT,
2520 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2521 .data = &(struct clk_regmap_gate_data){
2522 .offset = HHI_SD_EMMC_CLK_CNTL,
2525 .hw.init = &(struct clk_init_data){
2526 .name = "sd_emmc_a_clk0",
2527 .ops = &clk_regmap_gate_ops,
2528 .parent_hws = (const struct clk_hw *[]) {
2529 &g12a_sd_emmc_a_clk0_div.hw
2532 .flags = CLK_SET_RATE_PARENT,
2537 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2538 .data = &(struct clk_regmap_mux_data){
2539 .offset = HHI_SD_EMMC_CLK_CNTL,
2543 .hw.init = &(struct clk_init_data) {
2544 .name = "sd_emmc_b_clk0_sel",
2545 .ops = &clk_regmap_mux_ops,
2546 .parent_data = g12a_sd_emmc_clk0_parent_data,
2547 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2548 .flags = CLK_SET_RATE_PARENT,
2552 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2553 .data = &(struct clk_regmap_div_data){
2554 .offset = HHI_SD_EMMC_CLK_CNTL,
2558 .hw.init = &(struct clk_init_data) {
2559 .name = "sd_emmc_b_clk0_div",
2560 .ops = &clk_regmap_divider_ops,
2561 .parent_hws = (const struct clk_hw *[]) {
2562 &g12a_sd_emmc_b_clk0_sel.hw
2565 .flags = CLK_SET_RATE_PARENT,
2569 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2570 .data = &(struct clk_regmap_gate_data){
2571 .offset = HHI_SD_EMMC_CLK_CNTL,
2574 .hw.init = &(struct clk_init_data){
2575 .name = "sd_emmc_b_clk0",
2576 .ops = &clk_regmap_gate_ops,
2577 .parent_hws = (const struct clk_hw *[]) {
2578 &g12a_sd_emmc_b_clk0_div.hw
2581 .flags = CLK_SET_RATE_PARENT,
2585 /* EMMC/NAND clock */
2586 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2587 .data = &(struct clk_regmap_mux_data){
2588 .offset = HHI_NAND_CLK_CNTL,
2592 .hw.init = &(struct clk_init_data) {
2593 .name = "sd_emmc_c_clk0_sel",
2594 .ops = &clk_regmap_mux_ops,
2595 .parent_data = g12a_sd_emmc_clk0_parent_data,
2596 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2597 .flags = CLK_SET_RATE_PARENT,
2601 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2602 .data = &(struct clk_regmap_div_data){
2603 .offset = HHI_NAND_CLK_CNTL,
2607 .hw.init = &(struct clk_init_data) {
2608 .name = "sd_emmc_c_clk0_div",
2609 .ops = &clk_regmap_divider_ops,
2610 .parent_hws = (const struct clk_hw *[]) {
2611 &g12a_sd_emmc_c_clk0_sel.hw
2614 .flags = CLK_SET_RATE_PARENT,
2618 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2619 .data = &(struct clk_regmap_gate_data){
2620 .offset = HHI_NAND_CLK_CNTL,
2623 .hw.init = &(struct clk_init_data){
2624 .name = "sd_emmc_c_clk0",
2625 .ops = &clk_regmap_gate_ops,
2626 .parent_hws = (const struct clk_hw *[]) {
2627 &g12a_sd_emmc_c_clk0_div.hw
2630 .flags = CLK_SET_RATE_PARENT,
2636 static struct clk_regmap g12a_vid_pll_div = {
2637 .data = &(struct meson_vid_pll_div_data){
2639 .reg_off = HHI_VID_PLL_CLK_DIV,
2644 .reg_off = HHI_VID_PLL_CLK_DIV,
2649 .hw.init = &(struct clk_init_data) {
2650 .name = "vid_pll_div",
2651 .ops = &meson_vid_pll_div_ro_ops,
2652 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2654 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2658 static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2659 &g12a_vid_pll_div.hw,
2663 static struct clk_regmap g12a_vid_pll_sel = {
2664 .data = &(struct clk_regmap_mux_data){
2665 .offset = HHI_VID_PLL_CLK_DIV,
2669 .hw.init = &(struct clk_init_data){
2670 .name = "vid_pll_sel",
2671 .ops = &clk_regmap_mux_ops,
2673 * bit 18 selects from 2 possible parents:
2674 * vid_pll_div or hdmi_pll
2676 .parent_hws = g12a_vid_pll_parent_hws,
2677 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2678 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2682 static struct clk_regmap g12a_vid_pll = {
2683 .data = &(struct clk_regmap_gate_data){
2684 .offset = HHI_VID_PLL_CLK_DIV,
2687 .hw.init = &(struct clk_init_data) {
2689 .ops = &clk_regmap_gate_ops,
2690 .parent_hws = (const struct clk_hw *[]) {
2691 &g12a_vid_pll_sel.hw
2694 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2700 static const struct clk_hw *g12a_vpu_parent_hws[] = {
2711 static struct clk_regmap g12a_vpu_0_sel = {
2712 .data = &(struct clk_regmap_mux_data){
2713 .offset = HHI_VPU_CLK_CNTL,
2717 .hw.init = &(struct clk_init_data){
2718 .name = "vpu_0_sel",
2719 .ops = &clk_regmap_mux_ops,
2720 .parent_hws = g12a_vpu_parent_hws,
2721 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2722 .flags = CLK_SET_RATE_NO_REPARENT,
2726 static struct clk_regmap g12a_vpu_0_div = {
2727 .data = &(struct clk_regmap_div_data){
2728 .offset = HHI_VPU_CLK_CNTL,
2732 .hw.init = &(struct clk_init_data){
2733 .name = "vpu_0_div",
2734 .ops = &clk_regmap_divider_ops,
2735 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2737 .flags = CLK_SET_RATE_PARENT,
2741 static struct clk_regmap g12a_vpu_0 = {
2742 .data = &(struct clk_regmap_gate_data){
2743 .offset = HHI_VPU_CLK_CNTL,
2746 .hw.init = &(struct clk_init_data) {
2748 .ops = &clk_regmap_gate_ops,
2749 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2751 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2755 static struct clk_regmap g12a_vpu_1_sel = {
2756 .data = &(struct clk_regmap_mux_data){
2757 .offset = HHI_VPU_CLK_CNTL,
2761 .hw.init = &(struct clk_init_data){
2762 .name = "vpu_1_sel",
2763 .ops = &clk_regmap_mux_ops,
2764 .parent_hws = g12a_vpu_parent_hws,
2765 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2766 .flags = CLK_SET_RATE_NO_REPARENT,
2770 static struct clk_regmap g12a_vpu_1_div = {
2771 .data = &(struct clk_regmap_div_data){
2772 .offset = HHI_VPU_CLK_CNTL,
2776 .hw.init = &(struct clk_init_data){
2777 .name = "vpu_1_div",
2778 .ops = &clk_regmap_divider_ops,
2779 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2781 .flags = CLK_SET_RATE_PARENT,
2785 static struct clk_regmap g12a_vpu_1 = {
2786 .data = &(struct clk_regmap_gate_data){
2787 .offset = HHI_VPU_CLK_CNTL,
2790 .hw.init = &(struct clk_init_data) {
2792 .ops = &clk_regmap_gate_ops,
2793 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2795 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2799 static struct clk_regmap g12a_vpu = {
2800 .data = &(struct clk_regmap_mux_data){
2801 .offset = HHI_VPU_CLK_CNTL,
2805 .hw.init = &(struct clk_init_data){
2807 .ops = &clk_regmap_mux_ops,
2809 * bit 31 selects from 2 possible parents:
2812 .parent_hws = (const struct clk_hw *[]) {
2817 .flags = CLK_SET_RATE_NO_REPARENT,
2823 static const struct clk_hw *g12a_vdec_parent_hws[] = {
2824 &g12a_fclk_div2p5.hw,
2833 static struct clk_regmap g12a_vdec_1_sel = {
2834 .data = &(struct clk_regmap_mux_data){
2835 .offset = HHI_VDEC_CLK_CNTL,
2838 .flags = CLK_MUX_ROUND_CLOSEST,
2840 .hw.init = &(struct clk_init_data){
2841 .name = "vdec_1_sel",
2842 .ops = &clk_regmap_mux_ops,
2843 .parent_hws = g12a_vdec_parent_hws,
2844 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2845 .flags = CLK_SET_RATE_PARENT,
2849 static struct clk_regmap g12a_vdec_1_div = {
2850 .data = &(struct clk_regmap_div_data){
2851 .offset = HHI_VDEC_CLK_CNTL,
2854 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2856 .hw.init = &(struct clk_init_data){
2857 .name = "vdec_1_div",
2858 .ops = &clk_regmap_divider_ops,
2859 .parent_hws = (const struct clk_hw *[]) {
2863 .flags = CLK_SET_RATE_PARENT,
2867 static struct clk_regmap g12a_vdec_1 = {
2868 .data = &(struct clk_regmap_gate_data){
2869 .offset = HHI_VDEC_CLK_CNTL,
2872 .hw.init = &(struct clk_init_data) {
2874 .ops = &clk_regmap_gate_ops,
2875 .parent_hws = (const struct clk_hw *[]) {
2879 .flags = CLK_SET_RATE_PARENT,
2883 static struct clk_regmap g12a_vdec_hevcf_sel = {
2884 .data = &(struct clk_regmap_mux_data){
2885 .offset = HHI_VDEC2_CLK_CNTL,
2888 .flags = CLK_MUX_ROUND_CLOSEST,
2890 .hw.init = &(struct clk_init_data){
2891 .name = "vdec_hevcf_sel",
2892 .ops = &clk_regmap_mux_ops,
2893 .parent_hws = g12a_vdec_parent_hws,
2894 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2895 .flags = CLK_SET_RATE_PARENT,
2899 static struct clk_regmap g12a_vdec_hevcf_div = {
2900 .data = &(struct clk_regmap_div_data){
2901 .offset = HHI_VDEC2_CLK_CNTL,
2904 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2906 .hw.init = &(struct clk_init_data){
2907 .name = "vdec_hevcf_div",
2908 .ops = &clk_regmap_divider_ops,
2909 .parent_hws = (const struct clk_hw *[]) {
2910 &g12a_vdec_hevcf_sel.hw
2913 .flags = CLK_SET_RATE_PARENT,
2917 static struct clk_regmap g12a_vdec_hevcf = {
2918 .data = &(struct clk_regmap_gate_data){
2919 .offset = HHI_VDEC2_CLK_CNTL,
2922 .hw.init = &(struct clk_init_data) {
2923 .name = "vdec_hevcf",
2924 .ops = &clk_regmap_gate_ops,
2925 .parent_hws = (const struct clk_hw *[]) {
2926 &g12a_vdec_hevcf_div.hw
2929 .flags = CLK_SET_RATE_PARENT,
2933 static struct clk_regmap g12a_vdec_hevc_sel = {
2934 .data = &(struct clk_regmap_mux_data){
2935 .offset = HHI_VDEC2_CLK_CNTL,
2938 .flags = CLK_MUX_ROUND_CLOSEST,
2940 .hw.init = &(struct clk_init_data){
2941 .name = "vdec_hevc_sel",
2942 .ops = &clk_regmap_mux_ops,
2943 .parent_hws = g12a_vdec_parent_hws,
2944 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2945 .flags = CLK_SET_RATE_PARENT,
2949 static struct clk_regmap g12a_vdec_hevc_div = {
2950 .data = &(struct clk_regmap_div_data){
2951 .offset = HHI_VDEC2_CLK_CNTL,
2954 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2956 .hw.init = &(struct clk_init_data){
2957 .name = "vdec_hevc_div",
2958 .ops = &clk_regmap_divider_ops,
2959 .parent_hws = (const struct clk_hw *[]) {
2960 &g12a_vdec_hevc_sel.hw
2963 .flags = CLK_SET_RATE_PARENT,
2967 static struct clk_regmap g12a_vdec_hevc = {
2968 .data = &(struct clk_regmap_gate_data){
2969 .offset = HHI_VDEC2_CLK_CNTL,
2972 .hw.init = &(struct clk_init_data) {
2973 .name = "vdec_hevc",
2974 .ops = &clk_regmap_gate_ops,
2975 .parent_hws = (const struct clk_hw *[]) {
2976 &g12a_vdec_hevc_div.hw
2979 .flags = CLK_SET_RATE_PARENT,
2985 static const struct clk_hw *g12a_vapb_parent_hws[] = {
2993 &g12a_fclk_div2p5.hw,
2996 static struct clk_regmap g12a_vapb_0_sel = {
2997 .data = &(struct clk_regmap_mux_data){
2998 .offset = HHI_VAPBCLK_CNTL,
3002 .hw.init = &(struct clk_init_data){
3003 .name = "vapb_0_sel",
3004 .ops = &clk_regmap_mux_ops,
3005 .parent_hws = g12a_vapb_parent_hws,
3006 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3007 .flags = CLK_SET_RATE_NO_REPARENT,
3011 static struct clk_regmap g12a_vapb_0_div = {
3012 .data = &(struct clk_regmap_div_data){
3013 .offset = HHI_VAPBCLK_CNTL,
3017 .hw.init = &(struct clk_init_data){
3018 .name = "vapb_0_div",
3019 .ops = &clk_regmap_divider_ops,
3020 .parent_hws = (const struct clk_hw *[]) {
3024 .flags = CLK_SET_RATE_PARENT,
3028 static struct clk_regmap g12a_vapb_0 = {
3029 .data = &(struct clk_regmap_gate_data){
3030 .offset = HHI_VAPBCLK_CNTL,
3033 .hw.init = &(struct clk_init_data) {
3035 .ops = &clk_regmap_gate_ops,
3036 .parent_hws = (const struct clk_hw *[]) {
3040 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3044 static struct clk_regmap g12a_vapb_1_sel = {
3045 .data = &(struct clk_regmap_mux_data){
3046 .offset = HHI_VAPBCLK_CNTL,
3050 .hw.init = &(struct clk_init_data){
3051 .name = "vapb_1_sel",
3052 .ops = &clk_regmap_mux_ops,
3053 .parent_hws = g12a_vapb_parent_hws,
3054 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3055 .flags = CLK_SET_RATE_NO_REPARENT,
3059 static struct clk_regmap g12a_vapb_1_div = {
3060 .data = &(struct clk_regmap_div_data){
3061 .offset = HHI_VAPBCLK_CNTL,
3065 .hw.init = &(struct clk_init_data){
3066 .name = "vapb_1_div",
3067 .ops = &clk_regmap_divider_ops,
3068 .parent_hws = (const struct clk_hw *[]) {
3072 .flags = CLK_SET_RATE_PARENT,
3076 static struct clk_regmap g12a_vapb_1 = {
3077 .data = &(struct clk_regmap_gate_data){
3078 .offset = HHI_VAPBCLK_CNTL,
3081 .hw.init = &(struct clk_init_data) {
3083 .ops = &clk_regmap_gate_ops,
3084 .parent_hws = (const struct clk_hw *[]) {
3088 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3092 static struct clk_regmap g12a_vapb_sel = {
3093 .data = &(struct clk_regmap_mux_data){
3094 .offset = HHI_VAPBCLK_CNTL,
3098 .hw.init = &(struct clk_init_data){
3100 .ops = &clk_regmap_mux_ops,
3102 * bit 31 selects from 2 possible parents:
3105 .parent_hws = (const struct clk_hw *[]) {
3110 .flags = CLK_SET_RATE_NO_REPARENT,
3114 static struct clk_regmap g12a_vapb = {
3115 .data = &(struct clk_regmap_gate_data){
3116 .offset = HHI_VAPBCLK_CNTL,
3119 .hw.init = &(struct clk_init_data) {
3121 .ops = &clk_regmap_gate_ops,
3122 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3124 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3128 static const struct clk_hw *g12a_vclk_parent_hws[] = {
3139 static struct clk_regmap g12a_vclk_sel = {
3140 .data = &(struct clk_regmap_mux_data){
3141 .offset = HHI_VID_CLK_CNTL,
3145 .hw.init = &(struct clk_init_data){
3147 .ops = &clk_regmap_mux_ops,
3148 .parent_hws = g12a_vclk_parent_hws,
3149 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3150 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3154 static struct clk_regmap g12a_vclk2_sel = {
3155 .data = &(struct clk_regmap_mux_data){
3156 .offset = HHI_VIID_CLK_CNTL,
3160 .hw.init = &(struct clk_init_data){
3161 .name = "vclk2_sel",
3162 .ops = &clk_regmap_mux_ops,
3163 .parent_hws = g12a_vclk_parent_hws,
3164 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3165 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3169 static struct clk_regmap g12a_vclk_input = {
3170 .data = &(struct clk_regmap_gate_data){
3171 .offset = HHI_VID_CLK_DIV,
3174 .hw.init = &(struct clk_init_data) {
3175 .name = "vclk_input",
3176 .ops = &clk_regmap_gate_ops,
3177 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3179 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3183 static struct clk_regmap g12a_vclk2_input = {
3184 .data = &(struct clk_regmap_gate_data){
3185 .offset = HHI_VIID_CLK_DIV,
3188 .hw.init = &(struct clk_init_data) {
3189 .name = "vclk2_input",
3190 .ops = &clk_regmap_gate_ops,
3191 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3193 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3197 static struct clk_regmap g12a_vclk_div = {
3198 .data = &(struct clk_regmap_div_data){
3199 .offset = HHI_VID_CLK_DIV,
3203 .hw.init = &(struct clk_init_data){
3205 .ops = &clk_regmap_divider_ops,
3206 .parent_hws = (const struct clk_hw *[]) {
3210 .flags = CLK_GET_RATE_NOCACHE,
3214 static struct clk_regmap g12a_vclk2_div = {
3215 .data = &(struct clk_regmap_div_data){
3216 .offset = HHI_VIID_CLK_DIV,
3220 .hw.init = &(struct clk_init_data){
3221 .name = "vclk2_div",
3222 .ops = &clk_regmap_divider_ops,
3223 .parent_hws = (const struct clk_hw *[]) {
3224 &g12a_vclk2_input.hw
3227 .flags = CLK_GET_RATE_NOCACHE,
3231 static struct clk_regmap g12a_vclk = {
3232 .data = &(struct clk_regmap_gate_data){
3233 .offset = HHI_VID_CLK_CNTL,
3236 .hw.init = &(struct clk_init_data) {
3238 .ops = &clk_regmap_gate_ops,
3239 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3241 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3245 static struct clk_regmap g12a_vclk2 = {
3246 .data = &(struct clk_regmap_gate_data){
3247 .offset = HHI_VIID_CLK_CNTL,
3250 .hw.init = &(struct clk_init_data) {
3252 .ops = &clk_regmap_gate_ops,
3253 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3255 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3259 static struct clk_regmap g12a_vclk_div1 = {
3260 .data = &(struct clk_regmap_gate_data){
3261 .offset = HHI_VID_CLK_CNTL,
3264 .hw.init = &(struct clk_init_data) {
3265 .name = "vclk_div1",
3266 .ops = &clk_regmap_gate_ops,
3267 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3269 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3273 static struct clk_regmap g12a_vclk_div2_en = {
3274 .data = &(struct clk_regmap_gate_data){
3275 .offset = HHI_VID_CLK_CNTL,
3278 .hw.init = &(struct clk_init_data) {
3279 .name = "vclk_div2_en",
3280 .ops = &clk_regmap_gate_ops,
3281 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3283 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3287 static struct clk_regmap g12a_vclk_div4_en = {
3288 .data = &(struct clk_regmap_gate_data){
3289 .offset = HHI_VID_CLK_CNTL,
3292 .hw.init = &(struct clk_init_data) {
3293 .name = "vclk_div4_en",
3294 .ops = &clk_regmap_gate_ops,
3295 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3297 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3301 static struct clk_regmap g12a_vclk_div6_en = {
3302 .data = &(struct clk_regmap_gate_data){
3303 .offset = HHI_VID_CLK_CNTL,
3306 .hw.init = &(struct clk_init_data) {
3307 .name = "vclk_div6_en",
3308 .ops = &clk_regmap_gate_ops,
3309 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3311 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3315 static struct clk_regmap g12a_vclk_div12_en = {
3316 .data = &(struct clk_regmap_gate_data){
3317 .offset = HHI_VID_CLK_CNTL,
3320 .hw.init = &(struct clk_init_data) {
3321 .name = "vclk_div12_en",
3322 .ops = &clk_regmap_gate_ops,
3323 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3325 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3329 static struct clk_regmap g12a_vclk2_div1 = {
3330 .data = &(struct clk_regmap_gate_data){
3331 .offset = HHI_VIID_CLK_CNTL,
3334 .hw.init = &(struct clk_init_data) {
3335 .name = "vclk2_div1",
3336 .ops = &clk_regmap_gate_ops,
3337 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3339 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3343 static struct clk_regmap g12a_vclk2_div2_en = {
3344 .data = &(struct clk_regmap_gate_data){
3345 .offset = HHI_VIID_CLK_CNTL,
3348 .hw.init = &(struct clk_init_data) {
3349 .name = "vclk2_div2_en",
3350 .ops = &clk_regmap_gate_ops,
3351 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3353 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3357 static struct clk_regmap g12a_vclk2_div4_en = {
3358 .data = &(struct clk_regmap_gate_data){
3359 .offset = HHI_VIID_CLK_CNTL,
3362 .hw.init = &(struct clk_init_data) {
3363 .name = "vclk2_div4_en",
3364 .ops = &clk_regmap_gate_ops,
3365 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3367 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3371 static struct clk_regmap g12a_vclk2_div6_en = {
3372 .data = &(struct clk_regmap_gate_data){
3373 .offset = HHI_VIID_CLK_CNTL,
3376 .hw.init = &(struct clk_init_data) {
3377 .name = "vclk2_div6_en",
3378 .ops = &clk_regmap_gate_ops,
3379 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3381 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3385 static struct clk_regmap g12a_vclk2_div12_en = {
3386 .data = &(struct clk_regmap_gate_data){
3387 .offset = HHI_VIID_CLK_CNTL,
3390 .hw.init = &(struct clk_init_data) {
3391 .name = "vclk2_div12_en",
3392 .ops = &clk_regmap_gate_ops,
3393 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3395 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3399 static struct clk_fixed_factor g12a_vclk_div2 = {
3402 .hw.init = &(struct clk_init_data){
3403 .name = "vclk_div2",
3404 .ops = &clk_fixed_factor_ops,
3405 .parent_hws = (const struct clk_hw *[]) {
3406 &g12a_vclk_div2_en.hw
3412 static struct clk_fixed_factor g12a_vclk_div4 = {
3415 .hw.init = &(struct clk_init_data){
3416 .name = "vclk_div4",
3417 .ops = &clk_fixed_factor_ops,
3418 .parent_hws = (const struct clk_hw *[]) {
3419 &g12a_vclk_div4_en.hw
3425 static struct clk_fixed_factor g12a_vclk_div6 = {
3428 .hw.init = &(struct clk_init_data){
3429 .name = "vclk_div6",
3430 .ops = &clk_fixed_factor_ops,
3431 .parent_hws = (const struct clk_hw *[]) {
3432 &g12a_vclk_div6_en.hw
3438 static struct clk_fixed_factor g12a_vclk_div12 = {
3441 .hw.init = &(struct clk_init_data){
3442 .name = "vclk_div12",
3443 .ops = &clk_fixed_factor_ops,
3444 .parent_hws = (const struct clk_hw *[]) {
3445 &g12a_vclk_div12_en.hw
3451 static struct clk_fixed_factor g12a_vclk2_div2 = {
3454 .hw.init = &(struct clk_init_data){
3455 .name = "vclk2_div2",
3456 .ops = &clk_fixed_factor_ops,
3457 .parent_hws = (const struct clk_hw *[]) {
3458 &g12a_vclk2_div2_en.hw
3464 static struct clk_fixed_factor g12a_vclk2_div4 = {
3467 .hw.init = &(struct clk_init_data){
3468 .name = "vclk2_div4",
3469 .ops = &clk_fixed_factor_ops,
3470 .parent_hws = (const struct clk_hw *[]) {
3471 &g12a_vclk2_div4_en.hw
3477 static struct clk_fixed_factor g12a_vclk2_div6 = {
3480 .hw.init = &(struct clk_init_data){
3481 .name = "vclk2_div6",
3482 .ops = &clk_fixed_factor_ops,
3483 .parent_hws = (const struct clk_hw *[]) {
3484 &g12a_vclk2_div6_en.hw
3490 static struct clk_fixed_factor g12a_vclk2_div12 = {
3493 .hw.init = &(struct clk_init_data){
3494 .name = "vclk2_div12",
3495 .ops = &clk_fixed_factor_ops,
3496 .parent_hws = (const struct clk_hw *[]) {
3497 &g12a_vclk2_div12_en.hw
3503 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3504 static const struct clk_hw *g12a_cts_parent_hws[] = {
3509 &g12a_vclk_div12.hw,
3510 &g12a_vclk2_div1.hw,
3511 &g12a_vclk2_div2.hw,
3512 &g12a_vclk2_div4.hw,
3513 &g12a_vclk2_div6.hw,
3514 &g12a_vclk2_div12.hw,
3517 static struct clk_regmap g12a_cts_enci_sel = {
3518 .data = &(struct clk_regmap_mux_data){
3519 .offset = HHI_VID_CLK_DIV,
3522 .table = mux_table_cts_sel,
3524 .hw.init = &(struct clk_init_data){
3525 .name = "cts_enci_sel",
3526 .ops = &clk_regmap_mux_ops,
3527 .parent_hws = g12a_cts_parent_hws,
3528 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3529 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3533 static struct clk_regmap g12a_cts_encp_sel = {
3534 .data = &(struct clk_regmap_mux_data){
3535 .offset = HHI_VID_CLK_DIV,
3538 .table = mux_table_cts_sel,
3540 .hw.init = &(struct clk_init_data){
3541 .name = "cts_encp_sel",
3542 .ops = &clk_regmap_mux_ops,
3543 .parent_hws = g12a_cts_parent_hws,
3544 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3545 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3549 static struct clk_regmap g12a_cts_vdac_sel = {
3550 .data = &(struct clk_regmap_mux_data){
3551 .offset = HHI_VIID_CLK_DIV,
3554 .table = mux_table_cts_sel,
3556 .hw.init = &(struct clk_init_data){
3557 .name = "cts_vdac_sel",
3558 .ops = &clk_regmap_mux_ops,
3559 .parent_hws = g12a_cts_parent_hws,
3560 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3561 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3565 /* TOFIX: add support for cts_tcon */
3566 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3567 static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3572 &g12a_vclk_div12.hw,
3573 &g12a_vclk2_div1.hw,
3574 &g12a_vclk2_div2.hw,
3575 &g12a_vclk2_div4.hw,
3576 &g12a_vclk2_div6.hw,
3577 &g12a_vclk2_div12.hw,
3580 static struct clk_regmap g12a_hdmi_tx_sel = {
3581 .data = &(struct clk_regmap_mux_data){
3582 .offset = HHI_HDMI_CLK_CNTL,
3585 .table = mux_table_hdmi_tx_sel,
3587 .hw.init = &(struct clk_init_data){
3588 .name = "hdmi_tx_sel",
3589 .ops = &clk_regmap_mux_ops,
3590 .parent_hws = g12a_cts_hdmi_tx_parent_hws,
3591 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3592 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3596 static struct clk_regmap g12a_cts_enci = {
3597 .data = &(struct clk_regmap_gate_data){
3598 .offset = HHI_VID_CLK_CNTL2,
3601 .hw.init = &(struct clk_init_data) {
3603 .ops = &clk_regmap_gate_ops,
3604 .parent_hws = (const struct clk_hw *[]) {
3605 &g12a_cts_enci_sel.hw
3608 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3612 static struct clk_regmap g12a_cts_encp = {
3613 .data = &(struct clk_regmap_gate_data){
3614 .offset = HHI_VID_CLK_CNTL2,
3617 .hw.init = &(struct clk_init_data) {
3619 .ops = &clk_regmap_gate_ops,
3620 .parent_hws = (const struct clk_hw *[]) {
3621 &g12a_cts_encp_sel.hw
3624 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3628 static struct clk_regmap g12a_cts_vdac = {
3629 .data = &(struct clk_regmap_gate_data){
3630 .offset = HHI_VID_CLK_CNTL2,
3633 .hw.init = &(struct clk_init_data) {
3635 .ops = &clk_regmap_gate_ops,
3636 .parent_hws = (const struct clk_hw *[]) {
3637 &g12a_cts_vdac_sel.hw
3640 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3644 static struct clk_regmap g12a_hdmi_tx = {
3645 .data = &(struct clk_regmap_gate_data){
3646 .offset = HHI_VID_CLK_CNTL2,
3649 .hw.init = &(struct clk_init_data) {
3651 .ops = &clk_regmap_gate_ops,
3652 .parent_hws = (const struct clk_hw *[]) {
3653 &g12a_hdmi_tx_sel.hw
3656 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3662 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3663 { .fw_name = "xtal", },
3664 { .hw = &g12a_fclk_div4.hw },
3665 { .hw = &g12a_fclk_div3.hw },
3666 { .hw = &g12a_fclk_div5.hw },
3669 static struct clk_regmap g12a_hdmi_sel = {
3670 .data = &(struct clk_regmap_mux_data){
3671 .offset = HHI_HDMI_CLK_CNTL,
3674 .flags = CLK_MUX_ROUND_CLOSEST,
3676 .hw.init = &(struct clk_init_data){
3678 .ops = &clk_regmap_mux_ops,
3679 .parent_data = g12a_hdmi_parent_data,
3680 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3681 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3685 static struct clk_regmap g12a_hdmi_div = {
3686 .data = &(struct clk_regmap_div_data){
3687 .offset = HHI_HDMI_CLK_CNTL,
3691 .hw.init = &(struct clk_init_data){
3693 .ops = &clk_regmap_divider_ops,
3694 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3696 .flags = CLK_GET_RATE_NOCACHE,
3700 static struct clk_regmap g12a_hdmi = {
3701 .data = &(struct clk_regmap_gate_data){
3702 .offset = HHI_HDMI_CLK_CNTL,
3705 .hw.init = &(struct clk_init_data) {
3707 .ops = &clk_regmap_gate_ops,
3708 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3710 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3715 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3716 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3717 * mux because it does top-to-bottom updates the each clock tree and
3718 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
3720 static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3721 { .fw_name = "xtal", },
3722 { .hw = &g12a_gp0_pll.hw },
3723 { .hw = &g12a_hifi_pll.hw },
3724 { .hw = &g12a_fclk_div2p5.hw },
3725 { .hw = &g12a_fclk_div3.hw },
3726 { .hw = &g12a_fclk_div4.hw },
3727 { .hw = &g12a_fclk_div5.hw },
3728 { .hw = &g12a_fclk_div7.hw },
3731 static struct clk_regmap g12a_mali_0_sel = {
3732 .data = &(struct clk_regmap_mux_data){
3733 .offset = HHI_MALI_CLK_CNTL,
3737 .hw.init = &(struct clk_init_data){
3738 .name = "mali_0_sel",
3739 .ops = &clk_regmap_mux_ops,
3740 .parent_data = g12a_mali_0_1_parent_data,
3743 * Don't request the parent to change the rate because
3744 * all GPU frequencies can be derived from the fclk_*
3745 * clocks and one special GP0_PLL setting. This is
3746 * important because we need the MPLL clocks for audio.
3752 static struct clk_regmap g12a_mali_0_div = {
3753 .data = &(struct clk_regmap_div_data){
3754 .offset = HHI_MALI_CLK_CNTL,
3758 .hw.init = &(struct clk_init_data){
3759 .name = "mali_0_div",
3760 .ops = &clk_regmap_divider_ops,
3761 .parent_hws = (const struct clk_hw *[]) {
3765 .flags = CLK_SET_RATE_PARENT,
3769 static struct clk_regmap g12a_mali_0 = {
3770 .data = &(struct clk_regmap_gate_data){
3771 .offset = HHI_MALI_CLK_CNTL,
3774 .hw.init = &(struct clk_init_data){
3776 .ops = &clk_regmap_gate_ops,
3777 .parent_hws = (const struct clk_hw *[]) {
3781 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3785 static struct clk_regmap g12a_mali_1_sel = {
3786 .data = &(struct clk_regmap_mux_data){
3787 .offset = HHI_MALI_CLK_CNTL,
3791 .hw.init = &(struct clk_init_data){
3792 .name = "mali_1_sel",
3793 .ops = &clk_regmap_mux_ops,
3794 .parent_data = g12a_mali_0_1_parent_data,
3797 * Don't request the parent to change the rate because
3798 * all GPU frequencies can be derived from the fclk_*
3799 * clocks and one special GP0_PLL setting. This is
3800 * important because we need the MPLL clocks for audio.
3806 static struct clk_regmap g12a_mali_1_div = {
3807 .data = &(struct clk_regmap_div_data){
3808 .offset = HHI_MALI_CLK_CNTL,
3812 .hw.init = &(struct clk_init_data){
3813 .name = "mali_1_div",
3814 .ops = &clk_regmap_divider_ops,
3815 .parent_hws = (const struct clk_hw *[]) {
3819 .flags = CLK_SET_RATE_PARENT,
3823 static struct clk_regmap g12a_mali_1 = {
3824 .data = &(struct clk_regmap_gate_data){
3825 .offset = HHI_MALI_CLK_CNTL,
3828 .hw.init = &(struct clk_init_data){
3830 .ops = &clk_regmap_gate_ops,
3831 .parent_hws = (const struct clk_hw *[]) {
3835 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3839 static const struct clk_hw *g12a_mali_parent_hws[] = {
3844 static struct clk_regmap g12a_mali = {
3845 .data = &(struct clk_regmap_mux_data){
3846 .offset = HHI_MALI_CLK_CNTL,
3850 .hw.init = &(struct clk_init_data){
3852 .ops = &clk_regmap_mux_ops,
3853 .parent_hws = g12a_mali_parent_hws,
3855 .flags = CLK_SET_RATE_PARENT,
3859 static struct clk_regmap g12a_ts_div = {
3860 .data = &(struct clk_regmap_div_data){
3861 .offset = HHI_TS_CLK_CNTL,
3865 .hw.init = &(struct clk_init_data){
3867 .ops = &clk_regmap_divider_ro_ops,
3868 .parent_data = &(const struct clk_parent_data) {
3875 static struct clk_regmap g12a_ts = {
3876 .data = &(struct clk_regmap_gate_data){
3877 .offset = HHI_TS_CLK_CNTL,
3880 .hw.init = &(struct clk_init_data){
3882 .ops = &clk_regmap_gate_ops,
3883 .parent_hws = (const struct clk_hw *[]) {
3890 /* SPICC SCLK source clock */
3892 static const struct clk_parent_data spicc_sclk_parent_data[] = {
3893 { .fw_name = "xtal", },
3894 { .hw = &g12a_clk81.hw },
3895 { .hw = &g12a_fclk_div4.hw },
3896 { .hw = &g12a_fclk_div3.hw },
3897 { .hw = &g12a_fclk_div5.hw },
3898 { .hw = &g12a_fclk_div7.hw },
3901 static struct clk_regmap g12a_spicc0_sclk_sel = {
3902 .data = &(struct clk_regmap_mux_data){
3903 .offset = HHI_SPICC_CLK_CNTL,
3907 .hw.init = &(struct clk_init_data){
3908 .name = "spicc0_sclk_sel",
3909 .ops = &clk_regmap_mux_ops,
3910 .parent_data = spicc_sclk_parent_data,
3911 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3915 static struct clk_regmap g12a_spicc0_sclk_div = {
3916 .data = &(struct clk_regmap_div_data){
3917 .offset = HHI_SPICC_CLK_CNTL,
3921 .hw.init = &(struct clk_init_data){
3922 .name = "spicc0_sclk_div",
3923 .ops = &clk_regmap_divider_ops,
3924 .parent_hws = (const struct clk_hw *[]) {
3925 &g12a_spicc0_sclk_sel.hw
3928 .flags = CLK_SET_RATE_PARENT,
3932 static struct clk_regmap g12a_spicc0_sclk = {
3933 .data = &(struct clk_regmap_gate_data){
3934 .offset = HHI_SPICC_CLK_CNTL,
3937 .hw.init = &(struct clk_init_data){
3938 .name = "spicc0_sclk",
3939 .ops = &clk_regmap_gate_ops,
3940 .parent_hws = (const struct clk_hw *[]) {
3941 &g12a_spicc0_sclk_div.hw
3944 .flags = CLK_SET_RATE_PARENT,
3948 static struct clk_regmap g12a_spicc1_sclk_sel = {
3949 .data = &(struct clk_regmap_mux_data){
3950 .offset = HHI_SPICC_CLK_CNTL,
3954 .hw.init = &(struct clk_init_data){
3955 .name = "spicc1_sclk_sel",
3956 .ops = &clk_regmap_mux_ops,
3957 .parent_data = spicc_sclk_parent_data,
3958 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3962 static struct clk_regmap g12a_spicc1_sclk_div = {
3963 .data = &(struct clk_regmap_div_data){
3964 .offset = HHI_SPICC_CLK_CNTL,
3968 .hw.init = &(struct clk_init_data){
3969 .name = "spicc1_sclk_div",
3970 .ops = &clk_regmap_divider_ops,
3971 .parent_hws = (const struct clk_hw *[]) {
3972 &g12a_spicc1_sclk_sel.hw
3975 .flags = CLK_SET_RATE_PARENT,
3979 static struct clk_regmap g12a_spicc1_sclk = {
3980 .data = &(struct clk_regmap_gate_data){
3981 .offset = HHI_SPICC_CLK_CNTL,
3984 .hw.init = &(struct clk_init_data){
3985 .name = "spicc1_sclk",
3986 .ops = &clk_regmap_gate_ops,
3987 .parent_hws = (const struct clk_hw *[]) {
3988 &g12a_spicc1_sclk_div.hw
3991 .flags = CLK_SET_RATE_PARENT,
3995 /* Neural Network Accelerator source clock */
3997 static const struct clk_parent_data nna_clk_parent_data[] = {
3998 { .fw_name = "xtal", },
3999 { .hw = &g12a_gp0_pll.hw, },
4000 { .hw = &g12a_hifi_pll.hw, },
4001 { .hw = &g12a_fclk_div2p5.hw, },
4002 { .hw = &g12a_fclk_div3.hw, },
4003 { .hw = &g12a_fclk_div4.hw, },
4004 { .hw = &g12a_fclk_div5.hw, },
4005 { .hw = &g12a_fclk_div7.hw },
4008 static struct clk_regmap sm1_nna_axi_clk_sel = {
4009 .data = &(struct clk_regmap_mux_data){
4010 .offset = HHI_NNA_CLK_CNTL,
4014 .hw.init = &(struct clk_init_data){
4015 .name = "nna_axi_clk_sel",
4016 .ops = &clk_regmap_mux_ops,
4017 .parent_data = nna_clk_parent_data,
4018 .num_parents = ARRAY_SIZE(nna_clk_parent_data),
4022 static struct clk_regmap sm1_nna_axi_clk_div = {
4023 .data = &(struct clk_regmap_div_data){
4024 .offset = HHI_NNA_CLK_CNTL,
4028 .hw.init = &(struct clk_init_data){
4029 .name = "nna_axi_clk_div",
4030 .ops = &clk_regmap_divider_ops,
4031 .parent_hws = (const struct clk_hw *[]) {
4032 &sm1_nna_axi_clk_sel.hw
4035 .flags = CLK_SET_RATE_PARENT,
4039 static struct clk_regmap sm1_nna_axi_clk = {
4040 .data = &(struct clk_regmap_gate_data){
4041 .offset = HHI_NNA_CLK_CNTL,
4044 .hw.init = &(struct clk_init_data){
4045 .name = "nna_axi_clk",
4046 .ops = &clk_regmap_gate_ops,
4047 .parent_hws = (const struct clk_hw *[]) {
4048 &sm1_nna_axi_clk_div.hw
4051 .flags = CLK_SET_RATE_PARENT,
4055 static struct clk_regmap sm1_nna_core_clk_sel = {
4056 .data = &(struct clk_regmap_mux_data){
4057 .offset = HHI_NNA_CLK_CNTL,
4061 .hw.init = &(struct clk_init_data){
4062 .name = "nna_core_clk_sel",
4063 .ops = &clk_regmap_mux_ops,
4064 .parent_data = nna_clk_parent_data,
4065 .num_parents = ARRAY_SIZE(nna_clk_parent_data),
4069 static struct clk_regmap sm1_nna_core_clk_div = {
4070 .data = &(struct clk_regmap_div_data){
4071 .offset = HHI_NNA_CLK_CNTL,
4075 .hw.init = &(struct clk_init_data){
4076 .name = "nna_core_clk_div",
4077 .ops = &clk_regmap_divider_ops,
4078 .parent_hws = (const struct clk_hw *[]) {
4079 &sm1_nna_core_clk_sel.hw
4082 .flags = CLK_SET_RATE_PARENT,
4086 static struct clk_regmap sm1_nna_core_clk = {
4087 .data = &(struct clk_regmap_gate_data){
4088 .offset = HHI_NNA_CLK_CNTL,
4091 .hw.init = &(struct clk_init_data){
4092 .name = "nna_core_clk",
4093 .ops = &clk_regmap_gate_ops,
4094 .parent_hws = (const struct clk_hw *[]) {
4095 &sm1_nna_core_clk_div.hw
4098 .flags = CLK_SET_RATE_PARENT,
4102 #define MESON_GATE(_name, _reg, _bit) \
4103 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4105 #define MESON_GATE_RO(_name, _reg, _bit) \
4106 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4108 /* Everything Else (EE) domain gates */
4109 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
4110 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
4111 static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
4112 static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
4113 static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
4114 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
4115 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
4116 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
4117 static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
4118 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
4119 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
4120 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
4121 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
4122 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
4123 static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
4124 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
4125 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
4126 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
4127 static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
4128 static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
4129 static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
4130 static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
4132 static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
4133 static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
4134 static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
4135 static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
4136 static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
4137 static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
4138 static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
4139 static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
4140 static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
4141 static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
4142 static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
4143 static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
4144 static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
4146 static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
4147 static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
4148 static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
4149 static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
4150 static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
4151 static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
4152 static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
4153 static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
4154 static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
4155 static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
4157 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
4158 static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
4159 static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
4160 static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
4161 static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
4162 static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
4163 static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
4164 static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
4165 static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
4166 static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
4167 static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
4168 static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
4169 static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
4170 static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
4171 static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
4172 static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
4173 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
4174 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
4175 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
4177 static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
4178 static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
4179 static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
4180 static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
4181 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
4183 /* Array of all clocks provided by this provider */
4184 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
4186 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4187 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4188 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4189 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4190 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4191 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4192 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4193 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4194 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4195 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4196 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4197 [CLKID_CLK81] = &g12a_clk81.hw,
4198 [CLKID_MPLL0] = &g12a_mpll0.hw,
4199 [CLKID_MPLL1] = &g12a_mpll1.hw,
4200 [CLKID_MPLL2] = &g12a_mpll2.hw,
4201 [CLKID_MPLL3] = &g12a_mpll3.hw,
4202 [CLKID_DDR] = &g12a_ddr.hw,
4203 [CLKID_DOS] = &g12a_dos.hw,
4204 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4205 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4206 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4207 [CLKID_ISA] = &g12a_isa.hw,
4208 [CLKID_PL301] = &g12a_pl301.hw,
4209 [CLKID_PERIPHS] = &g12a_periphs.hw,
4210 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4211 [CLKID_I2C] = &g12a_i2c.hw,
4212 [CLKID_SANA] = &g12a_sana.hw,
4213 [CLKID_SD] = &g12a_sd.hw,
4214 [CLKID_RNG0] = &g12a_rng0.hw,
4215 [CLKID_UART0] = &g12a_uart0.hw,
4216 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4217 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4218 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4219 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4220 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4221 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4222 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4223 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4224 [CLKID_AUDIO] = &g12a_audio.hw,
4225 [CLKID_ETH] = &g12a_eth_core.hw,
4226 [CLKID_DEMUX] = &g12a_demux.hw,
4227 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4228 [CLKID_ADC] = &g12a_adc.hw,
4229 [CLKID_UART1] = &g12a_uart1.hw,
4230 [CLKID_G2D] = &g12a_g2d.hw,
4231 [CLKID_RESET] = &g12a_reset.hw,
4232 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4233 [CLKID_PARSER] = &g12a_parser.hw,
4234 [CLKID_USB] = &g12a_usb_general.hw,
4235 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4236 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4237 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4238 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4239 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4240 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4241 [CLKID_BT656] = &g12a_bt656.hw,
4242 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4243 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4244 [CLKID_UART2] = &g12a_uart2.hw,
4245 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4246 [CLKID_GIC] = &g12a_gic.hw,
4247 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4248 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4249 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4250 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4251 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4252 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4253 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4254 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4255 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4256 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4257 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4258 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4259 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4260 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4261 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4262 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4263 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4264 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4265 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4266 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4267 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4268 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4269 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4270 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4271 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4272 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4273 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4274 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4275 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4276 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4277 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4278 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4279 [CLKID_ENC480P] = &g12a_enc480p.hw,
4280 [CLKID_RNG1] = &g12a_rng1.hw,
4281 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4282 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4283 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4284 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4285 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4286 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4287 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4288 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4289 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4290 [CLKID_DMA] = &g12a_dma.hw,
4291 [CLKID_EFUSE] = &g12a_efuse.hw,
4292 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4293 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4294 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4295 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4296 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4297 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4298 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4299 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4300 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4301 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4302 [CLKID_VPU] = &g12a_vpu.hw,
4303 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4304 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4305 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4306 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4307 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4308 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4309 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4310 [CLKID_VAPB] = &g12a_vapb.hw,
4311 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4312 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4313 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4314 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4315 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4316 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4317 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4318 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4319 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4320 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4321 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4322 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4323 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4324 [CLKID_VCLK] = &g12a_vclk.hw,
4325 [CLKID_VCLK2] = &g12a_vclk2.hw,
4326 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4327 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4328 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4329 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4330 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4331 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4332 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4333 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4334 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4335 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4336 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4337 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4338 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4339 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4340 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4341 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4342 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4343 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4344 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4345 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4346 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4347 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4348 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4349 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4350 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4351 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4352 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4353 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4354 [CLKID_HDMI] = &g12a_hdmi.hw,
4355 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4356 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4357 [CLKID_MALI_0] = &g12a_mali_0.hw,
4358 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4359 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4360 [CLKID_MALI_1] = &g12a_mali_1.hw,
4361 [CLKID_MALI] = &g12a_mali.hw,
4362 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4363 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4364 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4365 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4366 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4367 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4368 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4369 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4370 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4371 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4372 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4373 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4374 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4375 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4376 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4377 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4378 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4379 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4380 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4381 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4382 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4383 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4384 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4385 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4386 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4387 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4388 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4389 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4390 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4391 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4392 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4393 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4394 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4395 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4396 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4397 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4398 [CLKID_TS] = &g12a_ts.hw,
4399 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4400 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4401 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4402 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4403 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4404 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4410 static struct clk_hw_onecell_data g12b_hw_onecell_data = {
4412 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4413 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4414 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4415 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4416 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4417 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4418 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4419 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4420 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4421 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4422 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4423 [CLKID_CLK81] = &g12a_clk81.hw,
4424 [CLKID_MPLL0] = &g12a_mpll0.hw,
4425 [CLKID_MPLL1] = &g12a_mpll1.hw,
4426 [CLKID_MPLL2] = &g12a_mpll2.hw,
4427 [CLKID_MPLL3] = &g12a_mpll3.hw,
4428 [CLKID_DDR] = &g12a_ddr.hw,
4429 [CLKID_DOS] = &g12a_dos.hw,
4430 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4431 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4432 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4433 [CLKID_ISA] = &g12a_isa.hw,
4434 [CLKID_PL301] = &g12a_pl301.hw,
4435 [CLKID_PERIPHS] = &g12a_periphs.hw,
4436 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4437 [CLKID_I2C] = &g12a_i2c.hw,
4438 [CLKID_SANA] = &g12a_sana.hw,
4439 [CLKID_SD] = &g12a_sd.hw,
4440 [CLKID_RNG0] = &g12a_rng0.hw,
4441 [CLKID_UART0] = &g12a_uart0.hw,
4442 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4443 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4444 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4445 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4446 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4447 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4448 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4449 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4450 [CLKID_AUDIO] = &g12a_audio.hw,
4451 [CLKID_ETH] = &g12a_eth_core.hw,
4452 [CLKID_DEMUX] = &g12a_demux.hw,
4453 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4454 [CLKID_ADC] = &g12a_adc.hw,
4455 [CLKID_UART1] = &g12a_uart1.hw,
4456 [CLKID_G2D] = &g12a_g2d.hw,
4457 [CLKID_RESET] = &g12a_reset.hw,
4458 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4459 [CLKID_PARSER] = &g12a_parser.hw,
4460 [CLKID_USB] = &g12a_usb_general.hw,
4461 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4462 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4463 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4464 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4465 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4466 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4467 [CLKID_BT656] = &g12a_bt656.hw,
4468 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4469 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4470 [CLKID_UART2] = &g12a_uart2.hw,
4471 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4472 [CLKID_GIC] = &g12a_gic.hw,
4473 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4474 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4475 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4476 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4477 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4478 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4479 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4480 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4481 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4482 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4483 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4484 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4485 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4486 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4487 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4488 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4489 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4490 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4491 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4492 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4493 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4494 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4495 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4496 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4497 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4498 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4499 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4500 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4501 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4502 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4503 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4504 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4505 [CLKID_ENC480P] = &g12a_enc480p.hw,
4506 [CLKID_RNG1] = &g12a_rng1.hw,
4507 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4508 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4509 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4510 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4511 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4512 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4513 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4514 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4515 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4516 [CLKID_DMA] = &g12a_dma.hw,
4517 [CLKID_EFUSE] = &g12a_efuse.hw,
4518 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4519 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4520 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4521 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4522 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4523 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4524 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4525 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4526 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4527 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4528 [CLKID_VPU] = &g12a_vpu.hw,
4529 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4530 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4531 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4532 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4533 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4534 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4535 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4536 [CLKID_VAPB] = &g12a_vapb.hw,
4537 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4538 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4539 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4540 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4541 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4542 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4543 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4544 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4545 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4546 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4547 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4548 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4549 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4550 [CLKID_VCLK] = &g12a_vclk.hw,
4551 [CLKID_VCLK2] = &g12a_vclk2.hw,
4552 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4553 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4554 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4555 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4556 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4557 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4558 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4559 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4560 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4561 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4562 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4563 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4564 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4565 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4566 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4567 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4568 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4569 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4570 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4571 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4572 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4573 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4574 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4575 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4576 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4577 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4578 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4579 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4580 [CLKID_HDMI] = &g12a_hdmi.hw,
4581 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4582 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4583 [CLKID_MALI_0] = &g12a_mali_0.hw,
4584 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4585 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4586 [CLKID_MALI_1] = &g12a_mali_1.hw,
4587 [CLKID_MALI] = &g12a_mali.hw,
4588 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4589 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4590 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4591 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4592 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4593 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4594 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4595 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4596 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4597 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4598 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4599 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4600 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4601 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4602 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4603 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4604 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4605 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4606 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4607 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4608 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4609 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4610 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4611 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4612 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4613 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4614 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4615 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4616 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4617 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4618 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4619 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4620 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4621 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4622 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4623 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4624 [CLKID_TS] = &g12a_ts.hw,
4625 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4626 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4627 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4628 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4629 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4630 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4631 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4632 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4633 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4634 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4635 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4636 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4637 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4638 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4639 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4640 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4641 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4642 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4643 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4644 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4645 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4646 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4647 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4648 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4649 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4650 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4651 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4652 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4653 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4654 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4655 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4656 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4657 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4658 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4659 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4665 static struct clk_hw_onecell_data sm1_hw_onecell_data = {
4667 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4668 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4669 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4670 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4671 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4672 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4673 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4674 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4675 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4676 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4677 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4678 [CLKID_CLK81] = &g12a_clk81.hw,
4679 [CLKID_MPLL0] = &g12a_mpll0.hw,
4680 [CLKID_MPLL1] = &g12a_mpll1.hw,
4681 [CLKID_MPLL2] = &g12a_mpll2.hw,
4682 [CLKID_MPLL3] = &g12a_mpll3.hw,
4683 [CLKID_DDR] = &g12a_ddr.hw,
4684 [CLKID_DOS] = &g12a_dos.hw,
4685 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4686 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4687 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4688 [CLKID_ISA] = &g12a_isa.hw,
4689 [CLKID_PL301] = &g12a_pl301.hw,
4690 [CLKID_PERIPHS] = &g12a_periphs.hw,
4691 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4692 [CLKID_I2C] = &g12a_i2c.hw,
4693 [CLKID_SANA] = &g12a_sana.hw,
4694 [CLKID_SD] = &g12a_sd.hw,
4695 [CLKID_RNG0] = &g12a_rng0.hw,
4696 [CLKID_UART0] = &g12a_uart0.hw,
4697 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4698 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4699 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4700 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4701 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4702 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4703 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4704 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4705 [CLKID_AUDIO] = &g12a_audio.hw,
4706 [CLKID_ETH] = &g12a_eth_core.hw,
4707 [CLKID_DEMUX] = &g12a_demux.hw,
4708 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4709 [CLKID_ADC] = &g12a_adc.hw,
4710 [CLKID_UART1] = &g12a_uart1.hw,
4711 [CLKID_G2D] = &g12a_g2d.hw,
4712 [CLKID_RESET] = &g12a_reset.hw,
4713 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4714 [CLKID_PARSER] = &g12a_parser.hw,
4715 [CLKID_USB] = &g12a_usb_general.hw,
4716 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4717 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4718 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4719 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4720 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4721 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4722 [CLKID_BT656] = &g12a_bt656.hw,
4723 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4724 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4725 [CLKID_UART2] = &g12a_uart2.hw,
4726 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4727 [CLKID_GIC] = &g12a_gic.hw,
4728 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4729 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4730 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4731 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4732 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4733 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4734 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4735 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4736 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4737 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4738 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4739 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4740 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4741 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4742 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4743 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4744 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4745 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4746 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4747 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4748 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4749 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4750 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4751 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4752 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4753 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4754 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4755 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4756 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4757 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4758 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4759 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4760 [CLKID_ENC480P] = &g12a_enc480p.hw,
4761 [CLKID_RNG1] = &g12a_rng1.hw,
4762 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4763 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4764 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4765 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4766 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4767 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4768 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4769 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4770 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4771 [CLKID_DMA] = &g12a_dma.hw,
4772 [CLKID_EFUSE] = &g12a_efuse.hw,
4773 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4774 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4775 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4776 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4777 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4778 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4779 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4780 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4781 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4782 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4783 [CLKID_VPU] = &g12a_vpu.hw,
4784 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4785 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4786 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4787 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4788 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4789 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4790 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4791 [CLKID_VAPB] = &g12a_vapb.hw,
4792 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4793 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4794 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4795 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4796 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4797 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4798 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4799 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4800 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4801 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4802 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4803 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4804 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4805 [CLKID_VCLK] = &g12a_vclk.hw,
4806 [CLKID_VCLK2] = &g12a_vclk2.hw,
4807 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4808 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4809 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4810 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4811 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4812 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4813 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4814 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4815 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4816 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4817 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4818 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4819 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4820 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4821 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4822 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4823 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4824 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4825 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4826 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4827 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4828 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4829 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4830 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4831 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4832 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4833 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4834 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4835 [CLKID_HDMI] = &g12a_hdmi.hw,
4836 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4837 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4838 [CLKID_MALI_0] = &g12a_mali_0.hw,
4839 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4840 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4841 [CLKID_MALI_1] = &g12a_mali_1.hw,
4842 [CLKID_MALI] = &g12a_mali.hw,
4843 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4844 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4845 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4846 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4847 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4848 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4849 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4850 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4851 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4852 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4853 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4854 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4855 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4856 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4857 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4858 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4859 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4860 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4861 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4862 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4863 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4864 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4865 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4866 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4867 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4868 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4869 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4870 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4871 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4872 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4873 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4874 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4875 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4876 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4877 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4878 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4879 [CLKID_TS] = &g12a_ts.hw,
4880 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4881 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4882 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4883 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4884 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4885 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4886 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4887 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4888 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4889 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4890 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4891 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4892 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4893 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4894 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4895 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4896 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4897 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4898 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4899 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4900 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4901 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4902 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4903 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4904 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4905 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4911 /* Convenience table to populate regmap in .probe */
4912 static struct clk_regmap *const g12a_clk_regmaps[] = {
4917 &g12a_mipi_dsi_host,
4959 &g12a_sd_emmc_a_clk0,
4960 &g12a_sd_emmc_b_clk0,
4961 &g12a_sd_emmc_c_clk0,
4963 &g12a_sd_emmc_a_clk0_div,
4964 &g12a_sd_emmc_b_clk0_div,
4965 &g12a_sd_emmc_c_clk0_div,
4967 &g12a_sd_emmc_a_clk0_sel,
4968 &g12a_sd_emmc_b_clk0_sel,
4969 &g12a_sd_emmc_c_clk0_sel,
4998 &g12a_vclk2_venclmmc,
5001 &g12a_fixed_pll_dco,
5050 &g12a_vclk_div12_en,
5052 &g12a_vclk2_div2_en,
5053 &g12a_vclk2_div4_en,
5054 &g12a_vclk2_div6_en,
5055 &g12a_vclk2_div12_en,
5075 &g12a_sys_pll_div16_en,
5076 &g12a_cpu_clk_premux0,
5077 &g12a_cpu_clk_mux0_div,
5078 &g12a_cpu_clk_postmux0,
5079 &g12a_cpu_clk_premux1,
5080 &g12a_cpu_clk_mux1_div,
5081 &g12a_cpu_clk_postmux1,
5084 &g12a_cpu_clk_div16_en,
5085 &g12a_cpu_clk_apb_div,
5087 &g12a_cpu_clk_atb_div,
5089 &g12a_cpu_clk_axi_div,
5091 &g12a_cpu_clk_trace_div,
5092 &g12a_cpu_clk_trace,
5098 &g12a_vdec_hevc_sel,
5099 &g12a_vdec_hevc_div,
5101 &g12a_vdec_hevcf_sel,
5102 &g12a_vdec_hevcf_div,
5109 &g12b_sys1_pll_div16_en,
5110 &g12b_cpub_clk_premux0,
5111 &g12b_cpub_clk_mux0_div,
5112 &g12b_cpub_clk_postmux0,
5113 &g12b_cpub_clk_premux1,
5114 &g12b_cpub_clk_mux1_div,
5115 &g12b_cpub_clk_postmux1,
5118 &g12b_cpub_clk_div16_en,
5119 &g12b_cpub_clk_apb_sel,
5121 &g12b_cpub_clk_atb_sel,
5123 &g12b_cpub_clk_axi_sel,
5125 &g12b_cpub_clk_trace_sel,
5126 &g12b_cpub_clk_trace,
5129 &sm1_dsu_clk_premux0,
5130 &sm1_dsu_clk_premux1,
5131 &sm1_dsu_clk_mux0_div,
5132 &sm1_dsu_clk_postmux0,
5133 &sm1_dsu_clk_mux1_div,
5134 &sm1_dsu_clk_postmux1,
5141 &g12a_spicc0_sclk_sel,
5142 &g12a_spicc0_sclk_div,
5144 &g12a_spicc1_sclk_sel,
5145 &g12a_spicc1_sclk_div,
5147 &sm1_nna_axi_clk_sel,
5148 &sm1_nna_axi_clk_div,
5150 &sm1_nna_core_clk_sel,
5151 &sm1_nna_core_clk_div,
5155 static const struct reg_sequence g12a_init_regs[] = {
5156 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
5159 static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
5160 struct clk_hw **hws)
5162 const char *notifier_clk_name;
5163 struct clk *notifier_clk;
5164 struct clk_hw *xtal;
5167 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5169 /* Setup clock notifier for cpu_clk_postmux0 */
5170 g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5171 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
5172 notifier_clk = __clk_lookup(notifier_clk_name);
5173 ret = clk_notifier_register(notifier_clk,
5174 &g12a_cpu_clk_postmux0_nb_data.nb);
5176 dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
5180 /* Setup clock notifier for cpu_clk_dyn mux */
5181 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
5182 notifier_clk = __clk_lookup(notifier_clk_name);
5183 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5185 dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
5192 static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5194 struct clk_hw **hws = g12b_hw_onecell_data.hws;
5195 const char *notifier_clk_name;
5196 struct clk *notifier_clk;
5197 struct clk_hw *xtal;
5200 ret = meson_g12a_dvfs_setup_common(pdev, hws);
5204 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5206 /* Setup clock notifier for cpu_clk mux */
5207 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
5208 notifier_clk = __clk_lookup(notifier_clk_name);
5209 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5211 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
5215 /* Setup clock notifier for sys1_pll */
5216 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
5217 notifier_clk = __clk_lookup(notifier_clk_name);
5218 ret = clk_notifier_register(notifier_clk,
5219 &g12b_cpu_clk_sys1_pll_nb_data.nb);
5221 dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
5225 /* Add notifiers for the second CPU cluster */
5227 /* Setup clock notifier for cpub_clk_postmux0 */
5228 g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5229 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
5230 notifier_clk = __clk_lookup(notifier_clk_name);
5231 ret = clk_notifier_register(notifier_clk,
5232 &g12b_cpub_clk_postmux0_nb_data.nb);
5234 dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
5238 /* Setup clock notifier for cpub_clk_dyn mux */
5239 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
5240 notifier_clk = __clk_lookup(notifier_clk_name);
5241 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5243 dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
5247 /* Setup clock notifier for cpub_clk mux */
5248 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
5249 notifier_clk = __clk_lookup(notifier_clk_name);
5250 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5252 dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
5256 /* Setup clock notifier for sys_pll */
5257 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
5258 notifier_clk = __clk_lookup(notifier_clk_name);
5259 ret = clk_notifier_register(notifier_clk,
5260 &g12b_cpub_clk_sys_pll_nb_data.nb);
5262 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
5269 static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5271 struct clk_hw **hws = g12a_hw_onecell_data.hws;
5272 const char *notifier_clk_name;
5273 struct clk *notifier_clk;
5276 ret = meson_g12a_dvfs_setup_common(pdev, hws);
5280 /* Setup clock notifier for cpu_clk mux */
5281 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
5282 notifier_clk = __clk_lookup(notifier_clk_name);
5283 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5285 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
5289 /* Setup clock notifier for sys_pll */
5290 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
5291 notifier_clk = __clk_lookup(notifier_clk_name);
5292 ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
5294 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
5301 struct meson_g12a_data {
5302 const struct meson_eeclkc_data eeclkc_data;
5303 int (*dvfs_setup)(struct platform_device *pdev);
5306 static int meson_g12a_probe(struct platform_device *pdev)
5308 const struct meson_eeclkc_data *eeclkc_data;
5309 const struct meson_g12a_data *g12a_data;
5312 eeclkc_data = of_device_get_match_data(&pdev->dev);
5316 ret = meson_eeclkc_probe(pdev);
5320 g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5323 if (g12a_data->dvfs_setup)
5324 return g12a_data->dvfs_setup(pdev);
5329 static const struct meson_g12a_data g12a_clkc_data = {
5331 .regmap_clks = g12a_clk_regmaps,
5332 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5333 .hw_onecell_data = &g12a_hw_onecell_data,
5334 .init_regs = g12a_init_regs,
5335 .init_count = ARRAY_SIZE(g12a_init_regs),
5337 .dvfs_setup = meson_g12a_dvfs_setup,
5340 static const struct meson_g12a_data g12b_clkc_data = {
5342 .regmap_clks = g12a_clk_regmaps,
5343 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5344 .hw_onecell_data = &g12b_hw_onecell_data,
5346 .dvfs_setup = meson_g12b_dvfs_setup,
5349 static const struct meson_g12a_data sm1_clkc_data = {
5351 .regmap_clks = g12a_clk_regmaps,
5352 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5353 .hw_onecell_data = &sm1_hw_onecell_data,
5355 .dvfs_setup = meson_g12a_dvfs_setup,
5358 static const struct of_device_id clkc_match_table[] = {
5360 .compatible = "amlogic,g12a-clkc",
5361 .data = &g12a_clkc_data.eeclkc_data
5364 .compatible = "amlogic,g12b-clkc",
5365 .data = &g12b_clkc_data.eeclkc_data
5368 .compatible = "amlogic,sm1-clkc",
5369 .data = &sm1_clkc_data.eeclkc_data
5374 static struct platform_driver g12a_driver = {
5375 .probe = meson_g12a_probe,
5377 .name = "g12a-clkc",
5378 .of_match_table = clkc_match_table,
5382 builtin_platform_driver(g12a_driver);