drivers/clk/meson/g12a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Amlogic Meson-G12A Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2018 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  * Author: Jian Hu <jian.hu@amlogic.com>
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/module.h>
  19
  20 #include "clk-mpll.h"
  21 #include "clk-pll.h"
  22 #include "clk-regmap.h"
  23 #include "clk-cpu-dyndiv.h"
  24 #include "vid-pll-div.h"
  25 #include "meson-eeclk.h"
  26 #include "g12a.h"
  27
  28 #include <dt-bindings/clock/g12a-clkc.h>
  29
  30 static DEFINE_SPINLOCK(meson_clk_lock);
  31
  32 static struct clk_regmap g12a_fixed_pll_dco = {
  33         .data = &(struct meson_clk_pll_data){
  34                 .en = {
  35                         .reg_off = HHI_FIX_PLL_CNTL0,
  36                         .shift   = 28,
  37                         .width   = 1,
  38                 },
  39                 .m = {
  40                         .reg_off = HHI_FIX_PLL_CNTL0,
  41                         .shift   = 0,
  42                         .width   = 8,
  43                 },
  44                 .n = {
  45                         .reg_off = HHI_FIX_PLL_CNTL0,
  46                         .shift   = 10,
  47                         .width   = 5,
  48                 },
  49                 .frac = {
  50                         .reg_off = HHI_FIX_PLL_CNTL1,
  51                         .shift   = 0,
  52                         .width   = 17,
  53                 },
  54                 .l = {
  55                         .reg_off = HHI_FIX_PLL_CNTL0,
  56                         .shift   = 31,
  57                         .width   = 1,
  58                 },
  59                 .rst = {
  60                         .reg_off = HHI_FIX_PLL_CNTL0,
  61                         .shift   = 29,
  62                         .width   = 1,
  63                 },
  64         },
  65         .hw.init = &(struct clk_init_data){
  66                 .name = "fixed_pll_dco",
  67                 .ops = &meson_clk_pll_ro_ops,
  68                 .parent_data = &(const struct clk_parent_data) {
  69                         .fw_name = "xtal",
  70                 },
  71                 .num_parents = 1,
  72         },
  73 };
  74
  75 static struct clk_regmap g12a_fixed_pll = {
  76         .data = &(struct clk_regmap_div_data){
  77                 .offset = HHI_FIX_PLL_CNTL0,
  78                 .shift = 16,
  79                 .width = 2,
  80                 .flags = CLK_DIVIDER_POWER_OF_TWO,
  81         },
  82         .hw.init = &(struct clk_init_data){
  83                 .name = "fixed_pll",
  84                 .ops = &clk_regmap_divider_ro_ops,
  85                 .parent_hws = (const struct clk_hw *[]) {
  86                         &g12a_fixed_pll_dco.hw
  87                 },
  88                 .num_parents = 1,
  89                 /*
  90                  * This clock won't ever change at runtime so
  91                  * CLK_SET_RATE_PARENT is not required
  92                  */
  93         },
  94 };
  95
  96 static const struct pll_mult_range g12a_sys_pll_mult_range = {
  97         .min = 128,
  98         .max = 250,
  99 };
 100
 101 static struct clk_regmap g12a_sys_pll_dco = {
 102         .data = &(struct meson_clk_pll_data){
 103                 .en = {
 104                         .reg_off = HHI_SYS_PLL_CNTL0,
 105                         .shift   = 28,
 106                         .width   = 1,
 107                 },
 108                 .m = {
 109                         .reg_off = HHI_SYS_PLL_CNTL0,
 110                         .shift   = 0,
 111                         .width   = 8,
 112                 },
 113                 .n = {
 114                         .reg_off = HHI_SYS_PLL_CNTL0,
 115                         .shift   = 10,
 116                         .width   = 5,
 117                 },
 118                 .l = {
 119                         .reg_off = HHI_SYS_PLL_CNTL0,
 120                         .shift   = 31,
 121                         .width   = 1,
 122                 },
 123                 .rst = {
 124                         .reg_off = HHI_SYS_PLL_CNTL0,
 125                         .shift   = 29,
 126                         .width   = 1,
 127                 },
 128                 .range = &g12a_sys_pll_mult_range,
 129         },
 130         .hw.init = &(struct clk_init_data){
 131                 .name = "sys_pll_dco",
 132                 .ops = &meson_clk_pll_ops,
 133                 .parent_data = &(const struct clk_parent_data) {
 134                         .fw_name = "xtal",
 135                 },
 136                 .num_parents = 1,
 137                 /* This clock feeds the CPU, avoid disabling it */
 138                 .flags = CLK_IS_CRITICAL,
 139         },
 140 };
 141
 142 static struct clk_regmap g12a_sys_pll = {
 143         .data = &(struct clk_regmap_div_data){
 144                 .offset = HHI_SYS_PLL_CNTL0,
 145                 .shift = 16,
 146                 .width = 3,
 147                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 148         },
 149         .hw.init = &(struct clk_init_data){
 150                 .name = "sys_pll",
 151                 .ops = &clk_regmap_divider_ops,
 152                 .parent_hws = (const struct clk_hw *[]) {
 153                         &g12a_sys_pll_dco.hw
 154                 },
 155                 .num_parents = 1,
 156                 .flags = CLK_SET_RATE_PARENT,
 157         },
 158 };
 159
 160 static struct clk_regmap g12b_sys1_pll_dco = {
 161         .data = &(struct meson_clk_pll_data){
 162                 .en = {
 163                         .reg_off = HHI_SYS1_PLL_CNTL0,
 164                         .shift   = 28,
 165                         .width   = 1,
 166                 },
 167                 .m = {
 168                         .reg_off = HHI_SYS1_PLL_CNTL0,
 169                         .shift   = 0,
 170                         .width   = 8,
 171                 },
 172                 .n = {
 173                         .reg_off = HHI_SYS1_PLL_CNTL0,
 174                         .shift   = 10,
 175                         .width   = 5,
 176                 },
 177                 .l = {
 178                         .reg_off = HHI_SYS1_PLL_CNTL0,
 179                         .shift   = 31,
 180                         .width   = 1,
 181                 },
 182                 .rst = {
 183                         .reg_off = HHI_SYS1_PLL_CNTL0,
 184                         .shift   = 29,
 185                         .width   = 1,
 186                 },
 187                 .range = &g12a_sys_pll_mult_range,
 188         },
 189         .hw.init = &(struct clk_init_data){
 190                 .name = "sys1_pll_dco",
 191                 .ops = &meson_clk_pll_ops,
 192                 .parent_data = &(const struct clk_parent_data) {
 193                         .fw_name = "xtal",
 194                 },
 195                 .num_parents = 1,
 196                 /* This clock feeds the CPU, avoid disabling it */
 197                 .flags = CLK_IS_CRITICAL,
 198         },
 199 };
 200
 201 static struct clk_regmap g12b_sys1_pll = {
 202         .data = &(struct clk_regmap_div_data){
 203                 .offset = HHI_SYS1_PLL_CNTL0,
 204                 .shift = 16,
 205                 .width = 3,
 206                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 207         },
 208         .hw.init = &(struct clk_init_data){
 209                 .name = "sys1_pll",
 210                 .ops = &clk_regmap_divider_ops,
 211                 .parent_hws = (const struct clk_hw *[]) {
 212                         &g12b_sys1_pll_dco.hw
 213                 },
 214                 .num_parents = 1,
 215                 .flags = CLK_SET_RATE_PARENT,
 216         },
 217 };
 218
 219 static struct clk_regmap g12a_sys_pll_div16_en = {
 220         .data = &(struct clk_regmap_gate_data){
 221                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 222                 .bit_idx = 24,
 223         },
 224         .hw.init = &(struct clk_init_data) {
 225                 .name = "sys_pll_div16_en",
 226                 .ops = &clk_regmap_gate_ro_ops,
 227                 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
 228                 .num_parents = 1,
 229                 /*
 230                  * This clock is used to debug the sys_pll range
 231                  * Linux should not change it at runtime
 232                  */
 233         },
 234 };
 235
 236 static struct clk_regmap g12b_sys1_pll_div16_en = {
 237         .data = &(struct clk_regmap_gate_data){
 238                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 239                 .bit_idx = 24,
 240         },
 241         .hw.init = &(struct clk_init_data) {
 242                 .name = "sys1_pll_div16_en",
 243                 .ops = &clk_regmap_gate_ro_ops,
 244                 .parent_hws = (const struct clk_hw *[]) {
 245                         &g12b_sys1_pll.hw
 246                 },
 247                 .num_parents = 1,
 248                 /*
 249                  * This clock is used to debug the sys_pll range
 250                  * Linux should not change it at runtime
 251                  */
 252         },
 253 };
 254
 255 static struct clk_fixed_factor g12a_sys_pll_div16 = {
 256         .mult = 1,
 257         .div = 16,
 258         .hw.init = &(struct clk_init_data){
 259                 .name = "sys_pll_div16",
 260                 .ops = &clk_fixed_factor_ops,
 261                 .parent_hws = (const struct clk_hw *[]) {
 262                         &g12a_sys_pll_div16_en.hw
 263                 },
 264                 .num_parents = 1,
 265         },
 266 };
 267
 268 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
 269         .mult = 1,
 270         .div = 16,
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "sys1_pll_div16",
 273                 .ops = &clk_fixed_factor_ops,
 274                 .parent_hws = (const struct clk_hw *[]) {
 275                         &g12b_sys1_pll_div16_en.hw
 276                 },
 277                 .num_parents = 1,
 278         },
 279 };
 280
 281 static struct clk_fixed_factor g12a_fclk_div2_div = {
 282         .mult = 1,
 283         .div = 2,
 284         .hw.init = &(struct clk_init_data){
 285                 .name = "fclk_div2_div",
 286                 .ops = &clk_fixed_factor_ops,
 287                 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 288                 .num_parents = 1,
 289         },
 290 };
 291
 292 static struct clk_regmap g12a_fclk_div2 = {
 293         .data = &(struct clk_regmap_gate_data){
 294                 .offset = HHI_FIX_PLL_CNTL1,
 295                 .bit_idx = 24,
 296         },
 297         .hw.init = &(struct clk_init_data){
 298                 .name = "fclk_div2",
 299                 .ops = &clk_regmap_gate_ops,
 300                 .parent_hws = (const struct clk_hw *[]) {
 301                         &g12a_fclk_div2_div.hw
 302                 },
 303                 .num_parents = 1,
 304                 /*
 305                  * Similar to fclk_div3, it seems that this clock is used by
 306                  * the resident firmware and is required by the platform to
 307                  * operate correctly.
 308                  * Until the following condition are met, we need this clock to
 309                  * be marked as critical:
 310                  * a) Mark the clock used by a firmware resource, if possible
 311                  * b) CCF has a clock hand-off mechanism to make the sure the
 312                  *    clock stays on until the proper driver comes along
 313                  */
 314                 .flags = CLK_IS_CRITICAL,
 315         },
 316 };
 317
 318 static struct clk_fixed_factor g12a_fclk_div3_div = {
 319         .mult = 1,
 320         .div = 3,
 321         .hw.init = &(struct clk_init_data){
 322                 .name = "fclk_div3_div",
 323                 .ops = &clk_fixed_factor_ops,
 324                 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 325                 .num_parents = 1,
 326         },
 327 };
 328
 329 static struct clk_regmap g12a_fclk_div3 = {
 330         .data = &(struct clk_regmap_gate_data){
 331                 .offset = HHI_FIX_PLL_CNTL1,
 332                 .bit_idx = 20,
 333         },
 334         .hw.init = &(struct clk_init_data){
 335                 .name = "fclk_div3",
 336                 .ops = &clk_regmap_gate_ops,
 337                 .parent_hws = (const struct clk_hw *[]) {
 338                         &g12a_fclk_div3_div.hw
 339                 },
 340                 .num_parents = 1,
 341                 /*
 342                  * This clock is used by the resident firmware and is required
 343                  * by the platform to operate correctly.
 344                  * Until the following condition are met, we need this clock to
 345                  * be marked as critical:
 346                  * a) Mark the clock used by a firmware resource, if possible
 347                  * b) CCF has a clock hand-off mechanism to make the sure the
 348                  *    clock stays on until the proper driver comes along
 349                  */
 350                 .flags = CLK_IS_CRITICAL,
 351         },
 352 };
 353
 354 /* Datasheet names this field as "premux0" */
 355 static struct clk_regmap g12a_cpu_clk_premux0 = {
 356         .data = &(struct clk_regmap_mux_data){
 357                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 358                 .mask = 0x3,
 359                 .shift = 0,
 360                 .flags = CLK_MUX_ROUND_CLOSEST,
 361         },
 362         .hw.init = &(struct clk_init_data){
 363                 .name = "cpu_clk_dyn0_sel",
 364                 .ops = &clk_regmap_mux_ops,
 365                 .parent_data = (const struct clk_parent_data []) {
 366                         { .fw_name = "xtal", },
 367                         { .hw = &g12a_fclk_div2.hw },
 368                         { .hw = &g12a_fclk_div3.hw },
 369                 },
 370                 .num_parents = 3,
 371                 .flags = CLK_SET_RATE_PARENT,
 372         },
 373 };
 374
 375 /* Datasheet names this field as "premux1" */
 376 static struct clk_regmap g12a_cpu_clk_premux1 = {
 377         .data = &(struct clk_regmap_mux_data){
 378                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 379                 .mask = 0x3,
 380                 .shift = 16,
 381         },
 382         .hw.init = &(struct clk_init_data){
 383                 .name = "cpu_clk_dyn1_sel",
 384                 .ops = &clk_regmap_mux_ops,
 385                 .parent_data = (const struct clk_parent_data []) {
 386                         { .fw_name = "xtal", },
 387                         { .hw = &g12a_fclk_div2.hw },
 388                         { .hw = &g12a_fclk_div3.hw },
 389                 },
 390                 .num_parents = 3,
 391                 /* This sub-tree is used a parking clock */
 392                 .flags = CLK_SET_RATE_NO_REPARENT
 393         },
 394 };
 395
 396 /* Datasheet names this field as "mux0_divn_tcnt" */
 397 static struct clk_regmap g12a_cpu_clk_mux0_div = {
 398         .data = &(struct meson_clk_cpu_dyndiv_data){
 399                 .div = {
 400                         .reg_off = HHI_SYS_CPU_CLK_CNTL0,
 401                         .shift = 4,
 402                         .width = 6,
 403                 },
 404                 .dyn = {
 405                         .reg_off = HHI_SYS_CPU_CLK_CNTL0,
 406                         .shift = 26,
 407                         .width = 1,
 408                 },
 409         },
 410         .hw.init = &(struct clk_init_data){
 411                 .name = "cpu_clk_dyn0_div",
 412                 .ops = &meson_clk_cpu_dyndiv_ops,
 413                 .parent_hws = (const struct clk_hw *[]) {
 414                         &g12a_cpu_clk_premux0.hw
 415                 },
 416                 .num_parents = 1,
 417                 .flags = CLK_SET_RATE_PARENT,
 418         },
 419 };
 420
 421 /* Datasheet names this field as "postmux0" */
 422 static struct clk_regmap g12a_cpu_clk_postmux0 = {
 423         .data = &(struct clk_regmap_mux_data){
 424                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 425                 .mask = 0x1,
 426                 .shift = 2,
 427                 .flags = CLK_MUX_ROUND_CLOSEST,
 428         },
 429         .hw.init = &(struct clk_init_data){
 430                 .name = "cpu_clk_dyn0",
 431                 .ops = &clk_regmap_mux_ops,
 432                 .parent_hws = (const struct clk_hw *[]) {
 433                         &g12a_cpu_clk_premux0.hw,
 434                         &g12a_cpu_clk_mux0_div.hw,
 435                 },
 436                 .num_parents = 2,
 437                 .flags = CLK_SET_RATE_PARENT,
 438         },
 439 };
 440
 441 /* Datasheet names this field as "Mux1_divn_tcnt" */
 442 static struct clk_regmap g12a_cpu_clk_mux1_div = {
 443         .data = &(struct clk_regmap_div_data){
 444                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 445                 .shift = 20,
 446                 .width = 6,
 447         },
 448         .hw.init = &(struct clk_init_data){
 449                 .name = "cpu_clk_dyn1_div",
 450                 .ops = &clk_regmap_divider_ro_ops,
 451                 .parent_hws = (const struct clk_hw *[]) {
 452                         &g12a_cpu_clk_premux1.hw
 453                 },
 454                 .num_parents = 1,
 455         },
 456 };
 457
 458 /* Datasheet names this field as "postmux1" */
 459 static struct clk_regmap g12a_cpu_clk_postmux1 = {
 460         .data = &(struct clk_regmap_mux_data){
 461                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 462                 .mask = 0x1,
 463                 .shift = 18,
 464         },
 465         .hw.init = &(struct clk_init_data){
 466                 .name = "cpu_clk_dyn1",
 467                 .ops = &clk_regmap_mux_ops,
 468                 .parent_hws = (const struct clk_hw *[]) {
 469                         &g12a_cpu_clk_premux1.hw,
 470                         &g12a_cpu_clk_mux1_div.hw,
 471                 },
 472                 .num_parents = 2,
 473                 /* This sub-tree is used a parking clock */
 474                 .flags = CLK_SET_RATE_NO_REPARENT,
 475         },
 476 };
 477
 478 /* Datasheet names this field as "Final_dyn_mux_sel" */
 479 static struct clk_regmap g12a_cpu_clk_dyn = {
 480         .data = &(struct clk_regmap_mux_data){
 481                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 482                 .mask = 0x1,
 483                 .shift = 10,
 484                 .flags = CLK_MUX_ROUND_CLOSEST,
 485         },
 486         .hw.init = &(struct clk_init_data){
 487                 .name = "cpu_clk_dyn",
 488                 .ops = &clk_regmap_mux_ops,
 489                 .parent_hws = (const struct clk_hw *[]) {
 490                         &g12a_cpu_clk_postmux0.hw,
 491                         &g12a_cpu_clk_postmux1.hw,
 492                 },
 493                 .num_parents = 2,
 494                 .flags = CLK_SET_RATE_PARENT,
 495         },
 496 };
 497
 498 /* Datasheet names this field as "Final_mux_sel" */
 499 static struct clk_regmap g12a_cpu_clk = {
 500         .data = &(struct clk_regmap_mux_data){
 501                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 502                 .mask = 0x1,
 503                 .shift = 11,
 504                 .flags = CLK_MUX_ROUND_CLOSEST,
 505         },
 506         .hw.init = &(struct clk_init_data){
 507                 .name = "cpu_clk",
 508                 .ops = &clk_regmap_mux_ops,
 509                 .parent_hws = (const struct clk_hw *[]) {
 510                         &g12a_cpu_clk_dyn.hw,
 511                         &g12a_sys_pll.hw,
 512                 },
 513                 .num_parents = 2,
 514                 .flags = CLK_SET_RATE_PARENT,
 515         },
 516 };
 517
 518 /* Datasheet names this field as "Final_mux_sel" */
 519 static struct clk_regmap g12b_cpu_clk = {
 520         .data = &(struct clk_regmap_mux_data){
 521                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 522                 .mask = 0x1,
 523                 .shift = 11,
 524                 .flags = CLK_MUX_ROUND_CLOSEST,
 525         },
 526         .hw.init = &(struct clk_init_data){
 527                 .name = "cpu_clk",
 528                 .ops = &clk_regmap_mux_ops,
 529                 .parent_hws = (const struct clk_hw *[]) {
 530                         &g12a_cpu_clk_dyn.hw,
 531                         &g12b_sys1_pll.hw
 532                 },
 533                 .num_parents = 2,
 534                 .flags = CLK_SET_RATE_PARENT,
 535         },
 536 };
 537
 538 /* Datasheet names this field as "premux0" */
 539 static struct clk_regmap g12b_cpub_clk_premux0 = {
 540         .data = &(struct clk_regmap_mux_data){
 541                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 542                 .mask = 0x3,
 543                 .shift = 0,
 544                 .flags = CLK_MUX_ROUND_CLOSEST,
 545         },
 546         .hw.init = &(struct clk_init_data){
 547                 .name = "cpub_clk_dyn0_sel",
 548                 .ops = &clk_regmap_mux_ops,
 549                 .parent_data = (const struct clk_parent_data []) {
 550                         { .fw_name = "xtal", },
 551                         { .hw = &g12a_fclk_div2.hw },
 552                         { .hw = &g12a_fclk_div3.hw },
 553                 },
 554                 .num_parents = 3,
 555                 .flags = CLK_SET_RATE_PARENT,
 556         },
 557 };
 558
 559 /* Datasheet names this field as "mux0_divn_tcnt" */
 560 static struct clk_regmap g12b_cpub_clk_mux0_div = {
 561         .data = &(struct meson_clk_cpu_dyndiv_data){
 562                 .div = {
 563                         .reg_off = HHI_SYS_CPUB_CLK_CNTL,
 564                         .shift = 4,
 565                         .width = 6,
 566                 },
 567                 .dyn = {
 568                         .reg_off = HHI_SYS_CPUB_CLK_CNTL,
 569                         .shift = 26,
 570                         .width = 1,
 571                 },
 572         },
 573         .hw.init = &(struct clk_init_data){
 574                 .name = "cpub_clk_dyn0_div",
 575                 .ops = &meson_clk_cpu_dyndiv_ops,
 576                 .parent_hws = (const struct clk_hw *[]) {
 577                         &g12b_cpub_clk_premux0.hw
 578                 },
 579                 .num_parents = 1,
 580                 .flags = CLK_SET_RATE_PARENT,
 581         },
 582 };
 583
 584 /* Datasheet names this field as "postmux0" */
 585 static struct clk_regmap g12b_cpub_clk_postmux0 = {
 586         .data = &(struct clk_regmap_mux_data){
 587                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 588                 .mask = 0x1,
 589                 .shift = 2,
 590                 .flags = CLK_MUX_ROUND_CLOSEST,
 591         },
 592         .hw.init = &(struct clk_init_data){
 593                 .name = "cpub_clk_dyn0",
 594                 .ops = &clk_regmap_mux_ops,
 595                 .parent_hws = (const struct clk_hw *[]) {
 596                         &g12b_cpub_clk_premux0.hw,
 597                         &g12b_cpub_clk_mux0_div.hw
 598                 },
 599                 .num_parents = 2,
 600                 .flags = CLK_SET_RATE_PARENT,
 601         },
 602 };
 603
 604 /* Datasheet names this field as "premux1" */
 605 static struct clk_regmap g12b_cpub_clk_premux1 = {
 606         .data = &(struct clk_regmap_mux_data){
 607                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 608                 .mask = 0x3,
 609                 .shift = 16,
 610         },
 611         .hw.init = &(struct clk_init_data){
 612                 .name = "cpub_clk_dyn1_sel",
 613                 .ops = &clk_regmap_mux_ops,
 614                 .parent_data = (const struct clk_parent_data []) {
 615                         { .fw_name = "xtal", },
 616                         { .hw = &g12a_fclk_div2.hw },
 617                         { .hw = &g12a_fclk_div3.hw },
 618                 },
 619                 .num_parents = 3,
 620                 /* This sub-tree is used a parking clock */
 621                 .flags = CLK_SET_RATE_NO_REPARENT,
 622         },
 623 };
 624
 625 /* Datasheet names this field as "Mux1_divn_tcnt" */
 626 static struct clk_regmap g12b_cpub_clk_mux1_div = {
 627         .data = &(struct clk_regmap_div_data){
 628                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 629                 .shift = 20,
 630                 .width = 6,
 631         },
 632         .hw.init = &(struct clk_init_data){
 633                 .name = "cpub_clk_dyn1_div",
 634                 .ops = &clk_regmap_divider_ro_ops,
 635                 .parent_hws = (const struct clk_hw *[]) {
 636                         &g12b_cpub_clk_premux1.hw
 637                 },
 638                 .num_parents = 1,
 639         },
 640 };
 641
 642 /* Datasheet names this field as "postmux1" */
 643 static struct clk_regmap g12b_cpub_clk_postmux1 = {
 644         .data = &(struct clk_regmap_mux_data){
 645                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 646                 .mask = 0x1,
 647                 .shift = 18,
 648         },
 649         .hw.init = &(struct clk_init_data){
 650                 .name = "cpub_clk_dyn1",
 651                 .ops = &clk_regmap_mux_ops,
 652                 .parent_hws = (const struct clk_hw *[]) {
 653                         &g12b_cpub_clk_premux1.hw,
 654                         &g12b_cpub_clk_mux1_div.hw
 655                 },
 656                 .num_parents = 2,
 657                 /* This sub-tree is used a parking clock */
 658                 .flags = CLK_SET_RATE_NO_REPARENT,
 659         },
 660 };
 661
 662 /* Datasheet names this field as "Final_dyn_mux_sel" */
 663 static struct clk_regmap g12b_cpub_clk_dyn = {
 664         .data = &(struct clk_regmap_mux_data){
 665                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 666                 .mask = 0x1,
 667                 .shift = 10,
 668                 .flags = CLK_MUX_ROUND_CLOSEST,
 669         },
 670         .hw.init = &(struct clk_init_data){
 671                 .name = "cpub_clk_dyn",
 672                 .ops = &clk_regmap_mux_ops,
 673                 .parent_hws = (const struct clk_hw *[]) {
 674                         &g12b_cpub_clk_postmux0.hw,
 675                         &g12b_cpub_clk_postmux1.hw
 676                 },
 677                 .num_parents = 2,
 678                 .flags = CLK_SET_RATE_PARENT,
 679         },
 680 };
 681
 682 /* Datasheet names this field as "Final_mux_sel" */
 683 static struct clk_regmap g12b_cpub_clk = {
 684         .data = &(struct clk_regmap_mux_data){
 685                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 686                 .mask = 0x1,
 687                 .shift = 11,
 688                 .flags = CLK_MUX_ROUND_CLOSEST,
 689         },
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "cpub_clk",
 692                 .ops = &clk_regmap_mux_ops,
 693                 .parent_hws = (const struct clk_hw *[]) {
 694                         &g12b_cpub_clk_dyn.hw,
 695                         &g12a_sys_pll.hw
 696                 },
 697                 .num_parents = 2,
 698                 .flags = CLK_SET_RATE_PARENT,
 699         },
 700 };
 701
 702 static struct clk_regmap sm1_gp1_pll;
 703
 704 /* Datasheet names this field as "premux0" */
 705 static struct clk_regmap sm1_dsu_clk_premux0 = {
 706         .data = &(struct clk_regmap_mux_data){
 707                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 708                 .mask = 0x3,
 709                 .shift = 0,
 710         },
 711         .hw.init = &(struct clk_init_data){
 712                 .name = "dsu_clk_dyn0_sel",
 713                 .ops = &clk_regmap_mux_ro_ops,
 714                 .parent_data = (const struct clk_parent_data []) {
 715                         { .fw_name = "xtal", },
 716                         { .hw = &g12a_fclk_div2.hw },
 717                         { .hw = &g12a_fclk_div3.hw },
 718                         { .hw = &sm1_gp1_pll.hw },
 719                 },
 720                 .num_parents = 4,
 721         },
 722 };
 723
 724 /* Datasheet names this field as "premux1" */
 725 static struct clk_regmap sm1_dsu_clk_premux1 = {
 726         .data = &(struct clk_regmap_mux_data){
 727                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 728                 .mask = 0x3,
 729                 .shift = 16,
 730         },
 731         .hw.init = &(struct clk_init_data){
 732                 .name = "dsu_clk_dyn1_sel",
 733                 .ops = &clk_regmap_mux_ro_ops,
 734                 .parent_data = (const struct clk_parent_data []) {
 735                         { .fw_name = "xtal", },
 736                         { .hw = &g12a_fclk_div2.hw },
 737                         { .hw = &g12a_fclk_div3.hw },
 738                         { .hw = &sm1_gp1_pll.hw },
 739                 },
 740                 .num_parents = 4,
 741         },
 742 };
 743
 744 /* Datasheet names this field as "Mux0_divn_tcnt" */
 745 static struct clk_regmap sm1_dsu_clk_mux0_div = {
 746         .data = &(struct clk_regmap_div_data){
 747                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 748                 .shift = 4,
 749                 .width = 6,
 750         },
 751         .hw.init = &(struct clk_init_data){
 752                 .name = "dsu_clk_dyn0_div",
 753                 .ops = &clk_regmap_divider_ro_ops,
 754                 .parent_hws = (const struct clk_hw *[]) {
 755                         &sm1_dsu_clk_premux0.hw
 756                 },
 757                 .num_parents = 1,
 758         },
 759 };
 760
 761 /* Datasheet names this field as "postmux0" */
 762 static struct clk_regmap sm1_dsu_clk_postmux0 = {
 763         .data = &(struct clk_regmap_mux_data){
 764                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 765                 .mask = 0x1,
 766                 .shift = 2,
 767         },
 768         .hw.init = &(struct clk_init_data){
 769                 .name = "dsu_clk_dyn0",
 770                 .ops = &clk_regmap_mux_ro_ops,
 771                 .parent_hws = (const struct clk_hw *[]) {
 772                         &sm1_dsu_clk_premux0.hw,
 773                         &sm1_dsu_clk_mux0_div.hw,
 774                 },
 775                 .num_parents = 2,
 776         },
 777 };
 778
 779 /* Datasheet names this field as "Mux1_divn_tcnt" */
 780 static struct clk_regmap sm1_dsu_clk_mux1_div = {
 781         .data = &(struct clk_regmap_div_data){
 782                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 783                 .shift = 20,
 784                 .width = 6,
 785         },
 786         .hw.init = &(struct clk_init_data){
 787                 .name = "dsu_clk_dyn1_div",
 788                 .ops = &clk_regmap_divider_ro_ops,
 789                 .parent_hws = (const struct clk_hw *[]) {
 790                         &sm1_dsu_clk_premux1.hw
 791                 },
 792                 .num_parents = 1,
 793         },
 794 };
 795
 796 /* Datasheet names this field as "postmux1" */
 797 static struct clk_regmap sm1_dsu_clk_postmux1 = {
 798         .data = &(struct clk_regmap_mux_data){
 799                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 800                 .mask = 0x1,
 801                 .shift = 18,
 802         },
 803         .hw.init = &(struct clk_init_data){
 804                 .name = "dsu_clk_dyn1",
 805                 .ops = &clk_regmap_mux_ro_ops,
 806                 .parent_hws = (const struct clk_hw *[]) {
 807                         &sm1_dsu_clk_premux1.hw,
 808                         &sm1_dsu_clk_mux1_div.hw,
 809                 },
 810                 .num_parents = 2,
 811         },
 812 };
 813
 814 /* Datasheet names this field as "Final_dyn_mux_sel" */
 815 static struct clk_regmap sm1_dsu_clk_dyn = {
 816         .data = &(struct clk_regmap_mux_data){
 817                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 818                 .mask = 0x1,
 819                 .shift = 10,
 820         },
 821         .hw.init = &(struct clk_init_data){
 822                 .name = "dsu_clk_dyn",
 823                 .ops = &clk_regmap_mux_ro_ops,
 824                 .parent_hws = (const struct clk_hw *[]) {
 825                         &sm1_dsu_clk_postmux0.hw,
 826                         &sm1_dsu_clk_postmux1.hw,
 827                 },
 828                 .num_parents = 2,
 829         },
 830 };
 831
 832 /* Datasheet names this field as "Final_mux_sel" */
 833 static struct clk_regmap sm1_dsu_final_clk = {
 834         .data = &(struct clk_regmap_mux_data){
 835                 .offset = HHI_SYS_CPU_CLK_CNTL5,
 836                 .mask = 0x1,
 837                 .shift = 11,
 838         },
 839         .hw.init = &(struct clk_init_data){
 840                 .name = "dsu_clk_final",
 841                 .ops = &clk_regmap_mux_ro_ops,
 842                 .parent_hws = (const struct clk_hw *[]) {
 843                         &sm1_dsu_clk_dyn.hw,
 844                         &g12a_sys_pll.hw,
 845                 },
 846                 .num_parents = 2,
 847         },
 848 };
 849
 850 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
 851 static struct clk_regmap sm1_cpu1_clk = {
 852         .data = &(struct clk_regmap_mux_data){
 853                 .offset = HHI_SYS_CPU_CLK_CNTL6,
 854                 .mask = 0x1,
 855                 .shift = 24,
 856         },
 857         .hw.init = &(struct clk_init_data){
 858                 .name = "cpu1_clk",
 859                 .ops = &clk_regmap_mux_ro_ops,
 860                 .parent_hws = (const struct clk_hw *[]) {
 861                         &g12a_cpu_clk.hw,
 862                         /* This CPU also have a dedicated clock tree */
 863                 },
 864                 .num_parents = 1,
 865         },
 866 };
 867
 868 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
 869 static struct clk_regmap sm1_cpu2_clk = {
 870         .data = &(struct clk_regmap_mux_data){
 871                 .offset = HHI_SYS_CPU_CLK_CNTL6,
 872                 .mask = 0x1,
 873                 .shift = 25,
 874         },
 875         .hw.init = &(struct clk_init_data){
 876                 .name = "cpu2_clk",
 877                 .ops = &clk_regmap_mux_ro_ops,
 878                 .parent_hws = (const struct clk_hw *[]) {
 879                         &g12a_cpu_clk.hw,
 880                         /* This CPU also have a dedicated clock tree */
 881                 },
 882                 .num_parents = 1,
 883         },
 884 };
 885
 886 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
 887 static struct clk_regmap sm1_cpu3_clk = {
 888         .data = &(struct clk_regmap_mux_data){
 889                 .offset = HHI_SYS_CPU_CLK_CNTL6,
 890                 .mask = 0x1,
 891                 .shift = 26,
 892         },
 893         .hw.init = &(struct clk_init_data){
 894                 .name = "cpu3_clk",
 895                 .ops = &clk_regmap_mux_ro_ops,
 896                 .parent_hws = (const struct clk_hw *[]) {
 897                         &g12a_cpu_clk.hw,
 898                         /* This CPU also have a dedicated clock tree */
 899                 },
 900                 .num_parents = 1,
 901         },
 902 };
 903
 904 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
 905 static struct clk_regmap sm1_dsu_clk = {
 906         .data = &(struct clk_regmap_mux_data){
 907                 .offset = HHI_SYS_CPU_CLK_CNTL6,
 908                 .mask = 0x1,
 909                 .shift = 27,
 910         },
 911         .hw.init = &(struct clk_init_data){
 912                 .name = "dsu_clk",
 913                 .ops = &clk_regmap_mux_ro_ops,
 914                 .parent_hws = (const struct clk_hw *[]) {
 915                         &g12a_cpu_clk.hw,
 916                         &sm1_dsu_final_clk.hw,
 917                 },
 918                 .num_parents = 2,
 919         },
 920 };
 921
 922 static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
 923                                         unsigned long event, void *data)
 924 {
 925         if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
 926                 /* Wait for clock propagation before/after changing the mux */
 927                 udelay(100);
 928                 return NOTIFY_OK;
 929         }
 930
 931         return NOTIFY_DONE;
 932 }
 933
 934 static struct notifier_block g12a_cpu_clk_mux_nb = {
 935         .notifier_call = g12a_cpu_clk_mux_notifier_cb,
 936 };
 937
 938 struct g12a_cpu_clk_postmux_nb_data {
 939         struct notifier_block nb;
 940         struct clk_hw *xtal;
 941         struct clk_hw *cpu_clk_dyn;
 942         struct clk_hw *cpu_clk_postmux0;
 943         struct clk_hw *cpu_clk_postmux1;
 944         struct clk_hw *cpu_clk_premux1;
 945 };
 946
 947 static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
 948                                             unsigned long event, void *data)
 949 {
 950         struct g12a_cpu_clk_postmux_nb_data *nb_data =
 951                 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
 952
 953         switch (event) {
 954         case PRE_RATE_CHANGE:
 955                 /*
 956                  * This notifier means cpu_clk_postmux0 clock will be changed
 957                  * to feed cpu_clk, this is the current path :
 958                  * cpu_clk
 959                  *    \- cpu_clk_dyn
 960                  *          \- cpu_clk_postmux0
 961                  *                \- cpu_clk_muxX_div
 962                  *                      \- cpu_clk_premux0
 963                  *                              \- fclk_div3 or fclk_div2
 964                  *              OR
 965                  *                \- cpu_clk_premux0
 966                  *                      \- fclk_div3 or fclk_div2
 967                  */
 968
 969                 /* Setup cpu_clk_premux1 to xtal */
 970                 clk_hw_set_parent(nb_data->cpu_clk_premux1,
 971                                   nb_data->xtal);
 972
 973                 /* Setup cpu_clk_postmux1 to bypass divider */
 974                 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
 975                                   nb_data->cpu_clk_premux1);
 976
 977                 /* Switch to parking clk on cpu_clk_postmux1 */
 978                 clk_hw_set_parent(nb_data->cpu_clk_dyn,
 979                                   nb_data->cpu_clk_postmux1);
 980
 981                 /*
 982                  * Now, cpu_clk is 24MHz in the current path :
 983                  * cpu_clk
 984                  *    \- cpu_clk_dyn
 985                  *          \- cpu_clk_postmux1
 986                  *                \- cpu_clk_premux1
 987                  *                      \- xtal
 988                  */
 989
 990                 udelay(100);
 991
 992                 return NOTIFY_OK;
 993
 994         case POST_RATE_CHANGE:
 995                 /*
 996                  * The cpu_clk_postmux0 has ben updated, now switch back
 997                  * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
 998                  * in account.
 999                  */
1000
1001                 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
1002                 clk_hw_set_parent(nb_data->cpu_clk_dyn,
1003                                   nb_data->cpu_clk_postmux0);
1004
1005                 /*
1006                  * new path :
1007                  * cpu_clk
1008                  *    \- cpu_clk_dyn
1009                  *          \- cpu_clk_postmux0
1010                  *                \- cpu_clk_muxX_div
1011                  *                      \- cpu_clk_premux0
1012                  *                              \- fclk_div3 or fclk_div2
1013                  *              OR
1014                  *                \- cpu_clk_premux0
1015                  *                      \- fclk_div3 or fclk_div2
1016                  */
1017
1018                 udelay(100);
1019
1020                 return NOTIFY_OK;
1021
1022         default:
1023                 return NOTIFY_DONE;
1024         }
1025 }
1026
1027 static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1028         .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1029         .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1030         .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1031         .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1032         .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1033 };
1034
1035 static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1036         .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1037         .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1038         .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1039         .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1040         .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1041 };
1042
1043 struct g12a_sys_pll_nb_data {
1044         struct notifier_block nb;
1045         struct clk_hw *sys_pll;
1046         struct clk_hw *cpu_clk;
1047         struct clk_hw *cpu_clk_dyn;
1048 };
1049
1050 static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1051                                     unsigned long event, void *data)
1052 {
1053         struct g12a_sys_pll_nb_data *nb_data =
1054                 container_of(nb, struct g12a_sys_pll_nb_data, nb);
1055
1056         switch (event) {
1057         case PRE_RATE_CHANGE:
1058                 /*
1059                  * This notifier means sys_pll clock will be changed
1060                  * to feed cpu_clk, this the current path :
1061                  * cpu_clk
1062                  *    \- sys_pll
1063                  *          \- sys_pll_dco
1064                  */
1065
1066                 /* Configure cpu_clk to use cpu_clk_dyn */
1067                 clk_hw_set_parent(nb_data->cpu_clk,
1068                                   nb_data->cpu_clk_dyn);
1069
1070                 /*
1071                  * Now, cpu_clk uses the dyn path
1072                  * cpu_clk
1073                  *    \- cpu_clk_dyn
1074                  *          \- cpu_clk_dynX
1075                  *                \- cpu_clk_dynX_sel
1076                  *                   \- cpu_clk_dynX_div
1077                  *                      \- xtal/fclk_div2/fclk_div3
1078                  *                   \- xtal/fclk_div2/fclk_div3
1079                  */
1080
1081                 udelay(100);
1082
1083                 return NOTIFY_OK;
1084
1085         case POST_RATE_CHANGE:
1086                 /*
1087                  * The sys_pll has ben updated, now switch back cpu_clk to
1088                  * sys_pll
1089                  */
1090
1091                 /* Configure cpu_clk to use sys_pll */
1092                 clk_hw_set_parent(nb_data->cpu_clk,
1093                                   nb_data->sys_pll);
1094
1095                 udelay(100);
1096
1097                 /* new path :
1098                  * cpu_clk
1099                  *    \- sys_pll
1100                  *          \- sys_pll_dco
1101                  */
1102
1103                 return NOTIFY_OK;
1104
1105         default:
1106                 return NOTIFY_DONE;
1107         }
1108 }
1109
1110 static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1111         .sys_pll = &g12a_sys_pll.hw,
1112         .cpu_clk = &g12a_cpu_clk.hw,
1113         .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1114         .nb.notifier_call = g12a_sys_pll_notifier_cb,
1115 };
1116
1117 /* G12B first CPU cluster uses sys1_pll */
1118 static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1119         .sys_pll = &g12b_sys1_pll.hw,
1120         .cpu_clk = &g12b_cpu_clk.hw,
1121         .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1122         .nb.notifier_call = g12a_sys_pll_notifier_cb,
1123 };
1124
1125 /* G12B second CPU cluster uses sys_pll */
1126 static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1127         .sys_pll = &g12a_sys_pll.hw,
1128         .cpu_clk = &g12b_cpub_clk.hw,
1129         .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1130         .nb.notifier_call = g12a_sys_pll_notifier_cb,
1131 };
1132
1133 static struct clk_regmap g12a_cpu_clk_div16_en = {
1134         .data = &(struct clk_regmap_gate_data){
1135                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1136                 .bit_idx = 1,
1137         },
1138         .hw.init = &(struct clk_init_data) {
1139                 .name = "cpu_clk_div16_en",
1140                 .ops = &clk_regmap_gate_ro_ops,
1141                 .parent_hws = (const struct clk_hw *[]) {
1142                         &g12a_cpu_clk.hw
1143                 },
1144                 .num_parents = 1,
1145                 /*
1146                  * This clock is used to debug the cpu_clk range
1147                  * Linux should not change it at runtime
1148                  */
1149         },
1150 };
1151
1152 static struct clk_regmap g12b_cpub_clk_div16_en = {
1153         .data = &(struct clk_regmap_gate_data){
1154                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1155                 .bit_idx = 1,
1156         },
1157         .hw.init = &(struct clk_init_data) {
1158                 .name = "cpub_clk_div16_en",
1159                 .ops = &clk_regmap_gate_ro_ops,
1160                 .parent_hws = (const struct clk_hw *[]) {
1161                         &g12b_cpub_clk.hw
1162                 },
1163                 .num_parents = 1,
1164                 /*
1165                  * This clock is used to debug the cpu_clk range
1166                  * Linux should not change it at runtime
1167                  */
1168         },
1169 };
1170
1171 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1172         .mult = 1,
1173         .div = 16,
1174         .hw.init = &(struct clk_init_data){
1175                 .name = "cpu_clk_div16",
1176                 .ops = &clk_fixed_factor_ops,
1177                 .parent_hws = (const struct clk_hw *[]) {
1178                         &g12a_cpu_clk_div16_en.hw
1179                 },
1180                 .num_parents = 1,
1181         },
1182 };
1183
1184 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1185         .mult = 1,
1186         .div = 16,
1187         .hw.init = &(struct clk_init_data){
1188                 .name = "cpub_clk_div16",
1189                 .ops = &clk_fixed_factor_ops,
1190                 .parent_hws = (const struct clk_hw *[]) {
1191                         &g12b_cpub_clk_div16_en.hw
1192                 },
1193                 .num_parents = 1,
1194         },
1195 };
1196
1197 static struct clk_regmap g12a_cpu_clk_apb_div = {
1198         .data = &(struct clk_regmap_div_data){
1199                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1200                 .shift = 3,
1201                 .width = 3,
1202                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1203         },
1204         .hw.init = &(struct clk_init_data){
1205                 .name = "cpu_clk_apb_div",
1206                 .ops = &clk_regmap_divider_ro_ops,
1207                 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1208                 .num_parents = 1,
1209         },
1210 };
1211
1212 static struct clk_regmap g12a_cpu_clk_apb = {
1213         .data = &(struct clk_regmap_gate_data){
1214                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1215                 .bit_idx = 1,
1216         },
1217         .hw.init = &(struct clk_init_data) {
1218                 .name = "cpu_clk_apb",
1219                 .ops = &clk_regmap_gate_ro_ops,
1220                 .parent_hws = (const struct clk_hw *[]) {
1221                         &g12a_cpu_clk_apb_div.hw
1222                 },
1223                 .num_parents = 1,
1224                 /*
1225                  * This clock is set by the ROM monitor code,
1226                  * Linux should not change it at runtime
1227                  */
1228         },
1229 };
1230
1231 static struct clk_regmap g12a_cpu_clk_atb_div = {
1232         .data = &(struct clk_regmap_div_data){
1233                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1234                 .shift = 6,
1235                 .width = 3,
1236                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1237         },
1238         .hw.init = &(struct clk_init_data){
1239                 .name = "cpu_clk_atb_div",
1240                 .ops = &clk_regmap_divider_ro_ops,
1241                 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1242                 .num_parents = 1,
1243         },
1244 };
1245
1246 static struct clk_regmap g12a_cpu_clk_atb = {
1247         .data = &(struct clk_regmap_gate_data){
1248                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1249                 .bit_idx = 17,
1250         },
1251         .hw.init = &(struct clk_init_data) {
1252                 .name = "cpu_clk_atb",
1253                 .ops = &clk_regmap_gate_ro_ops,
1254                 .parent_hws = (const struct clk_hw *[]) {
1255                         &g12a_cpu_clk_atb_div.hw
1256                 },
1257                 .num_parents = 1,
1258                 /*
1259                  * This clock is set by the ROM monitor code,
1260                  * Linux should not change it at runtime
1261                  */
1262         },
1263 };
1264
1265 static struct clk_regmap g12a_cpu_clk_axi_div = {
1266         .data = &(struct clk_regmap_div_data){
1267                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1268                 .shift = 9,
1269                 .width = 3,
1270                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1271         },
1272         .hw.init = &(struct clk_init_data){
1273                 .name = "cpu_clk_axi_div",
1274                 .ops = &clk_regmap_divider_ro_ops,
1275                 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1276                 .num_parents = 1,
1277         },
1278 };
1279
1280 static struct clk_regmap g12a_cpu_clk_axi = {
1281         .data = &(struct clk_regmap_gate_data){
1282                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1283                 .bit_idx = 18,
1284         },
1285         .hw.init = &(struct clk_init_data) {
1286                 .name = "cpu_clk_axi",
1287                 .ops = &clk_regmap_gate_ro_ops,
1288                 .parent_hws = (const struct clk_hw *[]) {
1289                         &g12a_cpu_clk_axi_div.hw
1290                 },
1291                 .num_parents = 1,
1292                 /*
1293                  * This clock is set by the ROM monitor code,
1294                  * Linux should not change it at runtime
1295                  */
1296         },
1297 };
1298
1299 static struct clk_regmap g12a_cpu_clk_trace_div = {
1300         .data = &(struct clk_regmap_div_data){
1301                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1302                 .shift = 20,
1303                 .width = 3,
1304                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1305         },
1306         .hw.init = &(struct clk_init_data){
1307                 .name = "cpu_clk_trace_div",
1308                 .ops = &clk_regmap_divider_ro_ops,
1309                 .parent_data = &(const struct clk_parent_data) {
1310                         /*
1311                          * Note:
1312                          * G12A and G12B have different cpu_clks (with
1313                          * different struct clk_hw). We fallback to the global
1314                          * naming string mechanism so cpu_clk_trace_div picks
1315                          * up the appropriate one.
1316                          */
1317                         .name = "cpu_clk",
1318                         .index = -1,
1319                 },
1320                 .num_parents = 1,
1321         },
1322 };
1323
1324 static struct clk_regmap g12a_cpu_clk_trace = {
1325         .data = &(struct clk_regmap_gate_data){
1326                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1327                 .bit_idx = 23,
1328         },
1329         .hw.init = &(struct clk_init_data) {
1330                 .name = "cpu_clk_trace",
1331                 .ops = &clk_regmap_gate_ro_ops,
1332                 .parent_hws = (const struct clk_hw *[]) {
1333                         &g12a_cpu_clk_trace_div.hw
1334                 },
1335                 .num_parents = 1,
1336                 /*
1337                  * This clock is set by the ROM monitor code,
1338                  * Linux should not change it at runtime
1339                  */
1340         },
1341 };
1342
1343 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1344         .mult = 1,
1345         .div = 2,
1346         .hw.init = &(struct clk_init_data){
1347                 .name = "cpub_clk_div2",
1348                 .ops = &clk_fixed_factor_ops,
1349                 .parent_hws = (const struct clk_hw *[]) {
1350                         &g12b_cpub_clk.hw
1351                 },
1352                 .num_parents = 1,
1353         },
1354 };
1355
1356 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1357         .mult = 1,
1358         .div = 3,
1359         .hw.init = &(struct clk_init_data){
1360                 .name = "cpub_clk_div3",
1361                 .ops = &clk_fixed_factor_ops,
1362                 .parent_hws = (const struct clk_hw *[]) {
1363                         &g12b_cpub_clk.hw
1364                 },
1365                 .num_parents = 1,
1366         },
1367 };
1368
1369 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1370         .mult = 1,
1371         .div = 4,
1372         .hw.init = &(struct clk_init_data){
1373                 .name = "cpub_clk_div4",
1374                 .ops = &clk_fixed_factor_ops,
1375                 .parent_hws = (const struct clk_hw *[]) {
1376                         &g12b_cpub_clk.hw
1377                 },
1378                 .num_parents = 1,
1379         },
1380 };
1381
1382 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1383         .mult = 1,
1384         .div = 5,
1385         .hw.init = &(struct clk_init_data){
1386                 .name = "cpub_clk_div5",
1387                 .ops = &clk_fixed_factor_ops,
1388                 .parent_hws = (const struct clk_hw *[]) {
1389                         &g12b_cpub_clk.hw
1390                 },
1391                 .num_parents = 1,
1392         },
1393 };
1394
1395 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1396         .mult = 1,
1397         .div = 6,
1398         .hw.init = &(struct clk_init_data){
1399                 .name = "cpub_clk_div6",
1400                 .ops = &clk_fixed_factor_ops,
1401                 .parent_hws = (const struct clk_hw *[]) {
1402                         &g12b_cpub_clk.hw
1403                 },
1404                 .num_parents = 1,
1405         },
1406 };
1407
1408 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1409         .mult = 1,
1410         .div = 7,
1411         .hw.init = &(struct clk_init_data){
1412                 .name = "cpub_clk_div7",
1413                 .ops = &clk_fixed_factor_ops,
1414                 .parent_hws = (const struct clk_hw *[]) {
1415                         &g12b_cpub_clk.hw
1416                 },
1417                 .num_parents = 1,
1418         },
1419 };
1420
1421 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1422         .mult = 1,
1423         .div = 8,
1424         .hw.init = &(struct clk_init_data){
1425                 .name = "cpub_clk_div8",
1426                 .ops = &clk_fixed_factor_ops,
1427                 .parent_hws = (const struct clk_hw *[]) {
1428                         &g12b_cpub_clk.hw
1429                 },
1430                 .num_parents = 1,
1431         },
1432 };
1433
1434 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1435 static struct clk_regmap g12b_cpub_clk_apb_sel = {
1436         .data = &(struct clk_regmap_mux_data){
1437                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1438                 .mask = 7,
1439                 .shift = 3,
1440                 .table = mux_table_cpub,
1441         },
1442         .hw.init = &(struct clk_init_data){
1443                 .name = "cpub_clk_apb_sel",
1444                 .ops = &clk_regmap_mux_ro_ops,
1445                 .parent_hws = (const struct clk_hw *[]) {
1446                         &g12b_cpub_clk_div2.hw,
1447                         &g12b_cpub_clk_div3.hw,
1448                         &g12b_cpub_clk_div4.hw,
1449                         &g12b_cpub_clk_div5.hw,
1450                         &g12b_cpub_clk_div6.hw,
1451                         &g12b_cpub_clk_div7.hw,
1452                         &g12b_cpub_clk_div8.hw
1453                 },
1454                 .num_parents = 7,
1455         },
1456 };
1457
1458 static struct clk_regmap g12b_cpub_clk_apb = {
1459         .data = &(struct clk_regmap_gate_data){
1460                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1461                 .bit_idx = 16,
1462                 .flags = CLK_GATE_SET_TO_DISABLE,
1463         },
1464         .hw.init = &(struct clk_init_data) {
1465                 .name = "cpub_clk_apb",
1466                 .ops = &clk_regmap_gate_ro_ops,
1467                 .parent_hws = (const struct clk_hw *[]) {
1468                         &g12b_cpub_clk_apb_sel.hw
1469                 },
1470                 .num_parents = 1,
1471                 /*
1472                  * This clock is set by the ROM monitor code,
1473                  * Linux should not change it at runtime
1474                  */
1475         },
1476 };
1477
1478 static struct clk_regmap g12b_cpub_clk_atb_sel = {
1479         .data = &(struct clk_regmap_mux_data){
1480                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1481                 .mask = 7,
1482                 .shift = 6,
1483                 .table = mux_table_cpub,
1484         },
1485         .hw.init = &(struct clk_init_data){
1486                 .name = "cpub_clk_atb_sel",
1487                 .ops = &clk_regmap_mux_ro_ops,
1488                 .parent_hws = (const struct clk_hw *[]) {
1489                         &g12b_cpub_clk_div2.hw,
1490                         &g12b_cpub_clk_div3.hw,
1491                         &g12b_cpub_clk_div4.hw,
1492                         &g12b_cpub_clk_div5.hw,
1493                         &g12b_cpub_clk_div6.hw,
1494                         &g12b_cpub_clk_div7.hw,
1495                         &g12b_cpub_clk_div8.hw
1496                 },
1497                 .num_parents = 7,
1498         },
1499 };
1500
1501 static struct clk_regmap g12b_cpub_clk_atb = {
1502         .data = &(struct clk_regmap_gate_data){
1503                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1504                 .bit_idx = 17,
1505                 .flags = CLK_GATE_SET_TO_DISABLE,
1506         },
1507         .hw.init = &(struct clk_init_data) {
1508                 .name = "cpub_clk_atb",
1509                 .ops = &clk_regmap_gate_ro_ops,
1510                 .parent_hws = (const struct clk_hw *[]) {
1511                         &g12b_cpub_clk_atb_sel.hw
1512                 },
1513                 .num_parents = 1,
1514                 /*
1515                  * This clock is set by the ROM monitor code,
1516                  * Linux should not change it at runtime
1517                  */
1518         },
1519 };
1520
1521 static struct clk_regmap g12b_cpub_clk_axi_sel = {
1522         .data = &(struct clk_regmap_mux_data){
1523                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1524                 .mask = 7,
1525                 .shift = 9,
1526                 .table = mux_table_cpub,
1527         },
1528         .hw.init = &(struct clk_init_data){
1529                 .name = "cpub_clk_axi_sel",
1530                 .ops = &clk_regmap_mux_ro_ops,
1531                 .parent_hws = (const struct clk_hw *[]) {
1532                         &g12b_cpub_clk_div2.hw,
1533                         &g12b_cpub_clk_div3.hw,
1534                         &g12b_cpub_clk_div4.hw,
1535                         &g12b_cpub_clk_div5.hw,
1536                         &g12b_cpub_clk_div6.hw,
1537                         &g12b_cpub_clk_div7.hw,
1538                         &g12b_cpub_clk_div8.hw
1539                 },
1540                 .num_parents = 7,
1541         },
1542 };
1543
1544 static struct clk_regmap g12b_cpub_clk_axi = {
1545         .data = &(struct clk_regmap_gate_data){
1546                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1547                 .bit_idx = 18,
1548                 .flags = CLK_GATE_SET_TO_DISABLE,
1549         },
1550         .hw.init = &(struct clk_init_data) {
1551                 .name = "cpub_clk_axi",
1552                 .ops = &clk_regmap_gate_ro_ops,
1553                 .parent_hws = (const struct clk_hw *[]) {
1554                         &g12b_cpub_clk_axi_sel.hw
1555                 },
1556                 .num_parents = 1,
1557                 /*
1558                  * This clock is set by the ROM monitor code,
1559                  * Linux should not change it at runtime
1560                  */
1561         },
1562 };
1563
1564 static struct clk_regmap g12b_cpub_clk_trace_sel = {
1565         .data = &(struct clk_regmap_mux_data){
1566                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1567                 .mask = 7,
1568                 .shift = 20,
1569                 .table = mux_table_cpub,
1570         },
1571         .hw.init = &(struct clk_init_data){
1572                 .name = "cpub_clk_trace_sel",
1573                 .ops = &clk_regmap_mux_ro_ops,
1574                 .parent_hws = (const struct clk_hw *[]) {
1575                         &g12b_cpub_clk_div2.hw,
1576                         &g12b_cpub_clk_div3.hw,
1577                         &g12b_cpub_clk_div4.hw,
1578                         &g12b_cpub_clk_div5.hw,
1579                         &g12b_cpub_clk_div6.hw,
1580                         &g12b_cpub_clk_div7.hw,
1581                         &g12b_cpub_clk_div8.hw
1582                 },
1583                 .num_parents = 7,
1584         },
1585 };
1586
1587 static struct clk_regmap g12b_cpub_clk_trace = {
1588         .data = &(struct clk_regmap_gate_data){
1589                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1590                 .bit_idx = 23,
1591                 .flags = CLK_GATE_SET_TO_DISABLE,
1592         },
1593         .hw.init = &(struct clk_init_data) {
1594                 .name = "cpub_clk_trace",
1595                 .ops = &clk_regmap_gate_ro_ops,
1596                 .parent_hws = (const struct clk_hw *[]) {
1597                         &g12b_cpub_clk_trace_sel.hw
1598                 },
1599                 .num_parents = 1,
1600                 /*
1601                  * This clock is set by the ROM monitor code,
1602                  * Linux should not change it at runtime
1603                  */
1604         },
1605 };
1606
1607 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1608         .min = 125,
1609         .max = 255,
1610 };
1611
1612 /*
1613  * Internal gp0 pll emulation configuration parameters
1614  */
1615 static const struct reg_sequence g12a_gp0_init_regs[] = {
1616         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0x00000000 },
1617         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x00000000 },
1618         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x48681c00 },
1619         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x33771290 },
1620         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x39272000 },
1621         { .reg = HHI_GP0_PLL_CNTL6,     .def = 0x56540000 },
1622 };
1623
1624 static struct clk_regmap g12a_gp0_pll_dco = {
1625         .data = &(struct meson_clk_pll_data){
1626                 .en = {
1627                         .reg_off = HHI_GP0_PLL_CNTL0,
1628                         .shift   = 28,
1629                         .width   = 1,
1630                 },
1631                 .m = {
1632                         .reg_off = HHI_GP0_PLL_CNTL0,
1633                         .shift   = 0,
1634                         .width   = 8,
1635                 },
1636                 .n = {
1637                         .reg_off = HHI_GP0_PLL_CNTL0,
1638                         .shift   = 10,
1639                         .width   = 5,
1640                 },
1641                 .frac = {
1642                         .reg_off = HHI_GP0_PLL_CNTL1,
1643                         .shift   = 0,
1644                         .width   = 17,
1645                 },
1646                 .l = {
1647                         .reg_off = HHI_GP0_PLL_CNTL0,
1648                         .shift   = 31,
1649                         .width   = 1,
1650                 },
1651                 .rst = {
1652                         .reg_off = HHI_GP0_PLL_CNTL0,
1653                         .shift   = 29,
1654                         .width   = 1,
1655                 },
1656                 .range = &g12a_gp0_pll_mult_range,
1657                 .init_regs = g12a_gp0_init_regs,
1658                 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1659         },
1660         .hw.init = &(struct clk_init_data){
1661                 .name = "gp0_pll_dco",
1662                 .ops = &meson_clk_pll_ops,
1663                 .parent_data = &(const struct clk_parent_data) {
1664                         .fw_name = "xtal",
1665                 },
1666                 .num_parents = 1,
1667         },
1668 };
1669
1670 static struct clk_regmap g12a_gp0_pll = {
1671         .data = &(struct clk_regmap_div_data){
1672                 .offset = HHI_GP0_PLL_CNTL0,
1673                 .shift = 16,
1674                 .width = 3,
1675                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1676                           CLK_DIVIDER_ROUND_CLOSEST),
1677         },
1678         .hw.init = &(struct clk_init_data){
1679                 .name = "gp0_pll",
1680                 .ops = &clk_regmap_divider_ops,
1681                 .parent_hws = (const struct clk_hw *[]) {
1682                         &g12a_gp0_pll_dco.hw
1683                 },
1684                 .num_parents = 1,
1685                 .flags = CLK_SET_RATE_PARENT,
1686         },
1687 };
1688
1689 static struct clk_regmap sm1_gp1_pll_dco = {
1690         .data = &(struct meson_clk_pll_data){
1691                 .en = {
1692                         .reg_off = HHI_GP1_PLL_CNTL0,
1693                         .shift   = 28,
1694                         .width   = 1,
1695                 },
1696                 .m = {
1697                         .reg_off = HHI_GP1_PLL_CNTL0,
1698                         .shift   = 0,
1699                         .width   = 8,
1700                 },
1701                 .n = {
1702                         .reg_off = HHI_GP1_PLL_CNTL0,
1703                         .shift   = 10,
1704                         .width   = 5,
1705                 },
1706                 .frac = {
1707                         .reg_off = HHI_GP1_PLL_CNTL1,
1708                         .shift   = 0,
1709                         .width   = 17,
1710                 },
1711                 .l = {
1712                         .reg_off = HHI_GP1_PLL_CNTL0,
1713                         .shift   = 31,
1714                         .width   = 1,
1715                 },
1716                 .rst = {
1717                         .reg_off = HHI_GP1_PLL_CNTL0,
1718                         .shift   = 29,
1719                         .width   = 1,
1720                 },
1721         },
1722         .hw.init = &(struct clk_init_data){
1723                 .name = "gp1_pll_dco",
1724                 .ops = &meson_clk_pll_ro_ops,
1725                 .parent_data = &(const struct clk_parent_data) {
1726                         .fw_name = "xtal",
1727                 },
1728                 .num_parents = 1,
1729                 /* This clock feeds the DSU, avoid disabling it */
1730                 .flags = CLK_IS_CRITICAL,
1731         },
1732 };
1733
1734 static struct clk_regmap sm1_gp1_pll = {
1735         .data = &(struct clk_regmap_div_data){
1736                 .offset = HHI_GP1_PLL_CNTL0,
1737                 .shift = 16,
1738                 .width = 3,
1739                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1740                           CLK_DIVIDER_ROUND_CLOSEST),
1741         },
1742         .hw.init = &(struct clk_init_data){
1743                 .name = "gp1_pll",
1744                 .ops = &clk_regmap_divider_ro_ops,
1745                 .parent_hws = (const struct clk_hw *[]) {
1746                         &sm1_gp1_pll_dco.hw
1747                 },
1748                 .num_parents = 1,
1749         },
1750 };
1751
1752 /*
1753  * Internal hifi pll emulation configuration parameters
1754  */
1755 static const struct reg_sequence g12a_hifi_init_regs[] = {
1756         { .reg = HHI_HIFI_PLL_CNTL1,    .def = 0x00000000 },
1757         { .reg = HHI_HIFI_PLL_CNTL2,    .def = 0x00000000 },
1758         { .reg = HHI_HIFI_PLL_CNTL3,    .def = 0x6a285c00 },
1759         { .reg = HHI_HIFI_PLL_CNTL4,    .def = 0x65771290 },
1760         { .reg = HHI_HIFI_PLL_CNTL5,    .def = 0x39272000 },
1761         { .reg = HHI_HIFI_PLL_CNTL6,    .def = 0x56540000 },
1762 };
1763
1764 static struct clk_regmap g12a_hifi_pll_dco = {
1765         .data = &(struct meson_clk_pll_data){
1766                 .en = {
1767                         .reg_off = HHI_HIFI_PLL_CNTL0,
1768                         .shift   = 28,
1769                         .width   = 1,
1770                 },
1771                 .m = {
1772                         .reg_off = HHI_HIFI_PLL_CNTL0,
1773                         .shift   = 0,
1774                         .width   = 8,
1775                 },
1776                 .n = {
1777                         .reg_off = HHI_HIFI_PLL_CNTL0,
1778                         .shift   = 10,
1779                         .width   = 5,
1780                 },
1781                 .frac = {
1782                         .reg_off = HHI_HIFI_PLL_CNTL1,
1783                         .shift   = 0,
1784                         .width   = 17,
1785                 },
1786                 .l = {
1787                         .reg_off = HHI_HIFI_PLL_CNTL0,
1788                         .shift   = 31,
1789                         .width   = 1,
1790                 },
1791                 .rst = {
1792                         .reg_off = HHI_HIFI_PLL_CNTL0,
1793                         .shift   = 29,
1794                         .width   = 1,
1795                 },
1796                 .range = &g12a_gp0_pll_mult_range,
1797                 .init_regs = g12a_hifi_init_regs,
1798                 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1799                 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
1800         },
1801         .hw.init = &(struct clk_init_data){
1802                 .name = "hifi_pll_dco",
1803                 .ops = &meson_clk_pll_ops,
1804                 .parent_data = &(const struct clk_parent_data) {
1805                         .fw_name = "xtal",
1806                 },
1807                 .num_parents = 1,
1808         },
1809 };
1810
1811 static struct clk_regmap g12a_hifi_pll = {
1812         .data = &(struct clk_regmap_div_data){
1813                 .offset = HHI_HIFI_PLL_CNTL0,
1814                 .shift = 16,
1815                 .width = 2,
1816                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1817                           CLK_DIVIDER_ROUND_CLOSEST),
1818         },
1819         .hw.init = &(struct clk_init_data){
1820                 .name = "hifi_pll",
1821                 .ops = &clk_regmap_divider_ops,
1822                 .parent_hws = (const struct clk_hw *[]) {
1823                         &g12a_hifi_pll_dco.hw
1824                 },
1825                 .num_parents = 1,
1826                 .flags = CLK_SET_RATE_PARENT,
1827         },
1828 };
1829
1830 /*
1831  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1832  * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1833  * a strict register sequence to enable the PLL.
1834  */
1835 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1836         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x20090496 },
1837         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x30090496 },
1838         { .reg = HHI_PCIE_PLL_CNTL1,    .def = 0x00000000 },
1839         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001100 },
1840         { .reg = HHI_PCIE_PLL_CNTL3,    .def = 0x10058e00 },
1841         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x000100c0 },
1842         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000048 },
1843         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000068, .delay_us = 20 },
1844         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x008100c0, .delay_us = 10 },
1845         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x34090496 },
1846         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x14090496, .delay_us = 10 },
1847         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001000 },
1848 };
1849
1850 /* Keep a single entry table for recalc/round_rate() ops */
1851 static const struct pll_params_table g12a_pcie_pll_table[] = {
1852         PLL_PARAMS(150, 1),
1853         {0, 0},
1854 };
1855
1856 static struct clk_regmap g12a_pcie_pll_dco = {
1857         .data = &(struct meson_clk_pll_data){
1858                 .en = {
1859                         .reg_off = HHI_PCIE_PLL_CNTL0,
1860                         .shift   = 28,
1861                         .width   = 1,
1862                 },
1863                 .m = {
1864                         .reg_off = HHI_PCIE_PLL_CNTL0,
1865                         .shift   = 0,
1866                         .width   = 8,
1867                 },
1868                 .n = {
1869                         .reg_off = HHI_PCIE_PLL_CNTL0,
1870                         .shift   = 10,
1871                         .width   = 5,
1872                 },
1873                 .frac = {
1874                         .reg_off = HHI_PCIE_PLL_CNTL1,
1875                         .shift   = 0,
1876                         .width   = 12,
1877                 },
1878                 .l = {
1879                         .reg_off = HHI_PCIE_PLL_CNTL0,
1880                         .shift   = 31,
1881                         .width   = 1,
1882                 },
1883                 .rst = {
1884                         .reg_off = HHI_PCIE_PLL_CNTL0,
1885                         .shift   = 29,
1886                         .width   = 1,
1887                 },
1888                 .table = g12a_pcie_pll_table,
1889                 .init_regs = g12a_pcie_pll_init_regs,
1890                 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1891         },
1892         .hw.init = &(struct clk_init_data){
1893                 .name = "pcie_pll_dco",
1894                 .ops = &meson_clk_pcie_pll_ops,
1895                 .parent_data = &(const struct clk_parent_data) {
1896                         .fw_name = "xtal",
1897                 },
1898                 .num_parents = 1,
1899         },
1900 };
1901
1902 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1903         .mult = 1,
1904         .div = 2,
1905         .hw.init = &(struct clk_init_data){
1906                 .name = "pcie_pll_dco_div2",
1907                 .ops = &clk_fixed_factor_ops,
1908                 .parent_hws = (const struct clk_hw *[]) {
1909                         &g12a_pcie_pll_dco.hw
1910                 },
1911                 .num_parents = 1,
1912                 .flags = CLK_SET_RATE_PARENT,
1913         },
1914 };
1915
1916 static struct clk_regmap g12a_pcie_pll_od = {
1917         .data = &(struct clk_regmap_div_data){
1918                 .offset = HHI_PCIE_PLL_CNTL0,
1919                 .shift = 16,
1920                 .width = 5,
1921                 .flags = CLK_DIVIDER_ROUND_CLOSEST |
1922                          CLK_DIVIDER_ONE_BASED |
1923                          CLK_DIVIDER_ALLOW_ZERO,
1924         },
1925         .hw.init = &(struct clk_init_data){
1926                 .name = "pcie_pll_od",
1927                 .ops = &clk_regmap_divider_ops,
1928                 .parent_hws = (const struct clk_hw *[]) {
1929                         &g12a_pcie_pll_dco_div2.hw
1930                 },
1931                 .num_parents = 1,
1932                 .flags = CLK_SET_RATE_PARENT,
1933         },
1934 };
1935
1936 static struct clk_fixed_factor g12a_pcie_pll = {
1937         .mult = 1,
1938         .div = 2,
1939         .hw.init = &(struct clk_init_data){
1940                 .name = "pcie_pll_pll",
1941                 .ops = &clk_fixed_factor_ops,
1942                 .parent_hws = (const struct clk_hw *[]) {
1943                         &g12a_pcie_pll_od.hw
1944                 },
1945                 .num_parents = 1,
1946                 .flags = CLK_SET_RATE_PARENT,
1947         },
1948 };
1949
1950 static struct clk_regmap g12a_hdmi_pll_dco = {
1951         .data = &(struct meson_clk_pll_data){
1952                 .en = {
1953                         .reg_off = HHI_HDMI_PLL_CNTL0,
1954                         .shift   = 28,
1955                         .width   = 1,
1956                 },
1957                 .m = {
1958                         .reg_off = HHI_HDMI_PLL_CNTL0,
1959                         .shift   = 0,
1960                         .width   = 8,
1961                 },
1962                 .n = {
1963                         .reg_off = HHI_HDMI_PLL_CNTL0,
1964                         .shift   = 10,
1965                         .width   = 5,
1966                 },
1967                 .frac = {
1968                         .reg_off = HHI_HDMI_PLL_CNTL1,
1969                         .shift   = 0,
1970                         .width   = 16,
1971                 },
1972                 .l = {
1973                         .reg_off = HHI_HDMI_PLL_CNTL0,
1974                         .shift   = 30,
1975                         .width   = 1,
1976                 },
1977                 .rst = {
1978                         .reg_off = HHI_HDMI_PLL_CNTL0,
1979                         .shift   = 29,
1980                         .width   = 1,
1981                 },
1982         },
1983         .hw.init = &(struct clk_init_data){
1984                 .name = "hdmi_pll_dco",
1985                 .ops = &meson_clk_pll_ro_ops,
1986                 .parent_data = &(const struct clk_parent_data) {
1987                         .fw_name = "xtal",
1988                 },
1989                 .num_parents = 1,
1990                 /*
1991                  * Display directly handle hdmi pll registers ATM, we need
1992                  * NOCACHE to keep our view of the clock as accurate as possible
1993                  */
1994                 .flags = CLK_GET_RATE_NOCACHE,
1995         },
1996 };
1997
1998 static struct clk_regmap g12a_hdmi_pll_od = {
1999         .data = &(struct clk_regmap_div_data){
2000                 .offset = HHI_HDMI_PLL_CNTL0,
2001                 .shift = 16,
2002                 .width = 2,
2003                 .flags = CLK_DIVIDER_POWER_OF_TWO,
2004         },
2005         .hw.init = &(struct clk_init_data){
2006                 .name = "hdmi_pll_od",
2007                 .ops = &clk_regmap_divider_ro_ops,
2008                 .parent_hws = (const struct clk_hw *[]) {
2009                         &g12a_hdmi_pll_dco.hw
2010                 },
2011                 .num_parents = 1,
2012                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2013         },
2014 };
2015
2016 static struct clk_regmap g12a_hdmi_pll_od2 = {
2017         .data = &(struct clk_regmap_div_data){
2018                 .offset = HHI_HDMI_PLL_CNTL0,
2019                 .shift = 18,
2020                 .width = 2,
2021                 .flags = CLK_DIVIDER_POWER_OF_TWO,
2022         },
2023         .hw.init = &(struct clk_init_data){
2024                 .name = "hdmi_pll_od2",
2025                 .ops = &clk_regmap_divider_ro_ops,
2026                 .parent_hws = (const struct clk_hw *[]) {
2027                         &g12a_hdmi_pll_od.hw
2028                 },
2029                 .num_parents = 1,
2030                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2031         },
2032 };
2033
2034 static struct clk_regmap g12a_hdmi_pll = {
2035         .data = &(struct clk_regmap_div_data){
2036                 .offset = HHI_HDMI_PLL_CNTL0,
2037                 .shift = 20,
2038                 .width = 2,
2039                 .flags = CLK_DIVIDER_POWER_OF_TWO,
2040         },
2041         .hw.init = &(struct clk_init_data){
2042                 .name = "hdmi_pll",
2043                 .ops = &clk_regmap_divider_ro_ops,
2044                 .parent_hws = (const struct clk_hw *[]) {
2045                         &g12a_hdmi_pll_od2.hw
2046                 },
2047                 .num_parents = 1,
2048                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2049         },
2050 };
2051
2052 static struct clk_fixed_factor g12a_fclk_div4_div = {
2053         .mult = 1,
2054         .div = 4,
2055         .hw.init = &(struct clk_init_data){
2056                 .name = "fclk_div4_div",
2057                 .ops = &clk_fixed_factor_ops,
2058                 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2059                 .num_parents = 1,
2060         },
2061 };
2062
2063 static struct clk_regmap g12a_fclk_div4 = {
2064         .data = &(struct clk_regmap_gate_data){
2065                 .offset = HHI_FIX_PLL_CNTL1,
2066                 .bit_idx = 21,
2067         },
2068         .hw.init = &(struct clk_init_data){
2069                 .name = "fclk_div4",
2070                 .ops = &clk_regmap_gate_ops,
2071                 .parent_hws = (const struct clk_hw *[]) {
2072                         &g12a_fclk_div4_div.hw
2073                 },
2074                 .num_parents = 1,
2075         },
2076 };
2077
2078 static struct clk_fixed_factor g12a_fclk_div5_div = {
2079         .mult = 1,
2080         .div = 5,
2081         .hw.init = &(struct clk_init_data){
2082                 .name = "fclk_div5_div",
2083                 .ops = &clk_fixed_factor_ops,
2084                 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2085                 .num_parents = 1,
2086         },
2087 };
2088
2089 static struct clk_regmap g12a_fclk_div5 = {
2090         .data = &(struct clk_regmap_gate_data){
2091                 .offset = HHI_FIX_PLL_CNTL1,
2092                 .bit_idx = 22,
2093         },
2094         .hw.init = &(struct clk_init_data){
2095                 .name = "fclk_div5",
2096                 .ops = &clk_regmap_gate_ops,
2097                 .parent_hws = (const struct clk_hw *[]) {
2098                         &g12a_fclk_div5_div.hw
2099                 },
2100                 .num_parents = 1,
2101         },
2102 };
2103
2104 static struct clk_fixed_factor g12a_fclk_div7_div = {
2105         .mult = 1,
2106         .div = 7,
2107         .hw.init = &(struct clk_init_data){
2108                 .name = "fclk_div7_div",
2109                 .ops = &clk_fixed_factor_ops,
2110                 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2111                 .num_parents = 1,
2112         },
2113 };
2114
2115 static struct clk_regmap g12a_fclk_div7 = {
2116         .data = &(struct clk_regmap_gate_data){
2117                 .offset = HHI_FIX_PLL_CNTL1,
2118                 .bit_idx = 23,
2119         },
2120         .hw.init = &(struct clk_init_data){
2121                 .name = "fclk_div7",
2122                 .ops = &clk_regmap_gate_ops,
2123                 .parent_hws = (const struct clk_hw *[]) {
2124                         &g12a_fclk_div7_div.hw
2125                 },
2126                 .num_parents = 1,
2127         },
2128 };
2129
2130 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2131         .mult = 1,
2132         .div = 5,
2133         .hw.init = &(struct clk_init_data){
2134                 .name = "fclk_div2p5_div",
2135                 .ops = &clk_fixed_factor_ops,
2136                 .parent_hws = (const struct clk_hw *[]) {
2137                         &g12a_fixed_pll_dco.hw
2138                 },
2139                 .num_parents = 1,
2140         },
2141 };
2142
2143 static struct clk_regmap g12a_fclk_div2p5 = {
2144         .data = &(struct clk_regmap_gate_data){
2145                 .offset = HHI_FIX_PLL_CNTL1,
2146                 .bit_idx = 25,
2147         },
2148         .hw.init = &(struct clk_init_data){
2149                 .name = "fclk_div2p5",
2150                 .ops = &clk_regmap_gate_ops,
2151                 .parent_hws = (const struct clk_hw *[]) {
2152                         &g12a_fclk_div2p5_div.hw
2153                 },
2154                 .num_parents = 1,
2155         },
2156 };
2157
2158 static struct clk_fixed_factor g12a_mpll_50m_div = {
2159         .mult = 1,
2160         .div = 80,
2161         .hw.init = &(struct clk_init_data){
2162                 .name = "mpll_50m_div",
2163                 .ops = &clk_fixed_factor_ops,
2164                 .parent_hws = (const struct clk_hw *[]) {
2165                         &g12a_fixed_pll_dco.hw
2166                 },
2167                 .num_parents = 1,
2168         },
2169 };
2170
2171 static struct clk_regmap g12a_mpll_50m = {
2172         .data = &(struct clk_regmap_mux_data){
2173                 .offset = HHI_FIX_PLL_CNTL3,
2174                 .mask = 0x1,
2175                 .shift = 5,
2176         },
2177         .hw.init = &(struct clk_init_data){
2178                 .name = "mpll_50m",
2179                 .ops = &clk_regmap_mux_ro_ops,
2180                 .parent_data = (const struct clk_parent_data []) {
2181                         { .fw_name = "xtal", },
2182                         { .hw = &g12a_mpll_50m_div.hw },
2183                 },
2184                 .num_parents = 2,
2185         },
2186 };
2187
2188 static struct clk_fixed_factor g12a_mpll_prediv = {
2189         .mult = 1,
2190         .div = 2,
2191         .hw.init = &(struct clk_init_data){
2192                 .name = "mpll_prediv",
2193                 .ops = &clk_fixed_factor_ops,
2194                 .parent_hws = (const struct clk_hw *[]) {
2195                         &g12a_fixed_pll_dco.hw
2196                 },
2197                 .num_parents = 1,
2198         },
2199 };
2200
2201 static const struct reg_sequence g12a_mpll0_init_regs[] = {
2202         { .reg = HHI_MPLL_CNTL2,        .def = 0x40000033 },
2203 };
2204
2205 static struct clk_regmap g12a_mpll0_div = {
2206         .data = &(struct meson_clk_mpll_data){
2207                 .sdm = {
2208                         .reg_off = HHI_MPLL_CNTL1,
2209                         .shift   = 0,
2210                         .width   = 14,
2211                 },
2212                 .sdm_en = {
2213                         .reg_off = HHI_MPLL_CNTL1,
2214                         .shift   = 30,
2215                         .width   = 1,
2216                 },
2217                 .n2 = {
2218                         .reg_off = HHI_MPLL_CNTL1,
2219                         .shift   = 20,
2220                         .width   = 9,
2221                 },
2222                 .ssen = {
2223                         .reg_off = HHI_MPLL_CNTL1,
2224                         .shift   = 29,
2225                         .width   = 1,
2226                 },
2227                 .lock = &meson_clk_lock,
2228                 .init_regs = g12a_mpll0_init_regs,
2229                 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2230         },
2231         .hw.init = &(struct clk_init_data){
2232                 .name = "mpll0_div",
2233                 .ops = &meson_clk_mpll_ops,
2234                 .parent_hws = (const struct clk_hw *[]) {
2235                         &g12a_mpll_prediv.hw
2236                 },
2237                 .num_parents = 1,
2238         },
2239 };
2240
2241 static struct clk_regmap g12a_mpll0 = {
2242         .data = &(struct clk_regmap_gate_data){
2243                 .offset = HHI_MPLL_CNTL1,
2244                 .bit_idx = 31,
2245         },
2246         .hw.init = &(struct clk_init_data){
2247                 .name = "mpll0",
2248                 .ops = &clk_regmap_gate_ops,
2249                 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2250                 .num_parents = 1,
2251                 .flags = CLK_SET_RATE_PARENT,
2252         },
2253 };
2254
2255 static const struct reg_sequence g12a_mpll1_init_regs[] = {
2256         { .reg = HHI_MPLL_CNTL4,        .def = 0x40000033 },
2257 };
2258
2259 static struct clk_regmap g12a_mpll1_div = {
2260         .data = &(struct meson_clk_mpll_data){
2261                 .sdm = {
2262                         .reg_off = HHI_MPLL_CNTL3,
2263                         .shift   = 0,
2264                         .width   = 14,
2265                 },
2266                 .sdm_en = {
2267                         .reg_off = HHI_MPLL_CNTL3,
2268                         .shift   = 30,
2269                         .width   = 1,
2270                 },
2271                 .n2 = {
2272                         .reg_off = HHI_MPLL_CNTL3,
2273                         .shift   = 20,
2274                         .width   = 9,
2275                 },
2276                 .ssen = {
2277                         .reg_off = HHI_MPLL_CNTL3,
2278                         .shift   = 29,
2279                         .width   = 1,
2280                 },
2281                 .lock = &meson_clk_lock,
2282                 .init_regs = g12a_mpll1_init_regs,
2283                 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2284         },
2285         .hw.init = &(struct clk_init_data){
2286                 .name = "mpll1_div",
2287                 .ops = &meson_clk_mpll_ops,
2288                 .parent_hws = (const struct clk_hw *[]) {
2289                         &g12a_mpll_prediv.hw
2290                 },
2291                 .num_parents = 1,
2292         },
2293 };
2294
2295 static struct clk_regmap g12a_mpll1 = {
2296         .data = &(struct clk_regmap_gate_data){
2297                 .offset = HHI_MPLL_CNTL3,
2298                 .bit_idx = 31,
2299         },
2300         .hw.init = &(struct clk_init_data){
2301                 .name = "mpll1",
2302                 .ops = &clk_regmap_gate_ops,
2303                 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2304                 .num_parents = 1,
2305                 .flags = CLK_SET_RATE_PARENT,
2306         },
2307 };
2308
2309 static const struct reg_sequence g12a_mpll2_init_regs[] = {
2310         { .reg = HHI_MPLL_CNTL6,        .def = 0x40000033 },
2311 };
2312
2313 static struct clk_regmap g12a_mpll2_div = {
2314         .data = &(struct meson_clk_mpll_data){
2315                 .sdm = {
2316                         .reg_off = HHI_MPLL_CNTL5,
2317                         .shift   = 0,
2318                         .width   = 14,
2319                 },
2320                 .sdm_en = {
2321                         .reg_off = HHI_MPLL_CNTL5,
2322                         .shift   = 30,
2323                         .width   = 1,
2324                 },
2325                 .n2 = {
2326                         .reg_off = HHI_MPLL_CNTL5,
2327                         .shift   = 20,
2328                         .width   = 9,
2329                 },
2330                 .ssen = {
2331                         .reg_off = HHI_MPLL_CNTL5,
2332                         .shift   = 29,
2333                         .width   = 1,
2334                 },
2335                 .lock = &meson_clk_lock,
2336                 .init_regs = g12a_mpll2_init_regs,
2337                 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2338         },
2339         .hw.init = &(struct clk_init_data){
2340                 .name = "mpll2_div",
2341                 .ops = &meson_clk_mpll_ops,
2342                 .parent_hws = (const struct clk_hw *[]) {
2343                         &g12a_mpll_prediv.hw
2344                 },
2345                 .num_parents = 1,
2346         },
2347 };
2348
2349 static struct clk_regmap g12a_mpll2 = {
2350         .data = &(struct clk_regmap_gate_data){
2351                 .offset = HHI_MPLL_CNTL5,
2352                 .bit_idx = 31,
2353         },
2354         .hw.init = &(struct clk_init_data){
2355                 .name = "mpll2",
2356                 .ops = &clk_regmap_gate_ops,
2357                 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2358                 .num_parents = 1,
2359                 .flags = CLK_SET_RATE_PARENT,
2360         },
2361 };
2362
2363 static const struct reg_sequence g12a_mpll3_init_regs[] = {
2364         { .reg = HHI_MPLL_CNTL8,        .def = 0x40000033 },
2365 };
2366
2367 static struct clk_regmap g12a_mpll3_div = {
2368         .data = &(struct meson_clk_mpll_data){
2369                 .sdm = {
2370                         .reg_off = HHI_MPLL_CNTL7,
2371                         .shift   = 0,
2372                         .width   = 14,
2373                 },
2374                 .sdm_en = {
2375                         .reg_off = HHI_MPLL_CNTL7,
2376                         .shift   = 30,
2377                         .width   = 1,
2378                 },
2379                 .n2 = {
2380                         .reg_off = HHI_MPLL_CNTL7,
2381                         .shift   = 20,
2382                         .width   = 9,
2383                 },
2384                 .ssen = {
2385                         .reg_off = HHI_MPLL_CNTL7,
2386                         .shift   = 29,
2387                         .width   = 1,
2388                 },
2389                 .lock = &meson_clk_lock,
2390                 .init_regs = g12a_mpll3_init_regs,
2391                 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2392         },
2393         .hw.init = &(struct clk_init_data){
2394                 .name = "mpll3_div",
2395                 .ops = &meson_clk_mpll_ops,
2396                 .parent_hws = (const struct clk_hw *[]) {
2397                         &g12a_mpll_prediv.hw
2398                 },
2399                 .num_parents = 1,
2400         },
2401 };
2402
2403 static struct clk_regmap g12a_mpll3 = {
2404         .data = &(struct clk_regmap_gate_data){
2405                 .offset = HHI_MPLL_CNTL7,
2406                 .bit_idx = 31,
2407         },
2408         .hw.init = &(struct clk_init_data){
2409                 .name = "mpll3",
2410                 .ops = &clk_regmap_gate_ops,
2411                 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2412                 .num_parents = 1,
2413                 .flags = CLK_SET_RATE_PARENT,
2414         },
2415 };
2416
2417 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
2418 static const struct clk_parent_data clk81_parent_data[] = {
2419         { .fw_name = "xtal", },
2420         { .hw = &g12a_fclk_div7.hw },
2421         { .hw = &g12a_mpll1.hw },
2422         { .hw = &g12a_mpll2.hw },
2423         { .hw = &g12a_fclk_div4.hw },
2424         { .hw = &g12a_fclk_div3.hw },
2425         { .hw = &g12a_fclk_div5.hw },
2426 };
2427
2428 static struct clk_regmap g12a_mpeg_clk_sel = {
2429         .data = &(struct clk_regmap_mux_data){
2430                 .offset = HHI_MPEG_CLK_CNTL,
2431                 .mask = 0x7,
2432                 .shift = 12,
2433                 .table = mux_table_clk81,
2434         },
2435         .hw.init = &(struct clk_init_data){
2436                 .name = "mpeg_clk_sel",
2437                 .ops = &clk_regmap_mux_ro_ops,
2438                 .parent_data = clk81_parent_data,
2439                 .num_parents = ARRAY_SIZE(clk81_parent_data),
2440         },
2441 };
2442
2443 static struct clk_regmap g12a_mpeg_clk_div = {
2444         .data = &(struct clk_regmap_div_data){
2445                 .offset = HHI_MPEG_CLK_CNTL,
2446                 .shift = 0,
2447                 .width = 7,
2448         },
2449         .hw.init = &(struct clk_init_data){
2450                 .name = "mpeg_clk_div",
2451                 .ops = &clk_regmap_divider_ops,
2452                 .parent_hws = (const struct clk_hw *[]) {
2453                         &g12a_mpeg_clk_sel.hw
2454                 },
2455                 .num_parents = 1,
2456                 .flags = CLK_SET_RATE_PARENT,
2457         },
2458 };
2459
2460 static struct clk_regmap g12a_clk81 = {
2461         .data = &(struct clk_regmap_gate_data){
2462                 .offset = HHI_MPEG_CLK_CNTL,
2463                 .bit_idx = 7,
2464         },
2465         .hw.init = &(struct clk_init_data){
2466                 .name = "clk81",
2467                 .ops = &clk_regmap_gate_ops,
2468                 .parent_hws = (const struct clk_hw *[]) {
2469                         &g12a_mpeg_clk_div.hw
2470                 },
2471                 .num_parents = 1,
2472                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2473         },
2474 };
2475
2476 static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2477         { .fw_name = "xtal", },
2478         { .hw = &g12a_fclk_div2.hw },
2479         { .hw = &g12a_fclk_div3.hw },
2480         { .hw = &g12a_fclk_div5.hw },
2481         { .hw = &g12a_fclk_div7.hw },
2482         /*
2483          * Following these parent clocks, we should also have had mpll2, mpll3
2484          * and gp0_pll but these clocks are too precious to be used here. All
2485          * the necessary rates for MMC and NAND operation can be acheived using
2486          * g12a_ee_core or fclk_div clocks
2487          */
2488 };
2489
2490 /* SDIO clock */
2491 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2492         .data = &(struct clk_regmap_mux_data){
2493                 .offset = HHI_SD_EMMC_CLK_CNTL,
2494                 .mask = 0x7,
2495                 .shift = 9,
2496         },
2497         .hw.init = &(struct clk_init_data) {
2498                 .name = "sd_emmc_a_clk0_sel",
2499                 .ops = &clk_regmap_mux_ops,
2500                 .parent_data = g12a_sd_emmc_clk0_parent_data,
2501                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2502                 .flags = CLK_SET_RATE_PARENT,
2503         },
2504 };
2505
2506 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2507         .data = &(struct clk_regmap_div_data){
2508                 .offset = HHI_SD_EMMC_CLK_CNTL,
2509                 .shift = 0,
2510                 .width = 7,
2511         },
2512         .hw.init = &(struct clk_init_data) {
2513                 .name = "sd_emmc_a_clk0_div",
2514                 .ops = &clk_regmap_divider_ops,
2515                 .parent_hws = (const struct clk_hw *[]) {
2516                         &g12a_sd_emmc_a_clk0_sel.hw
2517                 },
2518                 .num_parents = 1,
2519                 .flags = CLK_SET_RATE_PARENT,
2520         },
2521 };
2522
2523 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2524         .data = &(struct clk_regmap_gate_data){
2525                 .offset = HHI_SD_EMMC_CLK_CNTL,
2526                 .bit_idx = 7,
2527         },
2528         .hw.init = &(struct clk_init_data){
2529                 .name = "sd_emmc_a_clk0",
2530                 .ops = &clk_regmap_gate_ops,
2531                 .parent_hws = (const struct clk_hw *[]) {
2532                         &g12a_sd_emmc_a_clk0_div.hw
2533                 },
2534                 .num_parents = 1,
2535                 .flags = CLK_SET_RATE_PARENT,
2536         },
2537 };
2538
2539 /* SDcard clock */
2540 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2541         .data = &(struct clk_regmap_mux_data){
2542                 .offset = HHI_SD_EMMC_CLK_CNTL,
2543                 .mask = 0x7,
2544                 .shift = 25,
2545         },
2546         .hw.init = &(struct clk_init_data) {
2547                 .name = "sd_emmc_b_clk0_sel",
2548                 .ops = &clk_regmap_mux_ops,
2549                 .parent_data = g12a_sd_emmc_clk0_parent_data,
2550                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2551                 .flags = CLK_SET_RATE_PARENT,
2552         },
2553 };
2554
2555 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2556         .data = &(struct clk_regmap_div_data){
2557                 .offset = HHI_SD_EMMC_CLK_CNTL,
2558                 .shift = 16,
2559                 .width = 7,
2560         },
2561         .hw.init = &(struct clk_init_data) {
2562                 .name = "sd_emmc_b_clk0_div",
2563                 .ops = &clk_regmap_divider_ops,
2564                 .parent_hws = (const struct clk_hw *[]) {
2565                         &g12a_sd_emmc_b_clk0_sel.hw
2566                 },
2567                 .num_parents = 1,
2568                 .flags = CLK_SET_RATE_PARENT,
2569         },
2570 };
2571
2572 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2573         .data = &(struct clk_regmap_gate_data){
2574                 .offset = HHI_SD_EMMC_CLK_CNTL,
2575                 .bit_idx = 23,
2576         },
2577         .hw.init = &(struct clk_init_data){
2578                 .name = "sd_emmc_b_clk0",
2579                 .ops = &clk_regmap_gate_ops,
2580                 .parent_hws = (const struct clk_hw *[]) {
2581                         &g12a_sd_emmc_b_clk0_div.hw
2582                 },
2583                 .num_parents = 1,
2584                 .flags = CLK_SET_RATE_PARENT,
2585         },
2586 };
2587
2588 /* EMMC/NAND clock */
2589 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2590         .data = &(struct clk_regmap_mux_data){
2591                 .offset = HHI_NAND_CLK_CNTL,
2592                 .mask = 0x7,
2593                 .shift = 9,
2594         },
2595         .hw.init = &(struct clk_init_data) {
2596                 .name = "sd_emmc_c_clk0_sel",
2597                 .ops = &clk_regmap_mux_ops,
2598                 .parent_data = g12a_sd_emmc_clk0_parent_data,
2599                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2600                 .flags = CLK_SET_RATE_PARENT,
2601         },
2602 };
2603
2604 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2605         .data = &(struct clk_regmap_div_data){
2606                 .offset = HHI_NAND_CLK_CNTL,
2607                 .shift = 0,
2608                 .width = 7,
2609         },
2610         .hw.init = &(struct clk_init_data) {
2611                 .name = "sd_emmc_c_clk0_div",
2612                 .ops = &clk_regmap_divider_ops,
2613                 .parent_hws = (const struct clk_hw *[]) {
2614                         &g12a_sd_emmc_c_clk0_sel.hw
2615                 },
2616                 .num_parents = 1,
2617                 .flags = CLK_SET_RATE_PARENT,
2618         },
2619 };
2620
2621 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2622         .data = &(struct clk_regmap_gate_data){
2623                 .offset = HHI_NAND_CLK_CNTL,
2624                 .bit_idx = 7,
2625         },
2626         .hw.init = &(struct clk_init_data){
2627                 .name = "sd_emmc_c_clk0",
2628                 .ops = &clk_regmap_gate_ops,
2629                 .parent_hws = (const struct clk_hw *[]) {
2630                         &g12a_sd_emmc_c_clk0_div.hw
2631                 },
2632                 .num_parents = 1,
2633                 .flags = CLK_SET_RATE_PARENT,
2634         },
2635 };
2636
2637 /* Video Clocks */
2638
2639 static struct clk_regmap g12a_vid_pll_div = {
2640         .data = &(struct meson_vid_pll_div_data){
2641                 .val = {
2642                         .reg_off = HHI_VID_PLL_CLK_DIV,
2643                         .shift   = 0,
2644                         .width   = 15,
2645                 },
2646                 .sel = {
2647                         .reg_off = HHI_VID_PLL_CLK_DIV,
2648                         .shift   = 16,
2649                         .width   = 2,
2650                 },
2651         },
2652         .hw.init = &(struct clk_init_data) {
2653                 .name = "vid_pll_div",
2654                 .ops = &meson_vid_pll_div_ro_ops,
2655                 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2656                 .num_parents = 1,
2657                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2658         },
2659 };
2660
2661 static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2662         &g12a_vid_pll_div.hw,
2663         &g12a_hdmi_pll.hw,
2664 };
2665
2666 static struct clk_regmap g12a_vid_pll_sel = {
2667         .data = &(struct clk_regmap_mux_data){
2668                 .offset = HHI_VID_PLL_CLK_DIV,
2669                 .mask = 0x1,
2670                 .shift = 18,
2671         },
2672         .hw.init = &(struct clk_init_data){
2673                 .name = "vid_pll_sel",
2674                 .ops = &clk_regmap_mux_ops,
2675                 /*
2676                  * bit 18 selects from 2 possible parents:
2677                  * vid_pll_div or hdmi_pll
2678                  */
2679                 .parent_hws = g12a_vid_pll_parent_hws,
2680                 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2681                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2682         },
2683 };
2684
2685 static struct clk_regmap g12a_vid_pll = {
2686         .data = &(struct clk_regmap_gate_data){
2687                 .offset = HHI_VID_PLL_CLK_DIV,
2688                 .bit_idx = 19,
2689         },
2690         .hw.init = &(struct clk_init_data) {
2691                 .name = "vid_pll",
2692                 .ops = &clk_regmap_gate_ops,
2693                 .parent_hws = (const struct clk_hw *[]) {
2694                         &g12a_vid_pll_sel.hw
2695                 },
2696                 .num_parents = 1,
2697                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2698         },
2699 };
2700
2701 /* VPU Clock */
2702
2703 static const struct clk_hw *g12a_vpu_parent_hws[] = {
2704         &g12a_fclk_div3.hw,
2705         &g12a_fclk_div4.hw,
2706         &g12a_fclk_div5.hw,
2707         &g12a_fclk_div7.hw,
2708         &g12a_mpll1.hw,
2709         &g12a_vid_pll.hw,
2710         &g12a_hifi_pll.hw,
2711         &g12a_gp0_pll.hw,
2712 };
2713
2714 static struct clk_regmap g12a_vpu_0_sel = {
2715         .data = &(struct clk_regmap_mux_data){
2716                 .offset = HHI_VPU_CLK_CNTL,
2717                 .mask = 0x7,
2718                 .shift = 9,
2719         },
2720         .hw.init = &(struct clk_init_data){
2721                 .name = "vpu_0_sel",
2722                 .ops = &clk_regmap_mux_ops,
2723                 .parent_hws = g12a_vpu_parent_hws,
2724                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2725                 .flags = CLK_SET_RATE_NO_REPARENT,
2726         },
2727 };
2728
2729 static struct clk_regmap g12a_vpu_0_div = {
2730         .data = &(struct clk_regmap_div_data){
2731                 .offset = HHI_VPU_CLK_CNTL,
2732                 .shift = 0,
2733                 .width = 7,
2734         },
2735         .hw.init = &(struct clk_init_data){
2736                 .name = "vpu_0_div",
2737                 .ops = &clk_regmap_divider_ops,
2738                 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2739                 .num_parents = 1,
2740                 .flags = CLK_SET_RATE_PARENT,
2741         },
2742 };
2743
2744 static struct clk_regmap g12a_vpu_0 = {
2745         .data = &(struct clk_regmap_gate_data){
2746                 .offset = HHI_VPU_CLK_CNTL,
2747                 .bit_idx = 8,
2748         },
2749         .hw.init = &(struct clk_init_data) {
2750                 .name = "vpu_0",
2751                 .ops = &clk_regmap_gate_ops,
2752                 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2753                 .num_parents = 1,
2754                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2755         },
2756 };
2757
2758 static struct clk_regmap g12a_vpu_1_sel = {
2759         .data = &(struct clk_regmap_mux_data){
2760                 .offset = HHI_VPU_CLK_CNTL,
2761                 .mask = 0x7,
2762                 .shift = 25,
2763         },
2764         .hw.init = &(struct clk_init_data){
2765                 .name = "vpu_1_sel",
2766                 .ops = &clk_regmap_mux_ops,
2767                 .parent_hws = g12a_vpu_parent_hws,
2768                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2769                 .flags = CLK_SET_RATE_NO_REPARENT,
2770         },
2771 };
2772
2773 static struct clk_regmap g12a_vpu_1_div = {
2774         .data = &(struct clk_regmap_div_data){
2775                 .offset = HHI_VPU_CLK_CNTL,
2776                 .shift = 16,
2777                 .width = 7,
2778         },
2779         .hw.init = &(struct clk_init_data){
2780                 .name = "vpu_1_div",
2781                 .ops = &clk_regmap_divider_ops,
2782                 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2783                 .num_parents = 1,
2784                 .flags = CLK_SET_RATE_PARENT,
2785         },
2786 };
2787
2788 static struct clk_regmap g12a_vpu_1 = {
2789         .data = &(struct clk_regmap_gate_data){
2790                 .offset = HHI_VPU_CLK_CNTL,
2791                 .bit_idx = 24,
2792         },
2793         .hw.init = &(struct clk_init_data) {
2794                 .name = "vpu_1",
2795                 .ops = &clk_regmap_gate_ops,
2796                 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2797                 .num_parents = 1,
2798                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2799         },
2800 };
2801
2802 static struct clk_regmap g12a_vpu = {
2803         .data = &(struct clk_regmap_mux_data){
2804                 .offset = HHI_VPU_CLK_CNTL,
2805                 .mask = 1,
2806                 .shift = 31,
2807         },
2808         .hw.init = &(struct clk_init_data){
2809                 .name = "vpu",
2810                 .ops = &clk_regmap_mux_ops,
2811                 /*
2812                  * bit 31 selects from 2 possible parents:
2813                  * vpu_0 or vpu_1
2814                  */
2815                 .parent_hws = (const struct clk_hw *[]) {
2816                         &g12a_vpu_0.hw,
2817                         &g12a_vpu_1.hw,
2818                 },
2819                 .num_parents = 2,
2820                 .flags = CLK_SET_RATE_NO_REPARENT,
2821         },
2822 };
2823
2824 /* VDEC clocks */
2825
2826 static const struct clk_hw *g12a_vdec_parent_hws[] = {
2827         &g12a_fclk_div2p5.hw,
2828         &g12a_fclk_div3.hw,
2829         &g12a_fclk_div4.hw,
2830         &g12a_fclk_div5.hw,
2831         &g12a_fclk_div7.hw,
2832         &g12a_hifi_pll.hw,
2833         &g12a_gp0_pll.hw,
2834 };
2835
2836 static struct clk_regmap g12a_vdec_1_sel = {
2837         .data = &(struct clk_regmap_mux_data){
2838                 .offset = HHI_VDEC_CLK_CNTL,
2839                 .mask = 0x7,
2840                 .shift = 9,
2841                 .flags = CLK_MUX_ROUND_CLOSEST,
2842         },
2843         .hw.init = &(struct clk_init_data){
2844                 .name = "vdec_1_sel",
2845                 .ops = &clk_regmap_mux_ops,
2846                 .parent_hws = g12a_vdec_parent_hws,
2847                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2848                 .flags = CLK_SET_RATE_PARENT,
2849         },
2850 };
2851
2852 static struct clk_regmap g12a_vdec_1_div = {
2853         .data = &(struct clk_regmap_div_data){
2854                 .offset = HHI_VDEC_CLK_CNTL,
2855                 .shift = 0,
2856                 .width = 7,
2857                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2858         },
2859         .hw.init = &(struct clk_init_data){
2860                 .name = "vdec_1_div",
2861                 .ops = &clk_regmap_divider_ops,
2862                 .parent_hws = (const struct clk_hw *[]) {
2863                         &g12a_vdec_1_sel.hw
2864                 },
2865                 .num_parents = 1,
2866                 .flags = CLK_SET_RATE_PARENT,
2867         },
2868 };
2869
2870 static struct clk_regmap g12a_vdec_1 = {
2871         .data = &(struct clk_regmap_gate_data){
2872                 .offset = HHI_VDEC_CLK_CNTL,
2873                 .bit_idx = 8,
2874         },
2875         .hw.init = &(struct clk_init_data) {
2876                 .name = "vdec_1",
2877                 .ops = &clk_regmap_gate_ops,
2878                 .parent_hws = (const struct clk_hw *[]) {
2879                         &g12a_vdec_1_div.hw
2880                 },
2881                 .num_parents = 1,
2882                 .flags = CLK_SET_RATE_PARENT,
2883         },
2884 };
2885
2886 static struct clk_regmap g12a_vdec_hevcf_sel = {
2887         .data = &(struct clk_regmap_mux_data){
2888                 .offset = HHI_VDEC2_CLK_CNTL,
2889                 .mask = 0x7,
2890                 .shift = 9,
2891                 .flags = CLK_MUX_ROUND_CLOSEST,
2892         },
2893         .hw.init = &(struct clk_init_data){
2894                 .name = "vdec_hevcf_sel",
2895                 .ops = &clk_regmap_mux_ops,
2896                 .parent_hws = g12a_vdec_parent_hws,
2897                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2898                 .flags = CLK_SET_RATE_PARENT,
2899         },
2900 };
2901
2902 static struct clk_regmap g12a_vdec_hevcf_div = {
2903         .data = &(struct clk_regmap_div_data){
2904                 .offset = HHI_VDEC2_CLK_CNTL,
2905                 .shift = 0,
2906                 .width = 7,
2907                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2908         },
2909         .hw.init = &(struct clk_init_data){
2910                 .name = "vdec_hevcf_div",
2911                 .ops = &clk_regmap_divider_ops,
2912                 .parent_hws = (const struct clk_hw *[]) {
2913                         &g12a_vdec_hevcf_sel.hw
2914                 },
2915                 .num_parents = 1,
2916                 .flags = CLK_SET_RATE_PARENT,
2917         },
2918 };
2919
2920 static struct clk_regmap g12a_vdec_hevcf = {
2921         .data = &(struct clk_regmap_gate_data){
2922                 .offset = HHI_VDEC2_CLK_CNTL,
2923                 .bit_idx = 8,
2924         },
2925         .hw.init = &(struct clk_init_data) {
2926                 .name = "vdec_hevcf",
2927                 .ops = &clk_regmap_gate_ops,
2928                 .parent_hws = (const struct clk_hw *[]) {
2929                         &g12a_vdec_hevcf_div.hw
2930                 },
2931                 .num_parents = 1,
2932                 .flags = CLK_SET_RATE_PARENT,
2933         },
2934 };
2935
2936 static struct clk_regmap g12a_vdec_hevc_sel = {
2937         .data = &(struct clk_regmap_mux_data){
2938                 .offset = HHI_VDEC2_CLK_CNTL,
2939                 .mask = 0x7,
2940                 .shift = 25,
2941                 .flags = CLK_MUX_ROUND_CLOSEST,
2942         },
2943         .hw.init = &(struct clk_init_data){
2944                 .name = "vdec_hevc_sel",
2945                 .ops = &clk_regmap_mux_ops,
2946                 .parent_hws = g12a_vdec_parent_hws,
2947                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2948                 .flags = CLK_SET_RATE_PARENT,
2949         },
2950 };
2951
2952 static struct clk_regmap g12a_vdec_hevc_div = {
2953         .data = &(struct clk_regmap_div_data){
2954                 .offset = HHI_VDEC2_CLK_CNTL,
2955                 .shift = 16,
2956                 .width = 7,
2957                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2958         },
2959         .hw.init = &(struct clk_init_data){
2960                 .name = "vdec_hevc_div",
2961                 .ops = &clk_regmap_divider_ops,
2962                 .parent_hws = (const struct clk_hw *[]) {
2963                         &g12a_vdec_hevc_sel.hw
2964                 },
2965                 .num_parents = 1,
2966                 .flags = CLK_SET_RATE_PARENT,
2967         },
2968 };
2969
2970 static struct clk_regmap g12a_vdec_hevc = {
2971         .data = &(struct clk_regmap_gate_data){
2972                 .offset = HHI_VDEC2_CLK_CNTL,
2973                 .bit_idx = 24,
2974         },
2975         .hw.init = &(struct clk_init_data) {
2976                 .name = "vdec_hevc",
2977                 .ops = &clk_regmap_gate_ops,
2978                 .parent_hws = (const struct clk_hw *[]) {
2979                         &g12a_vdec_hevc_div.hw
2980                 },
2981                 .num_parents = 1,
2982                 .flags = CLK_SET_RATE_PARENT,
2983         },
2984 };
2985
2986 /* VAPB Clock */
2987
2988 static const struct clk_hw *g12a_vapb_parent_hws[] = {
2989         &g12a_fclk_div4.hw,
2990         &g12a_fclk_div3.hw,
2991         &g12a_fclk_div5.hw,
2992         &g12a_fclk_div7.hw,
2993         &g12a_mpll1.hw,
2994         &g12a_vid_pll.hw,
2995         &g12a_mpll2.hw,
2996         &g12a_fclk_div2p5.hw,
2997 };
2998
2999 static struct clk_regmap g12a_vapb_0_sel = {
3000         .data = &(struct clk_regmap_mux_data){
3001                 .offset = HHI_VAPBCLK_CNTL,
3002                 .mask = 0x3,
3003                 .shift = 9,
3004         },
3005         .hw.init = &(struct clk_init_data){
3006                 .name = "vapb_0_sel",
3007                 .ops = &clk_regmap_mux_ops,
3008                 .parent_hws = g12a_vapb_parent_hws,
3009                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3010                 .flags = CLK_SET_RATE_NO_REPARENT,
3011         },
3012 };
3013
3014 static struct clk_regmap g12a_vapb_0_div = {
3015         .data = &(struct clk_regmap_div_data){
3016                 .offset = HHI_VAPBCLK_CNTL,
3017                 .shift = 0,
3018                 .width = 7,
3019         },
3020         .hw.init = &(struct clk_init_data){
3021                 .name = "vapb_0_div",
3022                 .ops = &clk_regmap_divider_ops,
3023                 .parent_hws = (const struct clk_hw *[]) {
3024                         &g12a_vapb_0_sel.hw
3025                 },
3026                 .num_parents = 1,
3027                 .flags = CLK_SET_RATE_PARENT,
3028         },
3029 };
3030
3031 static struct clk_regmap g12a_vapb_0 = {
3032         .data = &(struct clk_regmap_gate_data){
3033                 .offset = HHI_VAPBCLK_CNTL,
3034                 .bit_idx = 8,
3035         },
3036         .hw.init = &(struct clk_init_data) {
3037                 .name = "vapb_0",
3038                 .ops = &clk_regmap_gate_ops,
3039                 .parent_hws = (const struct clk_hw *[]) {
3040                         &g12a_vapb_0_div.hw
3041                 },
3042                 .num_parents = 1,
3043                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3044         },
3045 };
3046
3047 static struct clk_regmap g12a_vapb_1_sel = {
3048         .data = &(struct clk_regmap_mux_data){
3049                 .offset = HHI_VAPBCLK_CNTL,
3050                 .mask = 0x3,
3051                 .shift = 25,
3052         },
3053         .hw.init = &(struct clk_init_data){
3054                 .name = "vapb_1_sel",
3055                 .ops = &clk_regmap_mux_ops,
3056                 .parent_hws = g12a_vapb_parent_hws,
3057                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3058                 .flags = CLK_SET_RATE_NO_REPARENT,
3059         },
3060 };
3061
3062 static struct clk_regmap g12a_vapb_1_div = {
3063         .data = &(struct clk_regmap_div_data){
3064                 .offset = HHI_VAPBCLK_CNTL,
3065                 .shift = 16,
3066                 .width = 7,
3067         },
3068         .hw.init = &(struct clk_init_data){
3069                 .name = "vapb_1_div",
3070                 .ops = &clk_regmap_divider_ops,
3071                 .parent_hws = (const struct clk_hw *[]) {
3072                         &g12a_vapb_1_sel.hw
3073                 },
3074                 .num_parents = 1,
3075                 .flags = CLK_SET_RATE_PARENT,
3076         },
3077 };
3078
3079 static struct clk_regmap g12a_vapb_1 = {
3080         .data = &(struct clk_regmap_gate_data){
3081                 .offset = HHI_VAPBCLK_CNTL,
3082                 .bit_idx = 24,
3083         },
3084         .hw.init = &(struct clk_init_data) {
3085                 .name = "vapb_1",
3086                 .ops = &clk_regmap_gate_ops,
3087                 .parent_hws = (const struct clk_hw *[]) {
3088                         &g12a_vapb_1_div.hw
3089                 },
3090                 .num_parents = 1,
3091                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3092         },
3093 };
3094
3095 static struct clk_regmap g12a_vapb_sel = {
3096         .data = &(struct clk_regmap_mux_data){
3097                 .offset = HHI_VAPBCLK_CNTL,
3098                 .mask = 1,
3099                 .shift = 31,
3100         },
3101         .hw.init = &(struct clk_init_data){
3102                 .name = "vapb_sel",
3103                 .ops = &clk_regmap_mux_ops,
3104                 /*
3105                  * bit 31 selects from 2 possible parents:
3106                  * vapb_0 or vapb_1
3107                  */
3108                 .parent_hws = (const struct clk_hw *[]) {
3109                         &g12a_vapb_0.hw,
3110                         &g12a_vapb_1.hw,
3111                 },
3112                 .num_parents = 2,
3113                 .flags = CLK_SET_RATE_NO_REPARENT,
3114         },
3115 };
3116
3117 static struct clk_regmap g12a_vapb = {
3118         .data = &(struct clk_regmap_gate_data){
3119                 .offset = HHI_VAPBCLK_CNTL,
3120                 .bit_idx = 30,
3121         },
3122         .hw.init = &(struct clk_init_data) {
3123                 .name = "vapb",
3124                 .ops = &clk_regmap_gate_ops,
3125                 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3126                 .num_parents = 1,
3127                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3128         },
3129 };
3130
3131 static const struct clk_hw *g12a_vclk_parent_hws[] = {
3132         &g12a_vid_pll.hw,
3133         &g12a_gp0_pll.hw,
3134         &g12a_hifi_pll.hw,
3135         &g12a_mpll1.hw,
3136         &g12a_fclk_div3.hw,
3137         &g12a_fclk_div4.hw,
3138         &g12a_fclk_div5.hw,
3139         &g12a_fclk_div7.hw,
3140 };
3141
3142 static struct clk_regmap g12a_vclk_sel = {
3143         .data = &(struct clk_regmap_mux_data){
3144                 .offset = HHI_VID_CLK_CNTL,
3145                 .mask = 0x7,
3146                 .shift = 16,
3147         },
3148         .hw.init = &(struct clk_init_data){
3149                 .name = "vclk_sel",
3150                 .ops = &clk_regmap_mux_ops,
3151                 .parent_hws = g12a_vclk_parent_hws,
3152                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3153                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3154         },
3155 };
3156
3157 static struct clk_regmap g12a_vclk2_sel = {
3158         .data = &(struct clk_regmap_mux_data){
3159                 .offset = HHI_VIID_CLK_CNTL,
3160                 .mask = 0x7,
3161                 .shift = 16,
3162         },
3163         .hw.init = &(struct clk_init_data){
3164                 .name = "vclk2_sel",
3165                 .ops = &clk_regmap_mux_ops,
3166                 .parent_hws = g12a_vclk_parent_hws,
3167                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3168                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3169         },
3170 };
3171
3172 static struct clk_regmap g12a_vclk_input = {
3173         .data = &(struct clk_regmap_gate_data){
3174                 .offset = HHI_VID_CLK_DIV,
3175                 .bit_idx = 16,
3176         },
3177         .hw.init = &(struct clk_init_data) {
3178                 .name = "vclk_input",
3179                 .ops = &clk_regmap_gate_ops,
3180                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3181                 .num_parents = 1,
3182                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3183         },
3184 };
3185
3186 static struct clk_regmap g12a_vclk2_input = {
3187         .data = &(struct clk_regmap_gate_data){
3188                 .offset = HHI_VIID_CLK_DIV,
3189                 .bit_idx = 16,
3190         },
3191         .hw.init = &(struct clk_init_data) {
3192                 .name = "vclk2_input",
3193                 .ops = &clk_regmap_gate_ops,
3194                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3195                 .num_parents = 1,
3196                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3197         },
3198 };
3199
3200 static struct clk_regmap g12a_vclk_div = {
3201         .data = &(struct clk_regmap_div_data){
3202                 .offset = HHI_VID_CLK_DIV,
3203                 .shift = 0,
3204                 .width = 8,
3205         },
3206         .hw.init = &(struct clk_init_data){
3207                 .name = "vclk_div",
3208                 .ops = &clk_regmap_divider_ops,
3209                 .parent_hws = (const struct clk_hw *[]) {
3210                         &g12a_vclk_input.hw
3211                 },
3212                 .num_parents = 1,
3213                 .flags = CLK_GET_RATE_NOCACHE,
3214         },
3215 };
3216
3217 static struct clk_regmap g12a_vclk2_div = {
3218         .data = &(struct clk_regmap_div_data){
3219                 .offset = HHI_VIID_CLK_DIV,
3220                 .shift = 0,
3221                 .width = 8,
3222         },
3223         .hw.init = &(struct clk_init_data){
3224                 .name = "vclk2_div",
3225                 .ops = &clk_regmap_divider_ops,
3226                 .parent_hws = (const struct clk_hw *[]) {
3227                         &g12a_vclk2_input.hw
3228                 },
3229                 .num_parents = 1,
3230                 .flags = CLK_GET_RATE_NOCACHE,
3231         },
3232 };
3233
3234 static struct clk_regmap g12a_vclk = {
3235         .data = &(struct clk_regmap_gate_data){
3236                 .offset = HHI_VID_CLK_CNTL,
3237                 .bit_idx = 19,
3238         },
3239         .hw.init = &(struct clk_init_data) {
3240                 .name = "vclk",
3241                 .ops = &clk_regmap_gate_ops,
3242                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3243                 .num_parents = 1,
3244                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3245         },
3246 };
3247
3248 static struct clk_regmap g12a_vclk2 = {
3249         .data = &(struct clk_regmap_gate_data){
3250                 .offset = HHI_VIID_CLK_CNTL,
3251                 .bit_idx = 19,
3252         },
3253         .hw.init = &(struct clk_init_data) {
3254                 .name = "vclk2",
3255                 .ops = &clk_regmap_gate_ops,
3256                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3257                 .num_parents = 1,
3258                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3259         },
3260 };
3261
3262 static struct clk_regmap g12a_vclk_div1 = {
3263         .data = &(struct clk_regmap_gate_data){
3264                 .offset = HHI_VID_CLK_CNTL,
3265                 .bit_idx = 0,
3266         },
3267         .hw.init = &(struct clk_init_data) {
3268                 .name = "vclk_div1",
3269                 .ops = &clk_regmap_gate_ops,
3270                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3271                 .num_parents = 1,
3272                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3273         },
3274 };
3275
3276 static struct clk_regmap g12a_vclk_div2_en = {
3277         .data = &(struct clk_regmap_gate_data){
3278                 .offset = HHI_VID_CLK_CNTL,
3279                 .bit_idx = 1,
3280         },
3281         .hw.init = &(struct clk_init_data) {
3282                 .name = "vclk_div2_en",
3283                 .ops = &clk_regmap_gate_ops,
3284                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3285                 .num_parents = 1,
3286                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3287         },
3288 };
3289
3290 static struct clk_regmap g12a_vclk_div4_en = {
3291         .data = &(struct clk_regmap_gate_data){
3292                 .offset = HHI_VID_CLK_CNTL,
3293                 .bit_idx = 2,
3294         },
3295         .hw.init = &(struct clk_init_data) {
3296                 .name = "vclk_div4_en",
3297                 .ops = &clk_regmap_gate_ops,
3298                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3299                 .num_parents = 1,
3300                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3301         },
3302 };
3303
3304 static struct clk_regmap g12a_vclk_div6_en = {
3305         .data = &(struct clk_regmap_gate_data){
3306                 .offset = HHI_VID_CLK_CNTL,
3307                 .bit_idx = 3,
3308         },
3309         .hw.init = &(struct clk_init_data) {
3310                 .name = "vclk_div6_en",
3311                 .ops = &clk_regmap_gate_ops,
3312                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3313                 .num_parents = 1,
3314                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3315         },
3316 };
3317
3318 static struct clk_regmap g12a_vclk_div12_en = {
3319         .data = &(struct clk_regmap_gate_data){
3320                 .offset = HHI_VID_CLK_CNTL,
3321                 .bit_idx = 4,
3322         },
3323         .hw.init = &(struct clk_init_data) {
3324                 .name = "vclk_div12_en",
3325                 .ops = &clk_regmap_gate_ops,
3326                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3327                 .num_parents = 1,
3328                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3329         },
3330 };
3331
3332 static struct clk_regmap g12a_vclk2_div1 = {
3333         .data = &(struct clk_regmap_gate_data){
3334                 .offset = HHI_VIID_CLK_CNTL,
3335                 .bit_idx = 0,
3336         },
3337         .hw.init = &(struct clk_init_data) {
3338                 .name = "vclk2_div1",
3339                 .ops = &clk_regmap_gate_ops,
3340                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3341                 .num_parents = 1,
3342                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3343         },
3344 };
3345
3346 static struct clk_regmap g12a_vclk2_div2_en = {
3347         .data = &(struct clk_regmap_gate_data){
3348                 .offset = HHI_VIID_CLK_CNTL,
3349                 .bit_idx = 1,
3350         },
3351         .hw.init = &(struct clk_init_data) {
3352                 .name = "vclk2_div2_en",
3353                 .ops = &clk_regmap_gate_ops,
3354                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3355                 .num_parents = 1,
3356                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3357         },
3358 };
3359
3360 static struct clk_regmap g12a_vclk2_div4_en = {
3361         .data = &(struct clk_regmap_gate_data){
3362                 .offset = HHI_VIID_CLK_CNTL,
3363                 .bit_idx = 2,
3364         },
3365         .hw.init = &(struct clk_init_data) {
3366                 .name = "vclk2_div4_en",
3367                 .ops = &clk_regmap_gate_ops,
3368                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3369                 .num_parents = 1,
3370                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3371         },
3372 };
3373
3374 static struct clk_regmap g12a_vclk2_div6_en = {
3375         .data = &(struct clk_regmap_gate_data){
3376                 .offset = HHI_VIID_CLK_CNTL,
3377                 .bit_idx = 3,
3378         },
3379         .hw.init = &(struct clk_init_data) {
3380                 .name = "vclk2_div6_en",
3381                 .ops = &clk_regmap_gate_ops,
3382                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3383                 .num_parents = 1,
3384                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3385         },
3386 };
3387
3388 static struct clk_regmap g12a_vclk2_div12_en = {
3389         .data = &(struct clk_regmap_gate_data){
3390                 .offset = HHI_VIID_CLK_CNTL,
3391                 .bit_idx = 4,
3392         },
3393         .hw.init = &(struct clk_init_data) {
3394                 .name = "vclk2_div12_en",
3395                 .ops = &clk_regmap_gate_ops,
3396                 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3397                 .num_parents = 1,
3398                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3399         },
3400 };
3401
3402 static struct clk_fixed_factor g12a_vclk_div2 = {
3403         .mult = 1,
3404         .div = 2,
3405         .hw.init = &(struct clk_init_data){
3406                 .name = "vclk_div2",
3407                 .ops = &clk_fixed_factor_ops,
3408                 .parent_hws = (const struct clk_hw *[]) {
3409                         &g12a_vclk_div2_en.hw
3410                 },
3411                 .num_parents = 1,
3412         },
3413 };
3414
3415 static struct clk_fixed_factor g12a_vclk_div4 = {
3416         .mult = 1,
3417         .div = 4,
3418         .hw.init = &(struct clk_init_data){
3419                 .name = "vclk_div4",
3420                 .ops = &clk_fixed_factor_ops,
3421                 .parent_hws = (const struct clk_hw *[]) {
3422                         &g12a_vclk_div4_en.hw
3423                 },
3424                 .num_parents = 1,
3425         },
3426 };
3427
3428 static struct clk_fixed_factor g12a_vclk_div6 = {
3429         .mult = 1,
3430         .div = 6,
3431         .hw.init = &(struct clk_init_data){
3432                 .name = "vclk_div6",
3433                 .ops = &clk_fixed_factor_ops,
3434                 .parent_hws = (const struct clk_hw *[]) {
3435                         &g12a_vclk_div6_en.hw
3436                 },
3437                 .num_parents = 1,
3438         },
3439 };
3440
3441 static struct clk_fixed_factor g12a_vclk_div12 = {
3442         .mult = 1,
3443         .div = 12,
3444         .hw.init = &(struct clk_init_data){
3445                 .name = "vclk_div12",
3446                 .ops = &clk_fixed_factor_ops,
3447                 .parent_hws = (const struct clk_hw *[]) {
3448                         &g12a_vclk_div12_en.hw
3449                 },
3450                 .num_parents = 1,
3451         },
3452 };
3453
3454 static struct clk_fixed_factor g12a_vclk2_div2 = {
3455         .mult = 1,
3456         .div = 2,
3457         .hw.init = &(struct clk_init_data){
3458                 .name = "vclk2_div2",
3459                 .ops = &clk_fixed_factor_ops,
3460                 .parent_hws = (const struct clk_hw *[]) {
3461                         &g12a_vclk2_div2_en.hw
3462                 },
3463                 .num_parents = 1,
3464         },
3465 };
3466
3467 static struct clk_fixed_factor g12a_vclk2_div4 = {
3468         .mult = 1,
3469         .div = 4,
3470         .hw.init = &(struct clk_init_data){
3471                 .name = "vclk2_div4",
3472                 .ops = &clk_fixed_factor_ops,
3473                 .parent_hws = (const struct clk_hw *[]) {
3474                         &g12a_vclk2_div4_en.hw
3475                 },
3476                 .num_parents = 1,
3477         },
3478 };
3479
3480 static struct clk_fixed_factor g12a_vclk2_div6 = {
3481         .mult = 1,
3482         .div = 6,
3483         .hw.init = &(struct clk_init_data){
3484                 .name = "vclk2_div6",
3485                 .ops = &clk_fixed_factor_ops,
3486                 .parent_hws = (const struct clk_hw *[]) {
3487                         &g12a_vclk2_div6_en.hw
3488                 },
3489                 .num_parents = 1,
3490         },
3491 };
3492
3493 static struct clk_fixed_factor g12a_vclk2_div12 = {
3494         .mult = 1,
3495         .div = 12,
3496         .hw.init = &(struct clk_init_data){
3497                 .name = "vclk2_div12",
3498                 .ops = &clk_fixed_factor_ops,
3499                 .parent_hws = (const struct clk_hw *[]) {
3500                         &g12a_vclk2_div12_en.hw
3501                 },
3502                 .num_parents = 1,
3503         },
3504 };
3505
3506 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3507 static const struct clk_hw *g12a_cts_parent_hws[] = {
3508         &g12a_vclk_div1.hw,
3509         &g12a_vclk_div2.hw,
3510         &g12a_vclk_div4.hw,
3511         &g12a_vclk_div6.hw,
3512         &g12a_vclk_div12.hw,
3513         &g12a_vclk2_div1.hw,
3514         &g12a_vclk2_div2.hw,
3515         &g12a_vclk2_div4.hw,
3516         &g12a_vclk2_div6.hw,
3517         &g12a_vclk2_div12.hw,
3518 };
3519
3520 static struct clk_regmap g12a_cts_enci_sel = {
3521         .data = &(struct clk_regmap_mux_data){
3522                 .offset = HHI_VID_CLK_DIV,
3523                 .mask = 0xf,
3524                 .shift = 28,
3525                 .table = mux_table_cts_sel,
3526         },
3527         .hw.init = &(struct clk_init_data){
3528                 .name = "cts_enci_sel",
3529                 .ops = &clk_regmap_mux_ops,
3530                 .parent_hws = g12a_cts_parent_hws,
3531                 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3532                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3533         },
3534 };
3535
3536 static struct clk_regmap g12a_cts_encp_sel = {
3537         .data = &(struct clk_regmap_mux_data){
3538                 .offset = HHI_VID_CLK_DIV,
3539                 .mask = 0xf,
3540                 .shift = 20,
3541                 .table = mux_table_cts_sel,
3542         },
3543         .hw.init = &(struct clk_init_data){
3544                 .name = "cts_encp_sel",
3545                 .ops = &clk_regmap_mux_ops,
3546                 .parent_hws = g12a_cts_parent_hws,
3547                 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3548                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3549         },
3550 };
3551
3552 static struct clk_regmap g12a_cts_encl_sel = {
3553         .data = &(struct clk_regmap_mux_data){
3554                 .offset = HHI_VIID_CLK_DIV,
3555                 .mask = 0xf,
3556                 .shift = 12,
3557                 .table = mux_table_cts_sel,
3558         },
3559         .hw.init = &(struct clk_init_data){
3560                 .name = "cts_encl_sel",
3561                 .ops = &clk_regmap_mux_ops,
3562                 .parent_hws = g12a_cts_parent_hws,
3563                 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3564                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3565         },
3566 };
3567
3568 static struct clk_regmap g12a_cts_vdac_sel = {
3569         .data = &(struct clk_regmap_mux_data){
3570                 .offset = HHI_VIID_CLK_DIV,
3571                 .mask = 0xf,
3572                 .shift = 28,
3573                 .table = mux_table_cts_sel,
3574         },
3575         .hw.init = &(struct clk_init_data){
3576                 .name = "cts_vdac_sel",
3577                 .ops = &clk_regmap_mux_ops,
3578                 .parent_hws = g12a_cts_parent_hws,
3579                 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3580                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3581         },
3582 };
3583
3584 /* TOFIX: add support for cts_tcon */
3585 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3586 static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3587         &g12a_vclk_div1.hw,
3588         &g12a_vclk_div2.hw,
3589         &g12a_vclk_div4.hw,
3590         &g12a_vclk_div6.hw,
3591         &g12a_vclk_div12.hw,
3592         &g12a_vclk2_div1.hw,
3593         &g12a_vclk2_div2.hw,
3594         &g12a_vclk2_div4.hw,
3595         &g12a_vclk2_div6.hw,
3596         &g12a_vclk2_div12.hw,
3597 };
3598
3599 static struct clk_regmap g12a_hdmi_tx_sel = {
3600         .data = &(struct clk_regmap_mux_data){
3601                 .offset = HHI_HDMI_CLK_CNTL,
3602                 .mask = 0xf,
3603                 .shift = 16,
3604                 .table = mux_table_hdmi_tx_sel,
3605         },
3606         .hw.init = &(struct clk_init_data){
3607                 .name = "hdmi_tx_sel",
3608                 .ops = &clk_regmap_mux_ops,
3609                 .parent_hws = g12a_cts_hdmi_tx_parent_hws,
3610                 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3611                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3612         },
3613 };
3614
3615 static struct clk_regmap g12a_cts_enci = {
3616         .data = &(struct clk_regmap_gate_data){
3617                 .offset = HHI_VID_CLK_CNTL2,
3618                 .bit_idx = 0,
3619         },
3620         .hw.init = &(struct clk_init_data) {
3621                 .name = "cts_enci",
3622                 .ops = &clk_regmap_gate_ops,
3623                 .parent_hws = (const struct clk_hw *[]) {
3624                         &g12a_cts_enci_sel.hw
3625                 },
3626                 .num_parents = 1,
3627                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3628         },
3629 };
3630
3631 static struct clk_regmap g12a_cts_encp = {
3632         .data = &(struct clk_regmap_gate_data){
3633                 .offset = HHI_VID_CLK_CNTL2,
3634                 .bit_idx = 2,
3635         },
3636         .hw.init = &(struct clk_init_data) {
3637                 .name = "cts_encp",
3638                 .ops = &clk_regmap_gate_ops,
3639                 .parent_hws = (const struct clk_hw *[]) {
3640                         &g12a_cts_encp_sel.hw
3641                 },
3642                 .num_parents = 1,
3643                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3644         },
3645 };
3646
3647 static struct clk_regmap g12a_cts_encl = {
3648         .data = &(struct clk_regmap_gate_data){
3649                 .offset = HHI_VID_CLK_CNTL2,
3650                 .bit_idx = 3,
3651         },
3652         .hw.init = &(struct clk_init_data) {
3653                 .name = "cts_encl",
3654                 .ops = &clk_regmap_gate_ops,
3655                 .parent_hws = (const struct clk_hw *[]) {
3656                         &g12a_cts_encl_sel.hw
3657                 },
3658                 .num_parents = 1,
3659                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3660         },
3661 };
3662
3663 static struct clk_regmap g12a_cts_vdac = {
3664         .data = &(struct clk_regmap_gate_data){
3665                 .offset = HHI_VID_CLK_CNTL2,
3666                 .bit_idx = 4,
3667         },
3668         .hw.init = &(struct clk_init_data) {
3669                 .name = "cts_vdac",
3670                 .ops = &clk_regmap_gate_ops,
3671                 .parent_hws = (const struct clk_hw *[]) {
3672                         &g12a_cts_vdac_sel.hw
3673                 },
3674                 .num_parents = 1,
3675                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3676         },
3677 };
3678
3679 static struct clk_regmap g12a_hdmi_tx = {
3680         .data = &(struct clk_regmap_gate_data){
3681                 .offset = HHI_VID_CLK_CNTL2,
3682                 .bit_idx = 5,
3683         },
3684         .hw.init = &(struct clk_init_data) {
3685                 .name = "hdmi_tx",
3686                 .ops = &clk_regmap_gate_ops,
3687                 .parent_hws = (const struct clk_hw *[]) {
3688                         &g12a_hdmi_tx_sel.hw
3689                 },
3690                 .num_parents = 1,
3691                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3692         },
3693 };
3694
3695 /* MIPI DSI Host Clocks */
3696
3697 static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
3698         &g12a_vid_pll.hw,
3699         &g12a_gp0_pll.hw,
3700         &g12a_hifi_pll.hw,
3701         &g12a_mpll1.hw,
3702         &g12a_fclk_div2.hw,
3703         &g12a_fclk_div2p5.hw,
3704         &g12a_fclk_div3.hw,
3705         &g12a_fclk_div7.hw,
3706 };
3707
3708 static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
3709         .data = &(struct clk_regmap_mux_data){
3710                 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3711                 .mask = 0x7,
3712                 .shift = 12,
3713                 .flags = CLK_MUX_ROUND_CLOSEST,
3714         },
3715         .hw.init = &(struct clk_init_data){
3716                 .name = "mipi_dsi_pxclk_sel",
3717                 .ops = &clk_regmap_mux_ops,
3718                 .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3719                 .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3720                 .flags = CLK_SET_RATE_NO_REPARENT,
3721         },
3722 };
3723
3724 static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
3725         .data = &(struct clk_regmap_div_data){
3726                 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3727                 .shift = 0,
3728                 .width = 7,
3729         },
3730         .hw.init = &(struct clk_init_data){
3731                 .name = "mipi_dsi_pxclk_div",
3732                 .ops = &clk_regmap_divider_ops,
3733                 .parent_hws = (const struct clk_hw *[]) {
3734                         &g12a_mipi_dsi_pxclk_sel.hw
3735                 },
3736                 .num_parents = 1,
3737                 .flags = CLK_SET_RATE_PARENT,
3738         },
3739 };
3740
3741 static struct clk_regmap g12a_mipi_dsi_pxclk = {
3742         .data = &(struct clk_regmap_gate_data){
3743                 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3744                 .bit_idx = 8,
3745         },
3746         .hw.init = &(struct clk_init_data) {
3747                 .name = "mipi_dsi_pxclk",
3748                 .ops = &clk_regmap_gate_ops,
3749                 .parent_hws = (const struct clk_hw *[]) {
3750                         &g12a_mipi_dsi_pxclk_div.hw
3751                 },
3752                 .num_parents = 1,
3753                 .flags = CLK_SET_RATE_PARENT,
3754         },
3755 };
3756
3757 /* MIPI ISP Clocks */
3758
3759 static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
3760         { .fw_name = "xtal", },
3761         { .hw = &g12a_gp0_pll.hw },
3762         { .hw = &g12a_hifi_pll.hw },
3763         { .hw = &g12a_fclk_div2p5.hw },
3764         { .hw = &g12a_fclk_div3.hw },
3765         { .hw = &g12a_fclk_div4.hw },
3766         { .hw = &g12a_fclk_div5.hw },
3767         { .hw = &g12a_fclk_div7.hw },
3768 };
3769
3770 static struct clk_regmap g12b_mipi_isp_sel = {
3771         .data = &(struct clk_regmap_mux_data){
3772                 .offset = HHI_ISP_CLK_CNTL,
3773                 .mask = 7,
3774                 .shift = 9,
3775         },
3776         .hw.init = &(struct clk_init_data){
3777                 .name = "mipi_isp_sel",
3778                 .ops = &clk_regmap_mux_ops,
3779                 .parent_data = g12b_mipi_isp_parent_data,
3780                 .num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
3781         },
3782 };
3783
3784 static struct clk_regmap g12b_mipi_isp_div = {
3785         .data = &(struct clk_regmap_div_data){
3786                 .offset = HHI_ISP_CLK_CNTL,
3787                 .shift = 0,
3788                 .width = 7,
3789         },
3790         .hw.init = &(struct clk_init_data){
3791                 .name = "mipi_isp_div",
3792                 .ops = &clk_regmap_divider_ops,
3793                 .parent_hws = (const struct clk_hw *[]) {
3794                         &g12b_mipi_isp_sel.hw
3795                 },
3796                 .num_parents = 1,
3797                 .flags = CLK_SET_RATE_PARENT,
3798         },
3799 };
3800
3801 static struct clk_regmap g12b_mipi_isp = {
3802         .data = &(struct clk_regmap_gate_data){
3803                 .offset = HHI_ISP_CLK_CNTL,
3804                 .bit_idx = 8,
3805         },
3806         .hw.init = &(struct clk_init_data) {
3807                 .name = "mipi_isp",
3808                 .ops = &clk_regmap_gate_ops,
3809                 .parent_hws = (const struct clk_hw *[]) {
3810                         &g12b_mipi_isp_div.hw
3811                 },
3812                 .num_parents = 1,
3813                 .flags = CLK_SET_RATE_PARENT,
3814         },
3815 };
3816
3817 /* HDMI Clocks */
3818
3819 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3820         { .fw_name = "xtal", },
3821         { .hw = &g12a_fclk_div4.hw },
3822         { .hw = &g12a_fclk_div3.hw },
3823         { .hw = &g12a_fclk_div5.hw },
3824 };
3825
3826 static struct clk_regmap g12a_hdmi_sel = {
3827         .data = &(struct clk_regmap_mux_data){
3828                 .offset = HHI_HDMI_CLK_CNTL,
3829                 .mask = 0x3,
3830                 .shift = 9,
3831                 .flags = CLK_MUX_ROUND_CLOSEST,
3832         },
3833         .hw.init = &(struct clk_init_data){
3834                 .name = "hdmi_sel",
3835                 .ops = &clk_regmap_mux_ops,
3836                 .parent_data = g12a_hdmi_parent_data,
3837                 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3838                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3839         },
3840 };
3841
3842 static struct clk_regmap g12a_hdmi_div = {
3843         .data = &(struct clk_regmap_div_data){
3844                 .offset = HHI_HDMI_CLK_CNTL,
3845                 .shift = 0,
3846                 .width = 7,
3847         },
3848         .hw.init = &(struct clk_init_data){
3849                 .name = "hdmi_div",
3850                 .ops = &clk_regmap_divider_ops,
3851                 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3852                 .num_parents = 1,
3853                 .flags = CLK_GET_RATE_NOCACHE,
3854         },
3855 };
3856
3857 static struct clk_regmap g12a_hdmi = {
3858         .data = &(struct clk_regmap_gate_data){
3859                 .offset = HHI_HDMI_CLK_CNTL,
3860                 .bit_idx = 8,
3861         },
3862         .hw.init = &(struct clk_init_data) {
3863                 .name = "hdmi",
3864                 .ops = &clk_regmap_gate_ops,
3865                 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3866                 .num_parents = 1,
3867                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3868         },
3869 };
3870
3871 /*
3872  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3873  * muxed by a glitch-free switch. The CCF can manage this glitch-free
3874  * mux because it does top-to-bottom updates the each clock tree and
3875  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
3876  */
3877 static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3878         { .fw_name = "xtal", },
3879         { .hw = &g12a_gp0_pll.hw },
3880         { .hw = &g12a_hifi_pll.hw },
3881         { .hw = &g12a_fclk_div2p5.hw },
3882         { .hw = &g12a_fclk_div3.hw },
3883         { .hw = &g12a_fclk_div4.hw },
3884         { .hw = &g12a_fclk_div5.hw },
3885         { .hw = &g12a_fclk_div7.hw },
3886 };
3887
3888 static struct clk_regmap g12a_mali_0_sel = {
3889         .data = &(struct clk_regmap_mux_data){
3890                 .offset = HHI_MALI_CLK_CNTL,
3891                 .mask = 0x7,
3892                 .shift = 9,
3893         },
3894         .hw.init = &(struct clk_init_data){
3895                 .name = "mali_0_sel",
3896                 .ops = &clk_regmap_mux_ops,
3897                 .parent_data = g12a_mali_0_1_parent_data,
3898                 .num_parents = 8,
3899                 /*
3900                  * Don't request the parent to change the rate because
3901                  * all GPU frequencies can be derived from the fclk_*
3902                  * clocks and one special GP0_PLL setting. This is
3903                  * important because we need the MPLL clocks for audio.
3904                  */
3905                 .flags = 0,
3906         },
3907 };
3908
3909 static struct clk_regmap g12a_mali_0_div = {
3910         .data = &(struct clk_regmap_div_data){
3911                 .offset = HHI_MALI_CLK_CNTL,
3912                 .shift = 0,
3913                 .width = 7,
3914         },
3915         .hw.init = &(struct clk_init_data){
3916                 .name = "mali_0_div",
3917                 .ops = &clk_regmap_divider_ops,
3918                 .parent_hws = (const struct clk_hw *[]) {
3919                         &g12a_mali_0_sel.hw
3920                 },
3921                 .num_parents = 1,
3922                 .flags = CLK_SET_RATE_PARENT,
3923         },
3924 };
3925
3926 static struct clk_regmap g12a_mali_0 = {
3927         .data = &(struct clk_regmap_gate_data){
3928                 .offset = HHI_MALI_CLK_CNTL,
3929                 .bit_idx = 8,
3930         },
3931         .hw.init = &(struct clk_init_data){
3932                 .name = "mali_0",
3933                 .ops = &clk_regmap_gate_ops,
3934                 .parent_hws = (const struct clk_hw *[]) {
3935                         &g12a_mali_0_div.hw
3936                 },
3937                 .num_parents = 1,
3938                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3939         },
3940 };
3941
3942 static struct clk_regmap g12a_mali_1_sel = {
3943         .data = &(struct clk_regmap_mux_data){
3944                 .offset = HHI_MALI_CLK_CNTL,
3945                 .mask = 0x7,
3946                 .shift = 25,
3947         },
3948         .hw.init = &(struct clk_init_data){
3949                 .name = "mali_1_sel",
3950                 .ops = &clk_regmap_mux_ops,
3951                 .parent_data = g12a_mali_0_1_parent_data,
3952                 .num_parents = 8,
3953                 /*
3954                  * Don't request the parent to change the rate because
3955                  * all GPU frequencies can be derived from the fclk_*
3956                  * clocks and one special GP0_PLL setting. This is
3957                  * important because we need the MPLL clocks for audio.
3958                  */
3959                 .flags = 0,
3960         },
3961 };
3962
3963 static struct clk_regmap g12a_mali_1_div = {
3964         .data = &(struct clk_regmap_div_data){
3965                 .offset = HHI_MALI_CLK_CNTL,
3966                 .shift = 16,
3967                 .width = 7,
3968         },
3969         .hw.init = &(struct clk_init_data){
3970                 .name = "mali_1_div",
3971                 .ops = &clk_regmap_divider_ops,
3972                 .parent_hws = (const struct clk_hw *[]) {
3973                         &g12a_mali_1_sel.hw
3974                 },
3975                 .num_parents = 1,
3976                 .flags = CLK_SET_RATE_PARENT,
3977         },
3978 };
3979
3980 static struct clk_regmap g12a_mali_1 = {
3981         .data = &(struct clk_regmap_gate_data){
3982                 .offset = HHI_MALI_CLK_CNTL,
3983                 .bit_idx = 24,
3984         },
3985         .hw.init = &(struct clk_init_data){
3986                 .name = "mali_1",
3987                 .ops = &clk_regmap_gate_ops,
3988                 .parent_hws = (const struct clk_hw *[]) {
3989                         &g12a_mali_1_div.hw
3990                 },
3991                 .num_parents = 1,
3992                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3993         },
3994 };
3995
3996 static const struct clk_hw *g12a_mali_parent_hws[] = {
3997         &g12a_mali_0.hw,
3998         &g12a_mali_1.hw,
3999 };
4000
4001 static struct clk_regmap g12a_mali = {
4002         .data = &(struct clk_regmap_mux_data){
4003                 .offset = HHI_MALI_CLK_CNTL,
4004                 .mask = 1,
4005                 .shift = 31,
4006         },
4007         .hw.init = &(struct clk_init_data){
4008                 .name = "mali",
4009                 .ops = &clk_regmap_mux_ops,
4010                 .parent_hws = g12a_mali_parent_hws,
4011                 .num_parents = 2,
4012                 .flags = CLK_SET_RATE_PARENT,
4013         },
4014 };
4015
4016 static struct clk_regmap g12a_ts_div = {
4017         .data = &(struct clk_regmap_div_data){
4018                 .offset = HHI_TS_CLK_CNTL,
4019                 .shift = 0,
4020                 .width = 8,
4021         },
4022         .hw.init = &(struct clk_init_data){
4023                 .name = "ts_div",
4024                 .ops = &clk_regmap_divider_ro_ops,
4025                 .parent_data = &(const struct clk_parent_data) {
4026                         .fw_name = "xtal",
4027                 },
4028                 .num_parents = 1,
4029         },
4030 };
4031
4032 static struct clk_regmap g12a_ts = {
4033         .data = &(struct clk_regmap_gate_data){
4034                 .offset = HHI_TS_CLK_CNTL,
4035                 .bit_idx = 8,
4036         },
4037         .hw.init = &(struct clk_init_data){
4038                 .name = "ts",
4039                 .ops = &clk_regmap_gate_ops,
4040                 .parent_hws = (const struct clk_hw *[]) {
4041                         &g12a_ts_div.hw
4042                 },
4043                 .num_parents = 1,
4044         },
4045 };
4046
4047 /* SPICC SCLK source clock */
4048
4049 static const struct clk_parent_data spicc_sclk_parent_data[] = {
4050         { .fw_name = "xtal", },
4051         { .hw = &g12a_clk81.hw },
4052         { .hw = &g12a_fclk_div4.hw },
4053         { .hw = &g12a_fclk_div3.hw },
4054         { .hw = &g12a_fclk_div5.hw },
4055         { .hw = &g12a_fclk_div7.hw },
4056 };
4057
4058 static struct clk_regmap g12a_spicc0_sclk_sel = {
4059         .data = &(struct clk_regmap_mux_data){
4060                 .offset = HHI_SPICC_CLK_CNTL,
4061                 .mask = 7,
4062                 .shift = 7,
4063         },
4064         .hw.init = &(struct clk_init_data){
4065                 .name = "spicc0_sclk_sel",
4066                 .ops = &clk_regmap_mux_ops,
4067                 .parent_data = spicc_sclk_parent_data,
4068                 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4069         },
4070 };
4071
4072 static struct clk_regmap g12a_spicc0_sclk_div = {
4073         .data = &(struct clk_regmap_div_data){
4074                 .offset = HHI_SPICC_CLK_CNTL,
4075                 .shift = 0,
4076                 .width = 6,
4077         },
4078         .hw.init = &(struct clk_init_data){
4079                 .name = "spicc0_sclk_div",
4080                 .ops = &clk_regmap_divider_ops,
4081                 .parent_hws = (const struct clk_hw *[]) {
4082                         &g12a_spicc0_sclk_sel.hw
4083                 },
4084                 .num_parents = 1,
4085                 .flags = CLK_SET_RATE_PARENT,
4086         },
4087 };
4088
4089 static struct clk_regmap g12a_spicc0_sclk = {
4090         .data = &(struct clk_regmap_gate_data){
4091                 .offset = HHI_SPICC_CLK_CNTL,
4092                 .bit_idx = 6,
4093         },
4094         .hw.init = &(struct clk_init_data){
4095                 .name = "spicc0_sclk",
4096                 .ops = &clk_regmap_gate_ops,
4097                 .parent_hws = (const struct clk_hw *[]) {
4098                         &g12a_spicc0_sclk_div.hw
4099                 },
4100                 .num_parents = 1,
4101                 .flags = CLK_SET_RATE_PARENT,
4102         },
4103 };
4104
4105 static struct clk_regmap g12a_spicc1_sclk_sel = {
4106         .data = &(struct clk_regmap_mux_data){
4107                 .offset = HHI_SPICC_CLK_CNTL,
4108                 .mask = 7,
4109                 .shift = 23,
4110         },
4111         .hw.init = &(struct clk_init_data){
4112                 .name = "spicc1_sclk_sel",
4113                 .ops = &clk_regmap_mux_ops,
4114                 .parent_data = spicc_sclk_parent_data,
4115                 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4116         },
4117 };
4118
4119 static struct clk_regmap g12a_spicc1_sclk_div = {
4120         .data = &(struct clk_regmap_div_data){
4121                 .offset = HHI_SPICC_CLK_CNTL,
4122                 .shift = 16,
4123                 .width = 6,
4124         },
4125         .hw.init = &(struct clk_init_data){
4126                 .name = "spicc1_sclk_div",
4127                 .ops = &clk_regmap_divider_ops,
4128                 .parent_hws = (const struct clk_hw *[]) {
4129                         &g12a_spicc1_sclk_sel.hw
4130                 },
4131                 .num_parents = 1,
4132                 .flags = CLK_SET_RATE_PARENT,
4133         },
4134 };
4135
4136 static struct clk_regmap g12a_spicc1_sclk = {
4137         .data = &(struct clk_regmap_gate_data){
4138                 .offset = HHI_SPICC_CLK_CNTL,
4139                 .bit_idx = 22,
4140         },
4141         .hw.init = &(struct clk_init_data){
4142                 .name = "spicc1_sclk",
4143                 .ops = &clk_regmap_gate_ops,
4144                 .parent_hws = (const struct clk_hw *[]) {
4145                         &g12a_spicc1_sclk_div.hw
4146                 },
4147                 .num_parents = 1,
4148                 .flags = CLK_SET_RATE_PARENT,
4149         },
4150 };
4151
4152 /* Neural Network Accelerator source clock */
4153
4154 static const struct clk_parent_data nna_clk_parent_data[] = {
4155         { .fw_name = "xtal", },
4156         { .hw = &g12a_gp0_pll.hw, },
4157         { .hw = &g12a_hifi_pll.hw, },
4158         { .hw = &g12a_fclk_div2p5.hw, },
4159         { .hw = &g12a_fclk_div3.hw, },
4160         { .hw = &g12a_fclk_div4.hw, },
4161         { .hw = &g12a_fclk_div5.hw, },
4162         { .hw = &g12a_fclk_div7.hw },
4163 };
4164
4165 static struct clk_regmap sm1_nna_axi_clk_sel = {
4166         .data = &(struct clk_regmap_mux_data){
4167                 .offset = HHI_NNA_CLK_CNTL,
4168                 .mask = 7,
4169                 .shift = 9,
4170         },
4171         .hw.init = &(struct clk_init_data){
4172                 .name = "nna_axi_clk_sel",
4173                 .ops = &clk_regmap_mux_ops,
4174                 .parent_data = nna_clk_parent_data,
4175                 .num_parents = ARRAY_SIZE(nna_clk_parent_data),
4176         },
4177 };
4178
4179 static struct clk_regmap sm1_nna_axi_clk_div = {
4180         .data = &(struct clk_regmap_div_data){
4181                 .offset = HHI_NNA_CLK_CNTL,
4182                 .shift = 0,
4183                 .width = 7,
4184         },
4185         .hw.init = &(struct clk_init_data){
4186                 .name = "nna_axi_clk_div",
4187                 .ops = &clk_regmap_divider_ops,
4188                 .parent_hws = (const struct clk_hw *[]) {
4189                         &sm1_nna_axi_clk_sel.hw
4190                 },
4191                 .num_parents = 1,
4192                 .flags = CLK_SET_RATE_PARENT,
4193         },
4194 };
4195
4196 static struct clk_regmap sm1_nna_axi_clk = {
4197         .data = &(struct clk_regmap_gate_data){
4198                 .offset = HHI_NNA_CLK_CNTL,
4199                 .bit_idx = 8,
4200         },
4201         .hw.init = &(struct clk_init_data){
4202                 .name = "nna_axi_clk",
4203                 .ops = &clk_regmap_gate_ops,
4204                 .parent_hws = (const struct clk_hw *[]) {
4205                         &sm1_nna_axi_clk_div.hw
4206                 },
4207                 .num_parents = 1,
4208                 .flags = CLK_SET_RATE_PARENT,
4209         },
4210 };
4211
4212 static struct clk_regmap sm1_nna_core_clk_sel = {
4213         .data = &(struct clk_regmap_mux_data){
4214                 .offset = HHI_NNA_CLK_CNTL,
4215                 .mask = 7,
4216                 .shift = 25,
4217         },
4218         .hw.init = &(struct clk_init_data){
4219                 .name = "nna_core_clk_sel",
4220                 .ops = &clk_regmap_mux_ops,
4221                 .parent_data = nna_clk_parent_data,
4222                 .num_parents = ARRAY_SIZE(nna_clk_parent_data),
4223         },
4224 };
4225
4226 static struct clk_regmap sm1_nna_core_clk_div = {
4227         .data = &(struct clk_regmap_div_data){
4228                 .offset = HHI_NNA_CLK_CNTL,
4229                 .shift = 16,
4230                 .width = 7,
4231         },
4232         .hw.init = &(struct clk_init_data){
4233                 .name = "nna_core_clk_div",
4234                 .ops = &clk_regmap_divider_ops,
4235                 .parent_hws = (const struct clk_hw *[]) {
4236                         &sm1_nna_core_clk_sel.hw
4237                 },
4238                 .num_parents = 1,
4239                 .flags = CLK_SET_RATE_PARENT,
4240         },
4241 };
4242
4243 static struct clk_regmap sm1_nna_core_clk = {
4244         .data = &(struct clk_regmap_gate_data){
4245                 .offset = HHI_NNA_CLK_CNTL,
4246                 .bit_idx = 24,
4247         },
4248         .hw.init = &(struct clk_init_data){
4249                 .name = "nna_core_clk",
4250                 .ops = &clk_regmap_gate_ops,
4251                 .parent_hws = (const struct clk_hw *[]) {
4252                         &sm1_nna_core_clk_div.hw
4253                 },
4254                 .num_parents = 1,
4255                 .flags = CLK_SET_RATE_PARENT,
4256         },
4257 };
4258
4259 #define MESON_GATE(_name, _reg, _bit) \
4260         MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4261
4262 #define MESON_GATE_RO(_name, _reg, _bit) \
4263         MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4264
4265 /* Everything Else (EE) domain gates */
4266 static MESON_GATE(g12a_ddr,                     HHI_GCLK_MPEG0, 0);
4267 static MESON_GATE(g12a_dos,                     HHI_GCLK_MPEG0, 1);
4268 static MESON_GATE(g12a_audio_locker,            HHI_GCLK_MPEG0, 2);
4269 static MESON_GATE(g12a_mipi_dsi_host,           HHI_GCLK_MPEG0, 3);
4270 static MESON_GATE(g12a_eth_phy,                 HHI_GCLK_MPEG0, 4);
4271 static MESON_GATE(g12a_isa,                     HHI_GCLK_MPEG0, 5);
4272 static MESON_GATE(g12a_pl301,                   HHI_GCLK_MPEG0, 6);
4273 static MESON_GATE(g12a_periphs,                 HHI_GCLK_MPEG0, 7);
4274 static MESON_GATE(g12a_spicc_0,                 HHI_GCLK_MPEG0, 8);
4275 static MESON_GATE(g12a_i2c,                     HHI_GCLK_MPEG0, 9);
4276 static MESON_GATE(g12a_sana,                    HHI_GCLK_MPEG0, 10);
4277 static MESON_GATE(g12a_sd,                      HHI_GCLK_MPEG0, 11);
4278 static MESON_GATE(g12a_rng0,                    HHI_GCLK_MPEG0, 12);
4279 static MESON_GATE(g12a_uart0,                   HHI_GCLK_MPEG0, 13);
4280 static MESON_GATE(g12a_spicc_1,                 HHI_GCLK_MPEG0, 14);
4281 static MESON_GATE(g12a_hiu_reg,                 HHI_GCLK_MPEG0, 19);
4282 static MESON_GATE(g12a_mipi_dsi_phy,            HHI_GCLK_MPEG0, 20);
4283 static MESON_GATE(g12a_assist_misc,             HHI_GCLK_MPEG0, 23);
4284 static MESON_GATE(g12a_emmc_a,                  HHI_GCLK_MPEG0, 4);
4285 static MESON_GATE(g12a_emmc_b,                  HHI_GCLK_MPEG0, 25);
4286 static MESON_GATE(g12a_emmc_c,                  HHI_GCLK_MPEG0, 26);
4287 static MESON_GATE(g12a_audio_codec,             HHI_GCLK_MPEG0, 28);
4288
4289 static MESON_GATE(g12a_audio,                   HHI_GCLK_MPEG1, 0);
4290 static MESON_GATE(g12a_eth_core,                HHI_GCLK_MPEG1, 3);
4291 static MESON_GATE(g12a_demux,                   HHI_GCLK_MPEG1, 4);
4292 static MESON_GATE(g12a_audio_ififo,             HHI_GCLK_MPEG1, 11);
4293 static MESON_GATE(g12a_adc,                     HHI_GCLK_MPEG1, 13);
4294 static MESON_GATE(g12a_uart1,                   HHI_GCLK_MPEG1, 16);
4295 static MESON_GATE(g12a_g2d,                     HHI_GCLK_MPEG1, 20);
4296 static MESON_GATE(g12a_reset,                   HHI_GCLK_MPEG1, 23);
4297 static MESON_GATE(g12a_pcie_comb,               HHI_GCLK_MPEG1, 24);
4298 static MESON_GATE(g12a_parser,                  HHI_GCLK_MPEG1, 25);
4299 static MESON_GATE(g12a_usb_general,             HHI_GCLK_MPEG1, 26);
4300 static MESON_GATE(g12a_pcie_phy,                HHI_GCLK_MPEG1, 27);
4301 static MESON_GATE(g12a_ahb_arb0,                HHI_GCLK_MPEG1, 29);
4302
4303 static MESON_GATE(g12a_ahb_data_bus,            HHI_GCLK_MPEG2, 1);
4304 static MESON_GATE(g12a_ahb_ctrl_bus,            HHI_GCLK_MPEG2, 2);
4305 static MESON_GATE(g12a_htx_hdcp22,              HHI_GCLK_MPEG2, 3);
4306 static MESON_GATE(g12a_htx_pclk,                HHI_GCLK_MPEG2, 4);
4307 static MESON_GATE(g12a_bt656,                   HHI_GCLK_MPEG2, 6);
4308 static MESON_GATE(g12a_usb1_to_ddr,             HHI_GCLK_MPEG2, 8);
4309 static MESON_GATE(g12b_mipi_isp_gate,           HHI_GCLK_MPEG2, 17);
4310 static MESON_GATE(g12a_mmc_pclk,                HHI_GCLK_MPEG2, 11);
4311 static MESON_GATE(g12a_uart2,                   HHI_GCLK_MPEG2, 15);
4312 static MESON_GATE(g12a_vpu_intr,                HHI_GCLK_MPEG2, 25);
4313 static MESON_GATE(g12b_csi_phy1,                HHI_GCLK_MPEG2, 28);
4314 static MESON_GATE(g12b_csi_phy0,                HHI_GCLK_MPEG2, 29);
4315 static MESON_GATE(g12a_gic,                     HHI_GCLK_MPEG2, 30);
4316
4317 static MESON_GATE(g12a_vclk2_venci0,            HHI_GCLK_OTHER, 1);
4318 static MESON_GATE(g12a_vclk2_venci1,            HHI_GCLK_OTHER, 2);
4319 static MESON_GATE(g12a_vclk2_vencp0,            HHI_GCLK_OTHER, 3);
4320 static MESON_GATE(g12a_vclk2_vencp1,            HHI_GCLK_OTHER, 4);
4321 static MESON_GATE(g12a_vclk2_venct0,            HHI_GCLK_OTHER, 5);
4322 static MESON_GATE(g12a_vclk2_venct1,            HHI_GCLK_OTHER, 6);
4323 static MESON_GATE(g12a_vclk2_other,             HHI_GCLK_OTHER, 7);
4324 static MESON_GATE(g12a_vclk2_enci,              HHI_GCLK_OTHER, 8);
4325 static MESON_GATE(g12a_vclk2_encp,              HHI_GCLK_OTHER, 9);
4326 static MESON_GATE(g12a_dac_clk,                 HHI_GCLK_OTHER, 10);
4327 static MESON_GATE(g12a_aoclk_gate,              HHI_GCLK_OTHER, 14);
4328 static MESON_GATE(g12a_iec958_gate,             HHI_GCLK_OTHER, 16);
4329 static MESON_GATE(g12a_enc480p,                 HHI_GCLK_OTHER, 20);
4330 static MESON_GATE(g12a_rng1,                    HHI_GCLK_OTHER, 21);
4331 static MESON_GATE(g12a_vclk2_enct,              HHI_GCLK_OTHER, 22);
4332 static MESON_GATE(g12a_vclk2_encl,              HHI_GCLK_OTHER, 23);
4333 static MESON_GATE(g12a_vclk2_venclmmc,          HHI_GCLK_OTHER, 24);
4334 static MESON_GATE(g12a_vclk2_vencl,             HHI_GCLK_OTHER, 25);
4335 static MESON_GATE(g12a_vclk2_other1,            HHI_GCLK_OTHER, 26);
4336
4337 static MESON_GATE_RO(g12a_dma,                  HHI_GCLK_OTHER2, 0);
4338 static MESON_GATE_RO(g12a_efuse,                HHI_GCLK_OTHER2, 1);
4339 static MESON_GATE_RO(g12a_rom_boot,             HHI_GCLK_OTHER2, 2);
4340 static MESON_GATE_RO(g12a_reset_sec,            HHI_GCLK_OTHER2, 3);
4341 static MESON_GATE_RO(g12a_sec_ahb_apb3,         HHI_GCLK_OTHER2, 4);
4342
4343 /* Array of all clocks provided by this provider */
4344 static struct clk_hw *g12a_hw_clks[] = {
4345         [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
4346         [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
4347         [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
4348         [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
4349         [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
4350         [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
4351         [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
4352         [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
4353         [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
4354         [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
4355         [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
4356         [CLKID_CLK81]                   = &g12a_clk81.hw,
4357         [CLKID_MPLL0]                   = &g12a_mpll0.hw,
4358         [CLKID_MPLL1]                   = &g12a_mpll1.hw,
4359         [CLKID_MPLL2]                   = &g12a_mpll2.hw,
4360         [CLKID_MPLL3]                   = &g12a_mpll3.hw,
4361         [CLKID_DDR]                     = &g12a_ddr.hw,
4362         [CLKID_DOS]                     = &g12a_dos.hw,
4363         [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
4364         [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
4365         [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
4366         [CLKID_ISA]                     = &g12a_isa.hw,
4367         [CLKID_PL301]                   = &g12a_pl301.hw,
4368         [CLKID_PERIPHS]                 = &g12a_periphs.hw,
4369         [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
4370         [CLKID_I2C]                     = &g12a_i2c.hw,
4371         [CLKID_SANA]                    = &g12a_sana.hw,
4372         [CLKID_SD]                      = &g12a_sd.hw,
4373         [CLKID_RNG0]                    = &g12a_rng0.hw,
4374         [CLKID_UART0]                   = &g12a_uart0.hw,
4375         [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
4376         [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
4377         [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
4378         [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
4379         [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
4380         [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
4381         [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
4382         [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
4383         [CLKID_AUDIO]                   = &g12a_audio.hw,
4384         [CLKID_ETH]                     = &g12a_eth_core.hw,
4385         [CLKID_DEMUX]                   = &g12a_demux.hw,
4386         [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
4387         [CLKID_ADC]                     = &g12a_adc.hw,
4388         [CLKID_UART1]                   = &g12a_uart1.hw,
4389         [CLKID_G2D]                     = &g12a_g2d.hw,
4390         [CLKID_RESET]                   = &g12a_reset.hw,
4391         [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
4392         [CLKID_PARSER]                  = &g12a_parser.hw,
4393         [CLKID_USB]                     = &g12a_usb_general.hw,
4394         [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
4395         [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
4396         [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
4397         [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
4398         [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
4399         [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
4400         [CLKID_BT656]                   = &g12a_bt656.hw,
4401         [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
4402         [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
4403         [CLKID_UART2]                   = &g12a_uart2.hw,
4404         [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
4405         [CLKID_GIC]                     = &g12a_gic.hw,
4406         [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
4407         [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
4408         [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
4409         [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
4410         [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
4411         [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
4412         [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
4413         [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
4414         [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
4415         [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
4416         [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
4417         [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
4418         [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
4419         [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
4420         [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
4421         [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
4422         [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
4423         [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
4424         [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
4425         [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
4426         [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
4427         [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
4428         [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
4429         [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
4430         [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
4431         [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
4432         [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
4433         [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
4434         [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
4435         [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
4436         [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
4437         [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
4438         [CLKID_ENC480P]                 = &g12a_enc480p.hw,
4439         [CLKID_RNG1]                    = &g12a_rng1.hw,
4440         [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
4441         [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
4442         [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
4443         [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
4444         [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
4445         [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
4446         [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
4447         [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
4448         [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
4449         [CLKID_DMA]                     = &g12a_dma.hw,
4450         [CLKID_EFUSE]                   = &g12a_efuse.hw,
4451         [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
4452         [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
4453         [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
4454         [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
4455         [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
4456         [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
4457         [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
4458         [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
4459         [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
4460         [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
4461         [CLKID_VPU]                     = &g12a_vpu.hw,
4462         [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
4463         [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
4464         [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
4465         [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
4466         [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
4467         [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
4468         [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
4469         [CLKID_VAPB]                    = &g12a_vapb.hw,
4470         [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
4471         [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
4472         [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
4473         [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
4474         [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
4475         [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
4476         [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
4477         [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
4478         [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
4479         [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
4480         [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
4481         [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
4482         [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
4483         [CLKID_VCLK]                    = &g12a_vclk.hw,
4484         [CLKID_VCLK2]                   = &g12a_vclk2.hw,
4485         [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
4486         [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
4487         [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
4488         [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
4489         [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
4490         [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
4491         [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
4492         [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
4493         [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
4494         [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
4495         [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
4496         [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
4497         [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
4498         [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
4499         [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
4500         [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
4501         [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
4502         [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
4503         [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
4504         [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
4505         [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
4506         [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
4507         [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
4508         [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
4509         [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
4510         [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
4511         [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
4512         [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
4513         [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
4514         [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
4515         [CLKID_HDMI]                    = &g12a_hdmi.hw,
4516         [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
4517         [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
4518         [CLKID_MALI_0]                  = &g12a_mali_0.hw,
4519         [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
4520         [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
4521         [CLKID_MALI_1]                  = &g12a_mali_1.hw,
4522         [CLKID_MALI]                    = &g12a_mali.hw,
4523         [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
4524         [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
4525         [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
4526         [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
4527         [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
4528         [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
4529         [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
4530         [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
4531         [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
4532         [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
4533         [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
4534         [CLKID_CPU_CLK]                 = &g12a_cpu_clk.hw,
4535         [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
4536         [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
4537         [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
4538         [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
4539         [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
4540         [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
4541         [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
4542         [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
4543         [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
4544         [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
4545         [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
4546         [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
4547         [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
4548         [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
4549         [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
4550         [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
4551         [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
4552         [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
4553         [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
4554         [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
4555         [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
4556         [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
4557         [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
4558         [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
4559         [CLKID_TS]                      = &g12a_ts.hw,
4560         [CLKID_SPICC0_SCLK_SEL]         = &g12a_spicc0_sclk_sel.hw,
4561         [CLKID_SPICC0_SCLK_DIV]         = &g12a_spicc0_sclk_div.hw,
4562         [CLKID_SPICC0_SCLK]             = &g12a_spicc0_sclk.hw,
4563         [CLKID_SPICC1_SCLK_SEL]         = &g12a_spicc1_sclk_sel.hw,
4564         [CLKID_SPICC1_SCLK_DIV]         = &g12a_spicc1_sclk_div.hw,
4565         [CLKID_SPICC1_SCLK]             = &g12a_spicc1_sclk.hw,
4566         [CLKID_MIPI_DSI_PXCLK_SEL]      = &g12a_mipi_dsi_pxclk_sel.hw,
4567         [CLKID_MIPI_DSI_PXCLK_DIV]      = &g12a_mipi_dsi_pxclk_div.hw,
4568         [CLKID_MIPI_DSI_PXCLK]          = &g12a_mipi_dsi_pxclk.hw,
4569 };
4570
4571 static struct clk_hw *g12b_hw_clks[] = {
4572         [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
4573         [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
4574         [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
4575         [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
4576         [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
4577         [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
4578         [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
4579         [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
4580         [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
4581         [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
4582         [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
4583         [CLKID_CLK81]                   = &g12a_clk81.hw,
4584         [CLKID_MPLL0]                   = &g12a_mpll0.hw,
4585         [CLKID_MPLL1]                   = &g12a_mpll1.hw,
4586         [CLKID_MPLL2]                   = &g12a_mpll2.hw,
4587         [CLKID_MPLL3]                   = &g12a_mpll3.hw,
4588         [CLKID_DDR]                     = &g12a_ddr.hw,
4589         [CLKID_DOS]                     = &g12a_dos.hw,
4590         [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
4591         [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
4592         [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
4593         [CLKID_ISA]                     = &g12a_isa.hw,
4594         [CLKID_PL301]                   = &g12a_pl301.hw,
4595         [CLKID_PERIPHS]                 = &g12a_periphs.hw,
4596         [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
4597         [CLKID_I2C]                     = &g12a_i2c.hw,
4598         [CLKID_SANA]                    = &g12a_sana.hw,
4599         [CLKID_SD]                      = &g12a_sd.hw,
4600         [CLKID_RNG0]                    = &g12a_rng0.hw,
4601         [CLKID_UART0]                   = &g12a_uart0.hw,
4602         [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
4603         [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
4604         [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
4605         [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
4606         [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
4607         [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
4608         [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
4609         [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
4610         [CLKID_AUDIO]                   = &g12a_audio.hw,
4611         [CLKID_ETH]                     = &g12a_eth_core.hw,
4612         [CLKID_DEMUX]                   = &g12a_demux.hw,
4613         [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
4614         [CLKID_ADC]                     = &g12a_adc.hw,
4615         [CLKID_UART1]                   = &g12a_uart1.hw,
4616         [CLKID_G2D]                     = &g12a_g2d.hw,
4617         [CLKID_RESET]                   = &g12a_reset.hw,
4618         [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
4619         [CLKID_PARSER]                  = &g12a_parser.hw,
4620         [CLKID_USB]                     = &g12a_usb_general.hw,
4621         [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
4622         [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
4623         [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
4624         [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
4625         [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
4626         [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
4627         [CLKID_BT656]                   = &g12a_bt656.hw,
4628         [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
4629         [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
4630         [CLKID_UART2]                   = &g12a_uart2.hw,
4631         [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
4632         [CLKID_GIC]                     = &g12a_gic.hw,
4633         [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
4634         [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
4635         [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
4636         [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
4637         [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
4638         [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
4639         [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
4640         [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
4641         [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
4642         [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
4643         [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
4644         [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
4645         [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
4646         [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
4647         [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
4648         [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
4649         [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
4650         [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
4651         [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
4652         [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
4653         [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
4654         [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
4655         [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
4656         [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
4657         [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
4658         [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
4659         [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
4660         [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
4661         [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
4662         [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
4663         [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
4664         [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
4665         [CLKID_ENC480P]                 = &g12a_enc480p.hw,
4666         [CLKID_RNG1]                    = &g12a_rng1.hw,
4667         [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
4668         [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
4669         [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
4670         [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
4671         [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
4672         [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
4673         [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
4674         [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
4675         [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
4676         [CLKID_DMA]                     = &g12a_dma.hw,
4677         [CLKID_EFUSE]                   = &g12a_efuse.hw,
4678         [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
4679         [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
4680         [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
4681         [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
4682         [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
4683         [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
4684         [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
4685         [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
4686         [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
4687         [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
4688         [CLKID_VPU]                     = &g12a_vpu.hw,
4689         [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
4690         [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
4691         [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
4692         [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
4693         [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
4694         [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
4695         [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
4696         [CLKID_VAPB]                    = &g12a_vapb.hw,
4697         [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
4698         [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
4699         [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
4700         [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
4701         [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
4702         [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
4703         [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
4704         [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
4705         [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
4706         [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
4707         [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
4708         [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
4709         [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
4710         [CLKID_VCLK]                    = &g12a_vclk.hw,
4711         [CLKID_VCLK2]                   = &g12a_vclk2.hw,
4712         [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
4713         [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
4714         [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
4715         [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
4716         [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
4717         [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
4718         [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
4719         [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
4720         [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
4721         [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
4722         [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
4723         [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
4724         [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
4725         [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
4726         [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
4727         [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
4728         [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
4729         [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
4730         [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
4731         [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
4732         [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
4733         [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
4734         [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
4735         [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
4736         [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
4737         [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
4738         [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
4739         [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
4740         [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
4741         [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
4742         [CLKID_HDMI]                    = &g12a_hdmi.hw,
4743         [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
4744         [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
4745         [CLKID_MALI_0]                  = &g12a_mali_0.hw,
4746         [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
4747         [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
4748         [CLKID_MALI_1]                  = &g12a_mali_1.hw,
4749         [CLKID_MALI]                    = &g12a_mali.hw,
4750         [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
4751         [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
4752         [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
4753         [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
4754         [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
4755         [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
4756         [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
4757         [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
4758         [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
4759         [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
4760         [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
4761         [CLKID_CPU_CLK]                 = &g12b_cpu_clk.hw,
4762         [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
4763         [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
4764         [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
4765         [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
4766         [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
4767         [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
4768         [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
4769         [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
4770         [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
4771         [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
4772         [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
4773         [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
4774         [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
4775         [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
4776         [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
4777         [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
4778         [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
4779         [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
4780         [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
4781         [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
4782         [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
4783         [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
4784         [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
4785         [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
4786         [CLKID_TS]                      = &g12a_ts.hw,
4787         [CLKID_SYS1_PLL_DCO]            = &g12b_sys1_pll_dco.hw,
4788         [CLKID_SYS1_PLL]                = &g12b_sys1_pll.hw,
4789         [CLKID_SYS1_PLL_DIV16_EN]       = &g12b_sys1_pll_div16_en.hw,
4790         [CLKID_SYS1_PLL_DIV16]          = &g12b_sys1_pll_div16.hw,
4791         [CLKID_CPUB_CLK_DYN0_SEL]       = &g12b_cpub_clk_premux0.hw,
4792         [CLKID_CPUB_CLK_DYN0_DIV]       = &g12b_cpub_clk_mux0_div.hw,
4793         [CLKID_CPUB_CLK_DYN0]           = &g12b_cpub_clk_postmux0.hw,
4794         [CLKID_CPUB_CLK_DYN1_SEL]       = &g12b_cpub_clk_premux1.hw,
4795         [CLKID_CPUB_CLK_DYN1_DIV]       = &g12b_cpub_clk_mux1_div.hw,
4796         [CLKID_CPUB_CLK_DYN1]           = &g12b_cpub_clk_postmux1.hw,
4797         [CLKID_CPUB_CLK_DYN]            = &g12b_cpub_clk_dyn.hw,
4798         [CLKID_CPUB_CLK]                = &g12b_cpub_clk.hw,
4799         [CLKID_CPUB_CLK_DIV16_EN]       = &g12b_cpub_clk_div16_en.hw,
4800         [CLKID_CPUB_CLK_DIV16]          = &g12b_cpub_clk_div16.hw,
4801         [CLKID_CPUB_CLK_DIV2]           = &g12b_cpub_clk_div2.hw,
4802         [CLKID_CPUB_CLK_DIV3]           = &g12b_cpub_clk_div3.hw,
4803         [CLKID_CPUB_CLK_DIV4]           = &g12b_cpub_clk_div4.hw,
4804         [CLKID_CPUB_CLK_DIV5]           = &g12b_cpub_clk_div5.hw,
4805         [CLKID_CPUB_CLK_DIV6]           = &g12b_cpub_clk_div6.hw,
4806         [CLKID_CPUB_CLK_DIV7]           = &g12b_cpub_clk_div7.hw,
4807         [CLKID_CPUB_CLK_DIV8]           = &g12b_cpub_clk_div8.hw,
4808         [CLKID_CPUB_CLK_APB_SEL]        = &g12b_cpub_clk_apb_sel.hw,
4809         [CLKID_CPUB_CLK_APB]            = &g12b_cpub_clk_apb.hw,
4810         [CLKID_CPUB_CLK_ATB_SEL]        = &g12b_cpub_clk_atb_sel.hw,
4811         [CLKID_CPUB_CLK_ATB]            = &g12b_cpub_clk_atb.hw,
4812         [CLKID_CPUB_CLK_AXI_SEL]        = &g12b_cpub_clk_axi_sel.hw,
4813         [CLKID_CPUB_CLK_AXI]            = &g12b_cpub_clk_axi.hw,
4814         [CLKID_CPUB_CLK_TRACE_SEL]      = &g12b_cpub_clk_trace_sel.hw,
4815         [CLKID_CPUB_CLK_TRACE]          = &g12b_cpub_clk_trace.hw,
4816         [CLKID_SPICC0_SCLK_SEL]         = &g12a_spicc0_sclk_sel.hw,
4817         [CLKID_SPICC0_SCLK_DIV]         = &g12a_spicc0_sclk_div.hw,
4818         [CLKID_SPICC0_SCLK]             = &g12a_spicc0_sclk.hw,
4819         [CLKID_SPICC1_SCLK_SEL]         = &g12a_spicc1_sclk_sel.hw,
4820         [CLKID_SPICC1_SCLK_DIV]         = &g12a_spicc1_sclk_div.hw,
4821         [CLKID_SPICC1_SCLK]             = &g12a_spicc1_sclk.hw,
4822         [CLKID_NNA_AXI_CLK_SEL]         = &sm1_nna_axi_clk_sel.hw,
4823         [CLKID_NNA_AXI_CLK_DIV]         = &sm1_nna_axi_clk_div.hw,
4824         [CLKID_NNA_AXI_CLK]             = &sm1_nna_axi_clk.hw,
4825         [CLKID_NNA_CORE_CLK_SEL]        = &sm1_nna_core_clk_sel.hw,
4826         [CLKID_NNA_CORE_CLK_DIV]        = &sm1_nna_core_clk_div.hw,
4827         [CLKID_NNA_CORE_CLK]            = &sm1_nna_core_clk.hw,
4828         [CLKID_MIPI_DSI_PXCLK_SEL]      = &g12a_mipi_dsi_pxclk_sel.hw,
4829         [CLKID_MIPI_DSI_PXCLK_DIV]      = &g12a_mipi_dsi_pxclk_div.hw,
4830         [CLKID_MIPI_DSI_PXCLK]          = &g12a_mipi_dsi_pxclk.hw,
4831         [CLKID_MIPI_ISP_SEL]            = &g12b_mipi_isp_sel.hw,
4832         [CLKID_MIPI_ISP_DIV]            = &g12b_mipi_isp_div.hw,
4833         [CLKID_MIPI_ISP]                = &g12b_mipi_isp.hw,
4834         [CLKID_MIPI_ISP_GATE]           = &g12b_mipi_isp_gate.hw,
4835         [CLKID_MIPI_ISP_CSI_PHY0]       = &g12b_csi_phy0.hw,
4836         [CLKID_MIPI_ISP_CSI_PHY1]       = &g12b_csi_phy1.hw,
4837 };
4838
4839 static struct clk_hw *sm1_hw_clks[] = {
4840         [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
4841         [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
4842         [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
4843         [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
4844         [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
4845         [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
4846         [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
4847         [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
4848         [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
4849         [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
4850         [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
4851         [CLKID_CLK81]                   = &g12a_clk81.hw,
4852         [CLKID_MPLL0]                   = &g12a_mpll0.hw,
4853         [CLKID_MPLL1]                   = &g12a_mpll1.hw,
4854         [CLKID_MPLL2]                   = &g12a_mpll2.hw,
4855         [CLKID_MPLL3]                   = &g12a_mpll3.hw,
4856         [CLKID_DDR]                     = &g12a_ddr.hw,
4857         [CLKID_DOS]                     = &g12a_dos.hw,
4858         [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
4859         [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
4860         [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
4861         [CLKID_ISA]                     = &g12a_isa.hw,
4862         [CLKID_PL301]                   = &g12a_pl301.hw,
4863         [CLKID_PERIPHS]                 = &g12a_periphs.hw,
4864         [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
4865         [CLKID_I2C]                     = &g12a_i2c.hw,
4866         [CLKID_SANA]                    = &g12a_sana.hw,
4867         [CLKID_SD]                      = &g12a_sd.hw,
4868         [CLKID_RNG0]                    = &g12a_rng0.hw,
4869         [CLKID_UART0]                   = &g12a_uart0.hw,
4870         [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
4871         [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
4872         [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
4873         [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
4874         [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
4875         [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
4876         [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
4877         [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
4878         [CLKID_AUDIO]                   = &g12a_audio.hw,
4879         [CLKID_ETH]                     = &g12a_eth_core.hw,
4880         [CLKID_DEMUX]                   = &g12a_demux.hw,
4881         [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
4882         [CLKID_ADC]                     = &g12a_adc.hw,
4883         [CLKID_UART1]                   = &g12a_uart1.hw,
4884         [CLKID_G2D]                     = &g12a_g2d.hw,
4885         [CLKID_RESET]                   = &g12a_reset.hw,
4886         [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
4887         [CLKID_PARSER]                  = &g12a_parser.hw,
4888         [CLKID_USB]                     = &g12a_usb_general.hw,
4889         [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
4890         [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
4891         [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
4892         [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
4893         [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
4894         [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
4895         [CLKID_BT656]                   = &g12a_bt656.hw,
4896         [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
4897         [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
4898         [CLKID_UART2]                   = &g12a_uart2.hw,
4899         [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
4900         [CLKID_GIC]                     = &g12a_gic.hw,
4901         [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
4902         [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
4903         [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
4904         [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
4905         [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
4906         [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
4907         [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
4908         [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
4909         [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
4910         [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
4911         [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
4912         [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
4913         [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
4914         [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
4915         [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
4916         [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
4917         [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
4918         [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
4919         [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
4920         [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
4921         [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
4922         [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
4923         [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
4924         [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
4925         [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
4926         [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
4927         [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
4928         [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
4929         [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
4930         [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
4931         [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
4932         [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
4933         [CLKID_ENC480P]                 = &g12a_enc480p.hw,
4934         [CLKID_RNG1]                    = &g12a_rng1.hw,
4935         [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
4936         [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
4937         [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
4938         [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
4939         [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
4940         [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
4941         [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
4942         [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
4943         [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
4944         [CLKID_DMA]                     = &g12a_dma.hw,
4945         [CLKID_EFUSE]                   = &g12a_efuse.hw,
4946         [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
4947         [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
4948         [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
4949         [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
4950         [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
4951         [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
4952         [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
4953         [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
4954         [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
4955         [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
4956         [CLKID_VPU]                     = &g12a_vpu.hw,
4957         [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
4958         [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
4959         [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
4960         [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
4961         [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
4962         [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
4963         [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
4964         [CLKID_VAPB]                    = &g12a_vapb.hw,
4965         [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
4966         [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
4967         [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
4968         [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
4969         [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
4970         [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
4971         [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
4972         [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
4973         [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
4974         [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
4975         [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
4976         [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
4977         [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
4978         [CLKID_VCLK]                    = &g12a_vclk.hw,
4979         [CLKID_VCLK2]                   = &g12a_vclk2.hw,
4980         [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
4981         [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
4982         [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
4983         [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
4984         [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
4985         [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
4986         [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
4987         [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
4988         [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
4989         [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
4990         [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
4991         [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
4992         [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
4993         [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
4994         [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
4995         [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
4996         [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
4997         [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
4998         [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
4999         [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
5000         [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
5001         [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
5002         [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
5003         [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
5004         [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
5005         [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
5006         [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
5007         [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
5008         [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
5009         [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
5010         [CLKID_HDMI]                    = &g12a_hdmi.hw,
5011         [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
5012         [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
5013         [CLKID_MALI_0]                  = &g12a_mali_0.hw,
5014         [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
5015         [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
5016         [CLKID_MALI_1]                  = &g12a_mali_1.hw,
5017         [CLKID_MALI]                    = &g12a_mali.hw,
5018         [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
5019         [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
5020         [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
5021         [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
5022         [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
5023         [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
5024         [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
5025         [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
5026         [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
5027         [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
5028         [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
5029         [CLKID_CPU_CLK]                 = &g12a_cpu_clk.hw,
5030         [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
5031         [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
5032         [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
5033         [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
5034         [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
5035         [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
5036         [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
5037         [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
5038         [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
5039         [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
5040         [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
5041         [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
5042         [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
5043         [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
5044         [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
5045         [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
5046         [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
5047         [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
5048         [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
5049         [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
5050         [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
5051         [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
5052         [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
5053         [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
5054         [CLKID_TS]                      = &g12a_ts.hw,
5055         [CLKID_GP1_PLL_DCO]             = &sm1_gp1_pll_dco.hw,
5056         [CLKID_GP1_PLL]                 = &sm1_gp1_pll.hw,
5057         [CLKID_DSU_CLK_DYN0_SEL]        = &sm1_dsu_clk_premux0.hw,
5058         [CLKID_DSU_CLK_DYN0_DIV]        = &sm1_dsu_clk_premux1.hw,
5059         [CLKID_DSU_CLK_DYN0]            = &sm1_dsu_clk_mux0_div.hw,
5060         [CLKID_DSU_CLK_DYN1_SEL]        = &sm1_dsu_clk_postmux0.hw,
5061         [CLKID_DSU_CLK_DYN1_DIV]        = &sm1_dsu_clk_mux1_div.hw,
5062         [CLKID_DSU_CLK_DYN1]            = &sm1_dsu_clk_postmux1.hw,
5063         [CLKID_DSU_CLK_DYN]             = &sm1_dsu_clk_dyn.hw,
5064         [CLKID_DSU_CLK_FINAL]           = &sm1_dsu_final_clk.hw,
5065         [CLKID_DSU_CLK]                 = &sm1_dsu_clk.hw,
5066         [CLKID_CPU1_CLK]                = &sm1_cpu1_clk.hw,
5067         [CLKID_CPU2_CLK]                = &sm1_cpu2_clk.hw,
5068         [CLKID_CPU3_CLK]                = &sm1_cpu3_clk.hw,
5069         [CLKID_SPICC0_SCLK_SEL]         = &g12a_spicc0_sclk_sel.hw,
5070         [CLKID_SPICC0_SCLK_DIV]         = &g12a_spicc0_sclk_div.hw,
5071         [CLKID_SPICC0_SCLK]             = &g12a_spicc0_sclk.hw,
5072         [CLKID_SPICC1_SCLK_SEL]         = &g12a_spicc1_sclk_sel.hw,
5073         [CLKID_SPICC1_SCLK_DIV]         = &g12a_spicc1_sclk_div.hw,
5074         [CLKID_SPICC1_SCLK]             = &g12a_spicc1_sclk.hw,
5075         [CLKID_NNA_AXI_CLK_SEL]         = &sm1_nna_axi_clk_sel.hw,
5076         [CLKID_NNA_AXI_CLK_DIV]         = &sm1_nna_axi_clk_div.hw,
5077         [CLKID_NNA_AXI_CLK]             = &sm1_nna_axi_clk.hw,
5078         [CLKID_NNA_CORE_CLK_SEL]        = &sm1_nna_core_clk_sel.hw,
5079         [CLKID_NNA_CORE_CLK_DIV]        = &sm1_nna_core_clk_div.hw,
5080         [CLKID_NNA_CORE_CLK]            = &sm1_nna_core_clk.hw,
5081         [CLKID_MIPI_DSI_PXCLK_SEL]      = &g12a_mipi_dsi_pxclk_sel.hw,
5082         [CLKID_MIPI_DSI_PXCLK_DIV]      = &g12a_mipi_dsi_pxclk_div.hw,
5083         [CLKID_MIPI_DSI_PXCLK]          = &g12a_mipi_dsi_pxclk.hw,
5084 };
5085
5086 /* Convenience table to populate regmap in .probe */
5087 static struct clk_regmap *const g12a_clk_regmaps[] = {
5088         &g12a_clk81,
5089         &g12a_dos,
5090         &g12a_ddr,
5091         &g12a_audio_locker,
5092         &g12a_mipi_dsi_host,
5093         &g12a_eth_phy,
5094         &g12a_isa,
5095         &g12a_pl301,
5096         &g12a_periphs,
5097         &g12a_spicc_0,
5098         &g12a_i2c,
5099         &g12a_sana,
5100         &g12a_sd,
5101         &g12a_rng0,
5102         &g12a_uart0,
5103         &g12a_spicc_1,
5104         &g12a_hiu_reg,
5105         &g12a_mipi_dsi_phy,
5106         &g12a_assist_misc,
5107         &g12a_emmc_a,
5108         &g12a_emmc_b,
5109         &g12a_emmc_c,
5110         &g12a_audio_codec,
5111         &g12a_audio,
5112         &g12a_eth_core,
5113         &g12a_demux,
5114         &g12a_audio_ififo,
5115         &g12a_adc,
5116         &g12a_uart1,
5117         &g12a_g2d,
5118         &g12a_reset,
5119         &g12a_pcie_comb,
5120         &g12a_parser,
5121         &g12a_usb_general,
5122         &g12a_pcie_phy,
5123         &g12a_ahb_arb0,
5124         &g12a_ahb_data_bus,
5125         &g12a_ahb_ctrl_bus,
5126         &g12a_htx_hdcp22,
5127         &g12a_htx_pclk,
5128         &g12a_bt656,
5129         &g12a_usb1_to_ddr,
5130         &g12a_mmc_pclk,
5131         &g12a_uart2,
5132         &g12a_vpu_intr,
5133         &g12a_gic,
5134         &g12a_sd_emmc_a_clk0,
5135         &g12a_sd_emmc_b_clk0,
5136         &g12a_sd_emmc_c_clk0,
5137         &g12a_mpeg_clk_div,
5138         &g12a_sd_emmc_a_clk0_div,
5139         &g12a_sd_emmc_b_clk0_div,
5140         &g12a_sd_emmc_c_clk0_div,
5141         &g12a_mpeg_clk_sel,
5142         &g12a_sd_emmc_a_clk0_sel,
5143         &g12a_sd_emmc_b_clk0_sel,
5144         &g12a_sd_emmc_c_clk0_sel,
5145         &g12a_mpll0,
5146         &g12a_mpll1,
5147         &g12a_mpll2,
5148         &g12a_mpll3,
5149         &g12a_mpll0_div,
5150         &g12a_mpll1_div,
5151         &g12a_mpll2_div,
5152         &g12a_mpll3_div,
5153         &g12a_fixed_pll,
5154         &g12a_sys_pll,
5155         &g12a_gp0_pll,
5156         &g12a_hifi_pll,
5157         &g12a_vclk2_venci0,
5158         &g12a_vclk2_venci1,
5159         &g12a_vclk2_vencp0,
5160         &g12a_vclk2_vencp1,
5161         &g12a_vclk2_venct0,
5162         &g12a_vclk2_venct1,
5163         &g12a_vclk2_other,
5164         &g12a_vclk2_enci,
5165         &g12a_vclk2_encp,
5166         &g12a_dac_clk,
5167         &g12a_aoclk_gate,
5168         &g12a_iec958_gate,
5169         &g12a_enc480p,
5170         &g12a_rng1,
5171         &g12a_vclk2_enct,
5172         &g12a_vclk2_encl,
5173         &g12a_vclk2_venclmmc,
5174         &g12a_vclk2_vencl,
5175         &g12a_vclk2_other1,
5176         &g12a_fixed_pll_dco,
5177         &g12a_sys_pll_dco,
5178         &g12a_gp0_pll_dco,
5179         &g12a_hifi_pll_dco,
5180         &g12a_fclk_div2,
5181         &g12a_fclk_div3,
5182         &g12a_fclk_div4,
5183         &g12a_fclk_div5,
5184         &g12a_fclk_div7,
5185         &g12a_fclk_div2p5,
5186         &g12a_dma,
5187         &g12a_efuse,
5188         &g12a_rom_boot,
5189         &g12a_reset_sec,
5190         &g12a_sec_ahb_apb3,
5191         &g12a_vpu_0_sel,
5192         &g12a_vpu_0_div,
5193         &g12a_vpu_0,
5194         &g12a_vpu_1_sel,
5195         &g12a_vpu_1_div,
5196         &g12a_vpu_1,
5197         &g12a_vpu,
5198         &g12a_vapb_0_sel,
5199         &g12a_vapb_0_div,
5200         &g12a_vapb_0,
5201         &g12a_vapb_1_sel,
5202         &g12a_vapb_1_div,
5203         &g12a_vapb_1,
5204         &g12a_vapb_sel,
5205         &g12a_vapb,
5206         &g12a_hdmi_pll_dco,
5207         &g12a_hdmi_pll_od,
5208         &g12a_hdmi_pll_od2,
5209         &g12a_hdmi_pll,
5210         &g12a_vid_pll_div,
5211         &g12a_vid_pll_sel,
5212         &g12a_vid_pll,
5213         &g12a_vclk_sel,
5214         &g12a_vclk2_sel,
5215         &g12a_vclk_input,
5216         &g12a_vclk2_input,
5217         &g12a_vclk_div,
5218         &g12a_vclk2_div,
5219         &g12a_vclk,
5220         &g12a_vclk2,
5221         &g12a_vclk_div1,
5222         &g12a_vclk_div2_en,
5223         &g12a_vclk_div4_en,
5224         &g12a_vclk_div6_en,
5225         &g12a_vclk_div12_en,
5226         &g12a_vclk2_div1,
5227         &g12a_vclk2_div2_en,
5228         &g12a_vclk2_div4_en,
5229         &g12a_vclk2_div6_en,
5230         &g12a_vclk2_div12_en,
5231         &g12a_cts_enci_sel,
5232         &g12a_cts_encp_sel,
5233         &g12a_cts_encl_sel,
5234         &g12a_cts_vdac_sel,
5235         &g12a_hdmi_tx_sel,
5236         &g12a_cts_enci,
5237         &g12a_cts_encp,
5238         &g12a_cts_encl,
5239         &g12a_cts_vdac,
5240         &g12a_hdmi_tx,
5241         &g12a_hdmi_sel,
5242         &g12a_hdmi_div,
5243         &g12a_hdmi,
5244         &g12a_mali_0_sel,
5245         &g12a_mali_0_div,
5246         &g12a_mali_0,
5247         &g12a_mali_1_sel,
5248         &g12a_mali_1_div,
5249         &g12a_mali_1,
5250         &g12a_mali,
5251         &g12a_mpll_50m,
5252         &g12a_sys_pll_div16_en,
5253         &g12a_cpu_clk_premux0,
5254         &g12a_cpu_clk_mux0_div,
5255         &g12a_cpu_clk_postmux0,
5256         &g12a_cpu_clk_premux1,
5257         &g12a_cpu_clk_mux1_div,
5258         &g12a_cpu_clk_postmux1,
5259         &g12a_cpu_clk_dyn,
5260         &g12a_cpu_clk,
5261         &g12a_cpu_clk_div16_en,
5262         &g12a_cpu_clk_apb_div,
5263         &g12a_cpu_clk_apb,
5264         &g12a_cpu_clk_atb_div,
5265         &g12a_cpu_clk_atb,
5266         &g12a_cpu_clk_axi_div,
5267         &g12a_cpu_clk_axi,
5268         &g12a_cpu_clk_trace_div,
5269         &g12a_cpu_clk_trace,
5270         &g12a_pcie_pll_od,
5271         &g12a_pcie_pll_dco,
5272         &g12a_vdec_1_sel,
5273         &g12a_vdec_1_div,
5274         &g12a_vdec_1,
5275         &g12a_vdec_hevc_sel,
5276         &g12a_vdec_hevc_div,
5277         &g12a_vdec_hevc,
5278         &g12a_vdec_hevcf_sel,
5279         &g12a_vdec_hevcf_div,
5280         &g12a_vdec_hevcf,
5281         &g12a_ts_div,
5282         &g12a_ts,
5283         &g12b_cpu_clk,
5284         &g12b_sys1_pll_dco,
5285         &g12b_sys1_pll,
5286         &g12b_sys1_pll_div16_en,
5287         &g12b_cpub_clk_premux0,
5288         &g12b_cpub_clk_mux0_div,
5289         &g12b_cpub_clk_postmux0,
5290         &g12b_cpub_clk_premux1,
5291         &g12b_cpub_clk_mux1_div,
5292         &g12b_cpub_clk_postmux1,
5293         &g12b_cpub_clk_dyn,
5294         &g12b_cpub_clk,
5295         &g12b_cpub_clk_div16_en,
5296         &g12b_cpub_clk_apb_sel,
5297         &g12b_cpub_clk_apb,
5298         &g12b_cpub_clk_atb_sel,
5299         &g12b_cpub_clk_atb,
5300         &g12b_cpub_clk_axi_sel,
5301         &g12b_cpub_clk_axi,
5302         &g12b_cpub_clk_trace_sel,
5303         &g12b_cpub_clk_trace,
5304         &sm1_gp1_pll_dco,
5305         &sm1_gp1_pll,
5306         &sm1_dsu_clk_premux0,
5307         &sm1_dsu_clk_premux1,
5308         &sm1_dsu_clk_mux0_div,
5309         &sm1_dsu_clk_postmux0,
5310         &sm1_dsu_clk_mux1_div,
5311         &sm1_dsu_clk_postmux1,
5312         &sm1_dsu_clk_dyn,
5313         &sm1_dsu_final_clk,
5314         &sm1_dsu_clk,
5315         &sm1_cpu1_clk,
5316         &sm1_cpu2_clk,
5317         &sm1_cpu3_clk,
5318         &g12a_spicc0_sclk_sel,
5319         &g12a_spicc0_sclk_div,
5320         &g12a_spicc0_sclk,
5321         &g12a_spicc1_sclk_sel,
5322         &g12a_spicc1_sclk_div,
5323         &g12a_spicc1_sclk,
5324         &sm1_nna_axi_clk_sel,
5325         &sm1_nna_axi_clk_div,
5326         &sm1_nna_axi_clk,
5327         &sm1_nna_core_clk_sel,
5328         &sm1_nna_core_clk_div,
5329         &sm1_nna_core_clk,
5330         &g12a_mipi_dsi_pxclk_sel,
5331         &g12a_mipi_dsi_pxclk_div,
5332         &g12a_mipi_dsi_pxclk,
5333         &g12b_mipi_isp_sel,
5334         &g12b_mipi_isp_div,
5335         &g12b_mipi_isp,
5336         &g12b_mipi_isp_gate,
5337         &g12b_csi_phy1,
5338         &g12b_csi_phy0,
5339 };
5340
5341 static const struct reg_sequence g12a_init_regs[] = {
5342         { .reg = HHI_MPLL_CNTL0,        .def = 0x00000543 },
5343 };
5344
5345 #define DVFS_CON_ID "dvfs"
5346
5347 static int meson_g12a_dvfs_setup_common(struct device *dev,
5348                                         struct clk_hw **hws)
5349 {
5350         struct clk *notifier_clk;
5351         struct clk_hw *xtal;
5352         int ret;
5353
5354         xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5355
5356         /* Setup clock notifier for cpu_clk_postmux0 */
5357         g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5358         notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5359                                            DVFS_CON_ID);
5360         ret = devm_clk_notifier_register(dev, notifier_clk,
5361                                          &g12a_cpu_clk_postmux0_nb_data.nb);
5362         if (ret) {
5363                 dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
5364                 return ret;
5365         }
5366
5367         /* Setup clock notifier for cpu_clk_dyn mux */
5368         notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5369                                            DVFS_CON_ID);
5370         ret = devm_clk_notifier_register(dev, notifier_clk,
5371                                          &g12a_cpu_clk_mux_nb);
5372         if (ret) {
5373                 dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
5374                 return ret;
5375         }
5376
5377         return 0;
5378 }
5379
5380 static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5381 {
5382         struct clk_hw **hws = g12b_hw_clks;
5383         struct device *dev = &pdev->dev;
5384         struct clk *notifier_clk;
5385         struct clk_hw *xtal;
5386         int ret;
5387
5388         ret = meson_g12a_dvfs_setup_common(dev, hws);
5389         if (ret)
5390                 return ret;
5391
5392         xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5393
5394         /* Setup clock notifier for cpu_clk mux */
5395         notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5396                                            DVFS_CON_ID);
5397         ret = devm_clk_notifier_register(dev, notifier_clk,
5398                                          &g12a_cpu_clk_mux_nb);
5399         if (ret) {
5400                 dev_err(dev, "failed to register the cpu_clk notifier\n");
5401                 return ret;
5402         }
5403
5404         /* Setup clock notifier for sys1_pll */
5405         notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5406                                            DVFS_CON_ID);
5407         ret = devm_clk_notifier_register(dev, notifier_clk,
5408                                          &g12b_cpu_clk_sys1_pll_nb_data.nb);
5409         if (ret) {
5410                 dev_err(dev, "failed to register the sys1_pll notifier\n");
5411                 return ret;
5412         }
5413
5414         /* Add notifiers for the second CPU cluster */
5415
5416         /* Setup clock notifier for cpub_clk_postmux0 */
5417         g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5418         notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5419                                            DVFS_CON_ID);
5420         ret = devm_clk_notifier_register(dev, notifier_clk,
5421                                          &g12b_cpub_clk_postmux0_nb_data.nb);
5422         if (ret) {
5423                 dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
5424                 return ret;
5425         }
5426
5427         /* Setup clock notifier for cpub_clk_dyn mux */
5428         notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5429         ret = devm_clk_notifier_register(dev, notifier_clk,
5430                                          &g12a_cpu_clk_mux_nb);
5431         if (ret) {
5432                 dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
5433                 return ret;
5434         }
5435
5436         /* Setup clock notifier for cpub_clk mux */
5437         notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5438         ret = devm_clk_notifier_register(dev, notifier_clk,
5439                                          &g12a_cpu_clk_mux_nb);
5440         if (ret) {
5441                 dev_err(dev, "failed to register the cpub_clk notifier\n");
5442                 return ret;
5443         }
5444
5445         /* Setup clock notifier for sys_pll */
5446         notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5447         ret = devm_clk_notifier_register(dev, notifier_clk,
5448                                          &g12b_cpub_clk_sys_pll_nb_data.nb);
5449         if (ret) {
5450                 dev_err(dev, "failed to register the sys_pll notifier\n");
5451                 return ret;
5452         }
5453
5454         return 0;
5455 }
5456
5457 static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5458 {
5459         struct clk_hw **hws = g12a_hw_clks;
5460         struct device *dev = &pdev->dev;
5461         struct clk *notifier_clk;
5462         int ret;
5463
5464         ret = meson_g12a_dvfs_setup_common(dev, hws);
5465         if (ret)
5466                 return ret;
5467
5468         /* Setup clock notifier for cpu_clk mux */
5469         notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5470         ret = devm_clk_notifier_register(dev, notifier_clk,
5471                                     &g12a_cpu_clk_mux_nb);
5472         if (ret) {
5473                 dev_err(dev, "failed to register the cpu_clk notifier\n");
5474                 return ret;
5475         }
5476
5477         /* Setup clock notifier for sys_pll */
5478         notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5479         ret = devm_clk_notifier_register(dev, notifier_clk,
5480                                          &g12a_sys_pll_nb_data.nb);
5481         if (ret) {
5482                 dev_err(dev, "failed to register the sys_pll notifier\n");
5483                 return ret;
5484         }
5485
5486         return 0;
5487 }
5488
5489 struct meson_g12a_data {
5490         const struct meson_eeclkc_data eeclkc_data;
5491         int (*dvfs_setup)(struct platform_device *pdev);
5492 };
5493
5494 static int meson_g12a_probe(struct platform_device *pdev)
5495 {
5496         const struct meson_eeclkc_data *eeclkc_data;
5497         const struct meson_g12a_data *g12a_data;
5498         int ret;
5499
5500         eeclkc_data = of_device_get_match_data(&pdev->dev);
5501         if (!eeclkc_data)
5502                 return -EINVAL;
5503
5504         ret = meson_eeclkc_probe(pdev);
5505         if (ret)
5506                 return ret;
5507
5508         g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5509                                  eeclkc_data);
5510
5511         if (g12a_data->dvfs_setup)
5512                 return g12a_data->dvfs_setup(pdev);
5513
5514         return 0;
5515 }
5516
5517 static const struct meson_g12a_data g12a_clkc_data = {
5518         .eeclkc_data = {
5519                 .regmap_clks = g12a_clk_regmaps,
5520                 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5521                 .hw_clks = {
5522                         .hws = g12a_hw_clks,
5523                         .num = ARRAY_SIZE(g12a_hw_clks),
5524                 },
5525                 .init_regs = g12a_init_regs,
5526                 .init_count = ARRAY_SIZE(g12a_init_regs),
5527         },
5528         .dvfs_setup = meson_g12a_dvfs_setup,
5529 };
5530
5531 static const struct meson_g12a_data g12b_clkc_data = {
5532         .eeclkc_data = {
5533                 .regmap_clks = g12a_clk_regmaps,
5534                 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5535                 .hw_clks = {
5536                         .hws = g12b_hw_clks,
5537                         .num = ARRAY_SIZE(g12b_hw_clks),
5538                 },
5539         },
5540         .dvfs_setup = meson_g12b_dvfs_setup,
5541 };
5542
5543 static const struct meson_g12a_data sm1_clkc_data = {
5544         .eeclkc_data = {
5545                 .regmap_clks = g12a_clk_regmaps,
5546                 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5547                 .hw_clks = {
5548                         .hws = sm1_hw_clks,
5549                         .num = ARRAY_SIZE(sm1_hw_clks),
5550                 },
5551         },
5552         .dvfs_setup = meson_g12a_dvfs_setup,
5553 };
5554
5555 static const struct of_device_id clkc_match_table[] = {
5556         {
5557                 .compatible = "amlogic,g12a-clkc",
5558                 .data = &g12a_clkc_data.eeclkc_data
5559         },
5560         {
5561                 .compatible = "amlogic,g12b-clkc",
5562                 .data = &g12b_clkc_data.eeclkc_data
5563         },
5564         {
5565                 .compatible = "amlogic,sm1-clkc",
5566                 .data = &sm1_clkc_data.eeclkc_data
5567         },
5568         {}
5569 };
5570 MODULE_DEVICE_TABLE(of, clkc_match_table);
5571
5572 static struct platform_driver g12a_driver = {
5573         .probe          = meson_g12a_probe,
5574         .driver         = {
5575                 .name   = "g12a-clkc",
5576                 .of_match_table = clkc_match_table,
5577         },
5578 };
5579
5580 module_platform_driver(g12a_driver);
5581 MODULE_LICENSE("GPL v2");