1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
12 #include <linux/clk-provider.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/platform_device.h>
16 #include <linux/module.h>
18 #include "clk-regmap.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
26 static DEFINE_SPINLOCK(meson_clk_lock);
28 static struct clk_regmap axg_fixed_pll_dco = {
29 .data = &(struct meson_clk_pll_data){
31 .reg_off = HHI_MPLL_CNTL,
36 .reg_off = HHI_MPLL_CNTL,
41 .reg_off = HHI_MPLL_CNTL,
46 .reg_off = HHI_MPLL_CNTL2,
51 .reg_off = HHI_MPLL_CNTL,
56 .reg_off = HHI_MPLL_CNTL,
61 .hw.init = &(struct clk_init_data){
62 .name = "fixed_pll_dco",
63 .ops = &meson_clk_pll_ro_ops,
64 .parent_data = &(const struct clk_parent_data) {
71 static struct clk_regmap axg_fixed_pll = {
72 .data = &(struct clk_regmap_div_data){
73 .offset = HHI_MPLL_CNTL,
76 .flags = CLK_DIVIDER_POWER_OF_TWO,
78 .hw.init = &(struct clk_init_data){
80 .ops = &clk_regmap_divider_ro_ops,
81 .parent_hws = (const struct clk_hw *[]) {
86 * This clock won't ever change at runtime so
87 * CLK_SET_RATE_PARENT is not required
92 static struct clk_regmap axg_sys_pll_dco = {
93 .data = &(struct meson_clk_pll_data){
95 .reg_off = HHI_SYS_PLL_CNTL,
100 .reg_off = HHI_SYS_PLL_CNTL,
105 .reg_off = HHI_SYS_PLL_CNTL,
110 .reg_off = HHI_SYS_PLL_CNTL,
115 .reg_off = HHI_SYS_PLL_CNTL,
120 .hw.init = &(struct clk_init_data){
121 .name = "sys_pll_dco",
122 .ops = &meson_clk_pll_ro_ops,
123 .parent_data = &(const struct clk_parent_data) {
130 static struct clk_regmap axg_sys_pll = {
131 .data = &(struct clk_regmap_div_data){
132 .offset = HHI_SYS_PLL_CNTL,
135 .flags = CLK_DIVIDER_POWER_OF_TWO,
137 .hw.init = &(struct clk_init_data){
139 .ops = &clk_regmap_divider_ro_ops,
140 .parent_hws = (const struct clk_hw *[]) {
144 .flags = CLK_SET_RATE_PARENT,
148 static const struct pll_params_table axg_gp0_pll_params_table[] = {
181 static const struct reg_sequence axg_gp0_init_regs[] = {
182 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
183 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
184 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
185 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
186 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
189 static struct clk_regmap axg_gp0_pll_dco = {
190 .data = &(struct meson_clk_pll_data){
192 .reg_off = HHI_GP0_PLL_CNTL,
197 .reg_off = HHI_GP0_PLL_CNTL,
202 .reg_off = HHI_GP0_PLL_CNTL,
207 .reg_off = HHI_GP0_PLL_CNTL1,
212 .reg_off = HHI_GP0_PLL_CNTL,
217 .reg_off = HHI_GP0_PLL_CNTL,
221 .table = axg_gp0_pll_params_table,
222 .init_regs = axg_gp0_init_regs,
223 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
225 .hw.init = &(struct clk_init_data){
226 .name = "gp0_pll_dco",
227 .ops = &meson_clk_pll_ops,
228 .parent_data = &(const struct clk_parent_data) {
235 static struct clk_regmap axg_gp0_pll = {
236 .data = &(struct clk_regmap_div_data){
237 .offset = HHI_GP0_PLL_CNTL,
240 .flags = CLK_DIVIDER_POWER_OF_TWO,
242 .hw.init = &(struct clk_init_data){
244 .ops = &clk_regmap_divider_ops,
245 .parent_hws = (const struct clk_hw *[]) {
249 .flags = CLK_SET_RATE_PARENT,
253 static const struct reg_sequence axg_hifi_init_regs[] = {
254 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
255 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
256 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
257 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
258 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
261 static struct clk_regmap axg_hifi_pll_dco = {
262 .data = &(struct meson_clk_pll_data){
264 .reg_off = HHI_HIFI_PLL_CNTL,
269 .reg_off = HHI_HIFI_PLL_CNTL,
274 .reg_off = HHI_HIFI_PLL_CNTL,
279 .reg_off = HHI_HIFI_PLL_CNTL5,
284 .reg_off = HHI_HIFI_PLL_CNTL,
289 .reg_off = HHI_HIFI_PLL_CNTL,
293 .table = axg_gp0_pll_params_table,
294 .init_regs = axg_hifi_init_regs,
295 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
296 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
298 .hw.init = &(struct clk_init_data){
299 .name = "hifi_pll_dco",
300 .ops = &meson_clk_pll_ops,
301 .parent_data = &(const struct clk_parent_data) {
308 static struct clk_regmap axg_hifi_pll = {
309 .data = &(struct clk_regmap_div_data){
310 .offset = HHI_HIFI_PLL_CNTL,
313 .flags = CLK_DIVIDER_POWER_OF_TWO,
315 .hw.init = &(struct clk_init_data){
317 .ops = &clk_regmap_divider_ops,
318 .parent_hws = (const struct clk_hw *[]) {
322 .flags = CLK_SET_RATE_PARENT,
326 static struct clk_fixed_factor axg_fclk_div2_div = {
329 .hw.init = &(struct clk_init_data){
330 .name = "fclk_div2_div",
331 .ops = &clk_fixed_factor_ops,
332 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
337 static struct clk_regmap axg_fclk_div2 = {
338 .data = &(struct clk_regmap_gate_data){
339 .offset = HHI_MPLL_CNTL6,
342 .hw.init = &(struct clk_init_data){
344 .ops = &clk_regmap_gate_ops,
345 .parent_hws = (const struct clk_hw *[]) {
346 &axg_fclk_div2_div.hw
349 .flags = CLK_IS_CRITICAL,
353 static struct clk_fixed_factor axg_fclk_div3_div = {
356 .hw.init = &(struct clk_init_data){
357 .name = "fclk_div3_div",
358 .ops = &clk_fixed_factor_ops,
359 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
364 static struct clk_regmap axg_fclk_div3 = {
365 .data = &(struct clk_regmap_gate_data){
366 .offset = HHI_MPLL_CNTL6,
369 .hw.init = &(struct clk_init_data){
371 .ops = &clk_regmap_gate_ops,
372 .parent_hws = (const struct clk_hw *[]) {
373 &axg_fclk_div3_div.hw
378 * This clock, as fdiv2, is used by the SCPI FW and is required
379 * by the platform to operate correctly.
380 * Until the following condition are met, we need this clock to
381 * be marked as critical:
382 * a) The SCPI generic driver claims and enable all the clocks
384 * b) CCF has a clock hand-off mechanism to make the sure the
385 * clock stays on until the proper driver comes along
387 .flags = CLK_IS_CRITICAL,
391 static struct clk_fixed_factor axg_fclk_div4_div = {
394 .hw.init = &(struct clk_init_data){
395 .name = "fclk_div4_div",
396 .ops = &clk_fixed_factor_ops,
397 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
402 static struct clk_regmap axg_fclk_div4 = {
403 .data = &(struct clk_regmap_gate_data){
404 .offset = HHI_MPLL_CNTL6,
407 .hw.init = &(struct clk_init_data){
409 .ops = &clk_regmap_gate_ops,
410 .parent_hws = (const struct clk_hw *[]) {
411 &axg_fclk_div4_div.hw
417 static struct clk_fixed_factor axg_fclk_div5_div = {
420 .hw.init = &(struct clk_init_data){
421 .name = "fclk_div5_div",
422 .ops = &clk_fixed_factor_ops,
423 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
428 static struct clk_regmap axg_fclk_div5 = {
429 .data = &(struct clk_regmap_gate_data){
430 .offset = HHI_MPLL_CNTL6,
433 .hw.init = &(struct clk_init_data){
435 .ops = &clk_regmap_gate_ops,
436 .parent_hws = (const struct clk_hw *[]) {
437 &axg_fclk_div5_div.hw
443 static struct clk_fixed_factor axg_fclk_div7_div = {
446 .hw.init = &(struct clk_init_data){
447 .name = "fclk_div7_div",
448 .ops = &clk_fixed_factor_ops,
449 .parent_hws = (const struct clk_hw *[]) {
456 static struct clk_regmap axg_fclk_div7 = {
457 .data = &(struct clk_regmap_gate_data){
458 .offset = HHI_MPLL_CNTL6,
461 .hw.init = &(struct clk_init_data){
463 .ops = &clk_regmap_gate_ops,
464 .parent_hws = (const struct clk_hw *[]) {
465 &axg_fclk_div7_div.hw
471 static struct clk_regmap axg_mpll_prediv = {
472 .data = &(struct clk_regmap_div_data){
473 .offset = HHI_MPLL_CNTL5,
477 .hw.init = &(struct clk_init_data){
478 .name = "mpll_prediv",
479 .ops = &clk_regmap_divider_ro_ops,
480 .parent_hws = (const struct clk_hw *[]) {
487 static struct clk_regmap axg_mpll0_div = {
488 .data = &(struct meson_clk_mpll_data){
490 .reg_off = HHI_MPLL_CNTL7,
495 .reg_off = HHI_MPLL_CNTL7,
500 .reg_off = HHI_MPLL_CNTL7,
505 .reg_off = HHI_PLL_TOP_MISC,
509 .lock = &meson_clk_lock,
510 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
512 .hw.init = &(struct clk_init_data){
514 .ops = &meson_clk_mpll_ops,
515 .parent_hws = (const struct clk_hw *[]) {
522 static struct clk_regmap axg_mpll0 = {
523 .data = &(struct clk_regmap_gate_data){
524 .offset = HHI_MPLL_CNTL7,
527 .hw.init = &(struct clk_init_data){
529 .ops = &clk_regmap_gate_ops,
530 .parent_hws = (const struct clk_hw *[]) {
534 .flags = CLK_SET_RATE_PARENT,
538 static struct clk_regmap axg_mpll1_div = {
539 .data = &(struct meson_clk_mpll_data){
541 .reg_off = HHI_MPLL_CNTL8,
546 .reg_off = HHI_MPLL_CNTL8,
551 .reg_off = HHI_MPLL_CNTL8,
556 .reg_off = HHI_PLL_TOP_MISC,
560 .lock = &meson_clk_lock,
561 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
563 .hw.init = &(struct clk_init_data){
565 .ops = &meson_clk_mpll_ops,
566 .parent_hws = (const struct clk_hw *[]) {
573 static struct clk_regmap axg_mpll1 = {
574 .data = &(struct clk_regmap_gate_data){
575 .offset = HHI_MPLL_CNTL8,
578 .hw.init = &(struct clk_init_data){
580 .ops = &clk_regmap_gate_ops,
581 .parent_hws = (const struct clk_hw *[]) {
585 .flags = CLK_SET_RATE_PARENT,
589 static struct clk_regmap axg_mpll2_div = {
590 .data = &(struct meson_clk_mpll_data){
592 .reg_off = HHI_MPLL_CNTL9,
597 .reg_off = HHI_MPLL_CNTL9,
602 .reg_off = HHI_MPLL_CNTL9,
607 .reg_off = HHI_MPLL_CNTL,
612 .reg_off = HHI_PLL_TOP_MISC,
616 .lock = &meson_clk_lock,
617 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
619 .hw.init = &(struct clk_init_data){
621 .ops = &meson_clk_mpll_ops,
622 .parent_hws = (const struct clk_hw *[]) {
629 static struct clk_regmap axg_mpll2 = {
630 .data = &(struct clk_regmap_gate_data){
631 .offset = HHI_MPLL_CNTL9,
634 .hw.init = &(struct clk_init_data){
636 .ops = &clk_regmap_gate_ops,
637 .parent_hws = (const struct clk_hw *[]) {
641 .flags = CLK_SET_RATE_PARENT,
645 static struct clk_regmap axg_mpll3_div = {
646 .data = &(struct meson_clk_mpll_data){
648 .reg_off = HHI_MPLL3_CNTL0,
653 .reg_off = HHI_MPLL3_CNTL0,
658 .reg_off = HHI_MPLL3_CNTL0,
663 .reg_off = HHI_PLL_TOP_MISC,
667 .lock = &meson_clk_lock,
668 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
670 .hw.init = &(struct clk_init_data){
672 .ops = &meson_clk_mpll_ops,
673 .parent_hws = (const struct clk_hw *[]) {
680 static struct clk_regmap axg_mpll3 = {
681 .data = &(struct clk_regmap_gate_data){
682 .offset = HHI_MPLL3_CNTL0,
685 .hw.init = &(struct clk_init_data){
687 .ops = &clk_regmap_gate_ops,
688 .parent_hws = (const struct clk_hw *[]) {
692 .flags = CLK_SET_RATE_PARENT,
696 static const struct pll_params_table axg_pcie_pll_params_table[] = {
704 static const struct reg_sequence axg_pcie_init_regs[] = {
705 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
706 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
707 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
708 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
709 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
710 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
711 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
714 static struct clk_regmap axg_pcie_pll_dco = {
715 .data = &(struct meson_clk_pll_data){
717 .reg_off = HHI_PCIE_PLL_CNTL,
722 .reg_off = HHI_PCIE_PLL_CNTL,
727 .reg_off = HHI_PCIE_PLL_CNTL,
732 .reg_off = HHI_PCIE_PLL_CNTL1,
737 .reg_off = HHI_PCIE_PLL_CNTL,
742 .reg_off = HHI_PCIE_PLL_CNTL,
746 .table = axg_pcie_pll_params_table,
747 .init_regs = axg_pcie_init_regs,
748 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
750 .hw.init = &(struct clk_init_data){
751 .name = "pcie_pll_dco",
752 .ops = &meson_clk_pll_ops,
753 .parent_data = &(const struct clk_parent_data) {
760 static struct clk_regmap axg_pcie_pll_od = {
761 .data = &(struct clk_regmap_div_data){
762 .offset = HHI_PCIE_PLL_CNTL,
765 .flags = CLK_DIVIDER_POWER_OF_TWO,
767 .hw.init = &(struct clk_init_data){
768 .name = "pcie_pll_od",
769 .ops = &clk_regmap_divider_ops,
770 .parent_hws = (const struct clk_hw *[]) {
774 .flags = CLK_SET_RATE_PARENT,
778 static struct clk_regmap axg_pcie_pll = {
779 .data = &(struct clk_regmap_div_data){
780 .offset = HHI_PCIE_PLL_CNTL6,
783 .flags = CLK_DIVIDER_POWER_OF_TWO,
785 .hw.init = &(struct clk_init_data){
787 .ops = &clk_regmap_divider_ops,
788 .parent_hws = (const struct clk_hw *[]) {
792 .flags = CLK_SET_RATE_PARENT,
796 static struct clk_regmap axg_pcie_mux = {
797 .data = &(struct clk_regmap_mux_data){
798 .offset = HHI_PCIE_PLL_CNTL6,
801 /* skip the parent mpll3, reserved for debug */
802 .table = (u32[]){ 1 },
804 .hw.init = &(struct clk_init_data){
806 .ops = &clk_regmap_mux_ops,
807 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
809 .flags = CLK_SET_RATE_PARENT,
813 static struct clk_regmap axg_pcie_ref = {
814 .data = &(struct clk_regmap_mux_data){
815 .offset = HHI_PCIE_PLL_CNTL6,
818 /* skip the parent 0, reserved for debug */
819 .table = (u32[]){ 1 },
821 .hw.init = &(struct clk_init_data){
823 .ops = &clk_regmap_mux_ops,
824 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
826 .flags = CLK_SET_RATE_PARENT,
830 static struct clk_regmap axg_pcie_cml_en0 = {
831 .data = &(struct clk_regmap_gate_data){
832 .offset = HHI_PCIE_PLL_CNTL6,
835 .hw.init = &(struct clk_init_data) {
836 .name = "pcie_cml_en0",
837 .ops = &clk_regmap_gate_ops,
838 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
840 .flags = CLK_SET_RATE_PARENT,
845 static struct clk_regmap axg_pcie_cml_en1 = {
846 .data = &(struct clk_regmap_gate_data){
847 .offset = HHI_PCIE_PLL_CNTL6,
850 .hw.init = &(struct clk_init_data) {
851 .name = "pcie_cml_en1",
852 .ops = &clk_regmap_gate_ops,
853 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
855 .flags = CLK_SET_RATE_PARENT,
859 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
860 static const struct clk_parent_data clk81_parent_data[] = {
861 { .fw_name = "xtal", },
862 { .hw = &axg_fclk_div7.hw },
863 { .hw = &axg_mpll1.hw },
864 { .hw = &axg_mpll2.hw },
865 { .hw = &axg_fclk_div4.hw },
866 { .hw = &axg_fclk_div3.hw },
867 { .hw = &axg_fclk_div5.hw },
870 static struct clk_regmap axg_mpeg_clk_sel = {
871 .data = &(struct clk_regmap_mux_data){
872 .offset = HHI_MPEG_CLK_CNTL,
875 .table = mux_table_clk81,
877 .hw.init = &(struct clk_init_data){
878 .name = "mpeg_clk_sel",
879 .ops = &clk_regmap_mux_ro_ops,
880 .parent_data = clk81_parent_data,
881 .num_parents = ARRAY_SIZE(clk81_parent_data),
885 static struct clk_regmap axg_mpeg_clk_div = {
886 .data = &(struct clk_regmap_div_data){
887 .offset = HHI_MPEG_CLK_CNTL,
891 .hw.init = &(struct clk_init_data){
892 .name = "mpeg_clk_div",
893 .ops = &clk_regmap_divider_ops,
894 .parent_hws = (const struct clk_hw *[]) {
898 .flags = CLK_SET_RATE_PARENT,
902 static struct clk_regmap axg_clk81 = {
903 .data = &(struct clk_regmap_gate_data){
904 .offset = HHI_MPEG_CLK_CNTL,
907 .hw.init = &(struct clk_init_data){
909 .ops = &clk_regmap_gate_ops,
910 .parent_hws = (const struct clk_hw *[]) {
914 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
918 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
919 { .fw_name = "xtal", },
920 { .hw = &axg_fclk_div2.hw },
921 { .hw = &axg_fclk_div3.hw },
922 { .hw = &axg_fclk_div5.hw },
923 { .hw = &axg_fclk_div7.hw },
925 * Following these parent clocks, we should also have had mpll2, mpll3
926 * and gp0_pll but these clocks are too precious to be used here. All
927 * the necessary rates for MMC and NAND operation can be acheived using
928 * xtal or fclk_div clocks
933 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
934 .data = &(struct clk_regmap_mux_data){
935 .offset = HHI_SD_EMMC_CLK_CNTL,
939 .hw.init = &(struct clk_init_data) {
940 .name = "sd_emmc_b_clk0_sel",
941 .ops = &clk_regmap_mux_ops,
942 .parent_data = axg_sd_emmc_clk0_parent_data,
943 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
944 .flags = CLK_SET_RATE_PARENT,
948 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
949 .data = &(struct clk_regmap_div_data){
950 .offset = HHI_SD_EMMC_CLK_CNTL,
953 .flags = CLK_DIVIDER_ROUND_CLOSEST,
955 .hw.init = &(struct clk_init_data) {
956 .name = "sd_emmc_b_clk0_div",
957 .ops = &clk_regmap_divider_ops,
958 .parent_hws = (const struct clk_hw *[]) {
959 &axg_sd_emmc_b_clk0_sel.hw
962 .flags = CLK_SET_RATE_PARENT,
966 static struct clk_regmap axg_sd_emmc_b_clk0 = {
967 .data = &(struct clk_regmap_gate_data){
968 .offset = HHI_SD_EMMC_CLK_CNTL,
971 .hw.init = &(struct clk_init_data){
972 .name = "sd_emmc_b_clk0",
973 .ops = &clk_regmap_gate_ops,
974 .parent_hws = (const struct clk_hw *[]) {
975 &axg_sd_emmc_b_clk0_div.hw
978 .flags = CLK_SET_RATE_PARENT,
982 /* EMMC/NAND clock */
983 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
984 .data = &(struct clk_regmap_mux_data){
985 .offset = HHI_NAND_CLK_CNTL,
989 .hw.init = &(struct clk_init_data) {
990 .name = "sd_emmc_c_clk0_sel",
991 .ops = &clk_regmap_mux_ops,
992 .parent_data = axg_sd_emmc_clk0_parent_data,
993 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
994 .flags = CLK_SET_RATE_PARENT,
998 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
999 .data = &(struct clk_regmap_div_data){
1000 .offset = HHI_NAND_CLK_CNTL,
1003 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1005 .hw.init = &(struct clk_init_data) {
1006 .name = "sd_emmc_c_clk0_div",
1007 .ops = &clk_regmap_divider_ops,
1008 .parent_hws = (const struct clk_hw *[]) {
1009 &axg_sd_emmc_c_clk0_sel.hw
1012 .flags = CLK_SET_RATE_PARENT,
1016 static struct clk_regmap axg_sd_emmc_c_clk0 = {
1017 .data = &(struct clk_regmap_gate_data){
1018 .offset = HHI_NAND_CLK_CNTL,
1021 .hw.init = &(struct clk_init_data){
1022 .name = "sd_emmc_c_clk0",
1023 .ops = &clk_regmap_gate_ops,
1024 .parent_hws = (const struct clk_hw *[]) {
1025 &axg_sd_emmc_c_clk0_div.hw
1028 .flags = CLK_SET_RATE_PARENT,
1034 static const struct clk_hw *axg_vpu_parent_hws[] = {
1041 static struct clk_regmap axg_vpu_0_sel = {
1042 .data = &(struct clk_regmap_mux_data){
1043 .offset = HHI_VPU_CLK_CNTL,
1047 .hw.init = &(struct clk_init_data){
1048 .name = "vpu_0_sel",
1049 .ops = &clk_regmap_mux_ops,
1050 .parent_hws = axg_vpu_parent_hws,
1051 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1052 /* We need a specific parent for VPU clock source, let it be set in DT */
1053 .flags = CLK_SET_RATE_NO_REPARENT,
1057 static struct clk_regmap axg_vpu_0_div = {
1058 .data = &(struct clk_regmap_div_data){
1059 .offset = HHI_VPU_CLK_CNTL,
1063 .hw.init = &(struct clk_init_data){
1064 .name = "vpu_0_div",
1065 .ops = &clk_regmap_divider_ops,
1066 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw },
1068 .flags = CLK_SET_RATE_PARENT,
1072 static struct clk_regmap axg_vpu_0 = {
1073 .data = &(struct clk_regmap_gate_data){
1074 .offset = HHI_VPU_CLK_CNTL,
1077 .hw.init = &(struct clk_init_data) {
1079 .ops = &clk_regmap_gate_ops,
1080 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw },
1083 * We want to avoid CCF to disable the VPU clock if
1084 * display has been set by Bootloader
1086 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1090 static struct clk_regmap axg_vpu_1_sel = {
1091 .data = &(struct clk_regmap_mux_data){
1092 .offset = HHI_VPU_CLK_CNTL,
1096 .hw.init = &(struct clk_init_data){
1097 .name = "vpu_1_sel",
1098 .ops = &clk_regmap_mux_ops,
1099 .parent_hws = axg_vpu_parent_hws,
1100 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1101 /* We need a specific parent for VPU clock source, let it be set in DT */
1102 .flags = CLK_SET_RATE_NO_REPARENT,
1106 static struct clk_regmap axg_vpu_1_div = {
1107 .data = &(struct clk_regmap_div_data){
1108 .offset = HHI_VPU_CLK_CNTL,
1112 .hw.init = &(struct clk_init_data){
1113 .name = "vpu_1_div",
1114 .ops = &clk_regmap_divider_ops,
1115 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw },
1117 .flags = CLK_SET_RATE_PARENT,
1121 static struct clk_regmap axg_vpu_1 = {
1122 .data = &(struct clk_regmap_gate_data){
1123 .offset = HHI_VPU_CLK_CNTL,
1126 .hw.init = &(struct clk_init_data) {
1128 .ops = &clk_regmap_gate_ops,
1129 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw },
1132 * We want to avoid CCF to disable the VPU clock if
1133 * display has been set by Bootloader
1135 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1139 static struct clk_regmap axg_vpu = {
1140 .data = &(struct clk_regmap_mux_data){
1141 .offset = HHI_VPU_CLK_CNTL,
1145 .hw.init = &(struct clk_init_data){
1147 .ops = &clk_regmap_mux_ops,
1148 .parent_hws = (const struct clk_hw *[]) {
1153 .flags = CLK_SET_RATE_NO_REPARENT,
1159 static struct clk_regmap axg_vapb_0_sel = {
1160 .data = &(struct clk_regmap_mux_data){
1161 .offset = HHI_VAPBCLK_CNTL,
1165 .hw.init = &(struct clk_init_data){
1166 .name = "vapb_0_sel",
1167 .ops = &clk_regmap_mux_ops,
1168 .parent_hws = axg_vpu_parent_hws,
1169 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1170 .flags = CLK_SET_RATE_NO_REPARENT,
1174 static struct clk_regmap axg_vapb_0_div = {
1175 .data = &(struct clk_regmap_div_data){
1176 .offset = HHI_VAPBCLK_CNTL,
1180 .hw.init = &(struct clk_init_data){
1181 .name = "vapb_0_div",
1182 .ops = &clk_regmap_divider_ops,
1183 .parent_hws = (const struct clk_hw *[]) {
1187 .flags = CLK_SET_RATE_PARENT,
1191 static struct clk_regmap axg_vapb_0 = {
1192 .data = &(struct clk_regmap_gate_data){
1193 .offset = HHI_VAPBCLK_CNTL,
1196 .hw.init = &(struct clk_init_data) {
1198 .ops = &clk_regmap_gate_ops,
1199 .parent_hws = (const struct clk_hw *[]) {
1203 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1207 static struct clk_regmap axg_vapb_1_sel = {
1208 .data = &(struct clk_regmap_mux_data){
1209 .offset = HHI_VAPBCLK_CNTL,
1213 .hw.init = &(struct clk_init_data){
1214 .name = "vapb_1_sel",
1215 .ops = &clk_regmap_mux_ops,
1216 .parent_hws = axg_vpu_parent_hws,
1217 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1218 .flags = CLK_SET_RATE_NO_REPARENT,
1222 static struct clk_regmap axg_vapb_1_div = {
1223 .data = &(struct clk_regmap_div_data){
1224 .offset = HHI_VAPBCLK_CNTL,
1228 .hw.init = &(struct clk_init_data){
1229 .name = "vapb_1_div",
1230 .ops = &clk_regmap_divider_ops,
1231 .parent_hws = (const struct clk_hw *[]) {
1235 .flags = CLK_SET_RATE_PARENT,
1239 static struct clk_regmap axg_vapb_1 = {
1240 .data = &(struct clk_regmap_gate_data){
1241 .offset = HHI_VAPBCLK_CNTL,
1244 .hw.init = &(struct clk_init_data) {
1246 .ops = &clk_regmap_gate_ops,
1247 .parent_hws = (const struct clk_hw *[]) {
1251 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1255 static struct clk_regmap axg_vapb_sel = {
1256 .data = &(struct clk_regmap_mux_data){
1257 .offset = HHI_VAPBCLK_CNTL,
1261 .hw.init = &(struct clk_init_data){
1263 .ops = &clk_regmap_mux_ops,
1264 .parent_hws = (const struct clk_hw *[]) {
1269 .flags = CLK_SET_RATE_NO_REPARENT,
1273 static struct clk_regmap axg_vapb = {
1274 .data = &(struct clk_regmap_gate_data){
1275 .offset = HHI_VAPBCLK_CNTL,
1278 .hw.init = &(struct clk_init_data) {
1280 .ops = &clk_regmap_gate_ops,
1281 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw },
1283 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1289 static const struct clk_hw *axg_vclk_parent_hws[] = {
1299 static struct clk_regmap axg_vclk_sel = {
1300 .data = &(struct clk_regmap_mux_data){
1301 .offset = HHI_VID_CLK_CNTL,
1305 .hw.init = &(struct clk_init_data){
1307 .ops = &clk_regmap_mux_ops,
1308 .parent_hws = axg_vclk_parent_hws,
1309 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1310 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1314 static struct clk_regmap axg_vclk2_sel = {
1315 .data = &(struct clk_regmap_mux_data){
1316 .offset = HHI_VIID_CLK_CNTL,
1320 .hw.init = &(struct clk_init_data){
1321 .name = "vclk2_sel",
1322 .ops = &clk_regmap_mux_ops,
1323 .parent_hws = axg_vclk_parent_hws,
1324 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1325 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1329 static struct clk_regmap axg_vclk_input = {
1330 .data = &(struct clk_regmap_gate_data){
1331 .offset = HHI_VID_CLK_DIV,
1334 .hw.init = &(struct clk_init_data) {
1335 .name = "vclk_input",
1336 .ops = &clk_regmap_gate_ops,
1337 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw },
1339 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1343 static struct clk_regmap axg_vclk2_input = {
1344 .data = &(struct clk_regmap_gate_data){
1345 .offset = HHI_VIID_CLK_DIV,
1348 .hw.init = &(struct clk_init_data) {
1349 .name = "vclk2_input",
1350 .ops = &clk_regmap_gate_ops,
1351 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw },
1353 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1357 static struct clk_regmap axg_vclk_div = {
1358 .data = &(struct clk_regmap_div_data){
1359 .offset = HHI_VID_CLK_DIV,
1363 .hw.init = &(struct clk_init_data){
1365 .ops = &clk_regmap_divider_ops,
1366 .parent_hws = (const struct clk_hw *[]) {
1370 .flags = CLK_GET_RATE_NOCACHE,
1374 static struct clk_regmap axg_vclk2_div = {
1375 .data = &(struct clk_regmap_div_data){
1376 .offset = HHI_VIID_CLK_DIV,
1380 .hw.init = &(struct clk_init_data){
1381 .name = "vclk2_div",
1382 .ops = &clk_regmap_divider_ops,
1383 .parent_hws = (const struct clk_hw *[]) {
1387 .flags = CLK_GET_RATE_NOCACHE,
1391 static struct clk_regmap axg_vclk = {
1392 .data = &(struct clk_regmap_gate_data){
1393 .offset = HHI_VID_CLK_CNTL,
1396 .hw.init = &(struct clk_init_data) {
1398 .ops = &clk_regmap_gate_ops,
1399 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw },
1401 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1405 static struct clk_regmap axg_vclk2 = {
1406 .data = &(struct clk_regmap_gate_data){
1407 .offset = HHI_VIID_CLK_CNTL,
1410 .hw.init = &(struct clk_init_data) {
1412 .ops = &clk_regmap_gate_ops,
1413 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw },
1415 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1419 static struct clk_regmap axg_vclk_div1 = {
1420 .data = &(struct clk_regmap_gate_data){
1421 .offset = HHI_VID_CLK_CNTL,
1424 .hw.init = &(struct clk_init_data) {
1425 .name = "vclk_div1",
1426 .ops = &clk_regmap_gate_ops,
1427 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1429 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1433 static struct clk_regmap axg_vclk_div2_en = {
1434 .data = &(struct clk_regmap_gate_data){
1435 .offset = HHI_VID_CLK_CNTL,
1438 .hw.init = &(struct clk_init_data) {
1439 .name = "vclk_div2_en",
1440 .ops = &clk_regmap_gate_ops,
1441 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1443 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1447 static struct clk_regmap axg_vclk_div4_en = {
1448 .data = &(struct clk_regmap_gate_data){
1449 .offset = HHI_VID_CLK_CNTL,
1452 .hw.init = &(struct clk_init_data) {
1453 .name = "vclk_div4_en",
1454 .ops = &clk_regmap_gate_ops,
1455 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1457 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1461 static struct clk_regmap axg_vclk_div6_en = {
1462 .data = &(struct clk_regmap_gate_data){
1463 .offset = HHI_VID_CLK_CNTL,
1466 .hw.init = &(struct clk_init_data) {
1467 .name = "vclk_div6_en",
1468 .ops = &clk_regmap_gate_ops,
1469 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1471 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1475 static struct clk_regmap axg_vclk_div12_en = {
1476 .data = &(struct clk_regmap_gate_data){
1477 .offset = HHI_VID_CLK_CNTL,
1480 .hw.init = &(struct clk_init_data) {
1481 .name = "vclk_div12_en",
1482 .ops = &clk_regmap_gate_ops,
1483 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1485 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1489 static struct clk_regmap axg_vclk2_div1 = {
1490 .data = &(struct clk_regmap_gate_data){
1491 .offset = HHI_VIID_CLK_CNTL,
1494 .hw.init = &(struct clk_init_data) {
1495 .name = "vclk2_div1",
1496 .ops = &clk_regmap_gate_ops,
1497 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1499 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1503 static struct clk_regmap axg_vclk2_div2_en = {
1504 .data = &(struct clk_regmap_gate_data){
1505 .offset = HHI_VIID_CLK_CNTL,
1508 .hw.init = &(struct clk_init_data) {
1509 .name = "vclk2_div2_en",
1510 .ops = &clk_regmap_gate_ops,
1511 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1513 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1517 static struct clk_regmap axg_vclk2_div4_en = {
1518 .data = &(struct clk_regmap_gate_data){
1519 .offset = HHI_VIID_CLK_CNTL,
1522 .hw.init = &(struct clk_init_data) {
1523 .name = "vclk2_div4_en",
1524 .ops = &clk_regmap_gate_ops,
1525 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1527 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1531 static struct clk_regmap axg_vclk2_div6_en = {
1532 .data = &(struct clk_regmap_gate_data){
1533 .offset = HHI_VIID_CLK_CNTL,
1536 .hw.init = &(struct clk_init_data) {
1537 .name = "vclk2_div6_en",
1538 .ops = &clk_regmap_gate_ops,
1539 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1541 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1545 static struct clk_regmap axg_vclk2_div12_en = {
1546 .data = &(struct clk_regmap_gate_data){
1547 .offset = HHI_VIID_CLK_CNTL,
1550 .hw.init = &(struct clk_init_data) {
1551 .name = "vclk2_div12_en",
1552 .ops = &clk_regmap_gate_ops,
1553 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1555 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1559 static struct clk_fixed_factor axg_vclk_div2 = {
1562 .hw.init = &(struct clk_init_data){
1563 .name = "vclk_div2",
1564 .ops = &clk_fixed_factor_ops,
1565 .parent_hws = (const struct clk_hw *[]) {
1566 &axg_vclk_div2_en.hw
1572 static struct clk_fixed_factor axg_vclk_div4 = {
1575 .hw.init = &(struct clk_init_data){
1576 .name = "vclk_div4",
1577 .ops = &clk_fixed_factor_ops,
1578 .parent_hws = (const struct clk_hw *[]) {
1579 &axg_vclk_div4_en.hw
1585 static struct clk_fixed_factor axg_vclk_div6 = {
1588 .hw.init = &(struct clk_init_data){
1589 .name = "vclk_div6",
1590 .ops = &clk_fixed_factor_ops,
1591 .parent_hws = (const struct clk_hw *[]) {
1592 &axg_vclk_div6_en.hw
1598 static struct clk_fixed_factor axg_vclk_div12 = {
1601 .hw.init = &(struct clk_init_data){
1602 .name = "vclk_div12",
1603 .ops = &clk_fixed_factor_ops,
1604 .parent_hws = (const struct clk_hw *[]) {
1605 &axg_vclk_div12_en.hw
1611 static struct clk_fixed_factor axg_vclk2_div2 = {
1614 .hw.init = &(struct clk_init_data){
1615 .name = "vclk2_div2",
1616 .ops = &clk_fixed_factor_ops,
1617 .parent_hws = (const struct clk_hw *[]) {
1618 &axg_vclk2_div2_en.hw
1624 static struct clk_fixed_factor axg_vclk2_div4 = {
1627 .hw.init = &(struct clk_init_data){
1628 .name = "vclk2_div4",
1629 .ops = &clk_fixed_factor_ops,
1630 .parent_hws = (const struct clk_hw *[]) {
1631 &axg_vclk2_div4_en.hw
1637 static struct clk_fixed_factor axg_vclk2_div6 = {
1640 .hw.init = &(struct clk_init_data){
1641 .name = "vclk2_div6",
1642 .ops = &clk_fixed_factor_ops,
1643 .parent_hws = (const struct clk_hw *[]) {
1644 &axg_vclk2_div6_en.hw
1650 static struct clk_fixed_factor axg_vclk2_div12 = {
1653 .hw.init = &(struct clk_init_data){
1654 .name = "vclk2_div12",
1655 .ops = &clk_fixed_factor_ops,
1656 .parent_hws = (const struct clk_hw *[]) {
1657 &axg_vclk2_div12_en.hw
1663 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1664 static const struct clk_hw *axg_cts_parent_hws[] = {
1674 &axg_vclk2_div12.hw,
1677 static struct clk_regmap axg_cts_encl_sel = {
1678 .data = &(struct clk_regmap_mux_data){
1679 .offset = HHI_VIID_CLK_DIV,
1682 .table = mux_table_cts_sel,
1684 .hw.init = &(struct clk_init_data){
1685 .name = "cts_encl_sel",
1686 .ops = &clk_regmap_mux_ops,
1687 .parent_hws = axg_cts_parent_hws,
1688 .num_parents = ARRAY_SIZE(axg_cts_parent_hws),
1689 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1693 static struct clk_regmap axg_cts_encl = {
1694 .data = &(struct clk_regmap_gate_data){
1695 .offset = HHI_VID_CLK_CNTL2,
1698 .hw.init = &(struct clk_init_data) {
1700 .ops = &clk_regmap_gate_ops,
1701 .parent_hws = (const struct clk_hw *[]) {
1702 &axg_cts_encl_sel.hw
1705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1709 /* MIPI DSI Host Clock */
1711 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
1712 static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
1713 { .fw_name = "xtal", },
1714 { .hw = &axg_fclk_div4.hw },
1715 { .hw = &axg_fclk_div3.hw },
1716 { .hw = &axg_fclk_div5.hw },
1717 { .hw = &axg_fclk_div2.hw },
1718 { .hw = &axg_fclk_div7.hw },
1721 static struct clk_regmap axg_vdin_meas_sel = {
1722 .data = &(struct clk_regmap_mux_data){
1723 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1726 .flags = CLK_MUX_ROUND_CLOSEST,
1727 .table = mux_table_axg_vdin_meas,
1729 .hw.init = &(struct clk_init_data){
1730 .name = "vdin_meas_sel",
1731 .ops = &clk_regmap_mux_ops,
1732 .parent_data = axg_vdin_meas_parent_data,
1733 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
1734 .flags = CLK_SET_RATE_PARENT,
1738 static struct clk_regmap axg_vdin_meas_div = {
1739 .data = &(struct clk_regmap_div_data){
1740 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1744 .hw.init = &(struct clk_init_data){
1745 .name = "vdin_meas_div",
1746 .ops = &clk_regmap_divider_ops,
1747 .parent_hws = (const struct clk_hw *[]) {
1748 &axg_vdin_meas_sel.hw },
1750 .flags = CLK_SET_RATE_PARENT,
1754 static struct clk_regmap axg_vdin_meas = {
1755 .data = &(struct clk_regmap_gate_data){
1756 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1759 .hw.init = &(struct clk_init_data) {
1760 .name = "vdin_meas",
1761 .ops = &clk_regmap_gate_ops,
1762 .parent_hws = (const struct clk_hw *[]) {
1763 &axg_vdin_meas_div.hw },
1765 .flags = CLK_SET_RATE_PARENT,
1769 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1770 9, 10, 11, 13, 14, };
1771 static const struct clk_parent_data gen_clk_parent_data[] = {
1772 { .fw_name = "xtal", },
1773 { .hw = &axg_hifi_pll.hw },
1774 { .hw = &axg_mpll0.hw },
1775 { .hw = &axg_mpll1.hw },
1776 { .hw = &axg_mpll2.hw },
1777 { .hw = &axg_mpll3.hw },
1778 { .hw = &axg_fclk_div4.hw },
1779 { .hw = &axg_fclk_div3.hw },
1780 { .hw = &axg_fclk_div5.hw },
1781 { .hw = &axg_fclk_div7.hw },
1782 { .hw = &axg_gp0_pll.hw },
1785 static struct clk_regmap axg_gen_clk_sel = {
1786 .data = &(struct clk_regmap_mux_data){
1787 .offset = HHI_GEN_CLK_CNTL,
1790 .table = mux_table_gen_clk,
1792 .hw.init = &(struct clk_init_data){
1793 .name = "gen_clk_sel",
1794 .ops = &clk_regmap_mux_ops,
1796 * bits 15:12 selects from 14 possible parents:
1797 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1798 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
1799 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1801 .parent_data = gen_clk_parent_data,
1802 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
1806 static struct clk_regmap axg_gen_clk_div = {
1807 .data = &(struct clk_regmap_div_data){
1808 .offset = HHI_GEN_CLK_CNTL,
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gen_clk_div",
1814 .ops = &clk_regmap_divider_ops,
1815 .parent_hws = (const struct clk_hw *[]) {
1819 .flags = CLK_SET_RATE_PARENT,
1823 static struct clk_regmap axg_gen_clk = {
1824 .data = &(struct clk_regmap_gate_data){
1825 .offset = HHI_GEN_CLK_CNTL,
1828 .hw.init = &(struct clk_init_data){
1830 .ops = &clk_regmap_gate_ops,
1831 .parent_hws = (const struct clk_hw *[]) {
1835 .flags = CLK_SET_RATE_PARENT,
1839 #define MESON_GATE(_name, _reg, _bit) \
1840 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
1842 /* Everything Else (EE) domain gates */
1843 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1844 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1845 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1846 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1847 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1848 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1849 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1850 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1851 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1852 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1853 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1854 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1855 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1856 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1857 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1858 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1859 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1860 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1861 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1862 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1864 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1865 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1866 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1867 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1868 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1869 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1870 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1871 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1872 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1873 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1874 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1876 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1877 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1878 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1879 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1880 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1881 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1882 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1883 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1885 /* Always On (AO) domain gates */
1887 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1888 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1889 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1890 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1891 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1893 /* Array of all clocks provided by this provider */
1895 static struct clk_hw *axg_hw_clks[] = {
1896 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1897 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1898 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1899 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1900 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1901 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1902 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1903 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1904 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1905 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1906 [CLKID_CLK81] = &axg_clk81.hw,
1907 [CLKID_MPLL0] = &axg_mpll0.hw,
1908 [CLKID_MPLL1] = &axg_mpll1.hw,
1909 [CLKID_MPLL2] = &axg_mpll2.hw,
1910 [CLKID_MPLL3] = &axg_mpll3.hw,
1911 [CLKID_DDR] = &axg_ddr.hw,
1912 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1913 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1914 [CLKID_ISA] = &axg_isa.hw,
1915 [CLKID_PL301] = &axg_pl301.hw,
1916 [CLKID_PERIPHS] = &axg_periphs.hw,
1917 [CLKID_SPICC0] = &axg_spicc_0.hw,
1918 [CLKID_I2C] = &axg_i2c.hw,
1919 [CLKID_RNG0] = &axg_rng0.hw,
1920 [CLKID_UART0] = &axg_uart0.hw,
1921 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1922 [CLKID_SPICC1] = &axg_spicc_1.hw,
1923 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1924 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1925 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1926 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1927 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1928 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1929 [CLKID_DMA] = &axg_dma.hw,
1930 [CLKID_SPI] = &axg_spi.hw,
1931 [CLKID_AUDIO] = &axg_audio.hw,
1932 [CLKID_ETH] = &axg_eth_core.hw,
1933 [CLKID_UART1] = &axg_uart1.hw,
1934 [CLKID_G2D] = &axg_g2d.hw,
1935 [CLKID_USB0] = &axg_usb0.hw,
1936 [CLKID_USB1] = &axg_usb1.hw,
1937 [CLKID_RESET] = &axg_reset.hw,
1938 [CLKID_USB] = &axg_usb_general.hw,
1939 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1940 [CLKID_EFUSE] = &axg_efuse.hw,
1941 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1942 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1943 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1944 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1945 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1946 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1947 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1948 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1949 [CLKID_GIC] = &axg_gic.hw,
1950 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1951 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1952 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1953 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1954 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1955 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1956 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1957 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1958 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1959 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1960 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1961 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1962 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1963 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1964 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1965 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1966 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1967 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1968 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1969 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1970 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1971 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1972 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1973 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1974 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1975 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1976 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1977 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1978 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1979 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1980 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1981 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1982 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1983 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1984 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1985 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1986 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
1987 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
1988 [CLKID_VPU_0] = &axg_vpu_0.hw,
1989 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
1990 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
1991 [CLKID_VPU_1] = &axg_vpu_1.hw,
1992 [CLKID_VPU] = &axg_vpu.hw,
1993 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
1994 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
1995 [CLKID_VAPB_0] = &axg_vapb_0.hw,
1996 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
1997 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
1998 [CLKID_VAPB_1] = &axg_vapb_1.hw,
1999 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
2000 [CLKID_VAPB] = &axg_vapb.hw,
2001 [CLKID_VCLK] = &axg_vclk.hw,
2002 [CLKID_VCLK2] = &axg_vclk2.hw,
2003 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
2004 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
2005 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
2006 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
2007 [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
2008 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
2009 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
2010 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
2011 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
2012 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
2013 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
2014 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
2015 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
2016 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
2017 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
2018 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
2019 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
2020 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
2021 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
2022 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
2023 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
2024 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
2025 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
2026 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
2027 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
2028 [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
2029 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
2030 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
2031 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2034 /* Convenience table to populate regmap in .probe */
2035 static struct clk_regmap *const axg_clk_regmaps[] = {
2074 &axg_sec_ahb_ahb3_bridge,
2081 &axg_sd_emmc_b_clk0,
2082 &axg_sd_emmc_c_clk0,
2084 &axg_sd_emmc_b_clk0_div,
2085 &axg_sd_emmc_c_clk0_div,
2087 &axg_sd_emmc_b_clk0_sel,
2088 &axg_sd_emmc_c_clk0_sel,
2155 &axg_vclk2_div12_en,
2163 static const struct meson_eeclkc_data axg_clkc_data = {
2164 .regmap_clks = axg_clk_regmaps,
2165 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
2168 .num = ARRAY_SIZE(axg_hw_clks),
2173 static const struct of_device_id clkc_match_table[] = {
2174 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2177 MODULE_DEVICE_TABLE(of, clkc_match_table);
2179 static struct platform_driver axg_driver = {
2180 .probe = meson_eeclkc_probe,
2183 .of_match_table = clkc_match_table,
2187 module_platform_driver(axg_driver);
2188 MODULE_LICENSE("GPL v2");