1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Owen Chen <owen.chen@mediatek.com>
7 #ifndef __DRV_CLK_MTK_MUX_H
8 #define __DRV_CLK_MTK_MUX_H
10 #include <linux/clk-provider.h>
14 struct regmap *regmap;
15 const struct mtk_mux *data;
22 const char * const *parent_names;
35 const struct clk_ops *ops;
37 signed char num_parents;
40 extern const struct clk_ops mtk_mux_ops;
41 extern const struct clk_ops mtk_mux_clr_set_upd_ops;
42 extern const struct clk_ops mtk_mux_gate_ops;
43 extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
45 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
46 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
47 _gate, _upd_ofs, _upd, _flags, _ops) { \
50 .mux_ofs = _mux_ofs, \
51 .set_ofs = _mux_set_ofs, \
52 .clr_ofs = _mux_clr_ofs, \
53 .upd_ofs = _upd_ofs, \
54 .mux_shift = _shift, \
55 .mux_width = _width, \
56 .gate_shift = _gate, \
58 .parent_names = _parents, \
59 .num_parents = ARRAY_SIZE(_parents), \
64 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
65 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
66 _gate, _upd_ofs, _upd, _flags) \
67 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
68 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
69 _gate, _upd_ofs, _upd, _flags, \
70 mtk_mux_gate_clr_set_upd_ops)
72 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
73 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
74 _gate, _upd_ofs, _upd) \
75 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
76 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
77 _width, _gate, _upd_ofs, _upd, \
80 struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
81 struct regmap *regmap,
84 int mtk_clk_register_muxes(const struct mtk_mux *muxes,
85 int num, struct device_node *node,
87 struct clk_onecell_data *clk_data);
89 #endif /* __DRV_CLK_MTK_MUX_H */