1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
8 #include <linux/clk-provider.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
17 #include <dt-bindings/clock/mt7629-clk.h>
19 #define GATE_ETH(_id, _name, _parent, _shift) { \
22 .parent_name = _parent, \
23 .regs = ð_cg_regs, \
25 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
28 static const struct mtk_gate_regs eth_cg_regs = {
34 static const struct mtk_gate eth_clks[] = {
35 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
36 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
37 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
38 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
39 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
42 static const struct mtk_gate_regs sgmii_cg_regs = {
48 #define GATE_SGMII(_id, _name, _parent, _shift) { \
51 .parent_name = _parent, \
52 .regs = &sgmii_cg_regs, \
54 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
57 static const struct mtk_gate sgmii_clks[2][4] = {
59 GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
61 GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
62 "ssusb_eq_rx250m", 3),
63 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
65 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
68 GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
70 GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
71 "ssusb_eq_rx250m", 3),
72 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
74 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
79 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
81 struct clk_onecell_data *clk_data;
82 struct device_node *node = pdev->dev.of_node;
85 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
87 mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
89 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
92 "could not register clock provider: %s: %d\n",
95 mtk_register_reset_controller(node, 1, 0x34);
100 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
102 struct clk_onecell_data *clk_data;
103 struct device_node *node = pdev->dev.of_node;
107 clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
109 mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
112 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
115 "could not register clock provider: %s: %d\n",
121 static const struct of_device_id of_match_clk_mt7629_eth[] = {
123 .compatible = "mediatek,mt7629-ethsys",
124 .data = clk_mt7629_ethsys_init,
126 .compatible = "mediatek,mt7629-sgmiisys",
127 .data = clk_mt7629_sgmiisys_init,
133 static int clk_mt7629_eth_probe(struct platform_device *pdev)
135 int (*clk_init)(struct platform_device *);
138 clk_init = of_device_get_match_data(&pdev->dev);
145 "could not register clock provider: %s: %d\n",
151 static struct platform_driver clk_mt7629_eth_drv = {
152 .probe = clk_mt7629_eth_probe,
154 .name = "clk-mt7629-eth",
155 .of_match_table = of_match_clk_mt7629_eth,
159 builtin_platform_driver(clk_mt7629_eth_drv);