1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 MediaTek Inc.
4 * Copyright (c) 2023 Collabora, Ltd.
5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
8 #include <dt-bindings/clock/mt7622-clk.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
12 #include "clk-cpumux.h"
17 #define GATE_INFRA(_id, _name, _parent, _shift) \
18 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
20 static const struct mtk_gate_regs infra_cg_regs = {
26 static const char * const infra_mux1_parents[] = {
33 static const struct mtk_composite cpu_muxes[] = {
34 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
37 static const struct mtk_gate infra_clks[] = {
38 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
39 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
40 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
41 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
42 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
43 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
46 static u16 infrasys_rst_ofs[] = { 0x30 };
48 static const struct mtk_clk_rst_desc clk_rst_desc = {
49 .version = MTK_RST_SIMPLE,
50 .rst_bank_ofs = infrasys_rst_ofs,
51 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
54 static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
55 { .compatible = "mediatek,mt7622-infracfg" },
58 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);
60 static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
62 struct clk_hw_onecell_data *clk_data;
63 struct device_node *node = pdev->dev.of_node;
67 base = devm_platform_ioremap_resource(pdev, 0);
71 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
75 ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
79 ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
80 ARRAY_SIZE(infra_clks), clk_data);
84 ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
85 ARRAY_SIZE(cpu_muxes), clk_data);
87 goto unregister_gates;
89 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
91 goto unregister_cpumuxes;
96 mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
98 mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
100 mtk_free_clk_data(clk_data);
104 static void clk_mt7622_infracfg_remove(struct platform_device *pdev)
106 struct device_node *node = pdev->dev.of_node;
107 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
109 of_clk_del_provider(node);
110 mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
111 mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
112 mtk_free_clk_data(clk_data);
115 static struct platform_driver clk_mt7622_infracfg_drv = {
117 .name = "clk-mt7622-infracfg",
118 .of_match_table = of_match_clk_mt7622_infracfg,
120 .probe = clk_mt7622_infracfg_probe,
121 .remove_new = clk_mt7622_infracfg_remove,
123 module_platform_driver(clk_mt7622_infracfg_drv);
125 MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
126 MODULE_LICENSE("GPL");