drivers/clk/mediatek/clk-mt7622-apmixedsys.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Copyright (c) 2023 Collabora, Ltd.
   5  *               AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt7622-clk.h>
   9 #include <linux/clk.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12
  13 #include "clk-gate.h"
  14 #include "clk-mtk.h"
  15 #include "clk-pll.h"
  16
  17 #define MT7622_PLL_FMAX         (2500UL * MHZ)
  18 #define CON0_MT7622_RST_BAR     BIT(27)
  19
  20 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  21                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
  22                         _pcw_shift, _div_table, _parent_name) {         \
  23                 .id = _id,                                              \
  24                 .name = _name,                                          \
  25                 .reg = _reg,                                            \
  26                 .pwr_reg = _pwr_reg,                                    \
  27                 .en_mask = _en_mask,                                    \
  28                 .flags = _flags,                                        \
  29                 .rst_bar_mask = CON0_MT7622_RST_BAR,                    \
  30                 .fmax = MT7622_PLL_FMAX,                                \
  31                 .pcwbits = _pcwbits,                                    \
  32                 .pd_reg = _pd_reg,                                      \
  33                 .pd_shift = _pd_shift,                                  \
  34                 .tuner_reg = _tuner_reg,                                \
  35                 .pcw_reg = _pcw_reg,                                    \
  36                 .pcw_shift = _pcw_shift,                                \
  37                 .div_table = _div_table,                                \
  38                 .parent_name = _parent_name,                            \
  39         }
  40
  41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
  42                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
  43                         _pcw_shift)                                     \
  44         PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  45                  _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
  46                  NULL, "clkxtal")
  47
  48 static const struct mtk_gate_regs apmixed_cg_regs = {
  49         .set_ofs = 0x8,
  50         .clr_ofs = 0x8,
  51         .sta_ofs = 0x8,
  52 };
  53
  54 #define GATE_APMIXED_AO(_id, _name, _parent, _shift)                    \
  55         GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift,   \
  56                  &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL)
  57
  58 static const struct mtk_pll_data plls[] = {
  59         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
  60             PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
  61         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
  62             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
  63         PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
  64             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
  65         PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
  66             0, 21, 0x0300, 1, 0, 0x0304, 0),
  67         PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
  68             0, 21, 0x0314, 1, 0, 0x0318, 0),
  69         PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
  70             0, 31, 0x0324, 1, 0, 0x0328, 0),
  71         PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
  72             0, 31, 0x0334, 1, 0, 0x0338, 0),
  73         PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
  74             0, 21, 0x0344, 1, 0, 0x0348, 0),
  75         PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
  76             0, 21, 0x0358, 1, 0, 0x035C, 0),
  77 };
  78
  79 static const struct mtk_gate apmixed_clks[] = {
  80         GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
  81 };
  82
  83 static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
  84 {
  85         void __iomem *base;
  86         struct clk_hw_onecell_data *clk_data;
  87         struct device_node *node = pdev->dev.of_node;
  88         struct device *dev = &pdev->dev;
  89         int ret;
  90
  91         base = devm_platform_ioremap_resource(pdev, 0);
  92         if (IS_ERR(base))
  93                 return PTR_ERR(base);
  94
  95         clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
  96         if (!clk_data)
  97                 return -ENOMEM;
  98
  99         ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 100         if (ret)
 101                 return ret;
 102
 103         ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 104                                      ARRAY_SIZE(apmixed_clks), clk_data);
 105         if (ret)
 106                 goto unregister_plls;
 107
 108         ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 109         if (ret)
 110                 goto unregister_gates;
 111
 112         return 0;
 113
 114 unregister_gates:
 115         mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
 116 unregister_plls:
 117         mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
 118
 119         return ret;
 120 }
 121
 122 static void clk_mt7622_apmixed_remove(struct platform_device *pdev)
 123 {
 124         struct device_node *node = pdev->dev.of_node;
 125         struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
 126
 127         of_clk_del_provider(node);
 128         mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
 129         mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
 130 }
 131
 132 static const struct of_device_id of_match_clk_mt7622_apmixed[] = {
 133         { .compatible = "mediatek,mt7622-apmixedsys" },
 134         { /* sentinel */ }
 135 };
 136 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed);
 137
 138 static struct platform_driver clk_mt7622_apmixed_drv = {
 139         .probe = clk_mt7622_apmixed_probe,
 140         .remove_new = clk_mt7622_apmixed_remove,
 141         .driver = {
 142                 .name = "clk-mt7622-apmixed",
 143                 .of_match_table = of_match_clk_mt7622_apmixed,
 144         },
 145 };
 146 module_platform_driver(clk_mt7622_apmixed_drv)
 147
 148 MODULE_DESCRIPTION("MediaTek MT7622 apmixedsys clocks driver");
 149 MODULE_LICENSE("GPL");