drivers/clk/mediatek/clk-mt6795-pericfg.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 Collabora Ltd.
   4  * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
   8 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include "clk-gate.h"
  12 #include "clk-mtk.h"
  13 #include "reset.h"
  14
  15 #define GATE_PERI(_id, _name, _parent, _shift)                  \
  16                 GATE_MTK(_id, _name, _parent, &peri_cg_regs,    \
  17                          _shift, &mtk_clk_gate_ops_setclr)
  18
  19 static DEFINE_SPINLOCK(mt6795_peri_clk_lock);
  20
  21 static const struct mtk_gate_regs peri_cg_regs = {
  22         .set_ofs = 0x0008,
  23         .clr_ofs = 0x0010,
  24         .sta_ofs = 0x0018,
  25 };
  26
  27 static const char * const uart_ck_sel_parents[] = {
  28         "clk26m",
  29         "uart_sel",
  30 };
  31
  32 static const struct mtk_composite peri_clks[] = {
  33         MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
  34         MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
  35         MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
  36         MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
  37 };
  38
  39 static const struct mtk_gate peri_gates[] = {
  40         GATE_PERI(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
  41         GATE_PERI(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
  42         GATE_PERI(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
  43         GATE_PERI(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
  44         GATE_PERI(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
  45         GATE_PERI(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
  46         GATE_PERI(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
  47         GATE_PERI(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
  48         GATE_PERI(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
  49         GATE_PERI(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
  50         GATE_PERI(CLK_PERI_USB0, "peri_usb0", "usb30_sel", 10),
  51         GATE_PERI(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
  52         GATE_PERI(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
  53         GATE_PERI(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
  54         GATE_PERI(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
  55         GATE_PERI(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
  56         GATE_PERI(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
  57         GATE_PERI(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
  58         GATE_PERI(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
  59         GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
  60         GATE_PERI(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
  61         GATE_PERI(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
  62         GATE_PERI(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
  63         GATE_PERI(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
  64         GATE_PERI(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
  65         GATE_PERI(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
  66         GATE_PERI(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
  67         GATE_PERI(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
  68         GATE_PERI(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
  69         GATE_PERI(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
  70 };
  71
  72 static u16 peri_rst_ofs[] = { 0x0 };
  73
  74 static u16 peri_idx_map[] = {
  75         [MT6795_PERI_NFI_SW_RST]   = 14,
  76         [MT6795_PERI_THERM_SW_RST] = 16,
  77         [MT6795_PERI_MSDC1_SW_RST] = 20,
  78 };
  79
  80 static const struct mtk_clk_rst_desc clk_rst_desc = {
  81         .version = MTK_RST_SIMPLE,
  82         .rst_bank_ofs = peri_rst_ofs,
  83         .rst_bank_nr = ARRAY_SIZE(peri_rst_ofs),
  84         .rst_idx_map = peri_idx_map,
  85         .rst_idx_map_nr = ARRAY_SIZE(peri_idx_map),
  86 };
  87
  88 static const struct of_device_id of_match_clk_mt6795_pericfg[] = {
  89         { .compatible = "mediatek,mt6795-pericfg" },
  90         { /* sentinel */ }
  91 };
  92 MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg);
  93
  94 static int clk_mt6795_pericfg_probe(struct platform_device *pdev)
  95 {
  96         struct clk_hw_onecell_data *clk_data;
  97         struct device_node *node = pdev->dev.of_node;
  98         void __iomem *base;
  99         int ret;
 100
 101         base = devm_platform_ioremap_resource(pdev, 0);
 102         if (IS_ERR(base))
 103                 return PTR_ERR(base);
 104
 105         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 106         if (!clk_data)
 107                 return -ENOMEM;
 108
 109         ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 110         if (ret)
 111                 goto free_clk_data;
 112
 113         ret = mtk_clk_register_gates(&pdev->dev, node, peri_gates,
 114                                      ARRAY_SIZE(peri_gates), clk_data);
 115         if (ret)
 116                 goto free_clk_data;
 117
 118         ret = mtk_clk_register_composites(&pdev->dev, peri_clks,
 119                                           ARRAY_SIZE(peri_clks), base,
 120                                           &mt6795_peri_clk_lock, clk_data);
 121         if (ret)
 122                 goto unregister_gates;
 123
 124         ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 125         if (ret)
 126                 goto unregister_composites;
 127
 128         return 0;
 129
 130 unregister_composites:
 131         mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
 132 unregister_gates:
 133         mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
 134 free_clk_data:
 135         mtk_free_clk_data(clk_data);
 136         return ret;
 137 }
 138
 139 static void clk_mt6795_pericfg_remove(struct platform_device *pdev)
 140 {
 141         struct device_node *node = pdev->dev.of_node;
 142         struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
 143
 144         of_clk_del_provider(node);
 145         mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
 146         mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
 147         mtk_free_clk_data(clk_data);
 148 }
 149
 150 static struct platform_driver clk_mt6795_pericfg_drv = {
 151         .driver = {
 152                 .name = "clk-mt6795-pericfg",
 153                 .of_match_table = of_match_clk_mt6795_pericfg,
 154         },
 155         .probe = clk_mt6795_pericfg_probe,
 156         .remove_new = clk_mt6795_pericfg_remove,
 157 };
 158 module_platform_driver(clk_mt6795_pericfg_drv);
 159
 160 MODULE_DESCRIPTION("MediaTek MT6795 pericfg clocks driver");
 161 MODULE_LICENSE("GPL");